forked from Imagelibrary/rtems
powerpc: Use PPC_HAS_FPU
Provide floating point context support only if PPC_HAS_FPU == 1.
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@@ -56,8 +56,12 @@
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#define PPC_CONTEXT_CACHE_LINE_3 (4 * PPC_DEFAULT_CACHE_LINE_SIZE)
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#define PPC_CONTEXT_CACHE_LINE_4 (5 * PPC_DEFAULT_CACHE_LINE_SIZE)
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BEGIN_CODE
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#if PPC_HAS_FPU == 1
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/*
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* Offsets for various Contexts
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* Offsets for Context_Control_fp
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*/
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#if (PPC_HAS_DOUBLE==1)
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@@ -104,7 +108,6 @@
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.set FP_31, (FP_30 + FP_SIZE)
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.set FP_FPSCR, (FP_31 + FP_SIZE)
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BEGIN_CODE
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/*
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* _CPU_Context_save_fp_context
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*
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@@ -121,7 +124,6 @@
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ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
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PUBLIC_PROC (_CPU_Context_save_fp)
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PROC (_CPU_Context_save_fp):
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#if (PPC_HAS_FPU == 1)
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/* A FP context switch may occur in an ISR or exception handler when the FPU is not
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* available. Therefore, we must explicitely enable it here!
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*/
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@@ -171,7 +173,6 @@ PROC (_CPU_Context_save_fp):
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mtmsr r4
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isync
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1:
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#endif
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blr
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/*
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@@ -190,7 +191,6 @@ PROC (_CPU_Context_save_fp):
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ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
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PUBLIC_PROC (_CPU_Context_restore_fp)
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PROC (_CPU_Context_restore_fp):
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#if (PPC_HAS_FPU == 1)
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lwz r3, 0(r3)
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/* A FP context switch may occur in an ISR or exception handler when the FPU is not
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* available. Therefore, we must explicitely enable it here!
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@@ -240,8 +240,8 @@ PROC (_CPU_Context_restore_fp):
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mtmsr r4
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isync
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1:
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#endif
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blr
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#endif /* PPC_HAS_FPU == 1 */
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ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
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PUBLIC_PROC (_CPU_Context_switch)
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@@ -392,6 +392,7 @@ static inline ppc_context *ppc_get_context( const Context_Control *context )
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#ifndef ASM
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typedef struct {
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#if (PPC_HAS_FPU == 1)
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/* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over
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* procedure calls. However, this would mean that the interrupt
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* frame had to hold f0-f13, and the fpscr. And as the majority
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@@ -405,6 +406,7 @@ typedef struct {
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float f[32];
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uint32_t fpscr;
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#endif
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#endif /* (PPC_HAS_FPU == 1) */
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} Context_Control_fp;
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typedef struct CPU_Interrupt_frame {
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