forked from Imagelibrary/rtems
2009-10-29 Till Straumann <strauman@slac.stanford.edu>
* shared/irq/irq_asm.S: Beautification; ajusted margins and spaces to make the whole thing more readable.
This commit is contained in:
Till Straumann
@@ -1,3 +1,8 @@
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2009-10-29 Till Straumann <strauman@slac.stanford.edu>
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* shared/irq/irq_asm.S: Beautification; ajusted margins and
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spaces to make the whole thing more readable.
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2009-10-29 Till Straumann <strauman@slac.stanford.edu>
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* shared/irq/irq_asm.S, shared/irq/irq.c: removed
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@@ -19,87 +19,87 @@
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#error "Missing header? CPU_STACK_ALIGNMENT is not defined here"
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#endif
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BEGIN_CODE
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BEGIN_CODE
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SYM (_ISR_Handler):
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/*
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* Before this was point is reached the vectors unique
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* entry point did the following:
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*
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* 1. saved scratch registers registers eax edx ecx"
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* 2. put the vector number in ecx.
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*
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* BEGINNING OF ESTABLISH SEGMENTS
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*
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* WARNING: If an interrupt can occur when the segments are
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* not correct, then this is where we should establish
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* the segments. In addition to establishing the
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* segments, it may be necessary to establish a stack
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* in the current data area on the outermost interrupt.
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*
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* NOTE: If the previous values of the segment registers are
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* pushed, do not forget to adjust SAVED_REGS.
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*
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* NOTE: Make sure the exit code which restores these
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* when this type of code is needed.
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*/
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/*
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* Before this was point is reached the vectors unique
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* entry point did the following:
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*
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* 1. saved scratch registers registers eax edx ecx"
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* 2. put the vector number in ecx.
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*
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* BEGINNING OF ESTABLISH SEGMENTS
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*
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* WARNING: If an interrupt can occur when the segments are
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* not correct, then this is where we should establish
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* the segments. In addition to establishing the
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* segments, it may be necessary to establish a stack
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* in the current data area on the outermost interrupt.
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*
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* NOTE: If the previous values of the segment registers are
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* pushed, do not forget to adjust SAVED_REGS.
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*
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* NOTE: Make sure the exit code which restores these
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* when this type of code is needed.
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*/
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/***** ESTABLISH SEGMENTS CODE GOES HERE ******/
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/***** ESTABLISH SEGMENTS CODE GOES HERE ******/
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/*
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* END OF ESTABLISH SEGMENTS
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*/
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/*
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* END OF ESTABLISH SEGMENTS
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*/
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/*
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* Now switch stacks if necessary
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*/
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/*
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* Now switch stacks if necessary
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*/
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movw SYM (i8259s_cache), ax /* move current i8259 interrupt mask in ax */
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pushl eax /* push it on the stack */
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movw SYM (i8259s_cache), ax /* move current i8259 interrupt mask in ax */
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pushl eax /* push it on the stack */
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/*
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* compute the new PIC mask:
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*
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* <new mask> = <old mask> | irq_mask_or_tbl[<intr number aka ecx>]
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*/
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movw SYM (irq_mask_or_tbl) (,ecx,2), dx
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orw dx, ax
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movw SYM (irq_mask_or_tbl) (,ecx,2), dx
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orw dx, ax
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/*
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* Install new computed value on the i8259 and update cache
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* accordingly
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*/
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movw ax, SYM (i8259s_cache)
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outb $PIC_MASTER_IMR_IO_PORT
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movb ah, al
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outb $PIC_SLAVE_IMR_IO_PORT
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outb $PIC_MASTER_IMR_IO_PORT
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movb ah, al
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outb $PIC_SLAVE_IMR_IO_PORT
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/*
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* acknowledge the interrupt
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*
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*/
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movb $PIC_EOI, al
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cmpl $7, ecx
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jbe .master
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outb $PIC_SLAVE_COMMAND_IO_PORT
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movb $PIC_EOI, al
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cmpl $7, ecx
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jbe .master
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outb $PIC_SLAVE_COMMAND_IO_PORT
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.master:
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outb $PIC_MASTER_COMMAND_IO_PORT
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outb $PIC_MASTER_COMMAND_IO_PORT
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.check_stack_switch:
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pushl ebp
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movl esp, ebp /* ebp = previous stack pointer */
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cmpl $0, SYM (_ISR_Nest_level) /* is this the outermost interrupt? */
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jne nested /* No, then continue */
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movl SYM (_CPU_Interrupt_stack_high), esp
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pushl ebp
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movl esp, ebp /* ebp = previous stack pointer */
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cmpl $0, SYM (_ISR_Nest_level) /* is this the outermost interrupt? */
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jne nested /* No, then continue */
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movl SYM (_CPU_Interrupt_stack_high), esp
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/*
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* We want to insure that the old stack pointer is on the
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* stack we will be on at the end of the ISR when we restore it.
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* By saving it on every interrupt, all we have to do is pop it
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* near the end of every interrupt.
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*/
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/*
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* We want to insure that the old stack pointer is on the
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* stack we will be on at the end of the ISR when we restore it.
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* By saving it on every interrupt, all we have to do is pop it
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* near the end of every interrupt.
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*/
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nested:
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incl SYM (_ISR_Nest_level) /* one nest level deeper */
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incl SYM (_Thread_Dispatch_disable_level) /* disable multitasking */
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incl SYM (_ISR_Nest_level) /* one nest level deeper */
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incl SYM (_Thread_Dispatch_disable_level) /* disable multitasking */
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/*
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* Ensure CPU_STACK_ALIGNMENT for C-code.
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@@ -107,9 +107,9 @@ nested:
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* makes sure 'esp' is aligned AND there is enough space
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* for the vector argument on the stack!
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*/
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subl $4, esp
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subl $4, esp
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andl $ - CPU_STACK_ALIGNMENT, esp
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andl $ - CPU_STACK_ALIGNMENT, esp
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/*
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* re-enable interrupts at processor level as the current
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* interrupt source is now masked via i8259
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@@ -121,8 +121,8 @@ nested:
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* so we must save it again.
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*/
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movl ecx, (esp) /* store vector arg in stack */
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call C_dispatch_isr
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movl ecx, (esp) /* store vector arg in stack */
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call C_dispatch_isr
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/*
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* disable interrupts_again
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@@ -132,47 +132,47 @@ nested:
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/*
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* restore stack
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*/
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movl ebp, esp
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popl ebp
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movl ebp, esp
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popl ebp
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/*
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* restore the original i8259 masks
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*/
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popl eax
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popl eax
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movw ax, SYM (i8259s_cache)
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outb $PIC_MASTER_IMR_IO_PORT
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movb ah, al
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outb $PIC_SLAVE_IMR_IO_PORT
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decl SYM (_ISR_Nest_level) /* one less ISR nest level */
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/* If interrupts are nested, */
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/* then dispatching is disabled */
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decl SYM (_ISR_Nest_level) /* one less ISR nest level */
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/* If interrupts are nested, */
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/* then dispatching is disabled */
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decl SYM (_Thread_Dispatch_disable_level)
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/* unnest multitasking */
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/* Is dispatch disabled */
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jne .exit /* Yes, then exit */
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decl SYM (_Thread_Dispatch_disable_level)
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/* unnest multitasking */
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/* Is dispatch disabled */
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jne .exit /* Yes, then exit */
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cmpb $0, SYM (_Context_Switch_necessary)
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/* Is task switch necessary? */
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jne .schedule /* Yes, then call the scheduler */
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cmpb $0, SYM (_Context_Switch_necessary)
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/* Is task switch necessary? */
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jne .schedule /* Yes, then call the scheduler */
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cmpb $0, SYM (_ISR_Signals_to_thread_executing)
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/* signals sent to Run_thread */
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/* while in interrupt handler? */
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je .exit /* No, exit */
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cmpb $0, SYM (_ISR_Signals_to_thread_executing)
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/* signals sent to Run_thread */
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/* while in interrupt handler? */
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je .exit /* No, exit */
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.bframe:
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movb $0, SYM (_ISR_Signals_to_thread_executing)
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movb $0, SYM (_ISR_Signals_to_thread_executing)
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/*
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* This code is the less critical path. In order to have a single
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* Thread Context, we take the same frame than the one pushed on
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* exceptions. This makes sense because Signal is a software
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* exception.
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*/
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call _ThreadProcessSignalsFromIrq
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call _ThreadProcessSignalsFromIrq
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jmp .exit
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jmp .exit
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.schedule:
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/*
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@@ -180,39 +180,39 @@ nested:
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* back on the thread system stack. So we can call _Thread_Displatch
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* directly
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*/
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call _Thread_Dispatch
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call _Thread_Dispatch
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/*
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* fall through exit to restore complete contex (scratch registers
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* eip, CS, Flags).
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*/
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.exit:
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/*
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* BEGINNING OF DE-ESTABLISH SEGMENTS
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*
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* NOTE: Make sure there is code here if code is added to
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* load the segment registers.
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*
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*/
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/*
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* BEGINNING OF DE-ESTABLISH SEGMENTS
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*
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* NOTE: Make sure there is code here if code is added to
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* load the segment registers.
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*
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*/
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/******* DE-ESTABLISH SEGMENTS CODE GOES HERE ********/
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/******* DE-ESTABLISH SEGMENTS CODE GOES HERE ********/
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/*
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* END OF DE-ESTABLISH SEGMENTS
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*/
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popl edx
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popl ecx
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popl eax
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/*
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* END OF DE-ESTABLISH SEGMENTS
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*/
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popl edx
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popl ecx
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popl eax
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iret
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#define DISTINCT_INTERRUPT_ENTRY(_vector) \
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.p2align 4 ; \
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PUBLIC (rtems_irq_prologue_ ## _vector ) ; \
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.p2align 4 ; \
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PUBLIC (rtems_irq_prologue_ ## _vector ) ; \
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SYM (rtems_irq_prologue_ ## _vector ): \
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pushl eax ; \
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pushl ecx ; \
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pushl edx ; \
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movl $ _vector, ecx ; \
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jmp SYM (_ISR_Handler) ;
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pushl eax ; \
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pushl ecx ; \
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pushl edx ; \
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movl $ _vector, ecx ; \
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jmp SYM (_ISR_Handler) ;
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DISTINCT_INTERRUPT_ENTRY(0)
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DISTINCT_INTERRUPT_ENTRY(1)
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