aarch64/zynqmp: Fix UART base addresses and IRQ

The base addresses and IRQ numbers for UART 0 and 1 were interchanged.
Fix this and set BSP_CONSOLE_MINOR to 0 for this BSP family.
This commit is contained in:
Sebastian Huber
2024-03-11 14:18:46 +01:00
parent 5cb666ba41
commit 283f783d5d
3 changed files with 5 additions and 4 deletions

View File

@@ -187,11 +187,11 @@ RTEMS_SYSINIT_ITEM(
static zynq_uart_context zynqmp_uart_instances[2] = { static zynq_uart_context zynqmp_uart_instances[2] = {
{ {
.base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 0" ), .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 0" ),
.regs = (volatile struct zynq_uart *) 0xff010000, .regs = (volatile struct zynq_uart *) 0xff000000,
.irq = ZYNQMP_IRQ_UART_0 .irq = ZYNQMP_IRQ_UART_0
}, { }, {
.base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 1" ), .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 1" ),
.regs = (volatile struct zynq_uart *) 0xff000000, .regs = (volatile struct zynq_uart *) 0xff010000,
.irq = ZYNQMP_IRQ_UART_1 .irq = ZYNQMP_IRQ_UART_1
} }
}; };

View File

@@ -56,8 +56,8 @@ extern "C" {
#define ZYNQMP_IRQ_QSPI 47 #define ZYNQMP_IRQ_QSPI 47
#define ZYNQMP_IRQ_I2C_0 49 #define ZYNQMP_IRQ_I2C_0 49
#define ZYNQMP_IRQ_I2C_1 50 #define ZYNQMP_IRQ_I2C_1 50
#define ZYNQMP_IRQ_UART_0 54 #define ZYNQMP_IRQ_UART_0 53
#define ZYNQMP_IRQ_UART_1 53 #define ZYNQMP_IRQ_UART_1 54
#define ZYNQMP_IRQ_ETHERNET_0 89 #define ZYNQMP_IRQ_ETHERNET_0 89
#define ZYNQMP_IRQ_ETHERNET_1 91 #define ZYNQMP_IRQ_ETHERNET_1 91
#define ZYNQMP_IRQ_ETHERNET_2 93 #define ZYNQMP_IRQ_ETHERNET_2 93

View File

@@ -7,6 +7,7 @@ copyrights:
- Copyright (C) 2020 embedded brains GmbH & Co. KG - Copyright (C) 2020 embedded brains GmbH & Co. KG
default: default:
- enabled-by: - enabled-by:
- aarch64/bsps/xilinx-zynqmp
- arm/xilinx_zynq_microzed - arm/xilinx_zynq_microzed
value: 0 value: 0
- enabled-by: true - enabled-by: true