forked from Imagelibrary/rtems
2001-08-09 Chris Johns <ccj@acm.org>
* cpu_asm.S: This patch was co-developed with Eric Norum <eric.norum@usask.ca>. It closes a one instruction window on some m68k CPU cores. It fixes symptoms seen as: 1) No more `interrupt handler invoked twice for a single interrupt'. 2) No more `lockup when mc68360 CPM and PIT interrupts are at different levels'. It does insert a little more overhead on machines without hardware interrupt stacks but correctness has a price.
This commit is contained in:
Joel Sherrill
@@ -3,7 +3,7 @@
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* This file contains all assembly code for the MC68020 implementation
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* of RTEMS.
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*
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* COPYRIGHT (c) 1989-1999.
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* COPYRIGHT (c) 1989-2001.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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@@ -68,7 +68,7 @@ SYM (_CPU_Context_save_fp):
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moval a1@,a0 | a0 = Save context area
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fsave a0@- | save 68881/68882 state frame
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tstb a0@ | check for a null frame
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beq nosv | Yes, skip save of user model
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beq.b nosv | Yes, skip save of user model
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fmovem fp0-fp7,a0@- | save data registers (fp0-fp7)
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fmovem fpc/fps/fpi,a0@- | and save control registers
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movl #-1,a0@- | place not-null flag on stack
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@@ -83,7 +83,7 @@ SYM (_CPU_Context_restore_fp):
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moval a7@(FPCONTEXT_ARG),a1 | a1 = &ptr to context area
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moval a1@,a0 | a0 = address of saved context
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tstb a0@ | Null context frame?
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beq norst | Yes, skip fp restore
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beq.b norst | Yes, skip fp restore
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addql #4,a0 | throwaway non-null flag
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fmovem a0@+,fpc/fps/fpi | restore control registers
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fmovem a0@+,fp0-fp7 | restore data regs (fp0-fp7)
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@@ -101,24 +101,12 @@ norst: frestore a0@+ | restore the fp state frame
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* NOTE:
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* Upon entry, the master stack will contain an interrupt stack frame
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* back to the interrupted thread and the interrupt stack will contain
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* a throwaway interrupt stack frame. If dispatching is enabled, this
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* is the outer most interrupt, and (a context switch is necessary or
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* the current thread has signals), then set up the master stack to
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* a throwaway interrupt stack frame. If dispatching is enabled, and this
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* is the outer most interrupt, and a context switch is necessary or
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* the current thread has pending signals, then set up the master stack to
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* transfer control to the interrupt dispatcher.
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*/
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/*
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* With this approach, lower priority interrupts may
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* execute twice if a higher priority interrupt is
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* acknowledged before _Thread_Dispatch_disable is
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* incremented and the higher priority interrupt
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* performs a context switch after executing. The lower
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* priority interrupt will execute (1) at the end of the
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* higher priority interrupt in the new context if
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* permitted by the new interrupt level mask, and (2) when
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* the original context regains the cpu.
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*/
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#if ( M68K_COLDFIRE_ARCH == 1 )
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.set SR_OFFSET, 2 | Status register offset
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.set PC_OFFSET, 4 | Program Counter offset
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@@ -142,45 +130,31 @@ SYM (_ISR_Handler):
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addql #1,SYM (_Thread_Dispatch_disable_level) | disable multitasking
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#if ( M68K_COLDFIRE_ARCH == 0 )
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moveml d0-d1/a0-a1,a7@- | save d0-d1,a0-a1
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movew a7@(SAVED+FVO_OFFSET),d0 | d0 = F/VO
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andl #0x0fff,d0 | d0 = vector offset in vbr
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#else
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lea a7@(-SAVED),a7
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movm.l d0-d1/a0-a1,a7@ | save d0-d1,a0-a1
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#endif
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movew a7@(SAVED+FVO_OFFSET),d0 | d0 = F/VO
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andl #0x0ffc,d0 | d0 = vector offset in vbr
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#endif
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#if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 )
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#if ( M68K_COLDFIRE_ARCH == 0 )
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movew sr,d1 | Save status register
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oriw #0x700,sr | Disable interrupts
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#else
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move.l d0,a7@- | Save d0 value
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move.l #0x700,d0 | Load in disable ints value
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move.w sr,d1 | Grab SR
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or.l d1,d0 | Create new SR
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move.w d0,sr | Disable interrupts
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move.l a7@+,d0 | Restore d0 value
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#endif
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tstl SYM (_ISR_Nest_level) | Interrupting an interrupt handler?
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bne 1f | Yes, just skip over stack switch code
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movel SYM(_CPU_Interrupt_stack_high),a0 | End of interrupt stack
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movel a7,a0@- | Save task stack pointer
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movel a0,a7 | Switch to interrupt stack
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movel _CPU_Interrupt_stack_high,a0 | a0 now point just above interrupt stack
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cmpl _CPU_Interrupt_stack_low,a7 | stack below interrupt stack?
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bcs.b 1f | yes, switch to interrupt stack
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cmpl a0,a7 | stack above interrupt stack?
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bcs.b 2f | no, do not switch stacks
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1:
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addql #1,SYM(_ISR_Nest_level) | one nest level deeper
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movew d1,sr | Restore status register
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#else
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addql #1,SYM (_ISR_Nest_level) | one nest level deeper
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movel a7,a1 | copy task stack pointer
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movel a0,a7 | switch to interrupt stack
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movel a1,a7@- | store task stack pointer on interrupt stack
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2:
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#endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */
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#if ( M68K_HAS_PREINDEXING == 1 )
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movel @( SYM (_ISR_Vector_table),d0:w:1),a0| fetch the ISR
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#else
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movel # SYM (_ISR_Vector_table),a0 | a0 = base of RTEMS table
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movel # SYM (_ISR_Vector_table),a0 | a0 = base of RTEMS table
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addal d0,a0 | a0 = address of vector
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movel (a0),a0 | a0 = address of user routine
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#endif
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@@ -191,45 +165,44 @@ SYM (_ISR_Handler):
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addql #4,a7 | remove vector number
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#if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 )
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#if ( M68K_COLDFIRE_ARCH == 0 )
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movew sr,d0 | Save status register
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oriw #0x700,sr | Disable interrupts
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#else
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move.l #0x700,d1 | Load in disable int value
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move.w sr,d0 | Grab SR
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or.l d0,d1 | Create new SR
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move.w d1,sr | Load to disable interrupts
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#endif
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subql #1,SYM(_ISR_Nest_level) | Reduce interrupt-nesting count
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bne 1f | Skip if return to interrupt
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movel _CPU_Interrupt_stack_high,a0
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subql #4,a0
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cmpl a0,a7 | At top of interrupt stack?
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bne.b 1f | No, do not restore task stack pointer
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movel (a7),a7 | Restore task stack pointer
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1:
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movew d0,sr | Restore status register
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#else
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subql #1,SYM (_ISR_Nest_level) | one less nest level
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#endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */
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subql #1,SYM (_Thread_Dispatch_disable_level)
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| unnest multitasking
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bne exit | If dispatch disabled, exit
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bne.b exit | If dispatch disabled, exit
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#if ( M68K_HAS_SEPARATE_STACKS == 1 )
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movew #0xf000,d0 | isolate format nibble
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andw a7@(SAVED+FVO_OFFSET),d0 | get F/VO
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cmpiw #0x1000,d0 | is it a throwaway isf?
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bne exit | NOT outer level, so branch
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bne.b exit | NOT outer level, so branch
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#else
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/*
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* If we have a CPU which allows a higher-priority interrupt to preempt a
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* lower priority handler before the lower-priority handler can increment
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* _Thread_Dispatch_disable_level then we must check the PC on the stack to
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* see if it is _ISR_Handler. If it is we have the case of nesting interrupts
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* without the dispatch level being incremented.
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*/
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#if ( M68K_COLDFIRE_ARCH == 0 && M68K_MC68060_ARCH == 0 )
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cmpl #_ISR_Handler,a7@(SAVED+PC_OFFSET)
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beq.b exit
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#endif
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#endif
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tstl SYM (_Context_Switch_necessary)
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| Is thread switch necessary?
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bne bframe | Yes, invoke dispatcher
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bne.b bframe | Yes, invoke dispatcher
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tstl SYM (_ISR_Signals_to_thread_executing)
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| signals sent to Run_thread
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| while in interrupt handler?
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beq exit | No, then exit
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beq.b exit | No, then exit
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bframe: clrl SYM (_ISR_Signals_to_thread_executing)
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| If sent, will be processed
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