forked from Imagelibrary/rtems
LIBPCI: added DRVMGR model for PCI bus
This commit is contained in:
Daniel Hellstrom
@@ -40,6 +40,11 @@ libpci_a_SOURCES += pci_get_dev.c
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libpci_a_SOURCES += pci_irq.c
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libpci_a_SOURCES += pci_print.c
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# Driver manager PCI bus
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libpci_a_SOURCES += pci_bus.c
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include_drvmgrdir = $(includedir)/drvmgr
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include_drvmgr_HEADERS = pci_bus.h
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endif
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include $(srcdir)/preinstall.am
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567
cpukit/libpci/pci_bus.c
Normal file
567
cpukit/libpci/pci_bus.c
Normal file
@@ -0,0 +1,567 @@
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/* PCI bus driver.
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*
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* COPYRIGHT (c) 2008.
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* Cobham Gaisler AB.
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*
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* General part of PCI Bus driver. The driver is typically
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* initialized from the PCI host driver separating the host
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* driver from the common parts in PCI drivers.
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* The PCI library must be initialized before starting the
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* PCI bus driver. The PCI library have set up BARs and
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* assigned system IRQs for targets.
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* This PCI bus driver rely on the PCI library (pci.c) for
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* interrupt registeration (pci_interrupt_register) and PCI
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* target set up.
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.com/license/LICENSE.
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*
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* 2008-12-03, Daniel Hellstrom <daniel@gaisler.com>
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* Created
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*
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*/
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/* Use PCI Configuration libarary pci_hb RAM device structure to find devices,
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* undefine to access PCI configuration space directly.
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*/
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#define USE_PCI_CFG_LIB
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/* On small systems undefine PCIBUS_INFO to avoid sprintf get dragged in */
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#define PCIBUS_INFO
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <pci.h>
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#ifdef USE_PCI_CFG_LIB
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#include <pci/cfg.h>
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#endif
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#include <pci/irq.h>
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#include <drvmgr/drvmgr.h>
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#include <drvmgr/pci_bus.h>
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#ifdef DEBUG
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#define DBG(args...) printk(args)
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#else
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#define DBG(args...)
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#endif
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int pcibus_bus_init1(struct drvmgr_bus *bus);
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int pcibus_unite(struct drvmgr_drv *drv, struct drvmgr_dev *dev);
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int pcibus_int_register(
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struct drvmgr_dev *dev,
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int index,
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const char *info,
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drvmgr_isr isr,
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void *arg);
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int pcibus_int_unregister(
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struct drvmgr_dev *dev,
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int index,
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drvmgr_isr isr,
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void *arg);
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int pcibus_int_clear(
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struct drvmgr_dev *dev,
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int index);
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int pcibus_freq_get(
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struct drvmgr_dev *dev,
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int options,
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unsigned int *freq_hz);
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int pcibus_get_params(struct drvmgr_dev *dev, struct drvmgr_bus_params *params);
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void pcibus_dev_info(
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struct drvmgr_dev *dev,
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void (*print_line)(void *p, char *str),
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void *p);
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struct drvmgr_bus_ops pcibus_ops = {
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.init = {
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pcibus_bus_init1,
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NULL,
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NULL,
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NULL
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},
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.remove = NULL,
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.unite = pcibus_unite,
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.int_register = pcibus_int_register,
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.int_unregister = pcibus_int_unregister,
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#if 0
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.int_enable = pcibus_int_enable,
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.int_disable = pcibus_int_disable,
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#endif
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.int_clear = pcibus_int_clear,
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.int_mask = NULL,
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.int_unmask = NULL,
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.get_params = pcibus_get_params,
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.freq_get = pcibus_freq_get,
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#ifdef PCIBUS_INFO
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.info_dev = pcibus_dev_info,
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#endif
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};
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struct drvmgr_func pcibus_funcs[] = {
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DRVMGR_FUNC(PCI_FUNC_MREG_R8, NULL),
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DRVMGR_FUNC(PCI_FUNC_MREG_R16, NULL),
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DRVMGR_FUNC(PCI_FUNC_MREG_R32, NULL),
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DRVMGR_FUNC(PCI_FUNC_MREG_W8, NULL),
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DRVMGR_FUNC(PCI_FUNC_MREG_W16, NULL),
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DRVMGR_FUNC(PCI_FUNC_MREG_W32, NULL),
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DRVMGR_FUNC_END
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};
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/* Driver resources configuration for the PCI bus. It is declared weak so that
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* the user may override it from the project file, if the default settings are
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* not enough.
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*/
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struct drvmgr_bus_res pcibus_drv_resources __attribute__((weak)) = {
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.next = NULL,
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.resource = {
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RES_EMPTY,
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},
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};
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struct pcibus_priv {
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struct drvmgr_dev *dev;
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};
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static int compatible(struct pci_dev_id *id, struct pci_dev_id_match *drv)
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{
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if (((drv->vendor==PCI_ID_ANY) || (id->vendor==drv->vendor)) &&
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((drv->device==PCI_ID_ANY) || (id->device==drv->device)) &&
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((drv->subvendor==PCI_ID_ANY) || (id->subvendor==drv->subvendor)) &&
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((drv->subdevice==PCI_ID_ANY) || (id->subdevice==drv->subdevice)) &&
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((id->class & drv->class_mask) == drv->class))
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return 1;
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else
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return 0;
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}
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int pcibus_unite(struct drvmgr_drv *drv,
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struct drvmgr_dev *dev)
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{
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struct pci_drv_info *pdrv;
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struct pci_dev_id_match *drvid;
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struct pci_dev_info *pci;
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if (!drv || !dev || !dev->parent)
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return 0;
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if ((drv->bus_type != DRVMGR_BUS_TYPE_PCI) ||
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(dev->parent->bus_type != DRVMGR_BUS_TYPE_PCI))
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return 0;
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pci = (struct pci_dev_info *)dev->businfo;
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if (!pci)
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return 0;
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pdrv = (struct pci_drv_info *)drv;
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drvid = pdrv->ids;
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if (!drvid)
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return 0;
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while (drvid->vendor != 0) {
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if (compatible(&pci->id, drvid)) {
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/* Unite device and driver */
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DBG("DRV %p and DEV %p united\n", drv, dev);
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return 1;
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}
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drvid++;
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}
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return 0;
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}
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static int pcibus_int_get(struct drvmgr_dev *dev, int index)
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{
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int irq;
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/* Relative (positive) or absolute (negative) IRQ number */
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if (index > 0) {
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/* PCI devices only have one IRQ per function */
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return -1;
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} else if (index == 0) {
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/* IRQ Index relative to Cores base IRQ */
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/* Get Base IRQ */
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irq = ((struct pci_dev_info *)dev->businfo)->irq;
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if (irq <= 0)
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return -1;
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} else {
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/* Absolute IRQ number */
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irq = -index;
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}
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return irq;
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}
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/* Use standard PCI facility to register interrupt handler */
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int pcibus_int_register(
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struct drvmgr_dev *dev,
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int index,
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const char *info,
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drvmgr_isr isr,
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void *arg)
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{
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#ifdef DEBUG
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struct drvmgr_dev *busdev = dev->parent->dev;
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#endif
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int irq;
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/* Get IRQ number from index and device information */
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irq = pcibus_int_get(dev, index);
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if (irq < 0)
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return -1;
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DBG("Register PCI interrupt on %p for dev %p (IRQ: %d)\n",
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busdev, dev, irq);
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return pci_interrupt_register(irq, info, isr, arg);
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}
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/* Use standard PCI facility to unregister interrupt handler */
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int pcibus_int_unregister(
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struct drvmgr_dev *dev,
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int index,
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drvmgr_isr isr,
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void *arg)
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{
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#ifdef DEBUG
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struct drvmgr_dev *busdev = dev->parent->dev;
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#endif
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int irq;
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/* Get IRQ number from index and device information */
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irq = pcibus_int_get(dev, index);
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if (irq < 0)
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return -1;
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DBG("Unregister PCI interrupt on %p for dev %p (IRQ: %d)\n",
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busdev, dev, irq);
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return pci_interrupt_unregister(irq, isr, arg);
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}
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/* Use standard PCI facility to clear interrupt */
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int pcibus_int_clear(
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struct drvmgr_dev *dev,
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int index)
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{
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int irq;
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/* Get IRQ number from index and device information */
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irq = pcibus_int_get(dev, index);
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if (irq < 0)
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return -1;
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pci_interrupt_clear(irq);
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return 0;
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}
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int pcibus_freq_get(
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struct drvmgr_dev *dev,
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int options,
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unsigned int *freq_hz)
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{
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/* Standard PCI Bus frequency */
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*freq_hz = 33000000;
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return 0;
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}
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int pcibus_get_params(struct drvmgr_dev *dev, struct drvmgr_bus_params *params)
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{
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/* No device prefix */
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params->dev_prefix = NULL;
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return 0;
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}
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#ifdef PCIBUS_INFO
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void pcibus_dev_info(
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struct drvmgr_dev *dev,
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void (*print_line)(void *p, char *str),
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void *p)
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{
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struct pci_dev_info *devinfo;
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struct pcibus_res *pcibusres;
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struct pci_res *res;
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char buf[64];
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int i;
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char *str1, *res_types[3] = {" IO16", "MEMIO", " MEM"};
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uint32_t pcistart;
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if (!dev)
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return;
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devinfo = (struct pci_dev_info *)dev->businfo;
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if (!devinfo)
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return;
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if ((devinfo->id.class >> 8) == PCI_CLASS_BRIDGE_PCI)
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print_line(p, "PCI BRIDGE DEVICE");
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else
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print_line(p, "PCI DEVICE");
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sprintf(buf, "LOCATION: BUS:SLOT:FUNCTION [%x:%x:%x]",
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PCI_DEV_EXPAND(devinfo->pcidev));
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print_line(p, buf);
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sprintf(buf, "PCIID 0x%lx", (uint32_t)devinfo->pcidev);
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print_line(p, buf);
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sprintf(buf, "VENDOR ID: %04x", devinfo->id.vendor);
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print_line(p, buf);
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sprintf(buf, "DEVICE ID: %04x", devinfo->id.device);
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print_line(p, buf);
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sprintf(buf, "SUBVEN ID: %04x", devinfo->id.subvendor);
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print_line(p, buf);
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sprintf(buf, "SUBDEV ID: %04x", devinfo->id.subdevice);
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print_line(p, buf);
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sprintf(buf, "CLASS: %lx", devinfo->id.class);
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print_line(p, buf);
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sprintf(buf, "REVISION: %x", devinfo->rev);
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print_line(p, buf);
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sprintf(buf, "IRQ: %d", devinfo->irq);
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print_line(p, buf);
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sprintf(buf, "PCIDEV ptr: %p", devinfo->pci_device);
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print_line(p, buf);
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/* List Resources */
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print_line(p, "RESOURCES");
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for (i = 0; i < PCIDEV_RES_CNT; i++) {
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pcibusres = &devinfo->resources[i];
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str1 = " RES";
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pcistart = -1;
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res = pcibusres->res;
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if (res && (res->flags & PCI_RES_TYPE_MASK)) {
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str1 = res_types[(res->flags & PCI_RES_TYPE_MASK) - 1];
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if (res->flags & PCI_RES_IO32)
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str1 = " IO32";
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pcistart = res->start;
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}
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if (res && (res->flags & PCI_RES_FAIL)) {
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sprintf(buf, " %s[%d]: NOT ASSIGNED", str1, i);
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print_line(p, buf);
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continue;
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}
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if (!pcibusres->size)
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continue;
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sprintf(buf, " %s[%d]: %08lx-%08lx [PCIADR %lx]",
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str1, i, pcibusres->address,
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pcibusres->address + pcibusres->size - 1, pcistart);
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print_line(p, buf);
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}
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}
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#endif
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#ifdef USE_PCI_CFG_LIB
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static int pcibus_dev_register(struct pci_dev *dev, void *arg)
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{
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struct drvmgr_bus *pcibus = arg;
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struct drvmgr_dev *newdev;
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struct pci_dev_info *pciinfo;
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int i, type;
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struct pcibus_res *pcibusres;
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struct pci_res *pcires;
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pci_dev_t pcidev = dev->busdevfun;
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DBG("PCI DEV REGISTER: %x:%x:%x\n", PCI_DEV_EXPAND(pcidev));
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/* Allocate a device */
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drvmgr_alloc_dev(&newdev, 24 + sizeof(struct pci_dev_info));
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newdev->next = NULL;
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newdev->parent = pcibus; /* Ourselfs */
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newdev->minor_drv = 0;
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newdev->minor_bus = 0;
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newdev->priv = NULL;
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newdev->drv = NULL;
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newdev->name = (char *)(newdev + 1);
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newdev->next_in_drv = NULL;
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newdev->bus = NULL;
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/* Init PnP information, Assign Core interfaces with this device */
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pciinfo = (struct pci_dev_info *)((char *)(newdev + 1) + 24);
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/* Read Device and Vendor */
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pciinfo->id.vendor = dev->vendor;
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pciinfo->id.device = dev->device;
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pciinfo->id.subvendor = dev->subvendor;
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pciinfo->id.subdevice = dev->subdevice;
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pciinfo->rev = dev->classrev & 0xff;
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pciinfo->id.class = (dev->classrev >> 8) & 0xffffff;
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/* Read IRQ information set by PCI layer */
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pciinfo->irq = dev->sysirq;
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/* Save Location on PCI bus */
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pciinfo->pcidev = pcidev;
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/* Connect device with PCI data structure */
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pciinfo->pci_device = dev;
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/* Build resources so that PCI device drivers doesn't have to scan
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* configuration space themselves, also the address is translated
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* into CPU accessible addresses.
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*/
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for (i = 0; i < PCIDEV_RES_CNT; i++) {
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pcibusres = &pciinfo->resources[i];
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pcires = &dev->resources[i];
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type = pcires->flags & PCI_RES_TYPE_MASK;
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if (type == 0 || (pcires->flags & PCI_RES_FAIL))
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continue; /* size=0 */
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pcibusres->address = pcires->start;
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if (pci_pci2cpu(&pcibusres->address, type))
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continue; /* size=0 */
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pcibusres->res = pcires;
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pcibusres->size = pcires->end - pcires->start;
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}
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/* Connect device with PCI information */
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newdev->businfo = (void *)pciinfo;
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/* Create Device Name */
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sprintf(newdev->name, "PCI_%x:%x:%x_%04x:%04x",
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PCI_DEV_BUS(pcidev), PCI_DEV_SLOT(pcidev), PCI_DEV_FUNC(pcidev),
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pciinfo->id.vendor, pciinfo->id.device);
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/* Register New Device */
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drvmgr_dev_register(newdev);
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return 0;
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}
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#else
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static int pcibus_dev_register(pci_dev_t pcidev, void *arg)
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{
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struct drvmgr_bus *pcibus = arg;
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struct drvmgr_dev *newdev;
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struct pci_dev_info *pciinfo;
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DBG("PCI DEV REGISTER: %x:%x:%x\n", PCI_DEV_EXPAND(pcidev));
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/* Allocate a device */
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drvmgr_alloc_dev(&newdev, 24 + sizeof(struct pci_dev_info));
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newdev->next = NULL;
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newdev->parent = pcibus; /* Ourselfs */
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newdev->minor_drv = 0;
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newdev->minor_bus = 0;
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newdev->priv = NULL;
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newdev->drv = NULL;
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newdev->name = (char *)(newdev + 1);
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newdev->next_in_drv = NULL;
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newdev->bus = NULL;
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/* Init PnP information, Assign Core interfaces with this device */
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pciinfo = (struct pci_dev_info *)((char *)(newdev + 1) + 24);
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/* Read Device and Vendor */
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pci_cfg_r16(pcidev, PCI_VENDOR_ID, &pciinfo->id.vendor);
|
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pci_cfg_r16(pcidev, PCI_DEVICE_ID, &pciinfo->id.device);
|
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pci_cfg_r32(pcidev, PCI_CLASS_REVISION, &pciinfo->id.class);
|
||||
pciinfo->rev = pciinfo->id.class & 0xff;
|
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pciinfo->id.class = pciinfo->id.class >> 8;
|
||||
|
||||
/* Devices have subsytem device and vendor ID */
|
||||
if ((pciinfo->id.class >> 8) != PCI_CLASS_BRIDGE_PCI) {
|
||||
pci_cfg_r16(pcidev, PCI_SUBSYSTEM_VENDOR_ID,
|
||||
&pciinfo->id.subvendor);
|
||||
pci_cfg_r16(pcidev, PCI_SUBSYSTEM_ID, &pciinfo->id.subdevice);
|
||||
} else {
|
||||
pciinfo->id.subvendor = 0;
|
||||
pciinfo->id.subdevice = 0;
|
||||
}
|
||||
|
||||
/* Read IRQ information set by PCI layer */
|
||||
pci_cfg_r8(pcidev, PCI_INTERRUPT_LINE, &pciinfo->irq);
|
||||
|
||||
/* Save Location */
|
||||
pciinfo->pcidev = pcidev;
|
||||
|
||||
/* There is no way we can know this information this way */
|
||||
pciinfo->pci_device = NULL;
|
||||
|
||||
/* Connect device with PCI information */
|
||||
newdev->businfo = (void *)pciinfo;
|
||||
|
||||
/* Create Device Name */
|
||||
sprintf(newdev->name, "PCI_%d:%d:%d_%04x:%04x",
|
||||
PCI_DEV_BUS(pcidev), PCI_DEV_SLOT(pcidev), PCI_DEV_FUNC(pcidev),
|
||||
pciinfo->id.vendor, pciinfo->id.device);
|
||||
|
||||
/* Register New Device */
|
||||
drvmgr_dev_register(newdev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/* Register all AMBA devices available on the AMBAPP bus */
|
||||
static int pcibus_devs_register(struct drvmgr_bus *bus)
|
||||
{
|
||||
/* return value 0=DRVMGR_OK works with pci_for_each/pci_for_each_dev */
|
||||
#ifdef USE_PCI_CFG_LIB
|
||||
/* Walk the PCI device tree in RAM */
|
||||
return pci_for_each_dev(pcibus_dev_register, bus);
|
||||
#else
|
||||
/* Scan PCI Configuration space */
|
||||
return pci_for_each(pcibus_dev_register, bus);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*** DEVICE FUNCTIONS ***/
|
||||
|
||||
int pcibus_register(struct drvmgr_dev *dev, struct pcibus_config *config)
|
||||
{
|
||||
struct pcibus_priv *priv;
|
||||
int i, fid, rc;
|
||||
|
||||
DBG("PCI BUS: initializing\n");
|
||||
|
||||
/* Create BUS */
|
||||
drvmgr_alloc_bus(&dev->bus, sizeof(struct pcibus_priv));
|
||||
dev->bus->bus_type = DRVMGR_BUS_TYPE_PCI;
|
||||
dev->bus->next = NULL;
|
||||
dev->bus->dev = dev;
|
||||
dev->bus->children = NULL;
|
||||
dev->bus->ops = &pcibus_ops;
|
||||
dev->bus->dev_cnt = 0;
|
||||
dev->bus->reslist = NULL;
|
||||
dev->bus->maps_up = config->maps_up;
|
||||
dev->bus->maps_down = config->maps_down;
|
||||
dev->bus->funcs = &pcibus_funcs[0];
|
||||
|
||||
/* Copy function definitions from PCI Layer */
|
||||
for (i=0; i<6; i++) {
|
||||
fid = pcibus_funcs[i].funcid;
|
||||
rc = pci_access_func(RW_DIR(fid), RW_SIZE(fid),
|
||||
&pcibus_funcs[i].func, PCI_LITTLE_ENDIAN, 3);
|
||||
if (rc != 0)
|
||||
DBG("PCI BUS: MEMREG 0x%x function not defined\n", fid);
|
||||
}
|
||||
|
||||
/* Add resource configuration if user overrided the default empty cfg */
|
||||
if (pcibus_drv_resources.resource[0].drv_id != 0)
|
||||
drvmgr_bus_res_add(dev->bus, &pcibus_drv_resources);
|
||||
|
||||
/* Init BUS private structures */
|
||||
priv = (struct pcibus_priv *)(dev->bus + 1);
|
||||
dev->bus->priv = priv;
|
||||
|
||||
/* Register BUS */
|
||||
drvmgr_bus_register(dev->bus);
|
||||
|
||||
return DRVMGR_OK;
|
||||
}
|
||||
|
||||
/*** BUS INITIALIZE FUNCTIONS ***/
|
||||
|
||||
int pcibus_bus_init1(struct drvmgr_bus *bus)
|
||||
{
|
||||
return pcibus_devs_register(bus);
|
||||
}
|
||||
159
cpukit/libpci/pci_bus.h
Normal file
159
cpukit/libpci/pci_bus.h
Normal file
@@ -0,0 +1,159 @@
|
||||
/* PCI bus driver Interface.
|
||||
*
|
||||
* COPYRIGHT (c) 2008.
|
||||
* Cobham Gaisler AB.
|
||||
*
|
||||
* General part of PCI Bus driver. The driver is typically
|
||||
* initialized from the PCI host driver separating the host
|
||||
* driver from the common parts in PCI drivers.
|
||||
* The PCI library must be initialized before starting the
|
||||
* PCI bus driver. The PCI library have set up BARs and
|
||||
* assigned system IRQs for targets.
|
||||
* This PCI bus driver rely on the PCI library (pci.c) for
|
||||
* interrupt registeration (pci_interrupt_register) and PCI
|
||||
* target set up.
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.com/license/LICENSE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __PCI_BUS_H__
|
||||
#define __PCI_BUS_H__
|
||||
|
||||
#include <drvmgr/drvmgr.h>
|
||||
#include <pci.h>
|
||||
#include <pci/access.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* PCI Driver ID generation (VENDOR: 16-bit, DEVICE: 16-bit) */
|
||||
#define DRIVER_PCI_ID(vendor, device) \
|
||||
DRIVER_ID(DRVMGR_BUS_TYPE_PCI, \
|
||||
((((vendor) & 0xffff) << 16) | ((device) & 0xffff)))
|
||||
|
||||
/* PCI Driver ID generation (CLASS: 24-bit) */
|
||||
#define DRIVER_PCI_CLASS(class) \
|
||||
DRIVER_ID(DRVMGR_BUS_TYPE_PCI, ((1 << 32) | ((class) & 0xffffff)))
|
||||
|
||||
/* PCI driver IDs (DRIVER_PCI_VENDOR_DEVICE or DRIVER_PCI_CLASS_NAME) */
|
||||
#define DRIVER_PCI_GAISLER_RASTAIO_ID DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_RASTA_IO)
|
||||
#define DRIVER_PCI_GAISLER_RASTATMTC_ID DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_RASTA_TMTC)
|
||||
#define DRIVER_PCI_GAISLER_GR701_ID DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_701)
|
||||
#define DRIVER_PCI_GAISLER_RASTAADCDAC_ID DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_RASTA_ADCDAC)
|
||||
#define DRIVER_PCI_GAISLER_TMTC_1553_ID DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_TMTC_1553)
|
||||
#define DRIVER_PCI_GAISLER_RASTA_SPW_ROUTER_ID DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_RASTA_SPW_RTR)
|
||||
|
||||
struct pci_dev_id {
|
||||
uint16_t vendor;
|
||||
uint16_t device;
|
||||
uint16_t subvendor;
|
||||
uint16_t subdevice;
|
||||
uint32_t class; /* 24 lower bits */
|
||||
};
|
||||
|
||||
struct pci_dev_id_match {
|
||||
uint16_t vendor;
|
||||
uint16_t device;
|
||||
uint16_t subvendor;
|
||||
uint16_t subdevice;
|
||||
uint32_t class; /* 24 lower bits */
|
||||
uint32_t class_mask; /* 24 lower bits */
|
||||
};
|
||||
#define PCIID_DEVVEND(vendor, device) \
|
||||
{vendor, device, PCI_ID_ANY, PCI_ID_ANY, 0, 0}
|
||||
#define PCIID_END_TABLE {0, 0, 0, 0, 0, 0}
|
||||
|
||||
enum {
|
||||
/* A Device has up to 6 BARs and an optional ROM BAR */
|
||||
PCIDEV_RES_BAR1 = 0,
|
||||
PCIDEV_RES_BAR2 = 1,
|
||||
PCIDEV_RES_BAR3 = 2,
|
||||
PCIDEV_RES_BAR4 = 3,
|
||||
PCIDEV_RES_BAR5 = 4,
|
||||
PCIDEV_RES_BAR6 = 5,
|
||||
PCIDEV_RES_ROM = 6,
|
||||
};
|
||||
/* Maximum Number of Resources of a device */
|
||||
#define PCIDEV_RES_CNT (PCIDEV_RES_ROM + 1)
|
||||
|
||||
/* IO, MEMIO or MEM resource. Can be BAR, ROM or Bridge Window */
|
||||
struct pcibus_res {
|
||||
uint32_t address; /* Base Address, CPU accessible */
|
||||
uint32_t size; /* 0=Unimplemented, 0!=Resource Size */
|
||||
struct pci_res *res; /* PCI-layer resource */
|
||||
};
|
||||
|
||||
struct pci_dev_info {
|
||||
struct pci_dev_id id;
|
||||
uint8_t rev;
|
||||
uint8_t irq; /* 0 = NO IRQ */
|
||||
pci_dev_t pcidev;
|
||||
struct pcibus_res resources[PCIDEV_RES_CNT];
|
||||
struct pci_dev *pci_device;
|
||||
};
|
||||
|
||||
struct pci_drv_info {
|
||||
struct drvmgr_drv general; /* General bus info */
|
||||
/* PCI specific bus information */
|
||||
struct pci_dev_id_match *ids; /* Supported hardware */
|
||||
};
|
||||
|
||||
/* Access routines */
|
||||
struct pcibus_regmem_ops {
|
||||
drvmgr_r8 r8;
|
||||
drvmgr_r16 r16;
|
||||
drvmgr_r32 r32;
|
||||
drvmgr_r64 r64;
|
||||
drvmgr_w8 w8;
|
||||
drvmgr_w16 w16;
|
||||
drvmgr_w32 w32;
|
||||
drvmgr_w64 w64;
|
||||
};
|
||||
|
||||
/* Let driver configure PCI bus driver */
|
||||
struct pcibus_config {
|
||||
struct drvmgr_map_entry *maps_up;
|
||||
struct drvmgr_map_entry *maps_down;
|
||||
};
|
||||
|
||||
/* PCI Configuration Space Access - Not implemented (use PCI Lib directly) */
|
||||
#define PCI_FUNC_CFG_R8 DRVMGR_RWFUNC(RW_SIZE_1|RW_READ|RW_CFG)
|
||||
#define PCI_FUNC_CFG_R16 DRVMGR_RWFUNC(RW_SIZE_2|RW_READ|RW_CFG)
|
||||
#define PCI_FUNC_CFG_R32 DRVMGR_RWFUNC(RW_SIZE_4|RW_READ|RW_CFG)
|
||||
#define PCI_FUNC_CFG_W8 DRVMGR_RWFUNC(RW_SIZE_1|RW_WRITE|RW_CFG)
|
||||
#define PCI_FUNC_CFG_W16 DRVMGR_RWFUNC(RW_SIZE_2|RW_WRITE|RW_CFG)
|
||||
#define PCI_FUNC_CFG_W32 DRVMGR_RWFUNC(RW_SIZE_4|RW_WRITE|RW_CFG)
|
||||
|
||||
/* PCI I/O Register Access - Not implemented (use PCI Lib directly) */
|
||||
#define PCI_FUNC_IO_R8 DRVMGR_RWFUNC(RW_SIZE_1|RW_READ|RW_IO)
|
||||
#define PCI_FUNC_IO_R16 DRVMGR_RWFUNC(RW_SIZE_2|RW_READ|RW_IO)
|
||||
#define PCI_FUNC_IO_R32 DRVMGR_RWFUNC(RW_SIZE_4|RW_READ|RW_IO)
|
||||
#define PCI_FUNC_IO_W8 DRVMGR_RWFUNC(RW_SIZE_1|RW_WRITE|RW_IO)
|
||||
#define PCI_FUNC_IO_W16 DRVMGR_RWFUNC(RW_SIZE_2|RW_WRITE|RW_IO)
|
||||
#define PCI_FUNC_IO_W32 DRVMGR_RWFUNC(RW_SIZE_4|RW_WRITE|RW_IO)
|
||||
|
||||
/* PCI Register Access over Memory Space (Little Endian) */
|
||||
#define PCI_FUNC_MREG_R8 DRVMGR_RWFUNC(RW_SIZE_1|RW_READ|RW_MEMREG)
|
||||
#define PCI_FUNC_MREG_R16 DRVMGR_RWFUNC(RW_SIZE_2|RW_READ|RW_MEMREG|RW_LITTLE)
|
||||
#define PCI_FUNC_MREG_R32 DRVMGR_RWFUNC(RW_SIZE_4|RW_READ|RW_MEMREG|RW_LITTLE)
|
||||
#define PCI_FUNC_MREG_W8 DRVMGR_RWFUNC(RW_SIZE_1|RW_WRITE|RW_MEMREG)
|
||||
#define PCI_FUNC_MREG_W16 DRVMGR_RWFUNC(RW_SIZE_2|RW_WRITE|RW_MEMREG|RW_LITTLE)
|
||||
#define PCI_FUNC_MREG_W32 DRVMGR_RWFUNC(RW_SIZE_4|RW_WRITE|RW_MEMREG|RW_LITTLE)
|
||||
|
||||
/* Weak default PCI driver resources, override this from project configuration
|
||||
* to set PCI Bus resources used to configure PCI device drivers.
|
||||
*/
|
||||
extern struct drvmgr_bus_res pcibus_drv_resources;
|
||||
|
||||
/* Attach a PCI bus on top of a PCI Host device */
|
||||
extern int pcibus_register(struct drvmgr_dev *dev, struct pcibus_config *cfg);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -63,4 +63,13 @@ PREINSTALL_FILES += $(PROJECT_INCLUDE)/pci/ids_extra.h
|
||||
$(PROJECT_INCLUDE)/pci/irq.h: pci/irq.h $(PROJECT_INCLUDE)/pci/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/pci/irq.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/pci/irq.h
|
||||
|
||||
$(PROJECT_INCLUDE)/drvmgr/$(dirstamp):
|
||||
@$(MKDIR_P) $(PROJECT_INCLUDE)/drvmgr
|
||||
@: > $(PROJECT_INCLUDE)/drvmgr/$(dirstamp)
|
||||
PREINSTALL_DIRS += $(PROJECT_INCLUDE)/drvmgr/$(dirstamp)
|
||||
|
||||
$(PROJECT_INCLUDE)/drvmgr/pci_bus.h: pci_bus.h $(PROJECT_INCLUDE)/drvmgr/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/drvmgr/pci_bus.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/drvmgr/pci_bus.h
|
||||
endif
|
||||
|
||||
Reference in New Issue
Block a user