forked from Imagelibrary/rtems
Patch from Eric Valette <valette@crf.canon.fr> and Yacine El Kolli
<elkolli@crf.canon.fr> to add support for the mbx860_005b.
This commit is contained in:
@@ -991,7 +991,7 @@ rtems_configuration_table Configuration = {
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(CONFIGURE_MAXIMUM_POSIX_THREADS == 0) && \
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(CONFIGURE_MAXIMUM_ADA_TASKS == 0) && \
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(CONFIGURE_MAXIMUM_ITRON_TASKS == 0)
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#error "CONFIGURATION ERROR: No tasks or threads configured!!
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#error "CONFIGURATION ERROR: No tasks or threads configured!!"
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#endif
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/*
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@@ -1002,7 +1002,7 @@ rtems_configuration_table Configuration = {
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#if !defined(CONFIGURE_RTEMS_INIT_TASKS_TABLE) && \
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!defined(CONFIGURE_POSIX_INIT_THREAD_TABLE) && \
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!defined(CONFIGURE_ITRON_INIT_TASK_TABLE)
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#error "CONFIGURATION ERROR: No initialization tasks or threads configured!!
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#error "CONFIGURATION ERROR: No initialization tasks or threads configured!!"
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#endif
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#endif
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@@ -274,12 +274,33 @@ void _InitMBX8xx (void)
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m8xx.plprck = M8xx_UNLOCK_KEY; /* unlock PLPRCR */
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#if ( defined(mbx821_001) || defined(mbx821_001b) || defined(mbx860_001b) )
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m8xx.plprcr = 0x5F500000;
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#else
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#elif ( defined(mbx860_005b) )
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/* Set the multiplication factor to 0 and clear the timer interrupt status*/
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m8xx.plprcr = 0x00005000;
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#elif ( defined(mbx860_001) || \
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defined(mbx860_002) || \
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defined(mbx860_003) || \
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defined(mbx860_004) || \
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defined(mbx860_005) || \
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defined(mbx860_002b) || \
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defined(mbx860_003b) || \
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defined(mbx860_004b) || \
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defined(mbx860_006b) || \
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defined(mbx821_002) || \
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defined(mbx821_003) || \
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defined(mbx821_004) || \
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defined(mbx821_005) || \
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defined(mbx821_002b) || \
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defined(mbx821_003b) || \
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defined(mbx821_004b) || \
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defined(mbx821_005b) )
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defined(mbx821_006b) )
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m8xx.plprcr = 0x4C400000;
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#else
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#error "MBX board not defined"
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#endif
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/* Unlock the timebase and decrementer registers. */
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m8xx.tbk = M8xx_UNLOCK_KEY;
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/*
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* Initialize decrementer register to a large value to
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* guarantee that a decrementer interrupt will not be
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@@ -458,8 +479,37 @@ void _InitMBX8xx (void)
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* m8xx.memc[1]._or = 0xFFC00400;
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* m8xx.memc[1]._br = 0x00000081;
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*/
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m8xx.memc[1]._or = M8xx_MEMC_OR_4M | M8xx_MEMC_OR_ATM(0) |
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M8xx_MEMC_OR_ACS_QRTR | M8xx_MEMC_OR_SCY(0);
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#if ( defined(mbx860_001b) )
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m8xx.memc[1]._or = M8xx_MEMC_OR_2M | M8xx_MEMC_OR_ATM(0) |
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M8xx_MEMC_OR_ACS_QRTR | M8xx_MEMC_OR_SCY(0);
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#elif ( defined(mbx860_002b) || \
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defined(mbx860_003b) || \
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defined(mbx821_001b) || \
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defined(mbx821_002b) || \
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defined(mbx821_003b) || \
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defined(mbx860_001) || \
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defined(mbx860_002) || \
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defined(mbx860_003) || \
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defined(mbx821_001) || \
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defined(mbx821_002) || \
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defined(mbx821_003) )
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m8xx.memc[1]._or = M8xx_MEMC_OR_4M | M8xx_MEMC_OR_ATM(0) |
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M8xx_MEMC_OR_ACS_QRTR | M8xx_MEMC_OR_SCY(0);
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#elif ( defined(mbx860_004) || \
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defined(mbx860_005) || \
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defined(mbx860_004b) || \
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defined(mbx860_005b) || \
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defined(mbx860_006b) || \
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defined(mbx821_004) || \
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defined(mbx821_005) || \
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defined(mbx821_004b) || \
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defined(mbx821_005b) || \
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defined(mbx821_006b) )
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m8xx.memc[1]._or = M8xx_MEMC_OR_16M | M8xx_MEMC_OR_ATM(0) |
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M8xx_MEMC_OR_ACS_QRTR | M8xx_MEMC_OR_SCY(0);
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#else
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#error "MBX board not defined"
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#endif
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m8xx.memc[1]._br = M8xx_BR_BA(0x00000000) | M8xx_BR_AT(0) | M8xx_BR_PS32 |
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M8xx_BR_MS_UPMA | M8xx_MEMC_BR_V;
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@@ -31,21 +31,65 @@
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* location is equal to its real address.
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*/
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MMU_TLB_table_t MMU_TLB_table[] = {
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/*
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#if ( defined(mbx860_001b) )
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/*
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* DRAM: CS1, Start address 0x00000000, 2M,
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* ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy,
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* R/W,X for all, no ASID comparison, not cache-inhibited.
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* Last 512K block is cache-inhibited, but not guarded for use by EPPCBug.
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* EPN TWC RPN
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*/
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{ 0x00000200, 0x05, 0x000009FD }, /* DRAM - PS=512K */
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{ 0x00080200, 0x05, 0x000809FD }, /* DRAM - PS=512K */
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{ 0x00100200, 0x05, 0x001009FD }, /* DRAM - PS=512K */
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{ 0x00180200, 0x05, 0x001809FF }, /* DRAM - PS=512K, cache-inhibited */
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#elif ( defined(mbx860_002b) || \
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defined(mbx860_003b) || \
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defined(mbx821_001b) || \
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defined(mbx821_002b) || \
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defined(mbx821_003b) || \
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defined(mbx860_001) || \
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defined(mbx860_002) || \
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defined(mbx860_003) || \
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defined(mbx821_001) || \
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defined(mbx821_002) || \
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defined(mbx821_003) )
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/*
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* DRAM: CS1, Start address 0x00000000, 4M,
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* ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy,
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* R/W,X for all, no ASID comparison, not cache-inhibited.
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* Last 512K block is cache-inhibited, but not guarded for use by EPPCBug.
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* EPN TWC RPN
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*/
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{ 0x00000200, 0x05, 0x000009FD }, /* DRAM - PS=512K */
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{ 0x00080200, 0x05, 0x000809FD }, /* DRAM - PS=512K */
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{ 0x00100200, 0x05, 0x001009FD }, /* DRAM - PS=512K */
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{ 0x00180200, 0x05, 0x001809FD }, /* DRAM - PS=512K */
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{ 0x00200200, 0x05, 0x002009FD }, /* DRAM - PS=512K */
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{ 0x00280200, 0x05, 0x002809FD }, /* DRAM - PS=512K */
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{ 0x00300200, 0x05, 0x003009FD }, /* DRAM - PS=512K */
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{ 0x00380200, 0x05, 0x003809FF }, /* DRAM - PS=512K, cache-inhibited */
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{ 0x00000200, 0x05, 0x000009FD }, /* DRAM - PS=512K */
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{ 0x00080200, 0x05, 0x000809FD }, /* DRAM - PS=512K */
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{ 0x00100200, 0x05, 0x001009FD }, /* DRAM - PS=512K */
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{ 0x00180200, 0x05, 0x001809FD }, /* DRAM - PS=512K */
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{ 0x00200200, 0x05, 0x002009FD }, /* DRAM - PS=512K */
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{ 0x00280200, 0x05, 0x002809FD }, /* DRAM - PS=512K */
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{ 0x00300200, 0x05, 0x003009FD }, /* DRAM - PS=512K */
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{ 0x00380200, 0x05, 0x003809FF }, /* DRAM - PS=512K, cache-inhibited */
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#elif ( defined(mbx860_004) || \
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defined(mbx860_005) || \
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defined(mbx860_004b) || \
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defined(mbx860_005b) || \
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defined(mbx860_006b) || \
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defined(mbx821_004) || \
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defined(mbx821_005) || \
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defined(mbx821_004b) || \
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defined(mbx821_005b) || \
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defined(mbx821_006b) )
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/*
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* DRAM: CS1, Start address 0x00000000, 16M,
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* ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy,
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* R/W,X for all, no ASID comparison, not cache-inhibited.
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* EPN TWC RPN
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*/
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{ 0x00000200, 0x0D, 0x000009FD }, /* DRAM - PS=8M */
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{ 0x00800200, 0x0D, 0x008009FD }, /* DRAM - PS=8M */
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#else
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#error "MBX board not defined"
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#endif
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/*
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*
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* NVRAM: CS4, Start address 0xFA000000, 32K,
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@@ -991,7 +991,7 @@ rtems_configuration_table Configuration = {
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(CONFIGURE_MAXIMUM_POSIX_THREADS == 0) && \
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(CONFIGURE_MAXIMUM_ADA_TASKS == 0) && \
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(CONFIGURE_MAXIMUM_ITRON_TASKS == 0)
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#error "CONFIGURATION ERROR: No tasks or threads configured!!
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#error "CONFIGURATION ERROR: No tasks or threads configured!!"
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#endif
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/*
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@@ -1002,7 +1002,7 @@ rtems_configuration_table Configuration = {
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#if !defined(CONFIGURE_RTEMS_INIT_TASKS_TABLE) && \
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!defined(CONFIGURE_POSIX_INIT_THREAD_TABLE) && \
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!defined(CONFIGURE_ITRON_INIT_TASK_TABLE)
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#error "CONFIGURATION ERROR: No initialization tasks or threads configured!!
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#error "CONFIGURATION ERROR: No initialization tasks or threads configured!!"
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#endif
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#endif
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38
make/custom/mbx860_005b.cfg
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38
make/custom/mbx860_005b.cfg
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@@ -0,0 +1,38 @@
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#
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# Config file for a PowerPC MPC860-based MBX860-005b card.
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#
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#
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# All MBX8xx configurations share the same base file, only a few
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# parameters differ.
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#
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RTEMS_MBX_MODEL=mbx860_005b
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# The 860_005b has 16M ram : org = 0x0, l = 16M
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MBX8xx_LDFLAGS=-Wl,--defsym -Wl,HeapSize=0x100000
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include $(RTEMS_ROOT)/make/custom/mbx8xx.cfg
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define make-target-options
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@echo "#ifdef mpc$(CPU_TYPE)" >>$@
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@echo "#undef mpc$(CPU_TYPE)" >>$@
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@echo "#endif" >>$@
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@echo "#define mpc$(CPU_TYPE) 1" >>$@
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@echo >>$@
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@echo "#define CONSOLE_MINOR SMC1_MINOR" >>$@
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@echo "#define UARTS_USE_INTERRUPTS 0" >>$@
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@echo "#define EPPCBUG_SMC1 1" >>$@
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@echo "#define EPPCBUG_VECTORS 1" >>$@
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@echo "#define INSTRUCTION_CACHE_ENABLE 1" >>$@
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@echo "#define DATA_CACHE_ENABLE 1" >>$@
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@echo >>$@
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@echo "#define PPC_VECTOR_FILE_BASE 0x0000" >>$@
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@echo "#define PPC_USE_SPRG 0" >>$@
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@echo "/* #define PPC_USE_DATA_CACHE 1" */ >>$@
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@echo >>$@
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@echo "/* #define NDEBUG 1 */ " >>$@
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@echo "#define RTEMS_TEST_NO_PAUSE 1" >>$@
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@echo "/* #define STACK_CHECKER_ON 1 */" >>$@
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@echo "/* #define STACK_CHECKER_REPORT_USAGE 1 */" >>$@
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@echo "/* #define RTEMS_DEBUG 1 */" >>$@
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endef
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@@ -181,8 +181,8 @@ define make-exe
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endef
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else
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define make-exe
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$(LINK.c) $(AM_CFLAGS) $(AM_LDFLAGS) -o $(basename $@).exe \
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$(LINK_OBJS) $(LINK_LIBS)
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$(LINK.c) $(AM_CFLAGS) $(AM_LDFLAGS) $(MBX8xx_LDFLAGS) \
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-o $(basename $@).exe $(LINK_OBJS) $(LINK_LIBS)
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$(NM) -g -n $@ > $(basename $@).nm
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$(STRIP) -o $(basename $@) $@
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$(SIZE) $@
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