RTOS/rtems
1
0
Fork 0
forked from Imagelibrary/rtems
Code Pull Requests Activity

aarch64: Use page table level 0

Browse Source 
This alters the AArch64 page table generation and mapping code and MMU
configuration to use page table level 0 in addition to levels 1, 2, and
3. This allows the mapping of up to 48 bits of memory space and is the
maximum that can be mapped without relying on additional processor
extensions. Mappings are restricted based on the number of physical
address bits that the CPU supports.
This commit is contained in:
Kinsey Moore
2022-07-14 18:10:45 -05:00
committed by Joel Sherrill
parent 6d4b390f99
commit 10ef7087f6
4 changed files with 58 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
bsps/include/bsp/fatal.h
View File

@@ -72,6 +72,7 @@ typedef enum {
BSP_FATAL_CONSOLE_INSTALL_0,
BSP_FATAL_CONSOLE_INSTALL_1,
BSP_FATAL_CONSOLE_REGISTER_DEV_2,
BSP_FATAL_MMU_ADDRESS_INVALID,
/* ARM fatal codes */
BSP_ARM_A9MPCORE_FATAL_CLOCK_IRQ_INSTALL = BSP_FATAL_CODE_BLOCK(1),