forked from Imagelibrary/rtems
2007-11-30 Till Straumann <strauman@slac.stanford.edu>
* irq/irq.h, irq/irq.c (removed), irq/no_pic.c (added), irq/irq_init.c, Makefile.am: The PSIM BSP (currently) has no support for an interrupt controller or interrupts other than the decrementer. Removed all definitions for PCI + ISA interrupts and all unnecessary code (leftovers from copying). Separated PIC-specific bits into 'no_pic.c' which allows us to use 'irq.c' (i.e., more code) from 'shared'.
This commit is contained in:
Till Straumann
@@ -1,3 +1,12 @@
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2007-11-30 Till Straumann <strauman@slac.stanford.edu>
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* irq/irq.h, irq/irq.c (removed), irq/no_pic.c (added),
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irq/irq_init.c, Makefile.am: The PSIM BSP (currently)
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has no support for an interrupt controller or interrupts
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other than the decrementer. Removed all definitions for PCI + ISA
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interrupts and all unnecessary code (leftovers from copying).
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Separated PIC-specific bits into 'no_pic.c' which allows us
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to use 'irq.c' (i.e., more code) from 'shared'.
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2007-11-30 Till Straumann <strauman@slac.stanford.edu>
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2007-11-30 Till Straumann <strauman@slac.stanford.edu>
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* startup/linkcmds.c, start/start.S: call __eabi() from start.S
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* startup/linkcmds.c, start/start.S: call __eabi() from start.S
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@@ -65,7 +65,7 @@ consoleio_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
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include_bsp_HEADERS = irq/irq.h
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include_bsp_HEADERS = irq/irq.h
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noinst_PROGRAMS += irq.rel
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noinst_PROGRAMS += irq.rel
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irq_rel_SOURCES = irq/irq.c irq/irq_init.c ../shared/irq/irq_asm.S
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irq_rel_SOURCES = ../shared/irq/irq.c irq/irq_init.c ../shared/irq/irq_asm.S irq/no_pic.c
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irq_rel_CPPFLAGS = $(AM_CPPFLAGS)
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irq_rel_CPPFLAGS = $(AM_CPPFLAGS)
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irq_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
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irq_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
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@@ -1,338 +0,0 @@
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/*
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*
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* This file contains the implementation of the function described in irq.h
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*
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* Copyright (C) 1998, 1999 valette@crf.canon.fr
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*
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* The license and distribution terms for this file may be
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* found in found in the file LICENSE in this distribution or at
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* http://www.rtems.com/license/LICENSE.
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*
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* irq.c,v 1.4.2.8 2003/09/04 18:45:20 joel Exp
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*/
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#include <rtems/system.h>
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#include <bsp.h>
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#include <bsp/irq.h>
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#if 0
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#include <bsp/VME.h>
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#include <bsp/openpic.h>
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#endif
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#include <stdlib.h>
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#include <rtems/score/thread.h>
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#include <rtems/score/apiext.h>
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#include <libcpu/raw_exception.h>
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#include <libcpu/io.h>
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#include <bsp/vectors.h>
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#include <rtems/bspIo.h> /* for printk */
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#define RAVEN_INTR_ACK_REG 0xfeff0030
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/*
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* pointer to the mask representing the additionnal irq vectors
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* that must be disabled when a particular entry is activated.
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* They will be dynamically computed from teh prioruty table given
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* in BSP_rtems_irq_mngt_set();
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* CAUTION : this table is accessed directly by interrupt routine
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* prologue.
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*/
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rtems_i8259_masks irq_mask_or_tbl[BSP_IRQ_NUMBER];
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/*
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* default handler connected on each irq after bsp initialization
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*/
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static rtems_irq_connect_data default_rtems_entry;
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/*
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* location used to store initial tables used for interrupt
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* management.
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*/
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static rtems_irq_global_settings* internal_config;
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static rtems_irq_connect_data* rtems_hdl_tbl;
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/*
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* Check if IRQ is an ISA IRQ
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*/
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static inline int is_isa_irq(const rtems_irq_number irqLine)
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{
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return (((int) irqLine <= BSP_ISA_IRQ_MAX_OFFSET) &
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((int) irqLine >= BSP_ISA_IRQ_LOWEST_OFFSET)
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);
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}
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/*
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* Check if IRQ is an OPENPIC IRQ
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*/
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static inline int is_pci_irq(const rtems_irq_number irqLine)
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{
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return (((int) irqLine <= BSP_PCI_IRQ_MAX_OFFSET) &
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((int) irqLine >= BSP_PCI_IRQ_LOWEST_OFFSET)
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);
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}
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/*
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* Check if IRQ is a Porcessor IRQ
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*/
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static inline int is_processor_irq(const rtems_irq_number irqLine)
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{
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return (((int) irqLine <= BSP_PROCESSOR_IRQ_MAX_OFFSET) &
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((int) irqLine >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
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);
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}
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/*
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* ------------------------ RTEMS Irq helper functions ----------------
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*/
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/*
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* This function check that the value given for the irq line
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* is valid.
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*/
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static int isValidInterrupt(int irq)
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{
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if ( (irq < BSP_LOWEST_OFFSET) || (irq > BSP_MAX_OFFSET))
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return 0;
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return 1;
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}
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/*
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* ------------------------ RTEMS Shared Irq Handler Mngt Routines ----------------
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*/
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int BSP_install_rtems_shared_irq_handler (const rtems_irq_connect_data* irq)
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{
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printk("BSP_insall_rtems_shared_irq_handler Not supported in psim\n");
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return 0;
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}
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/*
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* ------------------------ RTEMS Single Irq Handler Mngt Routines ----------------
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*/
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int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq)
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{
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rtems_interrupt_level level;
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if (!isValidInterrupt(irq->name)) {
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printk("Invalid interrupt vector %d\n",irq->name);
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return 0;
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}
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/*
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* Check if default handler is actually connected. If not issue an error.
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* You must first get the current handler via i386_get_current_idt_entry
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* and then disconnect it using i386_delete_idt_entry.
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* RATIONALE : to always have the same transition by forcing the user
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* to get the previous handler before accepting to disconnect.
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*/
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rtems_interrupt_disable(level);
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if (rtems_hdl_tbl[irq->name].hdl != default_rtems_entry.hdl) {
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rtems_interrupt_enable(level);
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printk("IRQ vector %d already connected\n",irq->name);
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return 0;
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}
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/*
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* store the data provided by user
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*/
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rtems_hdl_tbl[irq->name] = *irq;
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rtems_hdl_tbl[irq->name].next_handler = (void *)-1;
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if (is_isa_irq(irq->name)) {
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printk("What's a isa_irq on psim?");
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}
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if (is_processor_irq(irq->name)) {
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/*
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* Enable exception at processor level
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*/
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}
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/*
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* Enable interrupt on device
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*/
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if (irq->on)
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irq->on(irq);
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rtems_interrupt_enable(level);
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return 1;
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}
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int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* irq)
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{
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rtems_interrupt_level level;
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if (!isValidInterrupt(irq->name)) {
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return 0;
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}
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rtems_interrupt_disable(level);
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*irq = rtems_hdl_tbl[irq->name];
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rtems_interrupt_enable(level);
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return 1;
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}
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int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq)
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{
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rtems_irq_connect_data *pchain= NULL, *vchain = NULL;
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rtems_interrupt_level level;
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if (!isValidInterrupt(irq->name)) {
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return 0;
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}
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/*
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* Check if default handler is actually connected. If not issue an error.
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* You must first get the current handler via i386_get_current_idt_entry
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* and then disconnect it using i386_delete_idt_entry.
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* RATIONALE : to always have the same transition by forcing the user
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* to get the previous handler before accepting to disconnect.
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*/
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rtems_interrupt_disable(level);
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if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) {
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rtems_interrupt_enable(level);
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return 0;
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}
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if( (int)rtems_hdl_tbl[irq->name].next_handler != -1 )
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{
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int found = 0;
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for( (pchain= NULL, vchain = &rtems_hdl_tbl[irq->name]);
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(vchain->hdl != default_rtems_entry.hdl);
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(pchain= vchain, vchain = (rtems_irq_connect_data*)vchain->next_handler) )
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{
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if( vchain->hdl == irq->hdl )
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{
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found= -1; break;
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}
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}
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if( !found )
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{
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rtems_interrupt_enable(level);
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return 0;
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}
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}
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else
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{
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if (rtems_hdl_tbl[irq->name].hdl != irq->hdl)
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{
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rtems_interrupt_enable(level);
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return 0;
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}
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}
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if (is_isa_irq(irq->name)) {
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printk("isa irq on psim?");
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}
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if (is_processor_irq(irq->name)) {
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/*
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* disable exception at processor level
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*/
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}
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/*
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* Disable interrupt on device
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*/
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if (irq->off)
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irq->off(irq);
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/*
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* restore the default irq value
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*/
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if( !vchain )
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{
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/* single handler vector... */
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rtems_hdl_tbl[irq->name] = default_rtems_entry;
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}
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else
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{
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if( pchain )
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{
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/* non-first handler being removed */
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pchain->next_handler = vchain->next_handler;
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}
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else
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{
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/* first handler isn't malloc'ed, so just overwrite it. Since
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the contents of vchain are being struct copied, vchain itself
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goes away */
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rtems_hdl_tbl[irq->name]= *vchain;
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}
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free(vchain);
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}
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rtems_interrupt_enable(level);
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|
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return 1;
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|
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}
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||||||
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|
||||||
/*
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|
||||||
* ------------------------ RTEMS Global Irq Handler Mngt Routines ----------------
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|
||||||
*/
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|
||||||
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|
||||||
int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)
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|
||||||
{
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|
||||||
/*
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|
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* Store various code accelerators
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|
||||||
*/
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|
||||||
internal_config = config;
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|
||||||
default_rtems_entry = config->defaultEntry;
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|
||||||
rtems_hdl_tbl = config->irqHdlTbl;
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|
||||||
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|
||||||
return 1;
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|
||||||
}
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|
||||||
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|
||||||
int BSP_rtems_irq_mngt_get(rtems_irq_global_settings** config)
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|
||||||
{
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|
||||||
*config = internal_config;
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|
||||||
return 0;
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|
||||||
}
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|
||||||
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|
||||||
int _BSP_vme_bridge_irq = -1;
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|
||||||
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|
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unsigned BSP_spuriousIntr = 0;
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|
||||||
|
|
||||||
/*
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|
||||||
* High level IRQ handler called from shared_raw_irq_code_entry
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|
||||||
*/
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|
||||||
void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
|
|
||||||
{
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|
||||||
register unsigned msr;
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|
||||||
register unsigned new_msr;
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|
||||||
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|
||||||
if (excNum == ASM_DEC_VECTOR) {
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|
||||||
_CPU_MSR_GET(msr);
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|
||||||
new_msr = msr | MSR_EE;
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|
||||||
_CPU_MSR_SET(new_msr);
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|
||||||
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|
||||||
rtems_hdl_tbl[BSP_DECREMENTER].hdl(rtems_hdl_tbl[BSP_DECREMENTER].handle);
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|
||||||
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|
||||||
_CPU_MSR_SET(msr);
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|
||||||
return;
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|
||||||
|
|
||||||
}
|
|
||||||
}
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|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx)
|
|
||||||
{
|
|
||||||
/*
|
|
||||||
* Process pending signals that have not already been
|
|
||||||
* processed by _Thread_Displatch. This happens quite
|
|
||||||
* unfrequently : the ISR must have posted an action
|
|
||||||
* to the current running thread.
|
|
||||||
*/
|
|
||||||
if ( _Thread_Do_post_task_switch_extension ||
|
|
||||||
_Thread_Executing->do_post_task_switch_extension ) {
|
|
||||||
_Thread_Executing->do_post_task_switch_extension = FALSE;
|
|
||||||
_API_extensions_Run_postswitch();
|
|
||||||
}
|
|
||||||
/*
|
|
||||||
* I plan to process other thread related events here.
|
|
||||||
* This will include DEBUG session requested from keyboard...
|
|
||||||
*/
|
|
||||||
}
|
|
||||||
@@ -24,40 +24,7 @@
|
|||||||
#define BSP_SHARED_HANDLER_SUPPORT 1
|
#define BSP_SHARED_HANDLER_SUPPORT 1
|
||||||
#include <rtems/irq.h>
|
#include <rtems/irq.h>
|
||||||
|
|
||||||
/*
|
|
||||||
* 8259 edge/level control definitions at VIA
|
|
||||||
*/
|
|
||||||
#define ISA8259_M_ELCR 0x4d0
|
|
||||||
#define ISA8259_S_ELCR 0x4d1
|
|
||||||
|
|
||||||
#define ELCRS_INT15_LVL 0x80
|
|
||||||
#define ELCRS_INT14_LVL 0x40
|
|
||||||
#define ELCRS_INT13_LVL 0x20
|
|
||||||
#define ELCRS_INT12_LVL 0x10
|
|
||||||
#define ELCRS_INT11_LVL 0x08
|
|
||||||
#define ELCRS_INT10_LVL 0x04
|
|
||||||
#define ELCRS_INT9_LVL 0x02
|
|
||||||
#define ELCRS_INT8_LVL 0x01
|
|
||||||
#define ELCRM_INT7_LVL 0x80
|
|
||||||
#define ELCRM_INT6_LVL 0x40
|
|
||||||
#define ELCRM_INT5_LVL 0x20
|
|
||||||
#define ELCRM_INT4_LVL 0x10
|
|
||||||
#define ELCRM_INT3_LVL 0x8
|
|
||||||
#define ELCRM_INT2_LVL 0x4
|
|
||||||
#define ELCRM_INT1_LVL 0x2
|
|
||||||
#define ELCRM_INT0_LVL 0x1
|
|
||||||
|
|
||||||
#define BSP_ASM_IRQ_VECTOR_BASE 0x0
|
#define BSP_ASM_IRQ_VECTOR_BASE 0x0
|
||||||
/* PIC's command and mask registers */
|
|
||||||
#define PIC_MASTER_COMMAND_IO_PORT 0x20 /* Master PIC command register */
|
|
||||||
#define PIC_SLAVE_COMMAND_IO_PORT 0xa0 /* Slave PIC command register */
|
|
||||||
#define PIC_MASTER_IMR_IO_PORT 0x21 /* Master PIC Interrupt Mask Register */
|
|
||||||
#define PIC_SLAVE_IMR_IO_PORT 0xa1 /* Slave PIC Interrupt Mask Register */
|
|
||||||
|
|
||||||
/* Command for specific EOI (End Of Interrupt): Interrupt acknowledge */
|
|
||||||
#define PIC_EOSI 0x60 /* End of Specific Interrupt (EOSI) */
|
|
||||||
#define SLAVE_PIC_EOSI 0x62 /* End of Specific Interrupt (EOSI) for cascade */
|
|
||||||
#define PIC_EOI 0x20 /* Generic End of Interrupt (EOI) */
|
|
||||||
|
|
||||||
#ifndef ASM
|
#ifndef ASM
|
||||||
|
|
||||||
@@ -65,75 +32,27 @@
|
|||||||
* Symblolic IRQ names and related definitions.
|
* Symblolic IRQ names and related definitions.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Base vector for our ISA IRQ handlers. */
|
#define BSP_PROCESSOR_IRQ_NUMBER (1)
|
||||||
#define BSP_ISA_IRQ_VECTOR_BASE (BSP_ASM_IRQ_VECTOR_BASE)
|
#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (0)
|
||||||
/*
|
|
||||||
* ISA IRQ handler related definitions
|
|
||||||
*/
|
|
||||||
#define BSP_ISA_IRQ_NUMBER (16)
|
|
||||||
#define BSP_ISA_IRQ_LOWEST_OFFSET (0)
|
|
||||||
#define BSP_ISA_IRQ_MAX_OFFSET (BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER-1)
|
|
||||||
/*
|
|
||||||
* PCI IRQ handlers related definitions
|
|
||||||
* CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE
|
|
||||||
*/
|
|
||||||
#define BSP_PCI_IRQ_NUMBER (16)
|
|
||||||
#define BSP_PCI_IRQ_LOWEST_OFFSET (BSP_ISA_IRQ_NUMBER)
|
|
||||||
#define BSP_PCI_IRQ_MAX_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET+BSP_PCI_IRQ_NUMBER-1)
|
|
||||||
/*
|
|
||||||
* PowerPc exceptions handled as interrupt where a rtems managed interrupt
|
|
||||||
* handler might be connected
|
|
||||||
*/
|
|
||||||
#define BSP_PROCESSOR_IRQ_NUMBER (1)
|
|
||||||
#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET + 1)
|
|
||||||
#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET+BSP_PROCESSOR_IRQ_NUMBER-1)
|
#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET+BSP_PROCESSOR_IRQ_NUMBER-1)
|
||||||
/* Misc vectors for OPENPIC irqs (IPI, timers)
|
|
||||||
*/
|
|
||||||
#define BSP_MISC_IRQ_NUMBER (8)
|
|
||||||
#define BSP_MISC_IRQ_LOWEST_OFFSET (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1)
|
|
||||||
#define BSP_MISC_IRQ_MAX_OFFSET (BSP_MISC_IRQ_LOWEST_OFFSET+BSP_MISC_IRQ_NUMBER-1)
|
|
||||||
/*
|
/*
|
||||||
* Summary
|
* Summary
|
||||||
*/
|
*/
|
||||||
#define BSP_IRQ_NUMBER (BSP_MISC_IRQ_MAX_OFFSET + 1)
|
#define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1)
|
||||||
#define BSP_LOWEST_OFFSET (BSP_ISA_IRQ_LOWEST_OFFSET)
|
#define BSP_LOWEST_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
|
||||||
#define BSP_MAX_OFFSET (BSP_MISC_IRQ_MAX_OFFSET)
|
#define BSP_MAX_OFFSET (BSP_IRQ_NUMBER - 1)
|
||||||
/*
|
|
||||||
* Some ISA IRQ symbolic name definition
|
|
||||||
*/
|
|
||||||
#define BSP_ISA_PERIODIC_TIMER (0)
|
|
||||||
|
|
||||||
#define BSP_ISA_KEYBOARD (1)
|
/*
|
||||||
|
* Some Processor execption handled as rtems IRQ symbolic name definition
|
||||||
#define BSP_UART_COM2_IRQ (3)
|
*/
|
||||||
|
|
||||||
#define BSP_UART_COM1_IRQ (4)
|
|
||||||
|
|
||||||
#define BSP_ISA_RT_TIMER1 (8)
|
|
||||||
|
|
||||||
#define BSP_ISA_RT_TIMER3 (10)
|
|
||||||
/*
|
|
||||||
* Some PCI IRQ symbolic name definition
|
|
||||||
*/
|
|
||||||
#define BSP_PCI_IRQ0 (BSP_PCI_IRQ_LOWEST_OFFSET)
|
|
||||||
#define BSP_PCI_ISA_BRIDGE_IRQ (BSP_PCI_IRQ0)
|
|
||||||
/*
|
|
||||||
* Some Processor execption handled as rtems IRQ symbolic name definition
|
|
||||||
*/
|
|
||||||
#define BSP_DECREMENTER (BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
|
#define BSP_DECREMENTER (BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
|
||||||
|
|
||||||
typedef unsigned short rtems_i8259_masks;
|
/* dummy routines - there is no PIC */
|
||||||
extern volatile rtems_i8259_masks i8259s_cache;
|
void BSP_enable_irq_at_pic(const rtems_irq_number);
|
||||||
|
void BSP_disable_irq_at_pic(const rtems_irq_number);
|
||||||
|
int BSP_setup_the_pic(rtems_irq_global_settings *);
|
||||||
|
|
||||||
/*
|
|
||||||
* Some items required to make some drivers compile, even though they
|
|
||||||
* will not work with this BSP.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define BSP_irq_enabled_at_i8259s(_name) 0
|
|
||||||
|
|
||||||
#define PCI_DRAM_BASE 0
|
|
||||||
#define PCI_DRAM_OFFSET 0
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
#endif
|
||||||
|
|||||||
@@ -31,19 +31,10 @@
|
|||||||
#include <bsp/motorola.h>
|
#include <bsp/motorola.h>
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
#define SHOW_ISA_PCI_BRIDGE_SETTINGS
|
#define SHOW_ISA_PCI_BRIDGE_SETTINGS
|
||||||
*/
|
*/
|
||||||
|
|
||||||
typedef struct {
|
|
||||||
unsigned char bus; /* few chance the PCI/ISA bridge is not on first bus but ... */
|
|
||||||
unsigned char device;
|
|
||||||
unsigned char function;
|
|
||||||
} pci_isa_bridge_device;
|
|
||||||
|
|
||||||
pci_isa_bridge_device* via_82c586 = 0;
|
|
||||||
|
|
||||||
extern unsigned int external_exception_vector_prolog_code_size[];
|
extern unsigned int external_exception_vector_prolog_code_size[];
|
||||||
extern void external_exception_vector_prolog_code();
|
extern void external_exception_vector_prolog_code();
|
||||||
extern unsigned int decrementer_exception_vector_prolog_code_size[];
|
extern unsigned int decrementer_exception_vector_prolog_code_size[];
|
||||||
@@ -69,36 +60,12 @@ static rtems_irq_connect_data defaultIrq = {
|
|||||||
0, nop_func , NULL , nop_func , nop_func , not_connected
|
0, nop_func , NULL , nop_func , nop_func , not_connected
|
||||||
};
|
};
|
||||||
static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER]={
|
static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER]={
|
||||||
/*
|
|
||||||
* actual rpiorities for interrupt :
|
|
||||||
* 0 means that only current interrupt is masked
|
|
||||||
* 255 means all other interrupts are masked
|
|
||||||
*/
|
|
||||||
/*
|
|
||||||
* ISA interrupts.
|
|
||||||
* The second entry has a priority of 255 because
|
|
||||||
* it is the slave pic entry and is should always remain
|
|
||||||
* unmasked.
|
|
||||||
*/
|
|
||||||
0,0,
|
|
||||||
255,
|
|
||||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
||||||
/*
|
|
||||||
* PCI Interrupts
|
|
||||||
*/
|
|
||||||
8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, /* for raven prio 0 means unactive... */
|
|
||||||
/*
|
/*
|
||||||
* Processor exceptions handled as interrupts
|
* Processor exceptions handled as interrupts
|
||||||
*/
|
*/
|
||||||
0
|
0
|
||||||
};
|
};
|
||||||
|
|
||||||
void VIA_isa_bridge_interrupts_setup(void)
|
|
||||||
{
|
|
||||||
printk("VIA_isa_bridge_interrupts_setup - Shouldn't get here!\n");
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* This code assumes the exceptions management setup has already
|
* This code assumes the exceptions management setup has already
|
||||||
* been done. We just need to replace the exceptions that will
|
* been done. We just need to replace the exceptions that will
|
||||||
@@ -165,4 +132,3 @@ void BSP_rtems_irq_mng_init(unsigned cpuId)
|
|||||||
printk("RTEMS IRQ management is now operationnal\n");
|
printk("RTEMS IRQ management is now operationnal\n");
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|||||||
60
c/src/lib/libbsp/powerpc/psim/irq/no_pic.c
Normal file
60
c/src/lib/libbsp/powerpc/psim/irq/no_pic.c
Normal file
@@ -0,0 +1,60 @@
|
|||||||
|
/*
|
||||||
|
*
|
||||||
|
* This file contains the implementation of the function described in irq.h
|
||||||
|
*
|
||||||
|
* Copyright (C) 1998, 1999 valette@crf.canon.fr
|
||||||
|
*
|
||||||
|
* The license and distribution terms for this file may be
|
||||||
|
* found in found in the file LICENSE in this distribution or at
|
||||||
|
* http://www.rtems.com/license/LICENSE.
|
||||||
|
*
|
||||||
|
* Dummy support for just the decrementer interrupt but no PIC.
|
||||||
|
*
|
||||||
|
* T. Straumann, 2007/11/30
|
||||||
|
*
|
||||||
|
* irq.c,v 1.4.2.8 2003/09/04 18:45:20 joel Exp
|
||||||
|
*/
|
||||||
|
#include <rtems.h>
|
||||||
|
#include <bsp.h>
|
||||||
|
#include <bsp/irq.h>
|
||||||
|
#include <libcpu/raw_exception.h>
|
||||||
|
|
||||||
|
static rtems_irq_connect_data *rtems_hdl_tbl;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* High level IRQ handler called from shared_raw_irq_code_entry
|
||||||
|
*/
|
||||||
|
void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
|
||||||
|
{
|
||||||
|
register unsigned msr;
|
||||||
|
register unsigned new_msr;
|
||||||
|
|
||||||
|
if (excNum == ASM_DEC_VECTOR) {
|
||||||
|
_CPU_MSR_GET(msr);
|
||||||
|
new_msr = msr | MSR_EE;
|
||||||
|
_CPU_MSR_SET(new_msr);
|
||||||
|
|
||||||
|
rtems_hdl_tbl[BSP_DECREMENTER].hdl(rtems_hdl_tbl[BSP_DECREMENTER].handle);
|
||||||
|
|
||||||
|
_CPU_MSR_SET(msr);
|
||||||
|
return;
|
||||||
|
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
BSP_enable_irq_at_pic(const rtems_irq_number irq)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
BSP_disable_irq_at_pic(const rtems_irq_number irq)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
int
|
||||||
|
BSP_setup_the_pic(rtems_irq_global_settings *config)
|
||||||
|
{
|
||||||
|
rtems_hdl_tbl = config->irqHdlTbl;
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
Reference in New Issue
Block a user