RTOS/rtems
1
0
Fork 0
forked from Imagelibrary/rtems
Code Pull Requests Activity

2007-11-30 Till Straumann <strauman@slac.stanford.edu>

Browse Source 
* irq/irq.h, irq/irq.c (removed), irq/no_pic.c (added),
	irq/irq_init.c, Makefile.am: The PSIM BSP (currently)
	has no support for an interrupt controller or interrupts
	other than the decrementer. Removed all definitions for PCI + ISA
	interrupts and all unnecessary code (leftovers from copying).
	Separated PIC-specific bits into 'no_pic.c' which allows us
	to use 'irq.c' (i.e., more code) from 'shared'.
This commit is contained in:
Till Straumann
2007-11-30 19:55:46 +00:00
parent 431bcd7513
commit 10483cba75
6 changed files with 84 additions and 468 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
c/src/lib/libbsp/powerpc/psim/ChangeLog
View File

@@ -1,3 +1,12 @@
2007-11-30 Till Straumann <strauman@slac.stanford.edu>
* irq/irq.h, irq/irq.c (removed), irq/no_pic.c (added),
irq/irq_init.c, Makefile.am: The PSIM BSP (currently)
has no support for an interrupt controller or interrupts
other than the decrementer. Removed all definitions for PCI + ISA
interrupts and all unnecessary code (leftovers from copying).
Separated PIC-specific bits into 'no_pic.c' which allows us
to use 'irq.c' (i.e., more code) from 'shared'.
2007-11-30 Till Straumann <strauman@slac.stanford.edu>
* startup/linkcmds.c, start/start.S: call __eabi() from start.S

2
c/src/lib/libbsp/powerpc/psim/Makefile.am
View File

@@ -65,7 +65,7 @@ consoleio_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
include_bsp_HEADERS = irq/irq.h
noinst_PROGRAMS += irq.rel
irq_rel_SOURCES = irq/irq.c irq/irq_init.c ../shared/irq/irq_asm.S
irq_rel_SOURCES = ../shared/irq/irq.c irq/irq_init.c ../shared/irq/irq_asm.S irq/no_pic.c
irq_rel_CPPFLAGS = $(AM_CPPFLAGS)
irq_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)

338
c/src/lib/libbsp/powerpc/psim/irq/irq.c
View File

@@ -1,338 +0,0 @@
/*
*
* This file contains the implementation of the function described in irq.h
*
* Copyright (C) 1998, 1999 valette@crf.canon.fr
*
* The license and distribution terms for this file may be
* found in found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* irq.c,v 1.4.2.8 2003/09/04 18:45:20 joel Exp
*/
#include <rtems/system.h>
#include <bsp.h>
#include <bsp/irq.h>
#if 0
#include <bsp/VME.h>
#include <bsp/openpic.h>
#endif
#include <stdlib.h>
#include <rtems/score/thread.h>
#include <rtems/score/apiext.h>
#include <libcpu/raw_exception.h>
#include <libcpu/io.h>
#include <bsp/vectors.h>
#include <rtems/bspIo.h> /* for printk */
#define RAVEN_INTR_ACK_REG 0xfeff0030
/*
* pointer to the mask representing the additionnal irq vectors
* that must be disabled when a particular entry is activated.
* They will be dynamically computed from teh prioruty table given
* in BSP_rtems_irq_mngt_set();
* CAUTION : this table is accessed directly by interrupt routine
* prologue.
*/
rtems_i8259_masks irq_mask_or_tbl[BSP_IRQ_NUMBER];
/*
* default handler connected on each irq after bsp initialization
*/
static rtems_irq_connect_data default_rtems_entry;
/*
* location used to store initial tables used for interrupt
* management.
*/
static rtems_irq_global_settings* internal_config;
static rtems_irq_connect_data* rtems_hdl_tbl;
/*
* Check if IRQ is an ISA IRQ
*/
static inline int is_isa_irq(const rtems_irq_number irqLine)
{
return (((int) irqLine <= BSP_ISA_IRQ_MAX_OFFSET) &
((int) irqLine >= BSP_ISA_IRQ_LOWEST_OFFSET)
);
}
/*
* Check if IRQ is an OPENPIC IRQ
*/
static inline int is_pci_irq(const rtems_irq_number irqLine)
{
return (((int) irqLine <= BSP_PCI_IRQ_MAX_OFFSET) &
((int) irqLine >= BSP_PCI_IRQ_LOWEST_OFFSET)
);
}
/*
* Check if IRQ is a Porcessor IRQ
*/
static inline int is_processor_irq(const rtems_irq_number irqLine)
{
return (((int) irqLine <= BSP_PROCESSOR_IRQ_MAX_OFFSET) &
((int) irqLine >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
);
}
/*
* ------------------------ RTEMS Irq helper functions ----------------
*/
/*
* This function check that the value given for the irq line
* is valid.
*/
static int isValidInterrupt(int irq)
{
if ( (irq < BSP_LOWEST_OFFSET) || (irq > BSP_MAX_OFFSET))
return 0;
return 1;
}
/*
* ------------------------ RTEMS Shared Irq Handler Mngt Routines ----------------
*/
int BSP_install_rtems_shared_irq_handler (const rtems_irq_connect_data* irq)
{
printk("BSP_insall_rtems_shared_irq_handler Not supported in psim\n");
return 0;
}
/*
* ------------------------ RTEMS Single Irq Handler Mngt Routines ----------------
*/
int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq)
{
rtems_interrupt_level level;
if (!isValidInterrupt(irq->name)) {
printk("Invalid interrupt vector %d\n",irq->name);
return 0;
}
/*
* Check if default handler is actually connected. If not issue an error.
* You must first get the current handler via i386_get_current_idt_entry
* and then disconnect it using i386_delete_idt_entry.
* RATIONALE : to always have the same transition by forcing the user
* to get the previous handler before accepting to disconnect.
*/
rtems_interrupt_disable(level);
if (rtems_hdl_tbl[irq->name].hdl != default_rtems_entry.hdl) {
rtems_interrupt_enable(level);
printk("IRQ vector %d already connected\n",irq->name);
return 0;
}
/*
* store the data provided by user
*/
rtems_hdl_tbl[irq->name] = *irq;
rtems_hdl_tbl[irq->name].next_handler = (void *)-1;
if (is_isa_irq(irq->name)) {
printk("What's a isa_irq on psim?");
}
if (is_processor_irq(irq->name)) {
/*
* Enable exception at processor level
*/
}
/*
* Enable interrupt on device
*/
if (irq->on)
irq->on(irq);
rtems_interrupt_enable(level);
return 1;
}
int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* irq)
{
rtems_interrupt_level level;
if (!isValidInterrupt(irq->name)) {
return 0;
}
rtems_interrupt_disable(level);
*irq = rtems_hdl_tbl[irq->name];
rtems_interrupt_enable(level);
return 1;
}
int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq)
{
rtems_irq_connect_data *pchain= NULL, *vchain = NULL;
rtems_interrupt_level level;
if (!isValidInterrupt(irq->name)) {
return 0;
}
/*
* Check if default handler is actually connected. If not issue an error.
* You must first get the current handler via i386_get_current_idt_entry
* and then disconnect it using i386_delete_idt_entry.
* RATIONALE : to always have the same transition by forcing the user
* to get the previous handler before accepting to disconnect.
*/
rtems_interrupt_disable(level);
if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) {
rtems_interrupt_enable(level);
return 0;
}
if( (int)rtems_hdl_tbl[irq->name].next_handler != -1 )
{
int found = 0;
for( (pchain= NULL, vchain = &rtems_hdl_tbl[irq->name]);
(vchain->hdl != default_rtems_entry.hdl);
(pchain= vchain, vchain = (rtems_irq_connect_data*)vchain->next_handler) )
{
if( vchain->hdl == irq->hdl )
{
found= -1; break;
}
}
if( !found )
{
rtems_interrupt_enable(level);
return 0;
}
}
else
{
if (rtems_hdl_tbl[irq->name].hdl != irq->hdl)
{
rtems_interrupt_enable(level);
return 0;
}
}
if (is_isa_irq(irq->name)) {
printk("isa irq on psim?");
}
if (is_processor_irq(irq->name)) {
/*
* disable exception at processor level
*/
}
/*
* Disable interrupt on device
*/
if (irq->off)
irq->off(irq);
/*
* restore the default irq value
*/
if( !vchain )
{
/* single handler vector... */
rtems_hdl_tbl[irq->name] = default_rtems_entry;
}
else
{
if( pchain )
{
/* non-first handler being removed */
pchain->next_handler = vchain->next_handler;
}
else
{
/* first handler isn't malloc'ed, so just overwrite it. Since
the contents of vchain are being struct copied, vchain itself
goes away */
rtems_hdl_tbl[irq->name]= *vchain;
}
free(vchain);
}
rtems_interrupt_enable(level);
return 1;
}
/*
* ------------------------ RTEMS Global Irq Handler Mngt Routines ----------------
*/
int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)
{
/*
* Store various code accelerators
*/
internal_config = config;
default_rtems_entry = config->defaultEntry;
rtems_hdl_tbl = config->irqHdlTbl;
return 1;
}
int BSP_rtems_irq_mngt_get(rtems_irq_global_settings** config)
{
*config = internal_config;
return 0;
}
int _BSP_vme_bridge_irq = -1;
unsigned BSP_spuriousIntr = 0;
/*
* High level IRQ handler called from shared_raw_irq_code_entry
*/
void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
{
register unsigned msr;
register unsigned new_msr;
if (excNum == ASM_DEC_VECTOR) {
_CPU_MSR_GET(msr);
new_msr = msr | MSR_EE;
_CPU_MSR_SET(new_msr);
rtems_hdl_tbl[BSP_DECREMENTER].hdl(rtems_hdl_tbl[BSP_DECREMENTER].handle);
_CPU_MSR_SET(msr);
return;
}
}
void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx)
{
/*
* Process pending signals that have not already been
* processed by _Thread_Displatch. This happens quite
* unfrequently : the ISR must have posted an action
* to the current running thread.
*/
if ( _Thread_Do_post_task_switch_extension ||
_Thread_Executing->do_post_task_switch_extension ) {
_Thread_Executing->do_post_task_switch_extension = FALSE;
_API_extensions_Run_postswitch();
}
/*
* I plan to process other thread related events here.
* This will include DEBUG session requested from keyboard...
*/
}

109
c/src/lib/libbsp/powerpc/psim/irq/irq.h
View File

@@ -24,40 +24,7 @@
#define BSP_SHARED_HANDLER_SUPPORT 1
#include <rtems/irq.h>
/*
* 8259 edge/level control definitions at VIA
*/
#define ISA8259_M_ELCR 0x4d0
#define ISA8259_S_ELCR 0x4d1
#define ELCRS_INT15_LVL 0x80
#define ELCRS_INT14_LVL 0x40
#define ELCRS_INT13_LVL 0x20
#define ELCRS_INT12_LVL 0x10
#define ELCRS_INT11_LVL 0x08
#define ELCRS_INT10_LVL 0x04
#define ELCRS_INT9_LVL 0x02
#define ELCRS_INT8_LVL 0x01
#define ELCRM_INT7_LVL 0x80
#define ELCRM_INT6_LVL 0x40
#define ELCRM_INT5_LVL 0x20
#define ELCRM_INT4_LVL 0x10
#define ELCRM_INT3_LVL 0x8
#define ELCRM_INT2_LVL 0x4
#define ELCRM_INT1_LVL 0x2
#define ELCRM_INT0_LVL 0x1
#define BSP_ASM_IRQ_VECTOR_BASE 0x0
/* PIC's command and mask registers */
#define PIC_MASTER_COMMAND_IO_PORT 0x20 /* Master PIC command register */
#define PIC_SLAVE_COMMAND_IO_PORT 0xa0 /* Slave PIC command register */
#define PIC_MASTER_IMR_IO_PORT 0x21 /* Master PIC Interrupt Mask Register */
#define PIC_SLAVE_IMR_IO_PORT 0xa1 /* Slave PIC Interrupt Mask Register */
/* Command for specific EOI (End Of Interrupt): Interrupt acknowledge */
#define PIC_EOSI 0x60 /* End of Specific Interrupt (EOSI) */
#define SLAVE_PIC_EOSI 0x62 /* End of Specific Interrupt (EOSI) for cascade */
#define PIC_EOI 0x20 /* Generic End of Interrupt (EOI) */
#ifndef ASM
@@ -65,75 +32,27 @@
* Symblolic IRQ names and related definitions.
*/
/* Base vector for our ISA IRQ handlers. */
#define BSP_ISA_IRQ_VECTOR_BASE (BSP_ASM_IRQ_VECTOR_BASE)
/*
* ISA IRQ handler related definitions
*/
#define BSP_ISA_IRQ_NUMBER (16)
#define BSP_ISA_IRQ_LOWEST_OFFSET (0)
#define BSP_ISA_IRQ_MAX_OFFSET (BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER-1)
/*
* PCI IRQ handlers related definitions
* CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE
*/
#define BSP_PCI_IRQ_NUMBER (16)
#define BSP_PCI_IRQ_LOWEST_OFFSET (BSP_ISA_IRQ_NUMBER)
#define BSP_PCI_IRQ_MAX_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET+BSP_PCI_IRQ_NUMBER-1)
/*
* PowerPc exceptions handled as interrupt where a rtems managed interrupt
* handler might be connected
*/
#define BSP_PROCESSOR_IRQ_NUMBER (1)
#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET + 1)
#define BSP_PROCESSOR_IRQ_NUMBER (1)
#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (0)
#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET+BSP_PROCESSOR_IRQ_NUMBER-1)
/* Misc vectors for OPENPIC irqs (IPI, timers)
*/
#define BSP_MISC_IRQ_NUMBER (8)
#define BSP_MISC_IRQ_LOWEST_OFFSET (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1)
#define BSP_MISC_IRQ_MAX_OFFSET (BSP_MISC_IRQ_LOWEST_OFFSET+BSP_MISC_IRQ_NUMBER-1)
/*
* Summary
*/
#define BSP_IRQ_NUMBER (BSP_MISC_IRQ_MAX_OFFSET + 1)
#define BSP_LOWEST_OFFSET (BSP_ISA_IRQ_LOWEST_OFFSET)
#define BSP_MAX_OFFSET (BSP_MISC_IRQ_MAX_OFFSET)
/*
* Some ISA IRQ symbolic name definition
*/
#define BSP_ISA_PERIODIC_TIMER (0)
#define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1)
#define BSP_LOWEST_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
#define BSP_MAX_OFFSET (BSP_IRQ_NUMBER - 1)
#define BSP_ISA_KEYBOARD (1)
#define BSP_UART_COM2_IRQ (3)
#define BSP_UART_COM1_IRQ (4)
#define BSP_ISA_RT_TIMER1 (8)
#define BSP_ISA_RT_TIMER3 (10)
/*
* Some PCI IRQ symbolic name definition
*/
#define BSP_PCI_IRQ0 (BSP_PCI_IRQ_LOWEST_OFFSET)
#define BSP_PCI_ISA_BRIDGE_IRQ (BSP_PCI_IRQ0)
/*
* Some Processor execption handled as rtems IRQ symbolic name definition
*/
/*
* Some Processor execption handled as rtems IRQ symbolic name definition
*/
#define BSP_DECREMENTER (BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
typedef unsigned short rtems_i8259_masks;
extern volatile rtems_i8259_masks i8259s_cache;
/* dummy routines - there is no PIC */
void BSP_enable_irq_at_pic(const rtems_irq_number);
void BSP_disable_irq_at_pic(const rtems_irq_number);
int BSP_setup_the_pic(rtems_irq_global_settings *);
/*
* Some items required to make some drivers compile, even though they
* will not work with this BSP.
*/
#define BSP_irq_enabled_at_i8259s(_name) 0
#define PCI_DRAM_BASE 0
#define PCI_DRAM_OFFSET 0
#endif
#endif
#endif

34
c/src/lib/libbsp/powerpc/psim/irq/irq_init.c
View File

@@ -31,19 +31,10 @@
#include <bsp/motorola.h>
#endif
/*
#define SHOW_ISA_PCI_BRIDGE_SETTINGS
*/
typedef struct {
unsigned char bus; /* few chance the PCI/ISA bridge is not on first bus but ... */
unsigned char device;
unsigned char function;
} pci_isa_bridge_device;
pci_isa_bridge_device* via_82c586 = 0;
extern unsigned int external_exception_vector_prolog_code_size[];
extern void external_exception_vector_prolog_code();
extern unsigned int decrementer_exception_vector_prolog_code_size[];
@@ -69,36 +60,12 @@ static rtems_irq_connect_data defaultIrq = {
0, nop_func , NULL , nop_func , nop_func , not_connected
};
static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER]={
/*
* actual rpiorities for interrupt :
* 0 means that only current interrupt is masked
* 255 means all other interrupts are masked
*/
/*
* ISA interrupts.
* The second entry has a priority of 255 because
* it is the slave pic entry and is should always remain
* unmasked.
*/
0,0,
255,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/*
* PCI Interrupts
*/
8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, /* for raven prio 0 means unactive... */
/*
* Processor exceptions handled as interrupts
*/
0
};
void VIA_isa_bridge_interrupts_setup(void)
{
printk("VIA_isa_bridge_interrupts_setup - Shouldn't get here!\n");
return;
}
/*
* This code assumes the exceptions management setup has already
* been done. We just need to replace the exceptions that will
@@ -165,4 +132,3 @@ void BSP_rtems_irq_mng_init(unsigned cpuId)
printk("RTEMS IRQ management is now operationnal\n");
#endif
}

60
c/src/lib/libbsp/powerpc/psim/irq/no_pic.c Normal file
View File

@@ -0,0 +1,60 @@
/*
*
* This file contains the implementation of the function described in irq.h
*
* Copyright (C) 1998, 1999 valette@crf.canon.fr
*
* The license and distribution terms for this file may be
* found in found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* Dummy support for just the decrementer interrupt but no PIC.
*
* T. Straumann, 2007/11/30
*
* irq.c,v 1.4.2.8 2003/09/04 18:45:20 joel Exp
*/
#include <rtems.h>
#include <bsp.h>
#include <bsp/irq.h>
#include <libcpu/raw_exception.h>
static rtems_irq_connect_data *rtems_hdl_tbl;
/*
* High level IRQ handler called from shared_raw_irq_code_entry
*/
void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
{
register unsigned msr;
register unsigned new_msr;
if (excNum == ASM_DEC_VECTOR) {
_CPU_MSR_GET(msr);
new_msr = msr | MSR_EE;
_CPU_MSR_SET(new_msr);
rtems_hdl_tbl[BSP_DECREMENTER].hdl(rtems_hdl_tbl[BSP_DECREMENTER].handle);
_CPU_MSR_SET(msr);
return;
}
}
void
BSP_enable_irq_at_pic(const rtems_irq_number irq)
{
}
void
BSP_disable_irq_at_pic(const rtems_irq_number irq)
{
}
int
BSP_setup_the_pic(rtems_irq_global_settings *config)
{
rtems_hdl_tbl = config->irqHdlTbl;
return 1;
}