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SH libcpu and libbsp: Fix warnings

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This commit is contained in:
Joel Sherrill
2014-10-15 14:20:14 -05:00
parent 694debefe9
commit 0626dba48a
15 changed files with 350 additions and 332 deletions
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9
c/src/lib/libbsp/sh/gensh1/include/bsp.h
View File

@@ -1,8 +1,10 @@
/*
* This include file contains all board IO definitions.
*
* generic sh1
*
* This include file contains all board IO definitions.
*/
/*
* Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
@@ -68,8 +70,9 @@ extern void *CPU_Interrupt_stack_high;
console_read, console_write, console_control }
/*
* NOTE: Use the standard Clock driver entry
* BSP methods that cross file boundaries.
*/
void bsp_hw_init(void);
#ifdef __cplusplus
}

28
c/src/lib/libbsp/sh/gensh2/include/bsp.h
View File

@@ -1,8 +1,10 @@
/*
* This include file contains all board IO definitions.
*
* generic sh2
*
* This include file contains all board IO definitions.
*/
/*
* Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
@@ -45,12 +47,11 @@ extern "C" {
#include <bspopts.h>
#include <bsp/default-initial-extension.h>
#if 0
#include <rtems/devnull.h>
#define BSP_CONSOLE_DEVNAME "/dev/null"
#define BSP_CONSOLE_DRIVER_TABLE_ENTRY DEVNULL_DRIVER_TABLE_ENTRY
#else
#include <termios.h> /* for tcflag_t */
#include <sh/sci.h>
#if 1
/* FIXME:
* These definitions will be no longer necessary if the old
* implementation of SCI driver will be droped
@@ -66,17 +67,18 @@ extern "C" {
/*
* Defined in the linker script 'linkcmds'
*/
extern void *CPU_Interrupt_stack_low;
extern void *CPU_Interrupt_stack_high;
/*
* Device Driver Table Entries
*/
/*
* NOTE: Use the standard Clock driver entry
* BSP methods that cross file boundaries.
*/
void bsp_hw_init(void);
extern int _sci_get_brparms(
tcflag_t cflag,
unsigned char *smr,
unsigned char *brr
);
#ifdef __cplusplus
}

448
c/src/lib/libbsp/sh/gensh4/hw_init/hw_init.c
View File

@@ -1,9 +1,11 @@
/*
* SMFD board hardware initialization.
*
*/
/*
* Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
* Author: Victor V. Vengerov <vvv@oktet.ru>
* Alexandra Kossovsky <sasha@oktet.ru>
* Alexandra Kossovsky <sasha@oktet.ru>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
@@ -25,241 +27,234 @@
*
* This function should not access the memory! It should be compiled
* with -fomit-frame-pointer to avoid stack access.
*
* PARAMETERS:
* none
*
* RETURNS:
* none
*/
void
early_hw_init(void)
void early_hw_init(void)
{
/* Explicitly turn off the MMU */
write32(0, SH7750_MMUCR);
/* Explicitly turn off the MMU */
write32(0, SH7750_MMUCR);
/* Disable instruction and operand caches */
write32(0, SH7750_CCR);
/* Disable instruction and operand caches */
write32(0, SH7750_CCR);
/* Setup Clock Generator */
/*
* Input clock frequency is 16 MHz, MD0=1,
* CPU clock frequency already selected to 96MHz.
* Bus clock frequency should be set to 48 MHz, therefore divider 2
* should be applied (bus frequency is 48 MHz, clock period is 20.84ns).
* Peripheral frequency should be set to 24 MHz, therefore divider 4
* should be used.
*/
/* Prepare watchdog timer for frequency changing */
write16((read8(SH7750_WTCSR) & ~SH7750_WTCSR_TME) |
SH7750_WTCSR_KEY, SH7750_WTCSR);
write16(SH7750_WTCSR_MODE_IT | SH7750_WTCSR_CKS_DIV4096 |
SH7750_WTCSR_KEY, SH7750_WTCSR);
/* Setup Clock Generator */
/*
* Input clock frequency is 16 MHz, MD0=1,
* CPU clock frequency already selected to 96MHz.
* Bus clock frequency should be set to 48 MHz, therefore divider 2
* should be applied (bus frequency is 48 MHz, clock period is 20.84ns).
* Peripheral frequency should be set to 24 MHz, therefore divider 4
* should be used.
*/
/* Prepare watchdog timer for frequency changing */
write16((read8(SH7750_WTCSR) & ~SH7750_WTCSR_TME) |
SH7750_WTCSR_KEY, SH7750_WTCSR);
write16(SH7750_WTCSR_MODE_IT | SH7750_WTCSR_CKS_DIV4096 |
SH7750_WTCSR_KEY, SH7750_WTCSR);
/* Turn PLL1 on */
write16(0x40 | SH7750_WTCNT_KEY, SH7750_WTCNT);
write16(read16(SH7750_FRQCR) | SH7750_FRQCR_PLL1EN, SH7750_FRQCR);
/* Turn PLL1 on */
write16(0x40 | SH7750_WTCNT_KEY, SH7750_WTCNT);
write16(read16(SH7750_FRQCR) | SH7750_FRQCR_PLL1EN, SH7750_FRQCR);
/* Perform Frequency Selection */
write16(0x40 | SH7750_WTCNT_KEY, SH7750_WTCNT);
write16(SH7750_FRQCR_CKOEN | SH7750_FRQCR_PLL1EN |
SH7750_FRQCR_IFCDIV1 | SH7750_FRQCR_BFCDIV2 | SH7750_FRQCR_PFCDIV4,
SH7750_FRQCR);
/* Perform Frequency Selection */
write16(0x40 | SH7750_WTCNT_KEY, SH7750_WTCNT);
write16(SH7750_FRQCR_CKOEN | SH7750_FRQCR_PLL1EN |
SH7750_FRQCR_IFCDIV1 | SH7750_FRQCR_BFCDIV2 | SH7750_FRQCR_PFCDIV4,
SH7750_FRQCR);
/* Turn PLL2 on */
write16(0x40 | SH7750_WTCNT_KEY, SH7750_WTCNT);
write16(read16(SH7750_FRQCR) | SH7750_FRQCR_PLL2EN, SH7750_FRQCR);
/* Turn PLL2 on */
write16(0x40 | SH7750_WTCNT_KEY, SH7750_WTCNT);
write16(read16(SH7750_FRQCR) | SH7750_FRQCR_PLL2EN, SH7750_FRQCR);
/* Bus State Controller Initialization */
/*
* Area assignments:
* Area 0: Flash memory, SRAM interface
* Area 1: GDC
* Area 2: SDRAM
* Area 3-6: unused
*/
write32(
/* Pull-ups (IPUP, OPUP) enabled */
/* No Byte-Control SRAM mode for Area 1 and Area 3 */
SH7750_BCR1_BREQEN | /* Enable external bus requests */
/* No Partial Sharing Mode */
/* No MPX interface */
/* Memory and Control Signals are in HiZ */
SH7750_BCR1_A0BST_SRAM | /* No burst ROM in flash */
SH7750_BCR1_A5BST_SRAM | /* Area 5 is not in use */
SH7750_BCR1_A6BST_SRAM | /* Area 6 is not in use */
SH7750_BCR1_DRAMTP_2SDRAM_3SDRAM /* Select Area 2 SDRAM type */
/* Area 5,6 programmed as a SRAM interface (not PCMCIA) */,
SH7750_BCR1);
/* Bus State Controller Initialization */
/*
* Area assignments:
* Area 0: Flash memory, SRAM interface
* Area 1: GDC
* Area 2: SDRAM
* Area 3-6: unused
*/
write32(
/* Pull-ups (IPUP, OPUP) enabled */
/* No Byte-Control SRAM mode for Area 1 and Area 3 */
SH7750_BCR1_BREQEN | /* Enable external bus requests */
/* No Partial Sharing Mode */
/* No MPX interface */
/* Memory and Control Signals are in HiZ */
SH7750_BCR1_A0BST_SRAM | /* No burst ROM in flash */
SH7750_BCR1_A5BST_SRAM | /* Area 5 is not in use */
SH7750_BCR1_A6BST_SRAM | /* Area 6 is not in use */
SH7750_BCR1_DRAMTP_2SDRAM_3SDRAM /* Select Area 2 SDRAM type */
/* Area 5,6 programmed as a SRAM interface (not PCMCIA) */,
SH7750_BCR1);
write16(
(SH7750_BCR2_SZ_8 << SH7750_BCR2_A0SZ_S) | /* These bits is read-only
and set during reset */
(SH7750_BCR2_SZ_32 << SH7750_BCR2_A6SZ_S) | /* Area 6 not used */
(SH7750_BCR2_SZ_32 << SH7750_BCR2_A5SZ_S) | /* Area 5 not used */
(SH7750_BCR2_SZ_32 << SH7750_BCR2_A4SZ_S) | /* Area 4 not used */
(SH7750_BCR2_SZ_32 << SH7750_BCR2_A3SZ_S) | /* Area 3 not used */
(SH7750_BCR2_SZ_32 << SH7750_BCR2_A2SZ_S) | /* SDRAM is 32-bit width */
(SH7750_BCR2_SZ_32 << SH7750_BCR2_A1SZ_S) | /* GDC is 32-bit width */
SH7750_BCR2_PORTEN, /* Use D32-D51 as a port */
SH7750_BCR2);
write16(
(SH7750_BCR2_SZ_8 << SH7750_BCR2_A0SZ_S) | /* These bits is read-only
and set during reset */
(SH7750_BCR2_SZ_32 << SH7750_BCR2_A6SZ_S) | /* Area 6 not used */
(SH7750_BCR2_SZ_32 << SH7750_BCR2_A5SZ_S) | /* Area 5 not used */
(SH7750_BCR2_SZ_32 << SH7750_BCR2_A4SZ_S) | /* Area 4 not used */
(SH7750_BCR2_SZ_32 << SH7750_BCR2_A3SZ_S) | /* Area 3 not used */
(SH7750_BCR2_SZ_32 << SH7750_BCR2_A2SZ_S) | /* SDRAM is 32-bit width */
(SH7750_BCR2_SZ_32 << SH7750_BCR2_A1SZ_S) | /* GDC is 32-bit width */
SH7750_BCR2_PORTEN, /* Use D32-D51 as a port */
SH7750_BCR2);
write32(
(0 << SH7750_WCR1_DMAIW_S) | /* 0 required for SDRAM RAS down mode */
(7 << SH7750_WCR1_A6IW_S) | /* Area 6 not used */
(7 << SH7750_WCR1_A5IW_S) | /* Area 5 not used */
(7 << SH7750_WCR1_A4IW_S) | /* Area 4 not used */
(7 << SH7750_WCR1_A3IW_S) | /* Area 3 not used */
(1 << SH7750_WCR1_A2IW_S) | /* 1 idle cycles inserted between acc */
(7 << SH7750_WCR1_A1IW_S) | /* Don't have GDC specs... Set safer. */
(1 << SH7750_WCR1_A0IW_S), /* 1 idle cycles inserted between acc */
SH7750_WCR1);
write32(
(0 << SH7750_WCR1_DMAIW_S) | /* 0 required for SDRAM RAS down mode */
(7 << SH7750_WCR1_A6IW_S) | /* Area 6 not used */
(7 << SH7750_WCR1_A5IW_S) | /* Area 5 not used */
(7 << SH7750_WCR1_A4IW_S) | /* Area 4 not used */
(7 << SH7750_WCR1_A3IW_S) | /* Area 3 not used */
(1 << SH7750_WCR1_A2IW_S) | /* 1 idle cycles inserted between acc */
(7 << SH7750_WCR1_A1IW_S) | /* Don't have GDC specs... Set safer. */
(1 << SH7750_WCR1_A0IW_S), /* 1 idle cycles inserted between acc */
SH7750_WCR1);
write32(
(SH7750_WCR2_WS15 << SH7750_WCR2_A6W_S) | /* Area 6 not used */
(SH7750_WCR2_BPWS7 << SH7750_WCR2_A6B_S) |
(SH7750_WCR2_WS15 << SH7750_WCR2_A5W_S) | /* Area 5 not used */
(SH7750_WCR2_BPWS7 << SH7750_WCR2_A5B_S) |
(SH7750_WCR2_WS15 << SH7750_WCR2_A4W_S) | /* Area 4 not used */
(SH7750_WCR2_WS15 << SH7750_WCR2_A3W_S) | /*Area 3 not used*/
(SH7750_WCR2_SDRAM_CAS_LAT2 << SH7750_WCR2_A2W_S) | /* SDRAM CL = 2 */
(SH7750_WCR2_WS15 << SH7750_WCR2_A1W_S) | /* Area 1 (GDC)
requirements not known*/
(SH7750_WCR2_WS6 << SH7750_WCR2_A0W_S) | /* 4 wait states required
at 48MHz for 70ns mem.,
set closest greater */
(SH7750_WCR2_BPWS7 << SH7750_WCR2_A0B_S), /* burst mode disabled for
Area 0 flash ROM */
SH7750_WCR2);
write32(
SH7750_WCR3_A6S | /* Area 6 not used */
(SH7750_WCR3_DHWS_3 << SH7750_WCR3_A6H_S) |
SH7750_WCR3_A5S | /* Area 5 not used */
(SH7750_WCR3_DHWS_3 << SH7750_WCR3_A5H_S) |
SH7750_WCR3_A4S | /* Area 4 not used */
(SH7750_WCR3_DHWS_3 << SH7750_WCR3_A4H_S) |
SH7750_WCR3_A3S | /* Area 3 not used */
(SH7750_WCR3_DHWS_3 << SH7750_WCR3_A3H_S) |
SH7750_WCR3_A2S | /* SDRAM - ignored */
(SH7750_WCR3_DHWS_3 << SH7750_WCR3_A2H_S) |
SH7750_WCR3_A1S | /* GDC - unknown, set max*/
(SH7750_WCR3_DHWS_3 << SH7750_WCR3_A1H_S) |
0 | /* flash ROM - no write strobe setup time required */
(SH7750_WCR3_DHWS_0 << SH7750_WCR3_A0H_S),
SH7750_WCR3);
write32(
(SH7750_WCR2_WS15 << SH7750_WCR2_A6W_S) | /* Area 6 not used */
(SH7750_WCR2_BPWS7 << SH7750_WCR2_A6B_S) |
(SH7750_WCR2_WS15 << SH7750_WCR2_A5W_S) | /* Area 5 not used */
(SH7750_WCR2_BPWS7 << SH7750_WCR2_A5B_S) |
(SH7750_WCR2_WS15 << SH7750_WCR2_A4W_S) | /* Area 4 not used */
(SH7750_WCR2_WS15 << SH7750_WCR2_A3W_S) | /*Area 3 not used*/
(SH7750_WCR2_SDRAM_CAS_LAT2 << SH7750_WCR2_A2W_S) | /* SDRAM CL = 2 */
(SH7750_WCR2_WS15 << SH7750_WCR2_A1W_S) | /* Area 1 (GDC)
requirements not known*/
(SH7750_WCR2_WS6 << SH7750_WCR2_A0W_S) | /* 4 wait states required
at 48MHz for 70ns mem.,
set closest greater */
(SH7750_WCR2_BPWS7 << SH7750_WCR2_A0B_S), /* burst mode disabled for
Area 0 flash ROM */
SH7750_WCR2);
write32(
SH7750_WCR3_A6S | /* Area 6 not used */
(SH7750_WCR3_DHWS_3 << SH7750_WCR3_A6H_S) |
SH7750_WCR3_A5S | /* Area 5 not used */
(SH7750_WCR3_DHWS_3 << SH7750_WCR3_A5H_S) |
SH7750_WCR3_A4S | /* Area 4 not used */
(SH7750_WCR3_DHWS_3 << SH7750_WCR3_A4H_S) |
SH7750_WCR3_A3S | /* Area 3 not used */
(SH7750_WCR3_DHWS_3 << SH7750_WCR3_A3H_S) |
SH7750_WCR3_A2S | /* SDRAM - ignored */
(SH7750_WCR3_DHWS_3 << SH7750_WCR3_A2H_S) |
SH7750_WCR3_A1S | /* GDC - unknown, set max*/
(SH7750_WCR3_DHWS_3 << SH7750_WCR3_A1H_S) |
0 | /* flash ROM - no write strobe setup time required */
(SH7750_WCR3_DHWS_0 << SH7750_WCR3_A0H_S),
SH7750_WCR3);
#define MCRDEF \
/* SH7750_MCR_RASD | */ /* Set RAS Down mode */ \
(SH7750_MCR_TRC_0 | SH7750_MCR_TRAS_SDRAM_TRC_4 | \
/* RAS precharge time is 63ns; it corresponds to 4 clocks */ \
/* TCAS valid only for DRAM interface */ \
SH7750_MCR_TPC_SDRAM_1 | /* TPC = 20ns = 1 clock */ \
SH7750_MCR_RCD_SDRAM_2 | /* RCD = 21ns = 2 clock */ \
/* After write, next active command is not issued for a period of \
TPC + TRWL. SDRAM specifies that it should be BL+Trp clocks when \
CL=2. Trp = 20ns = 1clock; BL=8. Therefore we should wait 9 \
clocks. Don't know why, but 6 clocks (TRWL=5 and TPC=1) seems \
working. May be, something wrong in documentation? */ \
SH7750_MCR_TRWL_5 | /* TRWL = 5 clock */ \
SH7750_MCR_BE | /* Always enabled for SDRAM */ \
SH7750_MCR_SZ_32 | /* Memory data size is 32 bit */ \
(4 << SH7750_MCR_AMX_S) | /* Select memory device type */ \
SH7750_MCR_RFSH | /* Refresh is performed */ \
SH7750_MCR_RMODE_NORMAL) /* Auto-Refresh mode */
#define MCRDEF \
/* SH7750_MCR_RASD | */ /* Set RAS Down mode */ \
(SH7750_MCR_TRC_0 | SH7750_MCR_TRAS_SDRAM_TRC_4 | \
/* RAS precharge time is 63ns; it corresponds to 4 clocks */ \
/* TCAS valid only for DRAM interface */ \
SH7750_MCR_TPC_SDRAM_1 | /* TPC = 20ns = 1 clock */ \
SH7750_MCR_RCD_SDRAM_2 | /* RCD = 21ns = 2 clock */ \
/* After write, next active command is not issued for a period of \
TPC + TRWL. SDRAM specifies that it should be BL+Trp clocks when \
CL=2. Trp = 20ns = 1clock; BL=8. Therefore we should wait 9 \
clocks. Don't know why, but 6 clocks (TRWL=5 and TPC=1) seems \
working. May be, something wrong in documentation? */ \
SH7750_MCR_TRWL_5 | /* TRWL = 5 clock */ \
SH7750_MCR_BE | /* Always enabled for SDRAM */ \
SH7750_MCR_SZ_32 | /* Memory data size is 32 bit */ \
(4 << SH7750_MCR_AMX_S) | /* Select memory device type */ \
SH7750_MCR_RFSH | /* Refresh is performed */ \
SH7750_MCR_RMODE_NORMAL) /* Auto-Refresh mode */
/* Clear refresh timer counter */
write16(SH7750_RTCNT_KEY | 0, SH7750_RTCNT);
/* Clear refresh timer counter */
write16(SH7750_RTCNT_KEY | 0, SH7750_RTCNT);
/* Time between auto-refresh commands is 15.6 microseconds; refresh
timer counter frequency is 12 MHz; 1.56e-5*1.2e7= 187.2, therefore
program the refresh timer divider to 187 */
write16(SH7750_RTCOR_KEY | 187, SH7750_RTCOR);
/* Time between auto-refresh commands is 15.6 microseconds; refresh
timer counter frequency is 12 MHz; 1.56e-5*1.2e7= 187.2, therefore
program the refresh timer divider to 187 */
write16(SH7750_RTCOR_KEY | 187, SH7750_RTCOR);
/* Clear refresh counter */
write16(SH7750_RFCR_KEY | 0, SH7750_RFCR);
/* Clear refresh counter */
write16(SH7750_RFCR_KEY | 0, SH7750_RFCR);
/* Select refresh counter base frequency as bus frequency/4 = 12 MHz */
write16(SH7750_RTCSR_CKS_CKIO_DIV4 | SH7750_RTCSR_KEY, SH7750_RTCSR);
/* Select refresh counter base frequency as bus frequency/4 = 12 MHz */
write16(SH7750_RTCSR_CKS_CKIO_DIV4 | SH7750_RTCSR_KEY, SH7750_RTCSR);
/* Initialize Memory Control Register; disable refresh */
write32((MCRDEF & ~SH7750_MCR_RFSH) | SH7750_MCR_PALL, SH7750_MCR);
/* Initialize Memory Control Register; disable refresh */
write32((MCRDEF & ~SH7750_MCR_RFSH) | SH7750_MCR_PALL, SH7750_MCR);
/* SDRAM power-up initialization require 100 microseconds delay after
stable power and clock fed; 100 microseconds corresponds to 7 refresh
intervals */
while (read16(SH7750_RFCR) <= 7);
/* SDRAM power-up initialization require 100 microseconds delay after
stable power and clock fed; 100 microseconds corresponds to 7 refresh
intervals */
while (read16(SH7750_RFCR) <= 7);
/* Clear refresh timer counter */
write16(SH7750_RTCNT_KEY | 0, SH7750_RTCNT);
/* Clear refresh timer counter */
write16(SH7750_RTCNT_KEY | 0, SH7750_RTCNT);
/* Clear refresh counter */
write16(SH7750_RFCR_KEY | 0, SH7750_RFCR);
/* Clear refresh counter */
write16(SH7750_RFCR_KEY | 0, SH7750_RFCR);
/* Execute Precharge All command */
write32(0, SH7750_SDRAM_MODE_A2_32BIT(0));
/* Execute Precharge All command */
write32(0, SH7750_SDRAM_MODE_A2_32BIT(0));
/* Initialize Memory Control Register; enable refresh, prepare to
SDRAM mode register setting */
write32(MCRDEF | SH7750_MCR_MRSET, SH7750_MCR);
/* Initialize Memory Control Register; enable refresh, prepare to
SDRAM mode register setting */
write32(MCRDEF | SH7750_MCR_MRSET, SH7750_MCR);
/* Wait until at least 2 auto-refresh commands to be executed */
while (read16(SH7750_RFCR) <= 10);
/* Wait until at least 2 auto-refresh commands to be executed */
while (read16(SH7750_RFCR) <= 10);
/* SDRAM data width is 32 bit (4 bytes), cache line size is 32 bytes,
therefore burst length is 8 (32 / 4) */
write8(0,SH7750_SDRAM_MODE_A2_32BIT(
SDRAM_MODE_BL_8 |
SDRAM_MODE_BT_SEQ | /* Only sequential burst mode supported
in SH7750 */
SDRAM_MODE_CL_2 | /* CAS latency is 2 */
SDRAM_MODE_OPC_BRBW) /* Burst read/burst write */
);
/* Bus State Controller initialized now */
/* SDRAM data width is 32 bit (4 bytes), cache line size is 32 bytes,
therefore burst length is 8 (32 / 4) */
write8(0,SH7750_SDRAM_MODE_A2_32BIT(
SDRAM_MODE_BL_8 |
SDRAM_MODE_BT_SEQ | /* Only sequential burst mode supported
in SH7750 */
SDRAM_MODE_CL_2 | /* CAS latency is 2 */
SDRAM_MODE_OPC_BRBW) /* Burst read/burst write */
);
/* Bus State Controller initialized now */
/* Disable DMA controller */
write32(0, SH7750_DMAOR);
/* Disable DMA controller */
write32(0, SH7750_DMAOR);
/* I/O port setup */
/* Configure all port bits as output - to fasciliate debugging */
write32(
SH7750_PCTRA_PBOUT(0) | SH7750_PCTRA_PBOUT(1) |
SH7750_PCTRA_PBOUT(2) | SH7750_PCTRA_PBOUT(3) |
SH7750_PCTRA_PBOUT(4) | SH7750_PCTRA_PBOUT(5) |
SH7750_PCTRA_PBOUT(6) | SH7750_PCTRA_PBOUT(7) |
SH7750_PCTRA_PBOUT(8) | SH7750_PCTRA_PBOUT(9) |
SH7750_PCTRA_PBOUT(10) | SH7750_PCTRA_PBOUT(11) |
SH7750_PCTRA_PBOUT(12) | SH7750_PCTRA_PBOUT(13) |
SH7750_PCTRA_PBOUT(14) | SH7750_PCTRA_PBOUT(15),
SH7750_PCTRA);
write32(
SH7750_PCTRB_PBOUT(16) | SH7750_PCTRB_PBOUT(17) |
SH7750_PCTRB_PBOUT(18) | SH7750_PCTRB_PBOUT(19),
SH7750_PCTRB);
/* Clear data in port */
write32(0, SH7750_PDTRA);
write32(0, SH7750_PDTRB);
/* I/O port setup */
/* Configure all port bits as output - to fasciliate debugging */
write32(
SH7750_PCTRA_PBOUT(0) | SH7750_PCTRA_PBOUT(1) |
SH7750_PCTRA_PBOUT(2) | SH7750_PCTRA_PBOUT(3) |
SH7750_PCTRA_PBOUT(4) | SH7750_PCTRA_PBOUT(5) |
SH7750_PCTRA_PBOUT(6) | SH7750_PCTRA_PBOUT(7) |
SH7750_PCTRA_PBOUT(8) | SH7750_PCTRA_PBOUT(9) |
SH7750_PCTRA_PBOUT(10) | SH7750_PCTRA_PBOUT(11) |
SH7750_PCTRA_PBOUT(12) | SH7750_PCTRA_PBOUT(13) |
SH7750_PCTRA_PBOUT(14) | SH7750_PCTRA_PBOUT(15),
SH7750_PCTRA);
write32(
SH7750_PCTRB_PBOUT(16) | SH7750_PCTRB_PBOUT(17) |
SH7750_PCTRB_PBOUT(18) | SH7750_PCTRB_PBOUT(19),
SH7750_PCTRB);
/* Clear data in port */
write32(0, SH7750_PDTRA);
write32(0, SH7750_PDTRB);
/* Interrupt Controller Initialization */
write16(SH7750_ICR_IRLM, SH7750_ICR); /* IRLs serves as an independent
interrupt request lines */
/* Mask all requests at this time */
write16(
(0 << SH7750_IPRA_TMU0_S) |
(0 << SH7750_IPRA_TMU1_S) |
(0 << SH7750_IPRA_TMU2_S) |
(0 << SH7750_IPRA_RTC_S),
SH7750_IPRA);
write16(
(0 << SH7750_IPRB_WDT_S) |
(0 << SH7750_IPRB_REF_S) |
(0 << SH7750_IPRB_SCI1_S),
SH7750_IPRB);
write16(
(0 << SH7750_IPRC_GPIO_S) |
(0 << SH7750_IPRC_DMAC_S) |
(0 << SH7750_IPRC_SCIF_S) |
(0 << SH7750_IPRC_HUDI_S),
SH7750_IPRC);
/* Interrupt Controller Initialization */
write16(SH7750_ICR_IRLM, SH7750_ICR); /* IRLs serves as an independent
interrupt request lines */
/* Mask all requests at this time */
write16(
(0 << SH7750_IPRA_TMU0_S) |
(0 << SH7750_IPRA_TMU1_S) |
(0 << SH7750_IPRA_TMU2_S) |
(0 << SH7750_IPRA_RTC_S),
SH7750_IPRA);
write16(
(0 << SH7750_IPRB_WDT_S) |
(0 << SH7750_IPRB_REF_S) |
(0 << SH7750_IPRB_SCI1_S),
SH7750_IPRB);
write16(
(0 << SH7750_IPRC_GPIO_S) |
(0 << SH7750_IPRC_DMAC_S) |
(0 << SH7750_IPRC_SCIF_S) |
(0 << SH7750_IPRC_HUDI_S),
SH7750_IPRC);
}
@@ -269,21 +264,20 @@ early_hw_init(void)
*/
void bsp_cache_on(void)
{
switch (boot_mode)
{
case SH4_BOOT_MODE_FLASH:
write32(SH7750_CCR_ICI | SH7750_CCR_ICE |
SH7750_CCR_OCI | SH7750_CCR_CB | SH7750_CCR_OCE,
SH7750_CCR);
break;
case SH4_BOOT_MODE_IPL:
__asm__ volatile (
"mov #6, r0\n"
"xor r4, r4\n"
"trapa #0x3f\n"
: : : "r0", "r4");
break;
default: /* unreachable */
break;
}
switch (boot_mode) {
case SH4_BOOT_MODE_FLASH:
write32(SH7750_CCR_ICI | SH7750_CCR_ICE |
SH7750_CCR_OCI | SH7750_CCR_CB | SH7750_CCR_OCE,
SH7750_CCR);
break;
case SH4_BOOT_MODE_IPL:
__asm__ volatile (
"mov #6, r0\n"
"xor r4, r4\n"
"trapa #0x3f\n"
: : : "r0", "r4");
break;
default: /* unreachable */
break;
}
}

17
c/src/lib/libbsp/sh/gensh4/include/bsp.h
View File

@@ -1,8 +1,10 @@
/*
* This include file contains all board IO definitions.
*
* generic sh4 BSP
*
* This include file contains all board IO definitions.
*/
/*
* Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
* Author: Victor V. Vengerov <vvv@oktet.ru>
*
@@ -47,6 +49,7 @@ extern "C" {
#include <rtems/console.h>
#include <bspopts.h>
#include <bsp/default-initial-extension.h>
#include <termios.h> /* for tcflag_t */
#include "rtems/score/sh7750_regs.h"
@@ -79,8 +82,16 @@ extern uint32_t boot_mode;
console_read, console_write, console_control }
/*
* NOTE: Use the standard Clock driver entry
* BSP methods that cross file boundaries.
*/
void bsp_hw_init(void);
void early_hw_init(void);
void bsp_cache_on(void);
extern int _sci_get_brparms(
tcflag_t cflag,
unsigned char *smr,
unsigned char *brr
);
#ifdef __cplusplus
}

8
c/src/lib/libbsp/sh/shared/bsphwinit.c
View File

@@ -1,7 +1,9 @@
/*
* This is a dummy bsp_hw_init routine.
*
* COPYRIGHT (c) 1989-2008.
*/
/*
* COPYRIGHT (c) 1989-2014.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
@@ -9,6 +11,8 @@
* http://www.rtems.org/license/LICENSE.
*/
#include <bsp.h>
void bsp_hw_init( void )
{
}

5
c/src/lib/libbsp/sh/shsim/console/console-debugio.c
View File

@@ -1,9 +1,6 @@
/**
* @file
* @brief Stub printk() support
*
* This file contains a stub for the required printk() support.
* It is NOT functional!!!
*/
/*
@@ -27,7 +24,7 @@ void console_outbyte_polled(
char ch
);
void BSP_output_char_f(char c)
static void BSP_output_char_f(char c)
{
console_outbyte_polled( 0, c );
}

16
c/src/lib/libbsp/sh/shsim/console/console-io.c
View File

@@ -20,20 +20,13 @@
#include <bsp/syscall.h>
int errno;
extern int __trap34(int, int, void*, int );
/*
* console_initialize_hardware
*
* This routine initializes the console hardware.
*
*/
void console_initialize_hardware(void)
{
return;
}
/*
@@ -41,14 +34,12 @@ void console_initialize_hardware(void)
*
* This routine transmits a character using polling.
*/
void console_outbyte_polled(
int port,
char ch
)
{
__trap34 (SYS_write, 1, &ch, 1);
return;
}
/*
@@ -56,7 +47,6 @@ void console_outbyte_polled(
*
* This routine polls for a character.
*/
int console_inbyte_nonblocking(
int port
)
@@ -65,9 +55,3 @@ int console_inbyte_nonblocking(
return __trap34 (SYS_read, 0, &c, 1);
}
/* XXX wrong place for this */
int _sys_exit (int n)
{
return __trap34 (SYS_exit, n, 0, 0);
}

17
c/src/lib/libbsp/sh/shsim/include/bsp.h
View File

@@ -1,8 +1,10 @@
/*
* This include file contains all board IO definitions.
*
* SH-gdb simulator BSP
*
* This include file contains all board IO definitions.
*/
/*
* Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de)
*
* COPYRIGHT (c) 2001, Ralf Corsepius, Ulm, Germany
@@ -22,6 +24,8 @@
#ifndef _BSP_H
#define _BSP_H
#ifndef ASM
#ifdef __cplusplus
extern "C" {
#endif
@@ -46,12 +50,19 @@ Thread clock_driver_sim_idle_body(uintptr_t);
/*
* Defined in the linker script 'linkcmds'
*/
extern void *CPU_Interrupt_stack_low;
extern void *CPU_Interrupt_stack_high;
/*
* BSP methods that cross file boundaries.
*/
int __trap34(int, int, void*, int );
int _sys_exit (int n);
void bsp_hw_init(void);
#ifdef __cplusplus
}
#endif
#endif /* !ASM */
#endif

1
c/src/lib/libbsp/sh/shsim/start/start.S
View File

@@ -18,6 +18,7 @@
*/
#include <rtems/asm.h>
#include <bsp.h>
BEGIN_CODE
PUBLIC(start)

21
c/src/lib/libbsp/sh/shsim/startup/sysexit.c Normal file
View File

@@ -0,0 +1,21 @@
/*
* This file contains the simulator specific exit trap.
*/
/*
* COPYRIGHT (c) 1989-2014.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <bsp.h>
extern int __trap34(int, int, void*, int );
int _sys_exit (int n)
{
return __trap34 (SYS_exit, n, 0, 0);
}

1
c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c
View File

@@ -35,6 +35,7 @@
#include <rtems/score/isr.h>
#include <rtems/score/threaddispatch.h>
#include <rtems/score/sh.h>
#include <rtems/score/ispsh7032.h>
#include <rtems/score/ispsh7032.h>
#include <rtems/score/iosh7032.h>

89
c/src/lib/libcpu/sh/sh7045/sci/sci.c
View File

@@ -8,7 +8,9 @@
* This approach is similar to installing a sym-link from one device to
* another device. If rtems once will support sym-links for devices files,
* this implementation could be dropped.
*
*/
/*
* Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
@@ -75,11 +77,11 @@
/* #define SH_SCI_DEF_COMM_1 B9600 | CS8 */
struct scidev_t {
char * name;
uint32_t addr;
rtems_device_minor_number minor;
unsigned short opened;
tcflag_t cflags;
char * name;
uint32_t addr;
rtems_device_minor_number minor;
unsigned short opened;
tcflag_t cflags;
} sci_device[SCI_MINOR_DEVICES] =
{
{ "/dev/sci0", SH_SCI_BASE_0, 0, 0, SH_SCI_DEF_COMM_0 },
@@ -104,8 +106,8 @@ static int _sci_set_cflags(
tcflag_t c_cflag
)
{
uint8_t smr;
uint8_t brr;
uint8_t smr;
uint8_t brr;
if ( c_cflag & CBAUD )
{
@@ -148,7 +150,7 @@ static int _sci_set_cflags(
* local functions operate SCI ports 0 and 1
* called from polling routines or ISRs
*/
bool wrtSCI0(unsigned char ch)
static bool wrtSCI0(unsigned char ch)
{
uint8_t temp;
bool result = false;
@@ -164,7 +166,7 @@ bool wrtSCI0(unsigned char ch)
return result;
} /* wrtSCI0 */
bool wrtSCI1(unsigned char ch)
static bool wrtSCI1(unsigned char ch)
{
uint8_t temp;
bool result = false;
@@ -181,27 +183,27 @@ bool wrtSCI1(unsigned char ch)
} /* wrtSCI1 */
/* polled output steers byte to selected port */
void sh_sci_outbyte_polled(
static void sh_sci_outbyte_polled(
rtems_device_minor_number minor,
char ch )
{
if (minor == 0) /* blocks until port ready */
while (wrtSCI0(ch) != true); /* SCI0*/
else
while (wrtSCI1(ch) != true); /* SCI1*/
if (minor == 0) /* blocks until port ready */
while (wrtSCI0(ch) != true); /* SCI0*/
else
while (wrtSCI1(ch) != true); /* SCI1*/
} /* sh_sci_outbyte_polled */
/*
* Initial version calls polled output driver and blocks
*/
void outbyte(
static void outbyte(
rtems_device_minor_number minor,
char ch)
{
sh_sci_outbyte_polled(minor, (unsigned char)ch);
sh_sci_outbyte_polled(minor, (unsigned char)ch);
} /* outbyte */
bool rdSCI0(unsigned char *ch)
static bool rdSCI0(unsigned char *ch)
{
uint8_t temp;
bool result = false;
@@ -225,7 +227,7 @@ bool rdSCI0(unsigned char *ch)
return result;
} /* rdSCI0 */
bool rdSCI1(unsigned char *ch)
static bool rdSCI1(unsigned char *ch)
{
uint8_t temp;
bool result = false;
@@ -249,9 +251,8 @@ bool rdSCI1(unsigned char *ch)
return result;
} /* rdSCI1 */
/* initial version pulls byte from selected port */
char sh_sci_inbyte_polled( rtems_device_minor_number minor )
static char sh_sci_inbyte_polled( rtems_device_minor_number minor )
{
uint8_t ch = 0;
@@ -263,7 +264,7 @@ char sh_sci_inbyte_polled( rtems_device_minor_number minor )
} /* sh_sci_inbyte_polled */
/* Initial version calls polled input driver */
char inbyte( rtems_device_minor_number minor )
static char inbyte( rtems_device_minor_number minor )
{
char ch;
@@ -271,7 +272,6 @@ char inbyte( rtems_device_minor_number minor )
return ch;
} /* inbyte */
/* sh_sci_initialize
*
* This routine initializes (registers) the sh_sci IO drivers.
@@ -283,9 +283,7 @@ char inbyte( rtems_device_minor_number minor )
* Return values: RTEMS_SUCCESSFUL
* if all sci[...] register, else calls
* rtems_fatal_error_occurred(status)
*
*/
rtems_device_driver sh_sci_initialize(
rtems_device_major_number major,
rtems_device_minor_number minor,
@@ -295,7 +293,6 @@ rtems_device_driver sh_sci_initialize(
rtems_device_minor_number i;
rtems_driver_name_t driver;
/*
* register all possible devices.
* the initialization of the hardware is done by sci_open
@@ -303,19 +300,17 @@ rtems_device_driver sh_sci_initialize(
* One of devices could be previously registered by console
* initialization therefore we check it everytime
*/
for ( i = 0 ; i < SCI_MINOR_DEVICES ; i++ )
{
for ( i = 0 ; i < SCI_MINOR_DEVICES ; i++ ) {
status = rtems_io_lookup_name(
sci_device[i].name,
&driver);
if ( status != RTEMS_SUCCESSFUL )
{
if ( status != RTEMS_SUCCESSFUL ) {
/* OK. We assume it is not registered yet. */
status = rtems_io_register_name(
sci_device[i].name,
major,
sci_device[i].minor );
sci_device[i].minor
);
if (status != RTEMS_SUCCESSFUL)
rtems_fatal_error_occurred(status);
}
@@ -326,31 +321,27 @@ rtems_device_driver sh_sci_initialize(
return RTEMS_SUCCESSFUL;
}
/*
* Open entry point
* Sets up port and pins for selected sci.
*/
rtems_device_driver sh_sci_open(
rtems_device_major_number major,
rtems_device_minor_number minor,
void * arg )
{
uint8_t temp8;
uint8_t temp8;
uint16_t temp16;
unsigned a;
unsigned a;
/* check for valid minor number */
if (( minor > ( SCI_MINOR_DEVICES -1 )) || ( minor < 0 ))
{
return RTEMS_INVALID_NUMBER;
}
if (( minor > ( SCI_MINOR_DEVICES -1 )) || ( minor < 0 )) {
return RTEMS_INVALID_NUMBER;
}
/* device already opened */
if ( sci_device[minor].opened > 0 )
{
if ( sci_device[minor].opened > 0 ) {
sci_device[minor].opened++;
return RTEMS_SUCCESSFUL;
}
@@ -372,7 +363,7 @@ rtems_device_driver sh_sci_open(
} /* add other devices and pins as req'd. */
/* set up SCI registers */
write8(0x00, sci_device[minor].addr + SCI_SCR); /* Clear SCR */
write8(0x00, sci_device[minor].addr + SCI_SCR); /* Clear SCR */
/* set SMR and BRR */
_sci_set_cflags( &sci_device[minor], sci_device[minor].cflags );
@@ -381,7 +372,7 @@ rtems_device_driver sh_sci_open(
}
write8((SCI_RE | SCI_TE), /* enable async. Tx and Rx */
sci_device[minor].addr + SCI_SCR);
sci_device[minor].addr + SCI_SCR);
/* clear error flags */
temp8 = read8(sci_device[minor].addr + SCI_SSR);
@@ -409,7 +400,6 @@ rtems_device_driver sh_sci_open(
/*
* Close entry point
*/
rtems_device_driver sh_sci_close(
rtems_device_major_number major,
rtems_device_minor_number minor,
@@ -428,7 +418,6 @@ rtems_device_driver sh_sci_close(
/*
* read bytes from the serial port. We only have stdin.
*/
rtems_device_driver sh_sci_read(
rtems_device_major_number major,
rtems_device_minor_number minor,
@@ -460,7 +449,6 @@ rtems_device_driver sh_sci_read(
/*
* write bytes to the serial port. Stdout and stderr are the same.
*/
rtems_device_driver sh_sci_write(
rtems_device_major_number major,
rtems_device_minor_number minor,
@@ -491,7 +479,6 @@ rtems_device_driver sh_sci_write(
/*
* IO Control entry point
*/
rtems_device_driver sh_sci_control(
rtems_device_major_number major,
rtems_device_minor_number minor,
@@ -573,7 +560,7 @@ const rtems_termios_callbacks sci_interrupt_callbacks;
const rtems_termios_callbacks* sh_sci_get_termios_handlers( bool poll )
{
return poll ?
&sci_poll_callbacks :
&sci_interrupt_callbacks;
return poll ?
&sci_poll_callbacks :
&sci_interrupt_callbacks;
}

8
c/src/lib/libcpu/sh/sh7045/sci/sci_termios.c
View File

@@ -1,6 +1,8 @@
/*
* Termios console serial driver.
*
*/
/*
* Based on SCI driver by Ralf Corsepius and John M. Mills
*
* Author: Radzislaw Galler <rgaller@et.put.poznan.pl>
@@ -124,7 +126,7 @@ int sh_sci_set_attributes(
*
* The same routine for all interrupt sources of the same type.
*/
rtems_isr sh_sci_rx_isr(rtems_vector_number vector)
static rtems_isr sh_sci_rx_isr(rtems_vector_number vector)
{
int minor;
@@ -151,7 +153,7 @@ rtems_isr sh_sci_rx_isr(rtems_vector_number vector)
*
* The same routine for all interrupt sources of the same type.
*/
rtems_isr sh_sci_tx_isr(rtems_vector_number vector)
static rtems_isr sh_sci_tx_isr(rtems_vector_number vector)
{
int minor;

7
c/src/lib/libcpu/sh/sh7750/sci/sh4uart.c
View File

@@ -77,7 +77,7 @@ sh4uart_init(sh4uart *uart, void *tty, int chn, int int_driven)
* RETURNS:
* peripheral module clock in Hz.
*/
uint32_t
static uint32_t
sh4uart_get_Pph(void)
{
uint16_t frqcr = *(volatile uint16_t*)SH7750_FRQCR;
@@ -418,7 +418,7 @@ sh4uart_set_attributes(sh4uart *uart, const struct termios *t)
* RETURNS:
* nothing
*/
void
static void
sh4uart_handle_error(sh4uart *uart)
{
if (uart->chn == SH4_SCI) {
@@ -451,7 +451,6 @@ int
sh4uart_poll_read(sh4uart *uart)
{
int chn = uart->chn;
int error_occured = 0;
int parity_error = 0;
int break_occured = 0;
int ch;
@@ -464,7 +463,6 @@ sh4uart_poll_read(sh4uart *uart)
if (chn == SH4_SCI) {
if ((SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER |
SH7750_SCSSR1_ORER)) != 0) {
error_occured = 1;
if (SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER))
parity_error = 1;
sh4uart_handle_error(uart);
@@ -475,7 +473,6 @@ sh4uart_poll_read(sh4uart *uart)
if ((SCSSR2 & (SH7750_SCSSR2_ER | SH7750_SCSSR2_DR |
SH7750_SCSSR2_BRK)) != 0 ||
(SCLSR2 & SH7750_SCLSR2_ORER) != 0) {
error_occured = 1;
if (SCSSR2 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER))
parity_error = 1;
if (SCSSR2 & SH7750_SCSSR2_BRK)

7
c/src/lib/libcpu/sh/shgdb/score/cpu_asm.c
View File

@@ -1,6 +1,8 @@
/*
* Support for SuperH Simulator in GDB
*
*/
/*
* COPYRIGHT (c) 1989-2008.
* On-Line Applications Research Corporation (OAR).
*
@@ -22,10 +24,11 @@
register unsigned long *stack_ptr __asm__ ("r15");
void __ISR_Handler(uint32_t vector);
/*
* This routine provides the RTEMS interrupt management.
*/
void __ISR_Handler( uint32_t vector)
{
ISR_Level level;