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2011-02-11 Ralf Corsépius <ralf.corsepius@rtems.org>

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* context.c, cpu.c, rtems/score/cpu.h, rtems/score/sh.h:
	Use "__asm__" instead of "asm" for improved c99-compliance.
This commit is contained in:
Ralf Corsepius
2011-02-11 08:56:10 +00:00
parent f8958d9c7d
commit 05d72d5e09
5 changed files with 22 additions and 17 deletions
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5
cpukit/score/cpu/sh/ChangeLog
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@@ -1,3 +1,8 @@
2011-02-11 Ralf Corsépius <ralf.corsepius@rtems.org>
* context.c, cpu.c, rtems/score/cpu.h, rtems/score/sh.h:
Use "__asm__" instead of "asm" for improved c99-compliance.
2010-10-21 Joel Sherrill <joel.sherrill@oarcorp.com>
* rtems/score/cpu.h: Add RTEMS_COMPILER_NO_RETURN_ATTRIBUTE to

2
cpukit/score/cpu/sh/context.c
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@@ -201,7 +201,7 @@ __CPU_Context_switch:\n\
:: "i" (sizeof(Context_Control))
);
asm volatile("\n\
__asm__ volatile("\n\
.global __CPU_Context_restore\n\
__CPU_Context_restore:\n\
mov.l @r4+,r15\n\

4
cpukit/score/cpu/sh/cpu.c
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@@ -113,7 +113,7 @@ void _CPU_ISR_install_raw_handler(
#endif
/* get vbr */
asm ( "stc vbr,%0" : "=r" (vbr) );
__asm__ ( "stc vbr,%0" : "=r" (vbr) );
*old_handler = vbr[vector] ;
vbr[vector] = new_handler ;
@@ -191,7 +191,7 @@ void *_CPU_Thread_Idle_body( uintptr_t ignored )
for( ; ; )
{
asm volatile("nop");
__asm__ volatile("nop");
}
/* insert your "halt" instruction here */ ;
}

6
cpukit/score/cpu/sh/rtems/score/cpu.h
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@@ -670,9 +670,9 @@ SCORE_EXTERN void _CPU_Context_Initialize(
#else
#define _CPU_Fatal_halt( _error)\
{ \
asm volatile("mov.l %0,r0"::"m" (_error)); \
asm volatile("mov #1, r4"); \
asm volatile("trapa #34"); \
__asm__ volatile("mov.l %0,r0"::"m" (_error)); \
__asm__ volatile("mov #1, r4"); \
__asm__ volatile("trapa #34"); \
}
#endif

22
cpukit/score/cpu/sh/rtems/score/sh.h
View File

@@ -104,14 +104,14 @@ extern "C" {
#define SH_IRQDIS_VALUE 0xf0
#define sh_disable_interrupts( _level ) \
asm volatile ( \
__asm__ volatile ( \
"stc sr,%0\n\t" \
"ldc %1,sr\n\t"\
: "=&r" (_level ) \
: "r" (SH_IRQDIS_VALUE) );
#define sh_enable_interrupts( _level ) \
asm volatile( "ldc %0,sr\n\t" \
__asm__ volatile( "ldc %0,sr\n\t" \
"nop\n\t" \
:: "r" (_level) );
@@ -123,7 +123,7 @@ extern "C" {
*/
#define sh_flash_interrupts( _level ) \
asm volatile( \
__asm__ volatile( \
"ldc %1,sr\n\t" \
"nop\n\t" \
"ldc %0,sr\n\t" \
@@ -135,7 +135,7 @@ extern "C" {
#define SH_IRQDIS_MASK 0xf0
#define sh_disable_interrupts( _level ) \
asm volatile ( \
__asm__ volatile ( \
"stc sr,%0\n\t" \
"mov %0,r5\n\t" \
"or %1,r5\n\t" \
@@ -145,7 +145,7 @@ extern "C" {
: "r5" );
#define sh_enable_interrupts( _level ) \
asm volatile( "ldc %0,sr\n\t" \
__asm__ volatile( "ldc %0,sr\n\t" \
"nop\n\t" \
:: "r" (_level) );
@@ -157,7 +157,7 @@ extern "C" {
*/
#define sh_flash_interrupts( _level ) \
asm volatile( \
__asm__ volatile( \
"stc sr,r5\n\t" \
"ldc %1,sr\n\t" \
"nop\n\t" \
@@ -172,7 +172,7 @@ extern "C" {
{ \
register uint32_t _tmpsr ; \
\
asm volatile( "stc sr, %0" : "=r" (_tmpsr) ); \
__asm__ volatile( "stc sr, %0" : "=r" (_tmpsr) ); \
_level = (_tmpsr & 0xf0) >> 4 ; \
}
@@ -180,9 +180,9 @@ extern "C" {
{ \
register uint32_t _tmpsr; \
\
asm volatile ( "stc sr, %0" : "=r" (_tmpsr) ); \
__asm__ volatile ( "stc sr, %0" : "=r" (_tmpsr) ); \
_tmpsr = ( _tmpsr & ~0xf0 ) | ((_newlevel) << 4) ; \
asm volatile( "ldc %0,sr" :: "r" (_tmpsr) ); \
__asm__ volatile( "ldc %0,sr" :: "r" (_tmpsr) ); \
}
/*
@@ -196,7 +196,7 @@ static inline uint32_t sh_swap_u32(
{
register uint32_t swapped;
asm volatile (
__asm__ volatile (
"swap.b %1,%0; "
"swap.w %0,%0; "
"swap.b %0,%0"
@@ -212,7 +212,7 @@ static inline uint16_t sh_swap_u16(
{
register uint16_t swapped ;
asm volatile ( "swap.b %1,%0" : "=r" (swapped) : "r" (value) );
__asm__ volatile ( "swap.b %1,%0" : "=r" (swapped) : "r" (value) );
return( swapped );
}