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101 lines
2.7 KiB
C
101 lines
2.7 KiB
C
#include "uart.h"
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#include "csr.h"
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#include "plic.h"
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#include <stdint.h>
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// the UART control registers are memory-mapped
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// at address UART0. this macro returns the
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// address of one of the registers.
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#define Reg(reg) ((volatile unsigned char *)(UART0 + (reg)))
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// the UART control registers.
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// some have different meanings for
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// read vs write.
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// see http://byterunner.com/16550.html
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#define RHR 0 // receive holding register (for input bytes)
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#define THR 0 // transmit holding register (for output bytes)
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#define IER 1 // interrupt enable register
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#define IER_RX_ENABLE (1<<0)
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#define IER_TX_ENABLE (1<<1)
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#define FCR 2 // FIFO control register
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#define FCR_FIFO_ENABLE (1<<0)
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#define FCR_FIFO_CLEAR (3<<1) // clear the content of the two FIFOs
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#define ISR 2 // interrupt status register
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#define LCR 3 // line control register
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#define LCR_EIGHT_BITS (3<<0)
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#define LCR_BAUD_LATCH (1<<7) // special mode to set baud rate
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#define LSR 5 // line status register
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#define LSR_RX_READY (1<<0) // input is waiting to be read from RHR
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#define LSR_TX_IDLE (1<<5) // THR can accept another character to send
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#define ReadReg(reg) (*(Reg(reg)))
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#define WriteReg(reg, v) (*(Reg(reg)) = (v))
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int uart_init(void)
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{
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// disable interrupts.
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WriteReg(IER, 0x00);
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// special mode to set baud rate.
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WriteReg(LCR, LCR_BAUD_LATCH);
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// LSB for baud rate of 38.4K.
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WriteReg(0, 0x03);
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// MSB for baud rate of 38.4K.
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WriteReg(1, 0x00);
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// leave set-baud mode,
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// and set word length to 8 bits, no parity.
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WriteReg(LCR, LCR_EIGHT_BITS);
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// reset and enable FIFOs.
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WriteReg(FCR, FCR_FIFO_ENABLE | FCR_FIFO_CLEAR);
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// enable transmit and receive interrupts.
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// WriteReg(IER, IER_TX_ENABLE | IER_RX_ENABLE);
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//enable UART0 in PLIC
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plic_irq_enable(UART0_IRQ);
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//set UART0 priority in PLIC
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plic_prio_set(UART0_IRQ, 1);
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//register callback for UART0
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//plic_register_callback(UART0_IRQ, uart_intr);
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puts("[UART0] : Uart Init Done, this is Test output!");
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return 0;
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}
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static inline void uart_putc_nolock(int ch)
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{
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// wait for Transmit Holding Empty to be set in LSR.
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while((ReadReg(LSR) & LSR_TX_IDLE) == 0)
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;
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WriteReg(THR, ch);
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return;
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}
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int uart_putc(int ch)
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{
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int intr_enable = riscv_mintr_get();
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riscv_mintr_off();
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uart_putc_nolock(ch);
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riscv_mintr_restore(intr_enable);
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return 1;
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}
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int uart_puts(const char* str)
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{
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int i;
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int intr_enable = riscv_mintr_get();
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riscv_mintr_off();
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for(i=0;str[i]!=0;i++)
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{
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uart_putc_nolock(str[i]);
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}
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uart_putc_nolock('\n');
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riscv_mintr_restore(intr_enable);
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return i;
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}
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