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9 Commits
v6.1.2_rel ... v6.1.5_rel

Author SHA1 Message Date
Yuxin Zhou
10a7932b9d Release 6.1.5 2021-03-05 05:38:33 +00:00
Scott Larson
32e3b3b25f add cmake for rx 2021-01-08 15:50:14 -08:00
Scott Larson
f108ebdbaf update to v6.1.3 2021-01-08 13:31:36 -08:00
Scott Larson
b0e9b132b5 update nxp 2020-12-15 10:11:38 -08:00
Scott Larson
848e7d8169 add mediatek 2020-12-11 14:51:05 -08:00
Scott Larson
69287b8bb4 update workflows 2020-12-09 10:57:26 -08:00
Scott Larson
1777796996 Update ci_cortex_m0.yml 2020-12-07 14:56:14 -08:00
Scott Larson
64b4d510ba Update ci_cortex_m0.yml 2020-12-07 14:38:48 -08:00
Scott Larson
609c75a2e5 add ST to hw list 2020-11-17 09:32:36 -08:00
636 changed files with 113281 additions and 6452 deletions
Expand all files Collapse all files

6
.github/workflows/ci_cortex_m0.yml vendored
View File

@@ -43,12 +43,12 @@ jobs:
directory: $HOME/arm-none-eabi-gcc-9-2019-q4
# Get CMake into the environment
- name: Install cmake 3.17.1
uses: lukka/get-cmake@v3.17.1
- name: Install cmake 3.19.1
uses: lukka/get-cmake@v3.19.1
# Get Ninja into the environment
- name: Install ninja-build
uses: seanmiddleditch/gha-setup-ninja@v1
uses: seanmiddleditch/gha-setup-ninja@v3
# Prepare the build system
- name: Prepare build system

6
.github/workflows/ci_cortex_m3.yml vendored
View File

@@ -43,12 +43,12 @@ jobs:
directory: $HOME/arm-none-eabi-gcc-9-2019-q4
# Get CMake into the environment
- name: Install cmake 3.17.1
uses: lukka/get-cmake@v3.17.1
- name: Install cmake 3.19.1
uses: lukka/get-cmake@v3.19.1
# Get Ninja into the environment
- name: Install ninja-build
uses: seanmiddleditch/gha-setup-ninja@v1
uses: seanmiddleditch/gha-setup-ninja@v3
# Prepare the build system
- name: Prepare build system

6
.github/workflows/ci_cortex_m4.yml vendored
View File

@@ -43,12 +43,12 @@ jobs:
directory: $HOME/arm-none-eabi-gcc-9-2019-q4
# Get CMake into the environment
- name: Install cmake 3.17.1
uses: lukka/get-cmake@v3.17.1
- name: Install cmake 3.19.1
uses: lukka/get-cmake@v3.19.1
# Get Ninja into the environment
- name: Install ninja-build
uses: seanmiddleditch/gha-setup-ninja@v1
uses: seanmiddleditch/gha-setup-ninja@v3
# Prepare the build system
- name: Prepare build system

6
.github/workflows/ci_cortex_m7.yml vendored
View File

@@ -43,12 +43,12 @@ jobs:
directory: $HOME/arm-none-eabi-gcc-9-2019-q4
# Get CMake into the environment
- name: Install cmake 3.17.1
uses: lukka/get-cmake@v3.17.1
- name: Install cmake 3.19.1
uses: lukka/get-cmake@v3.19.1
# Get Ninja into the environment
- name: Install ninja-build
uses: seanmiddleditch/gha-setup-ninja@v1
uses: seanmiddleditch/gha-setup-ninja@v3
# Prepare the build system
- name: Prepare build system

17
LICENSED-HARDWARE.txt
View File

@@ -1,6 +1,6 @@
LICENSED HARDWARE LIST
Last Updated: 2020-10-15
Last Updated: 2020-12-15
Microsoft has entered into OEM Agreements with manufacturers of the following
microprocessors and microcontrollers (the “hardware”) to enable those
@@ -11,6 +11,16 @@ Production Use” rights in Section 2 of the Microsoft Software License Terms fo
Microsoft Azure RTOS. If hardware is not listed below, you do not have those
rights.
STMicroelectronics:
STM32 MCUs
STM32 MPUs
MediaTek:
MT3620 MCU (Azure Sphere)
Microchip:
PIC 32-bit MCUs
@@ -18,7 +28,8 @@ Microchip:
SAM 32-bit MPUs
NXP:
i.MX RT105x/6x cross over MCUs
NXP i.MX RT10xx series crossover MCUs
Renesas:
@@ -28,4 +39,4 @@ Renesas:
--------------------------------------------------------------------------------
More coming soon. Please check back frequently for updates.
More coming soon. Please check back frequently for updates.

4
README.md
View File

@@ -36,7 +36,7 @@ $ git clone https://github.com/azure-rtos/threadx.git
## Building as a static library
Each component of Azure RTOS comes with a composible CMake-based build system that supports many different MCUs and host systems. Integrating any of these components into your device app code is as simple as adding a git submodule and then including it in your build using the CMake command `add_subdirectory()`.
Each component of Azure RTOS comes with a composable CMake-based build system that supports many different MCUs and host systems. Integrating any of these components into your device app code is as simple as adding a git submodule and then including it in your build using the CMake command `add_subdirectory()`.
While the typical usage pattern is to include threadx into your device code source tree to be built & linked with your code, you can compile this project as a standalone static library to confirm your build is set up correctly.
@@ -103,7 +103,7 @@ The following are references to additional Azure RTOS and Azure IoT in general:
| | |
|---|---|
| TraceX Installer | https://aka.ms/azrtos-tracex-installer |
| Azure RTOS Documenation and Guides: | https://docs.microsoft.com/azure/rtos |
| Azure RTOS Documentation and Guides: | https://docs.microsoft.com/azure/rtos |
| Azure RTOS Website: | https://azure.microsoft.com/services/rtos/ |
| Azure RTOS Sales Questions: | https://azure-rtos.ms-iot-contact.com/ |
| For technical questions check out Microsoft Q/A for Azure IoT: | https://aka.ms/QnA/azure-rtos |

34
common/inc/tx_api.h
View File

@@ -26,7 +26,7 @@
/* APPLICATION INTERFACE DEFINITION RELEASE */
/* */
/* tx_api.h PORTABLE C */
/* 6.1.2 */
/* 6.1.5 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -43,21 +43,29 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 05-19-2020 William E. Lamie Initial Version 6.0 */
/* 09-30-2020 William E. Lamie Modified comment(s), and */
/* 05-19-2020 William E. Lamie Initial Version 6.0 */
/* 09-30-2020 William E. Lamie Modified comment(s), and */
/* updated product constants, */
/* added new thread execution */
/* state TX_PRIORITY_CHANGE, */
/* added macros for casting */
/* pointers to ALIGN_TYPE, */
/* resulting in version 6.1 */
/* 10-16-2020 William E. Lamie Modified comment(s), and */
/* 10-16-2020 William E. Lamie Modified comment(s), and */
/* increased patch version, */
/* resulting in version 6.1.1 */
/* 11-09-2020 Yuxin Zhou Modified comment(s), and */
/* 11-09-2020 Yuxin Zhou Modified comment(s), and */
/* moved TX_THREAD_GET_SYSTEM_ */
/* STATE to tx_api.h, */
/* resulting in version 6.1.2 */
/* 12-31-2020 William E. Lamie Modified comment(s), and */
/* increased patch version, */
/* resulting in version 6.1.3 */
/* 03-02-2021 Scott Larson Modified comment(s), and */
/* order defines numerically, */
/* add option to remove FileX */
/* pointer, */
/* resulting in version 6.1.5 */
/* */
/**************************************************************************/
@@ -90,7 +98,7 @@ extern "C" {
#define AZURE_RTOS_THREADX
#define THREADX_MAJOR_VERSION 6
#define THREADX_MINOR_VERSION 1
#define THREADX_PATCH_VERSION 2
#define THREADX_PATCH_VERSION 5
/* Define the following symbol for backward compatibility */
#define EL_PRODUCT_THREADX
@@ -151,7 +159,6 @@ extern "C" {
#define TX_SUCCESS ((UINT) 0x00)
#define TX_DELETED ((UINT) 0x01)
#define TX_NO_MEMORY ((UINT) 0x10)
#define TX_POOL_ERROR ((UINT) 0x02)
#define TX_PTR_ERROR ((UINT) 0x03)
#define TX_WAIT_ERROR ((UINT) 0x04)
@@ -166,6 +173,7 @@ extern "C" {
#define TX_NO_INSTANCE ((UINT) 0x0D)
#define TX_THREAD_ERROR ((UINT) 0x0E)
#define TX_PRIORITY_ERROR ((UINT) 0x0F)
#define TX_NO_MEMORY ((UINT) 0x10)
#define TX_START_ERROR ((UINT) 0x10)
#define TX_DELETE_ERROR ((UINT) 0x11)
#define TX_RESUME_ERROR ((UINT) 0x12)
@@ -419,8 +427,10 @@ typedef struct TX_THREAD_STRUCT
TX_THREAD_EXTENSION_2
/* Define a pointer type for FileX extensions. */
#ifndef TX_NO_FILEX_POINTER
VOID *tx_thread_filex_ptr;
#endif
/* Define the priority inheritance variables. These will be used
to manage priority inheritance changes applied to this thread
as a result of mutex get operations. */
@@ -1089,7 +1099,6 @@ UINT _tx_trace_interrupt_control(UINT new_posture);
#ifdef TX_ENABLE_MULTI_ERROR_CHECKING
/* Services with MULTI runtime error checking ThreadX. */
#define tx_block_allocate _txr_block_allocate
@@ -1787,7 +1796,6 @@ VOID _tx_misra_user_timer_pointer_get(TX_TIMER_INTERNAL *inte
VOID _tx_misra_thread_stack_check(TX_THREAD *thread_ptr, VOID **highest_stack);
VOID _tx_misra_trace_event_insert(ULONG event_id, VOID *info_field_1, ULONG info_field_2, ULONG info_field_3, ULONG info_field_4, ULONG filter, ULONG time_stamp);
UINT _tx_misra_always_true(void);
UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **pointer);
UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer);
UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool);
@@ -1820,7 +1828,6 @@ VOID _tx_misra_semaphore_put_notify_not_used(VOID (*semaphore
VOID _tx_misra_thread_not_used(TX_THREAD *thread_ptr);
VOID _tx_misra_thread_entry_exit_notify_not_used(VOID (*thread_entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT id));
#define TX_MEMSET(a,b,c) _tx_misra_memset((a), (UINT) (b), (UINT) (c))
#define TX_UCHAR_POINTER_ADD(a,b) _tx_misra_uchar_pointer_add((UCHAR *) (a), (ULONG) (b))
#define TX_UCHAR_POINTER_SUB(a,b) _tx_misra_uchar_pointer_sub((UCHAR *) (a), (ULONG) (b))
@@ -1839,8 +1846,6 @@ VOID _tx_misra_thread_entry_exit_notify_not_used(VOID (*threa
#define TX_TRACE_IN_LINE_INSERT(i,a,b,c,d,e) _tx_misra_trace_event_insert((ULONG) (i), (VOID *) (a), (ULONG) (b), (ULONG) (c), (ULONG) (d), (ULONG) (e), ((ULONG) TX_TRACE_TIME_SOURCE));
#endif
#define TX_LOOP_FOREVER (_tx_misra_always_true() == TX_TRUE)
#define TX_INDIRECT_VOID_TO_UCHAR_POINTER_CONVERT(a) _tx_misra_indirect_void_to_uchar_pointer_convert((a))
#define TX_UCHAR_TO_INDIRECT_UCHAR_POINTER_CONVERT(a) _tx_misra_uchar_to_indirect_uchar_pointer_convert((a))
#define TX_BLOCK_POOL_TO_UCHAR_POINTER_CONVERT(a) _tx_misra_block_pool_to_uchar_pointer_convert((a))
@@ -1876,7 +1881,6 @@ VOID _tx_misra_thread_entry_exit_notify_not_used(VOID (*threa
#define TX_THREAD_NOT_USED(a) _tx_misra_thread_not_used((a))
#define TX_THREAD_ENTRY_EXIT_NOTIFY_NOT_USED(a) _tx_misra_thread_entry_exit_notify_not_used((a))
#else
/* Define the TX_MEMSET macro to the standard library function, if not already defined. */
@@ -1905,8 +1909,6 @@ VOID _tx_misra_thread_entry_exit_notify_not_used(VOID (*threa
(b) = (TX_TIMER *) working_ptr; \
}
#define TX_LOOP_FOREVER ((UINT) 1)
#define TX_INDIRECT_VOID_TO_UCHAR_POINTER_CONVERT(a) ((UCHAR **) ((VOID *) (a)))
#define TX_UCHAR_TO_INDIRECT_UCHAR_POINTER_CONVERT(a) ((UCHAR **) ((VOID *) (a)))
#define TX_BLOCK_POOL_TO_UCHAR_POINTER_CONVERT(a) ((UCHAR *) ((VOID *) (a)))

21
common/inc/tx_user_sample.h
View File

@@ -26,7 +26,7 @@
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_user.h PORTABLE C */
/* 6.1 */
/* 6.1.5 */
/* */
/* AUTHOR */
/* */
@@ -44,9 +44,13 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 05-19-2020 William E. Lamie Initial Version 6.0 */
/* 09-30-2020 Yuxin Zhou Modified comment(s), */
/* 05-19-2020 William E. Lamie Initial Version 6.0 */
/* 09-30-2020 Yuxin Zhou Modified comment(s), */
/* resulting in version 6.1 */
/* 03-02-2021 Scott Larson Modified comment(s), */
/* added option to remove */
/* FileX pointer, */
/* resulting in version 6.1.5 */
/* */
/**************************************************************************/
@@ -76,6 +80,7 @@
TX_DISABLE_PREEMPTION_THRESHOLD
TX_DISABLE_REDUNDANT_CLEARING
TX_DISABLE_NOTIFY_CALLBACKS
TX_NO_FILEX_POINTER
TX_NOT_INTERRUPTABLE
TX_TIMER_PROCESS_IN_ISR
@@ -98,6 +103,16 @@
#define TX_TIMER_THREAD_PRIORITY ????
*/
/* Determine if there is a FileX pointer in the thread control block.
By default, the pointer is there for legacy/backwards compatibility.
The pointer must also be there for applications using FileX.
Define this to save space in the thread control block.
*/
/*
#define TX_NO_FILEX_POINTER
*/
/* Determine if timer expirations (application timers, timeouts, and tx_thread_sleep calls
should be processed within the a system timer thread or directly in the timer ISR.
By default, the timer thread is used. When the following is defined, the timer expiration

55
common_modules/inc/txm_module.h
View File

@@ -10,37 +10,40 @@
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Module Interface (API) */
/** */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Module Interface (API) */
/** */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/* */
/* APPLICATION INTERFACE DEFINITION RELEASE */
/* */
/* txm_module.h PORTABLE C */
/* 6.1 */
/**************************************************************************/
/* */
/* APPLICATION INTERFACE DEFINITION RELEASE */
/* */
/* txm_module.h PORTABLE C */
/* 6.1.3 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This file defines the basic module constants, interface structures, */
/* and function prototypes. */
/* */
/* RELEASE HISTORY */
/* */
/* DESCRIPTION */
/* */
/* This file defines the basic module constants, interface structures, */
/* and function prototypes. */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 12-31-2020 Scott Larson Modified comment(s), added */
/* port-specific extension, */
/* resulting in version 6.1.3 */
/* */
/**************************************************************************/
@@ -329,6 +332,8 @@ extern "C" {
#define TXM_MODULE_OBJECT_ALLOCATE_CALL 95
#define TXM_MODULE_OBJECT_DEALLOCATE_CALL 96
#define TXM_MODULE_PORT_EXTENSION_API_ID_START 500
#define TXM_MODULE_PORT_EXTENSION_API_ID_END 999
/* Determine the API call IDs for other components. */
@@ -508,7 +513,7 @@ typedef struct TXM_MODULE_ALLOCATED_OBJECT_STRUCT
*txm_module_allocated_object_next,
*txm_module_allocated_object_previous;
ULONG txm_module_object_size;
} TXM_MODULE_ALLOCATED_OBJECT;
} TXM_MODULE_ALLOCATED_OBJECT;
/* Determine if module code is being compiled. If so, remap the ThreadX API to
@@ -571,6 +576,7 @@ VOID _txm_module_usbx_duo_callback_request(TXM_MODULE_CALLBACK_MESSAGE *callbac
resident portion of the application. */
#define txm_module_manager_initialize _txm_module_manager_initialize
#define txm_module_manager_absolute_load _txm_module_manager_absolute_load
#define txm_module_manager_in_place_load _txm_module_manager_in_place_load
#define txm_module_manager_file_load _txm_module_manager_file_load
#define txm_module_manager_memory_load _txm_module_manager_memory_load
@@ -607,6 +613,7 @@ UINT _txm_module_manager_application_request(ULONG request, ALIGN_TYPE param_1,
UINT _txm_module_manager_file_load(TXM_MODULE_INSTANCE *module_instance, CHAR *module_name, FX_MEDIA *media_ptr, CHAR *file_name);
#endif
UINT _txm_module_manager_initialize(VOID *module_memory_start, ULONG module_memory_size);
UINT _txm_module_manager_absolute_load(TXM_MODULE_INSTANCE *module_instance, CHAR *name, VOID *module_location);
UINT _txm_module_manager_in_place_load(TXM_MODULE_INSTANCE *module_instance, CHAR *name, VOID *module_location);
UINT _txm_module_manager_internal_load(TXM_MODULE_INSTANCE *module_instance, CHAR *name, VOID *module_location,
ULONG code_size, VOID *code_allocation_ptr, ULONG code_allocation_size);

439
common_modules/module_manager/src/txm_module_manager_absolute_load.c Normal file
View File

@@ -0,0 +1,439 @@
/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Module Manager */
/** */
/**************************************************************************/
/**************************************************************************/
#define TX_SOURCE_CODE
#include "tx_api.h"
#include "tx_initialize.h"
#include "tx_mutex.h"
#include "tx_thread.h"
#include "tx_byte_pool.h"
#include "txm_module.h"
#include "txm_module_manager_util.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_absolute_load PORTABLE C */
/* 6.1.3 */
/* AUTHOR */
/* */
/* Andres Mlinar, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function ensures the code-related and data-related parts of */
/* the module preamble are valid and prepares the module for */
/* execution. */
/* */
/* INPUT */
/* */
/* module_instance Module instance pointer */
/* module_name Module name pointer */
/* module_location Module code location */
/* */
/* OUTPUT */
/* */
/* status Completion status */
/* */
/* CALLS */
/* */
/* _tx_byte_allocate Allocate data area */
/* _tx_mutex_get Get protection mutex */
/* _tx_mutex_put Release protection mutex */
/* */
/* CALLED BY */
/* */
/* Application code */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */
/* */
/**************************************************************************/
UINT _txm_module_manager_absolute_load(TXM_MODULE_INSTANCE *module_instance, CHAR *module_name, VOID *module_location)
{
TX_INTERRUPT_SAVE_AREA
TXM_MODULE_PREAMBLE *module_preamble;
ULONG code_size;
ULONG code_alignment;
ULONG code_allocation_size_ignored;
UINT status;
TXM_MODULE_INSTANCE *next_module, *previous_module;
ULONG start_stop_stack_size;
ULONG callback_stack_size;
ULONG code_size_ignored;
ULONG code_alignment_ignored;
ALIGN_TYPE data_start;
ULONG data_size;
ULONG data_alignment;
ULONG data_allocation_size;
ULONG module_properties;
CHAR *memory_ptr;
/* Check for interrupt call. */
if (TX_THREAD_GET_SYSTEM_STATE() != 0)
{
/* Now, make sure the call is from an interrupt and not initialization. */
if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS)
{
/* Invalid caller of this function, return appropriate error code. */
return(TX_CALLER_ERROR);
}
}
/* Determine if the module manager has not been initialized yet. */
if (_txm_module_manager_ready != TX_TRUE)
{
/* Module manager has not been initialized. */
return(TX_NOT_AVAILABLE);
}
/* Determine if the module is valid. */
if (module_instance == TX_NULL)
{
/* Invalid module pointer. */
return(TX_PTR_ERROR);
}
/* Get module manager protection mutex. */
_tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER);
/* Determine if the module is already valid. */
if (module_instance -> txm_module_instance_id == TXM_MODULE_ID)
{
/* Release the protection mutex. */
_tx_mutex_put(&_txm_module_manager_mutex);
/* Module already loaded. */
return(TXM_MODULE_ALREADY_LOADED);
}
/* Pickup the module's information. */
module_preamble = (TXM_MODULE_PREAMBLE *) module_location;
/* Check to make sure there is a valid module to load. */
if (module_preamble -> txm_module_preamble_id != TXM_MODULE_ID)
{
/* Release the protection mutex. */
_tx_mutex_put(&_txm_module_manager_mutex);
/* Invalid module preamble. */
return(TXM_MODULE_INVALID);
}
/* Check the properties of this module. */
module_properties = module_preamble -> txm_module_preamble_property_flags & TXM_MODULE_OPTIONS_MASK;
if (/* Ensure the requested properties are supported. */
((module_properties & _txm_module_manager_properties_supported) != module_properties) ||
/* Ensure the required properties are there. */
((_txm_module_manager_properties_required & module_properties) != _txm_module_manager_properties_required) ||
/* If memory protection is enabled, then so must user mode. */
((module_properties & TXM_MODULE_MEMORY_PROTECTION) && !(module_properties & TXM_MODULE_USER_MODE))
)
{
/* Release the protection mutex. */
_tx_mutex_put(&_txm_module_manager_mutex);
/* Invalid properties. Return error. */
return(TXM_MODULE_INVALID_PROPERTIES);
}
/* Check for valid module entry offsets. */
if ((module_preamble -> txm_module_preamble_shell_entry_function == 0) ||
(module_preamble -> txm_module_preamble_start_function == 0))
{
/* Release the protection mutex. */
_tx_mutex_put(&_txm_module_manager_mutex);
/* Invalid module preamble. */
return(TXM_MODULE_INVALID);
}
/* Check for valid sizes. */
if ((module_preamble -> txm_module_preamble_code_size == 0) ||
/* (module_preamble -> txm_module_preamble_data_size == 0) || *** a zero data size is valid */
(module_preamble -> txm_module_preamble_start_stop_stack_size == 0) ||
(module_preamble -> txm_module_preamble_callback_stack_size == 0))
{
/* Release the protection mutex. */
_tx_mutex_put(&_txm_module_manager_mutex);
/* Invalid module preamble. */
return(TXM_MODULE_INVALID);
}
/* Get the amount of the bytes we need to allocate for the module's code
as well as the required alignment. Note that because this is an absolute
load, we only want the code alignment so we can check it. */
status = _txm_module_manager_util_code_allocation_size_and_alignment_get(module_preamble, &code_alignment, &code_allocation_size_ignored);
if (status != TX_SUCCESS)
{
/* Math overflow error occurred. */
return(status);
}
/* Since this is an absolute load, check the alignment of the module's instruction area (code). */
TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment)
/* Initialize module control block to all zeros. */
TX_MEMSET(module_instance, 0, sizeof(TXM_MODULE_INSTANCE));
/* Pickup the basic module sizes. */
code_size = module_preamble -> txm_module_preamble_code_size;
data_size = module_preamble -> txm_module_preamble_data_size;
start_stop_stack_size = module_preamble -> txm_module_preamble_start_stop_stack_size;
callback_stack_size = module_preamble -> txm_module_preamble_callback_stack_size;
TXM_MODULE_MANAGER_UTIL_MATH_ADD_ULONG(data_size, TXM_MODULE_DATA_ALIGNMENT, data_size);
data_size = ((data_size - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT;
/* Adjust the size of the module elements to be aligned to the default alignment. We do this
so that when we partition the allocated memory, we can simply place these regions right beside
each other without having to align their pointers. Note this only works when they all have
the same alignment. */
TXM_MODULE_MANAGER_UTIL_MATH_ADD_ULONG(start_stop_stack_size, TXM_MODULE_DATA_ALIGNMENT, start_stop_stack_size);
start_stop_stack_size = ((start_stop_stack_size - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT;
TXM_MODULE_MANAGER_UTIL_MATH_ADD_ULONG(callback_stack_size, TXM_MODULE_DATA_ALIGNMENT, callback_stack_size);
callback_stack_size = ((callback_stack_size - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT;
/* Update the data size to account for the default thread stacks. */
data_allocation_size = 0;
TXM_MODULE_MANAGER_UTIL_MATH_ADD_ULONG(data_allocation_size, start_stop_stack_size, data_allocation_size);
TXM_MODULE_MANAGER_UTIL_MATH_ADD_ULONG(data_allocation_size, callback_stack_size, data_allocation_size);
/* Setup the default code and data alignments. */
data_alignment = (ULONG) TXM_MODULE_DATA_ALIGNMENT;
/* Get the port-specific alignment for the data size. Note we only want data
so we pass values of 1 for code (to avoid any possible div by 0 errors). */
code_size_ignored = 1;
code_alignment_ignored = 1;
TXM_MODULE_MANAGER_ALIGNMENT_ADJUST(module_preamble, code_size_ignored, code_alignment_ignored, data_allocation_size, data_alignment)
/* Calculate the module's total RAM memory requirement. This entire area is allocated from the module
manager's byte pool. The general layout is defined as follows:
Lowest Address: Start of start/stop thread stack
... [note: thread entry info is embedded near end of stack areas]
End of start/stop thread stack
Start of callback thread stack
... [note: thread entry info is embedded near end of stack areas]
End of callback thread stack
Highest Address: */
/* Add an extra alignment increment so we can align the pointer after allocation. */
TXM_MODULE_MANAGER_UTIL_MATH_ADD_ULONG(data_allocation_size, data_alignment, data_allocation_size);
/* Allocate memory for the module. */
status = _tx_byte_allocate(&_txm_module_manager_byte_pool, (VOID **) &memory_ptr, data_allocation_size, TX_NO_WAIT);
/* Determine if the module memory allocation was successful. */
if (status)
{
/* Release the protection mutex. */
_tx_mutex_put(&_txm_module_manager_mutex);
/* No memory, return an error. */
return(TX_NO_MEMORY);
}
/* Clear the allocated memory. */
TX_MEMSET(memory_ptr, ((UCHAR) 0), data_allocation_size);
/* Disable interrupts. */
TX_DISABLE
/* Setup the module instance structure. */
module_instance -> txm_module_instance_id = TXM_MODULE_ID;
/* Save the module name. */
module_instance -> txm_module_instance_name = module_name;
/* Save the module properties. */
module_instance -> txm_module_instance_property_flags = module_preamble -> txm_module_preamble_property_flags;
/* Set the module data memory allocation. This is the address released
when the module is unloaded. */
module_instance -> txm_module_instance_data_allocation_ptr = (VOID *) memory_ptr;
/* Save the data allocation size. */
module_instance -> txm_module_instance_data_allocation_size = data_allocation_size;
/* Calculate the actual start of the data area. This needs to be adjusted based on the alignment. */
data_start = (ALIGN_TYPE) memory_ptr;
data_start = (data_start + (((ALIGN_TYPE)data_alignment) - 1)) & ~(((ALIGN_TYPE)data_alignment) - 1);
memory_ptr = (CHAR *) data_start;
/* Compute the beginning and end of the data area. */
#ifdef ALIGN_TYPE_DEFINED
module_instance -> txm_module_instance_data_start = (VOID *) (((CHAR *) (ALIGN_TYPE) module_preamble->txm_module_preamble_code_size) + sizeof(TXM_MODULE_PREAMBLE));
module_instance -> txm_module_instance_data_end = (VOID *) (((CHAR *) (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) + module_preamble->txm_module_preamble_data_size);
#else
module_instance -> txm_module_instance_data_start = (VOID *) (((CHAR *) module_preamble->txm_module_preamble_code_size) + sizeof(TXM_MODULE_PREAMBLE));
module_instance -> txm_module_instance_data_end = (VOID *) (((CHAR *) module_instance -> txm_module_instance_data_start) + module_preamble->txm_module_preamble_data_size);
#endif
/* Save the size of the data area. */
module_instance -> txm_module_instance_data_size = data_size;
/* Set the module code memory allocation. This is the address released
when the module is unloaded. */
module_instance -> txm_module_instance_code_allocation_ptr = (VOID *) NULL;
/* Save the code allocation size. */
module_instance -> txm_module_instance_code_allocation_size = 0;
/* Setup the code pointers. Since the code was loaded in-place, this is effectively just the values supplied in the API call. */
module_instance -> txm_module_instance_code_start = (VOID *) module_location;
module_instance -> txm_module_instance_code_end = (VOID *) (((CHAR *) module_location) + (code_size - 1));
/* Setup the code size. */
module_instance -> txm_module_instance_code_size = code_size;
/* Save the module's total memory usage. */
module_instance -> txm_module_instance_total_ram_usage = 0 /* Code is executed in place */ + data_allocation_size /* just the size of stacks */;
/* Set the module state to started. */
module_instance -> txm_module_instance_state = TXM_MODULE_LOADED;
/* Save the preamble pointer. */
module_instance -> txm_module_instance_preamble_ptr = module_preamble;
/* Save the module application ID in the module instance. */
module_instance -> txm_module_instance_application_module_id = module_preamble -> txm_module_preamble_application_module_id;
/* Setup the module's start/stop thread stack area. */
module_instance -> txm_module_instance_start_stop_stack_start_address = (VOID *) (memory_ptr);
module_instance -> txm_module_instance_start_stop_stack_size = start_stop_stack_size;
module_instance -> txm_module_instance_start_stop_stack_end_address = (VOID *) (memory_ptr + (start_stop_stack_size - 1));
/* Move the memory pointer forward. */
memory_ptr = memory_ptr + start_stop_stack_size;
/* Save the start/stop thread priority. */
module_instance -> txm_module_instance_start_stop_priority = module_preamble -> txm_module_preamble_start_stop_priority;
/* Setup the module's callback thread stack area. */
module_instance -> txm_module_instance_callback_stack_start_address = (VOID *) (memory_ptr);
module_instance -> txm_module_instance_callback_stack_size = callback_stack_size;
module_instance -> txm_module_instance_callback_stack_end_address = (VOID *) (memory_ptr + (callback_stack_size - 1));
/* Move the memory pointer forward. */
memory_ptr = memory_ptr + callback_stack_size;
/* Save the callback thread priority. */
module_instance -> txm_module_instance_callback_priority = module_preamble -> txm_module_preamble_callback_priority;
/* Setup the start of the module data section. */
module_instance -> txm_module_instance_module_data_base_address = (VOID *) (memory_ptr);
/* Build actual addresses based on load... Setup all the function pointers. Any adjustments needed to shell entry, start function, and callback function are defined in the
module preamble. */
#ifdef ALIGN_TYPE_DEFINED
module_instance -> txm_module_instance_shell_entry_function = (VOID (*)(TX_THREAD *, TXM_MODULE_INSTANCE *)) ((VOID *) (ALIGN_TYPE) module_preamble -> txm_module_preamble_shell_entry_function);
module_instance -> txm_module_instance_start_thread_entry = (VOID (*)(ULONG)) ((VOID *) (ALIGN_TYPE) module_preamble -> txm_module_preamble_start_function);
module_instance -> txm_module_instance_callback_request_thread_entry = (VOID (*)(ULONG)) ((VOID *) (ALIGN_TYPE) module_preamble -> txm_module_preamble_callback_function);
#else
module_instance -> txm_module_instance_shell_entry_function = (VOID (*)(TX_THREAD *, TXM_MODULE_INSTANCE *)) ((VOID *) module_preamble -> txm_module_preamble_shell_entry_function);
module_instance -> txm_module_instance_start_thread_entry = (VOID (*)(ULONG)) ((VOID *) module_preamble -> txm_module_preamble_start_function);
module_instance -> txm_module_instance_callback_request_thread_entry = (VOID (*)(ULONG)) ((VOID *) module_preamble -> txm_module_preamble_callback_function);
#endif
/* Determine if there is a stop function for this module. */
if (module_preamble -> txm_module_preamble_stop_function)
{
/* Yes, there is a stop function, build the address. */
#ifdef ALIGN_TYPE_DEFINED
module_instance -> txm_module_instance_stop_thread_entry = (VOID (*)(ULONG)) ((VOID *) (ALIGN_TYPE) module_preamble -> txm_module_preamble_stop_function);
#else
module_instance -> txm_module_instance_stop_thread_entry = (VOID (*)(ULONG)) ((VOID *) module_preamble -> txm_module_preamble_stop_function);
#endif
}
else
{
/* No, there is no stop function. Just set the pointer to NULL. */
module_instance -> txm_module_instance_stop_thread_entry = TX_NULL;
}
/* Load the module control block with port-specific information. */
TXM_MODULE_MANAGER_MODULE_SETUP(module_instance);
/* Now add the module to the linked list of created modules. */
if (_txm_module_manger_loaded_count++ == 0)
{
/* The loaded module list is empty. Add module to empty list. */
_txm_module_manager_loaded_list_ptr = module_instance;
module_instance -> txm_module_instance_loaded_next = module_instance;
module_instance -> txm_module_instance_loaded_previous = module_instance;
}
else
{
/* This list is not NULL, add to the end of the list. */
next_module = _txm_module_manager_loaded_list_ptr;
previous_module = next_module -> txm_module_instance_loaded_previous;
/* Place the new module in the list. */
next_module -> txm_module_instance_loaded_previous = module_instance;
previous_module -> txm_module_instance_loaded_next = module_instance;
/* Setup this module's created links. */
module_instance -> txm_module_instance_loaded_previous = previous_module;
module_instance -> txm_module_instance_loaded_next = next_module;
}
/* Restore interrupts. */
TX_RESTORE
/* Release the protection mutex. */
_tx_mutex_put(&_txm_module_manager_mutex);
/* Return success. */
return(TX_SUCCESS);
}

92
common_modules/module_manager/src/txm_module_manager_kernel_dispatch.c
View File

@@ -12,8 +12,8 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Module Manager */
/** */
@@ -36,50 +36,53 @@
#include "txm_module_manager_util.h"
#include "txm_module_manager_dispatch.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_kernel_dispatch PORTABLE C */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_kernel_dispatch PORTABLE C */
/* 6.1.3 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function dispatches the module's kernel request based upon the */
/* ID and parameters specified in the request. */
/* */
/* INPUT */
/* */
/* kernel_request Module's kernel request */
/* param_1 First parameter */
/* param_2 Second parameter */
/* param_3 Third parameter */
/* */
/* OUTPUT */
/* */
/* status Completion status */
/* */
/* CALLS */
/* */
/* _txm_module_manager_application_request Application-specific req */
/* _txm_module_manager_object_pointer_get Find object pointer */
/* _txm_module_manager_thread_create Module thread create */
/* [_txm_module_manager_*_dispatch] Optional external */
/* component dispatch */
/* ThreadX API Calls */
/* */
/* CALLED BY */
/* */
/* Application code */
/* */
/* RELEASE HISTORY */
/* */
/* DESCRIPTION */
/* */
/* This function dispatches the module's kernel request based upon the */
/* ID and parameters specified in the request. */
/* */
/* INPUT */
/* */
/* kernel_request Module's kernel request */
/* param_1 First parameter */
/* param_2 Second parameter */
/* param_3 Third parameter */
/* */
/* OUTPUT */
/* */
/* status Completion status */
/* */
/* CALLS */
/* */
/* _txm_module_manager_application_request Application-specific req */
/* _txm_module_manager_object_pointer_get Find object pointer */
/* _txm_module_manager_thread_create Module thread create */
/* [_txm_module_manager_*_dispatch] Optional external */
/* component dispatch */
/* ThreadX API Calls */
/* */
/* CALLED BY */
/* */
/* Application code */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 12-31-2020 Scott Larson Modified comment(s), added */
/* port-specific dispatch, */
/* resulting in version 6.1.3 */
/* */
/**************************************************************************/
ALIGN_TYPE _txm_module_manager_kernel_dispatch(ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2)
@@ -679,6 +682,15 @@ TXM_MODULE_INSTANCE *module_instance;
default:
{
#ifdef TXM_MODULE_PORT_DISPATCH
/* Is this a port-specific request? */
if ((kernel_request >= TXM_MODULE_PORT_EXTENSION_API_ID_START) && (kernel_request <= TXM_MODULE_PORT_EXTENSION_API_ID_END))
{
/* Yes, call the port-specific dispatcher. */
return_value = (ALIGN_TYPE) _txm_module_manager_port_dispatch(module_instance, kernel_request, param_0, param_1, param_2);
}
#endif
/* Determine if an application request is present. */
if (kernel_request >= TXM_APPLICATION_REQUEST_ID_BASE)
{

89
common_modules/module_manager/src/txm_module_manager_start.c
View File

@@ -10,15 +10,15 @@
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Module Manager */
/** */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Module Manager */
/** */
/**************************************************************************/
/**************************************************************************/
#define TX_SOURCE_CODE
@@ -29,47 +29,48 @@
#include "txm_module.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_start PORTABLE C */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_start PORTABLE C */
/* 6.1.3 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function starts execution of the specified module. */
/* */
/* INPUT */
/* */
/* module_instance Module instance pointer */
/* */
/* OUTPUT */
/* */
/* status Completion status */
/* */
/* CALLS */
/* */
/* _txm_module_manager_name_build Build module:thread name */
/* _txm_module_manager_thread_create Module thread create */
/* _tx_mutex_get Get protection mutex */
/* _tx_mutex_put Release protection mutex */
/* _tx_queue_create Create module callback queue */
/* _tx_queue_delete Delete module callback queue */
/* _tx_thread_resume Resume start thread */
/* */
/* CALLED BY */
/* */
/* Application code */
/* */
/* RELEASE HISTORY */
/* */
/* DESCRIPTION */
/* */
/* This function starts execution of the specified module. */
/* */
/* INPUT */
/* */
/* module_instance Module instance pointer */
/* */
/* OUTPUT */
/* */
/* status Completion status */
/* */
/* CALLS */
/* */
/* _txm_module_manager_thread_create Module thread create */
/* _tx_mutex_get Get protection mutex */
/* _tx_mutex_put Release protection mutex */
/* _tx_queue_create Create module callback queue */
/* _tx_queue_delete Delete module callback queue */
/* _tx_thread_resume Resume start thread */
/* */
/* CALLED BY */
/* */
/* Application code */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 12-31-2020 Scott Larson Modified comment(s), */
/* resulting in version 6.1.3 */
/* */
/**************************************************************************/
UINT _txm_module_manager_start(TXM_MODULE_INSTANCE *module_instance)

13
common_modules/module_manager/src/txm_module_manager_stop.c
View File

@@ -60,7 +60,7 @@ extern UINT _txm_module_manager_usbx_stop(TXM_MODULE_INSTANCE *module_instance)
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_stop PORTABLE C */
/* 6.1 */
/* 6.1.5 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -108,7 +108,10 @@ extern UINT _txm_module_manager_usbx_stop(TXM_MODULE_INSTANCE *module_instance)
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 03-02-2021 Scott Larson Modified comments, fix */
/* object delete underflow, */
/* resulting in version 6.1.5 */
/* */
/**************************************************************************/
UINT _txm_module_manager_stop(TXM_MODULE_INSTANCE *module_instance)
@@ -531,9 +534,8 @@ TXM_MODULE_ALLOCATED_OBJECT *object_ptr;
#endif
/* Delete the allocated objects for this module. */
while (module_instance -> txm_module_instance_object_list_count--)
while (module_instance -> txm_module_instance_object_list_count != 0)
{
/* Pickup the current object pointer. */
object_ptr = module_instance -> txm_module_instance_object_list_head;
@@ -542,6 +544,9 @@ TXM_MODULE_ALLOCATED_OBJECT *object_ptr;
/* Release the object. */
_tx_byte_release((VOID *) object_ptr);
/* Decrement count. */
module_instance -> txm_module_instance_object_list_count--;
}
/* Set the allocated list head pointer to NULL. */

399
common_modules/module_manager/src/txm_module_manager_thread_create.c
View File

@@ -21,11 +21,15 @@
/**************************************************************************/
#define TX_SOURCE_CODE
#define TX_THREAD_SMP_SOURCE_CODE
/* Include necessary system files. */
#include "tx_api.h"
#include "tx_trace.h"
#include "tx_initialize.h"
#include "tx_thread.h"
#include "tx_initialize.h"
#include "tx_timer.h"
#include "txm_module.h"
@@ -35,7 +39,7 @@
/* FUNCTION RELEASE */
/* */
/* _txm_module_manager_thread_create PORTABLE C */
/* 6.1 */
/* 6.1.3 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -47,22 +51,22 @@
/* */
/* INPUT */
/* */
/* thread_ptr Thread control block pointer */
/* name Pointer to thread name string */
/* shell_function Shell function of the thread */
/* entry_function Entry function of the thread */
/* entry_input 32-bit input value to thread */
/* stack_start Pointer to start of stack */
/* stack_size Stack size in bytes */
/* priority Priority of thread */
/* (default 0-31) */
/* preempt_threshold Preemption threshold */
/* time_slice Thread time-slice value */
/* auto_start Automatic start selection */
/* thread_ptr Thread control block pointer */
/* name Pointer to thread name string */
/* shell_function Shell function of the thread */
/* entry_function Entry function of the thread */
/* entry_input 32-bit input value to thread */
/* stack_start Pointer to start of stack */
/* stack_size Stack size in bytes */
/* priority Priority of thread */
/* (default 0-31) */
/* preempt_threshold Preemption threshold */
/* time_slice Thread time-slice value */
/* auto_start Automatic start selection */
/* */
/* OUTPUT */
/* */
/* status Completion status */
/* return status Thread create return status */
/* */
/* CALLS */
/* */
@@ -81,35 +85,41 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 12-31-2020 Scott Larson Modified comment(s), */
/* fix stack overlap checking, */
/* added 64-bit support, */
/* added SMP support, */
/* resulting in version 6.1.3 */
/* */
/**************************************************************************/
UINT _txm_module_manager_thread_create(TX_THREAD *thread_ptr, CHAR *name, VOID (*shell_function)(TX_THREAD *, TXM_MODULE_INSTANCE *),
VOID (*entry_function)(ULONG), ULONG entry_input,
VOID *stack_start, ULONG stack_size, UINT priority, UINT preempt_threshold,
ULONG time_slice, UINT auto_start, UINT thread_control_block_size, TXM_MODULE_INSTANCE *module_instance)
UINT _txm_module_manager_thread_create(TX_THREAD *thread_ptr, CHAR *name_ptr,
VOID (*shell_function)(TX_THREAD *, TXM_MODULE_INSTANCE *),
VOID (*entry_function)(ULONG id), ULONG entry_input,
VOID *stack_start, ULONG stack_size, UINT priority, UINT preempt_threshold,
ULONG time_slice, UINT auto_start,
UINT thread_control_block_size, TXM_MODULE_INSTANCE *module_instance)
{
TX_INTERRUPT_SAVE_AREA
TX_THREAD *next_thread;
TX_THREAD *previous_thread;
#ifdef TX_THREAD_SMP
UINT core_index;
#endif
TX_THREAD *next_thread;
TX_THREAD *previous_thread;
#ifndef TX_DISABLE_PREEMPTION_THRESHOLD
TX_THREAD *saved_thread_ptr;
UINT saved_threshold = 0;
TX_THREAD *saved_thread_ptr;
UINT saved_threshold = ((UINT) 0);
#endif
UCHAR *temp_ptr;
#ifdef TX_ENABLE_STACK_CHECKING
ULONG new_stack_start;
#endif
TXM_MODULE_THREAD_ENTRY_INFO *thread_entry_info;
VOID *stack_end;
ULONG i;
#ifndef TX_TIMER_PROCESS_IN_ISR
TX_THREAD *current_thread;
#endif
#if TXM_MODULE_MEMORY_PROTECTION
ULONG status;
ALIGN_TYPE new_stack_start;
ALIGN_TYPE updated_stack_start;
#endif
TXM_MODULE_THREAD_ENTRY_INFO *thread_entry_info;
VOID *stack_end;
ULONG i;
/* First, check for an invalid thread pointer. */
if (thread_ptr == TX_NULL)
@@ -150,37 +160,12 @@ ULONG status;
}
/* Check the stack pointer to see if it overlaps with this thread's stack. */
/*lint -e{946} suppress pointer comparison, since this is necessary. */
if (((UCHAR *) ((VOID *) stack_start)) >= ((UCHAR *) ((VOID *) next_thread -> tx_thread_stack_start)))
if ((((UCHAR *) ((VOID *) stack_start)) <= ((UCHAR *) ((VOID *) next_thread -> tx_thread_stack_end))) &&
(((UCHAR *) ((VOID *) stack_end)) >= ((UCHAR *) ((VOID *) next_thread -> tx_thread_stack_start))))
{
/*lint -e{946} suppress pointer comparison, since this is necessary. */
if (((UCHAR *) ((VOID *) stack_start)) < ((UCHAR *) ((VOID *) next_thread -> tx_thread_stack_end)))
{
/* This stack overlaps with an existing thread, clear the stack pointer to
force a stack error below. */
stack_start = TX_NULL;
break;
}
}
/* Check the end of the stack to see if it is inside this thread's stack area as well. */
/*lint -e{946} suppress pointer comparison, since this is necessary. */
if (((UCHAR *) ((VOID *) stack_end)) >= ((UCHAR *) ((VOID *) next_thread -> tx_thread_stack_start)))
{
/*lint -e{946} suppress pointer comparison, since this is necessary. */
if (((UCHAR *) ((VOID *) stack_end)) < ((UCHAR *) ((VOID *) next_thread -> tx_thread_stack_end)))
{
/* This stack overlaps with an existing thread, clear the stack pointer to
force a stack error below. */
stack_start = TX_NULL;
break;
}
/* Stacks overlap, clear the stack pointer to force a stack error below. */
stack_start = TX_NULL;
break;
}
/* Move to the next thread. */
@@ -256,16 +241,19 @@ ULONG status;
}
#ifndef TX_TIMER_PROCESS_IN_ISR
/* Pickup thread pointer. */
TX_THREAD_GET_CURRENT(current_thread)
/* Check for invalid caller of this function. First check for a calling thread. */
if (current_thread == &_tx_timer_thread)
{
TX_THREAD *current_thread;
/* Invalid caller of this function, return appropriate error code. */
return(TX_CALLER_ERROR);
/* Pickup thread pointer. */
TX_THREAD_GET_CURRENT(current_thread)
/* Check for invalid caller of this function. First check for a calling thread. */
if (current_thread == &_tx_timer_thread)
{
/* Invalid caller of this function, return appropriate error code. */
return(TX_CALLER_ERROR);
}
}
#endif
@@ -295,21 +283,22 @@ ULONG status;
/* Ensure that there are two ULONG of 0xEF patterns at the top and
bottom of the thread's stack. This will be used to check for stack
overflow conditions during run-time. */
stack_size = ((stack_size/sizeof(ULONG)) * sizeof(ULONG)) - sizeof(ULONG);
stack_size = ((stack_size/(sizeof(ULONG))) * (sizeof(ULONG))) - (sizeof(ULONG));
/* Ensure the starting stack address is evenly aligned. */
new_stack_start = ((((ULONG) stack_start) + (sizeof(ULONG) - 1) ) & (~(sizeof(ULONG) - 1)));
new_stack_start = TX_POINTER_TO_ALIGN_TYPE_CONVERT(stack_start);
updated_stack_start = ((((ULONG) new_stack_start) + ((sizeof(ULONG)) - ((ULONG) 1)) ) & (~((sizeof(ULONG)) - ((ULONG) 1))));
/* Determine if the starting stack address is different. */
if (new_stack_start != ((ULONG) stack_start))
if (new_stack_start != updated_stack_start)
{
/* Yes, subtract another ULONG from the size to avoid going past the stack area. */
stack_size = stack_size - sizeof(ULONG);
stack_size = stack_size - (sizeof(ULONG));
}
/* Update the starting stack pointer. */
stack_start = (VOID *) new_stack_start;
stack_start = TX_ALIGN_TYPE_TO_POINTER_CONVERT(updated_stack_start);
#endif
/* Allocate the thread entry information at the top of thread's stack - Leaving one
@@ -321,53 +310,81 @@ ULONG status;
/* Initialize thread control block to all zeros. */
TX_MEMSET(thread_ptr, 0, sizeof(TX_THREAD));
#if TXM_MODULE_MEMORY_PROTECTION
/* If this is a memory protected module, allocate a kernel stack. */
if((module_instance -> txm_module_instance_property_flags) & TXM_MODULE_MEMORY_PROTECTION)
{
ULONG status;
/* Allocate kernel stack space. */
status = _txm_module_manager_object_allocate((VOID **) &(thread_ptr -> tx_thread_module_kernel_stack_start), TXM_MODULE_KERNEL_STACK_SIZE, module_instance);
if(status)
{
return(status);
}
#ifndef TX_DISABLE_STACK_FILLING
/* Set the thread stack to a pattern prior to creating the initial
stack frame. This pattern is used by the stack checking routines
to see how much has been used. */
TX_MEMSET(thread_ptr -> tx_thread_module_kernel_stack_start, ((UCHAR) TX_STACK_FILL), TXM_MODULE_KERNEL_STACK_SIZE);
#endif
/* Align kernel stack pointer. */
thread_ptr -> tx_thread_module_kernel_stack_end = (VOID *) (((ALIGN_TYPE)(thread_ptr -> tx_thread_module_kernel_stack_start) + TXM_MODULE_KERNEL_STACK_SIZE) & ~0x07);
/* Set kernel stack size. */
thread_ptr -> tx_thread_module_kernel_stack_size = TXM_MODULE_KERNEL_STACK_SIZE;
}
/* Place the stack parameters into the thread's control block. */
thread_ptr -> tx_thread_module_stack_start = stack_start;
thread_ptr -> tx_thread_module_stack_size = stack_size;
thread_ptr -> tx_thread_module_stack_start = stack_start;
thread_ptr -> tx_thread_module_stack_size = stack_size;
#endif
/* Place the supplied parameters into the thread's control block. */
thread_ptr -> tx_thread_name = name;
thread_ptr -> tx_thread_entry = entry_function;
thread_ptr -> tx_thread_entry_parameter = entry_input;
thread_ptr -> tx_thread_stack_start = stack_start;
thread_ptr -> tx_thread_stack_size = stack_size;
thread_ptr -> tx_thread_stack_end = (VOID *) (((UCHAR *) stack_start) + (stack_size-1));
thread_ptr -> tx_thread_name = name_ptr;
thread_ptr -> tx_thread_entry = entry_function;
thread_ptr -> tx_thread_entry_parameter = entry_input;
thread_ptr -> tx_thread_stack_start = stack_start;
thread_ptr -> tx_thread_stack_size = stack_size;
thread_ptr -> tx_thread_priority = priority;
thread_ptr -> tx_thread_user_priority = priority;
thread_ptr -> tx_thread_time_slice = time_slice;
thread_ptr -> tx_thread_new_time_slice = time_slice;
thread_ptr -> tx_thread_inherit_priority = ((UINT) TX_MAX_PRIORITIES);
#ifdef TX_THREAD_SMP
thread_ptr -> tx_thread_smp_core_executing = ((UINT) TX_THREAD_SMP_MAX_CORES);
thread_ptr -> tx_thread_smp_cores_excluded = ((ULONG) 0);
#ifndef TX_THREAD_SMP_DYNAMIC_CORE_MAX
thread_ptr -> tx_thread_smp_cores_allowed = ((ULONG) TX_THREAD_SMP_CORE_MASK);
#else
thread_ptr -> tx_thread_smp_cores_allowed = (((ULONG) 1) << _tx_thread_smp_max_cores) - 1;
#endif
#ifdef TX_THREAD_SMP_ONLY_CORE_0_DEFAULT
/* Default thread creation such that core0 is the only allowed core for execution, i.e., bit 1 is set to exclude core1. */
thread_ptr -> tx_thread_smp_cores_excluded = (TX_THREAD_SMP_CORE_MASK & 0xFFFFFFFE);
thread_ptr -> tx_thread_smp_cores_allowed = 1;
/* Default the timers to run on core 0 as well. */
thread_ptr -> tx_thread_timer.tx_timer_internal_smp_cores_excluded = (TX_THREAD_SMP_CORE_MASK & 0xFFFFFFFE);
/* Default the mapped to 0 too. */
thread_ptr -> tx_thread_smp_core_mapped = 0;
#endif
#endif
/* Calculate the end of the thread's stack area. */
temp_ptr = TX_VOID_TO_UCHAR_POINTER_CONVERT(stack_start);
temp_ptr = (TX_UCHAR_POINTER_ADD(temp_ptr, (stack_size - ((ULONG) 1))));
thread_ptr -> tx_thread_stack_end = TX_UCHAR_TO_VOID_POINTER_CONVERT(temp_ptr);
#if TXM_MODULE_MEMORY_PROTECTION
thread_ptr -> tx_thread_module_stack_end = thread_ptr -> tx_thread_stack_end;
#endif
thread_ptr -> tx_thread_priority = priority;
thread_ptr -> tx_thread_user_priority = priority;
thread_ptr -> tx_thread_time_slice = time_slice;
thread_ptr -> tx_thread_new_time_slice = time_slice;
thread_ptr -> tx_thread_inherit_priority = TX_MAX_PRIORITIES;
#endif /* TXM_MODULE_MEMORY_PROTECTION */
#ifndef TX_DISABLE_PREEMPTION_THRESHOLD
/* Preemption-threshold is enabled, setup accordingly. */
@@ -381,9 +398,9 @@ ULONG status;
/* Preemption-threshold specified. Since specific preemption-threshold is not supported,
disable all preemption. */
thread_ptr -> tx_thread_preempt_threshold = 0;
thread_ptr -> tx_thread_user_preempt_threshold = 0;
}
thread_ptr -> tx_thread_preempt_threshold = ((UINT) 0);
thread_ptr -> tx_thread_user_preempt_threshold = ((UINT) 0);
}
else
{
@@ -399,6 +416,9 @@ ULONG status;
/* Setup the necessary fields in the thread timer block. */
TX_THREAD_CREATE_TIMEOUT_SETUP(thread_ptr)
/* Perform any additional thread setup activities for tool or user purpose. */
TX_THREAD_CREATE_INTERNAL_EXTENSION(thread_ptr)
/* Setup pointer to the thread entry information structure, which will live at the top of each
module thread's stack. This will allow the module thread entry function to avoid direct
access to the actual thread control block. */
@@ -420,9 +440,9 @@ ULONG status;
#ifndef TX_DISABLE_NOTIFY_CALLBACKS
thread_entry_info -> txm_module_thread_entry_info_exit_notify = thread_ptr -> tx_thread_entry_exit_notify;
#else
#else /* TX_DISABLE_NOTIFY_CALLBACKS */
thread_entry_info -> txm_module_thread_entry_info_exit_notify = TX_NULL;
#endif
#endif /* TX_DISABLE_NOTIFY_CALLBACKS */
if (thread_ptr -> tx_thread_entry == module_instance -> txm_module_instance_start_thread_entry)
thread_entry_info -> txm_module_thread_entry_info_start_thread = TX_TRUE;
else
@@ -457,7 +477,7 @@ ULONG status;
/* Place the thread on the list of created threads. First,
check for an empty list. */
if (_tx_thread_created_count++ == 0)
if (_tx_thread_created_count == TX_EMPTY)
{
/* The created thread list is empty. Add thread to empty list. */
@@ -478,14 +498,17 @@ ULONG status;
/* Setup this thread's created links. */
thread_ptr -> tx_thread_created_previous = previous_thread;
thread_ptr -> tx_thread_created_next = next_thread;
thread_ptr -> tx_thread_created_next = next_thread;
}
/* Increment the thread created count. */
_tx_thread_created_count++;
/* If trace is enabled, register this object. */
TX_TRACE_OBJECT_REGISTER(TX_TRACE_OBJECT_TYPE_THREAD, thread_ptr, name, stack_start, stack_size)
TX_TRACE_OBJECT_REGISTER(TX_TRACE_OBJECT_TYPE_THREAD, thread_ptr, name_ptr, TX_POINTER_TO_ULONG_CONVERT(stack_start), stack_size)
/* If trace is enabled, insert this event into the trace buffer. */
TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_CREATE, thread_ptr, priority, stack_start, stack_size, TX_TRACE_THREAD_EVENTS)
TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_CREATE, thread_ptr, priority, TX_POINTER_TO_ULONG_CONVERT(stack_start), stack_size, TX_TRACE_THREAD_EVENTS)
/* Register thread in the thread array structure. */
TX_EL_THREAD_REGISTER(thread_ptr)
@@ -493,13 +516,131 @@ ULONG status;
/* Log this kernel call. */
TX_EL_THREAD_CREATE_INSERT
#ifdef TX_THREAD_SMP
#ifndef TX_NOT_INTERRUPTABLE
/* Temporarily disable preemption. */
_tx_thread_preempt_disable++;
#endif
/* Determine if an automatic start was requested. If so, call the resume
thread function and then check for a preemption condition. */
if (auto_start == TX_AUTO_START)
{
#ifdef TX_NOT_INTERRUPTABLE
/* Perform any additional activities for tool or user purpose. */
TX_THREAD_CREATE_EXTENSION(thread_ptr)
/* Resume the thread! */
_tx_thread_system_ni_resume(thread_ptr);
#else
/* Restore previous interrupt posture. */
TX_RESTORE
/* Perform any additional activities for tool or user purpose. */
TX_THREAD_CREATE_EXTENSION(thread_ptr)
/* Call the resume thread function to make this thread ready. */
_tx_thread_system_resume(thread_ptr);
/* Disable interrupts again. */
TX_DISABLE
#endif
/* Determine if the execution list needs to be re-evaluated. */
if (_tx_thread_smp_current_state_get() >= TX_INITIALIZE_IN_PROGRESS)
{
#ifndef TX_DISABLE_PREEMPTION_THRESHOLD
/* Clear the preemption bit maps, since nothing has yet run during initialization. */
TX_MEMSET(_tx_thread_preempted_maps, 0, sizeof(_tx_thread_preempted_maps));
#if TX_MAX_PRIORITIES > 32
_tx_thread_preempted_map_active = ((ULONG) 0);
#endif
/* Clear the entry in the preempted thread list. */
_tx_thread_preemption_threshold_list[priority] = TX_NULL;
#endif
/* Set the pointer to the thread currently with preemption-threshold set to NULL. */
_tx_thread_preemption__threshold_scheduled = TX_NULL;
#ifdef TX_THREAD_SMP_DEBUG_ENABLE
/* Debug entry. */
_tx_thread_smp_debug_entry_insert(12, 0, thread_ptr);
#endif
/* Get the core index. */
core_index = TX_SMP_CORE_ID;
/* Call the rebalance routine. This routine maps cores and ready threads. */
_tx_thread_smp_rebalance_execute_list(core_index);
#ifdef TX_THREAD_SMP_DEBUG_ENABLE
/* Debug entry. */
_tx_thread_smp_debug_entry_insert(13, 0, thread_ptr);
#endif
}
#ifndef TX_NOT_INTERRUPTABLE
/* Restore interrupts. */
TX_RESTORE
#endif
}
else
{
#ifdef TX_NOT_INTERRUPTABLE
/* Perform any additional activities for tool or user purpose. */
TX_THREAD_CREATE_EXTENSION(thread_ptr)
/* Restore interrupts. */
TX_RESTORE
#else
/* Restore interrupts. */
TX_RESTORE
/* Perform any additional activities for tool or user purpose. */
TX_THREAD_CREATE_EXTENSION(thread_ptr)
/* Disable interrupts. */
TX_DISABLE
/* Re-enable preemption. */
_tx_thread_preempt_disable--;
/* Restore interrupts. */
TX_RESTORE
/* Check for preemption. */
_tx_thread_system_preempt_check();
#endif
}
#else /* TX_THREAD_SMP */
#ifndef TX_NOT_INTERRUPTABLE
/* Temporarily disable preemption. */
_tx_thread_preempt_disable++;
#endif
/* Determine if an automatic start was requested. If so, call the resume
thread function and then check for a preemption condition. */
if (auto_start == TX_AUTO_START)
{
/* Determine if the create call is being called from initialization. */
if (TX_THREAD_GET_SYSTEM_STATE() >= TX_INITIALIZE_IN_PROGRESS)
{
@@ -526,14 +667,13 @@ ULONG status;
initialization is complete. */
saved_thread_ptr -> tx_thread_preempt_threshold = saved_thread_ptr -> tx_thread_priority;
}
}
}
else
{
/* Simply set the saved thread pointer to NULL. */
saved_thread_ptr = TX_NULL;
}
#endif
#ifdef TX_NOT_INTERRUPTABLE
@@ -547,20 +687,15 @@ ULONG status;
TX_RESTORE
#else
/* Temporarily disable preemption. */
_tx_thread_preempt_disable++;
/* Restore previous interrupt posture. */
TX_RESTORE
/* Perform any additional activities for tool or user purpose. */
TX_THREAD_CREATE_EXTENSION(thread_ptr)
/* Call the resume thread function to make this thread ready. */
/* Call the resume thread function to make this thread ready. */
_tx_thread_system_resume(thread_ptr);
#endif
#ifndef TX_DISABLE_PREEMPTION_THRESHOLD
/* Determine if the thread's preemption-threshold needs to be restored. */
if (saved_thread_ptr != TX_NULL)
@@ -569,15 +704,41 @@ ULONG status;
/* Yes, restore the previous highest-priority thread's preemption-threshold. This
can only happen if this routine is called from initialization. */
saved_thread_ptr -> tx_thread_preempt_threshold = saved_threshold;
}
#endif
}
}
else
{
/* Interrupts are already restored, simply return success. */
return(TX_SUCCESS);
#ifdef TX_NOT_INTERRUPTABLE
/* Perform any additional activities for tool or user purpose. */
TX_THREAD_CREATE_EXTENSION(thread_ptr)
/* Restore interrupts. */
TX_RESTORE
#else
/* Restore interrupts. */
TX_RESTORE
/* Perform any additional activities for tool or user purpose. */
TX_THREAD_CREATE_EXTENSION(thread_ptr)
/* Disable interrupts. */
TX_DISABLE
/* Re-enable preemption. */
_tx_thread_preempt_disable--;
/* Restore interrupts. */
TX_RESTORE
/* Check for preemption. */
_tx_thread_system_preempt_check();
#endif
}
/* Restore interrupts. */
TX_RESTORE
#endif /* TX_THREAD_SMP */
/* Return success. */
return(TX_SUCCESS);

160
common_smp/inc/tx_api.h
View File

@@ -12,7 +12,7 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** */
/** ThreadX Component */
/** */
/** Application Interface (API) */
@@ -21,32 +21,40 @@
/**************************************************************************/
/**************************************************************************/
/* */
/* APPLICATION INTERFACE DEFINITION RELEASE */
/* */
/* tx_api.h PORTABLE SMP */
/* 6.1.1 */
/**************************************************************************/
/* */
/* APPLICATION INTERFACE DEFINITION RELEASE */
/* */
/* tx_api.h PORTABLE SMP */
/* 6.1.5 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This file defines the basic Application Interface (API) to the */
/* high-performance ThreadX real-time kernel. All service prototypes */
/* and data structure definitions are defined in this file. */
/* Please note that basic data type definitions and other architecture-*/
/* specific information is contained in the file tx_port.h. */
/* */
/* RELEASE HISTORY */
/* */
/* */
/* This file defines the basic Application Interface (API) to the */
/* high-performance ThreadX real-time kernel. All service prototypes */
/* and data structure definitions are defined in this file. */
/* Please note that basic data type definitions and other architecture-*/
/* specific information is contained in the file tx_port.h. */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-16-2020 William E. Lamie Modified comment(s), and */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-16-2020 William E. Lamie Modified comment(s), and */
/* increased patch version, */
/* resulting in version 6.1.1 */
/* 12-31-2020 William E. Lamie Modified comment(s), and */
/* increased patch version, */
/* resulting in version 6.1.3 */
/* 03-02-2021 Scott Larson Modified comment(s), and */
/* order defines numerically, */
/* add option to remove FileX */
/* pointer, fix whitespace, */
/* resulting in version 6.1.5 */
/* */
/**************************************************************************/
@@ -86,7 +94,7 @@ extern "C" {
#define AZURE_RTOS_THREADX
#define THREADX_MAJOR_VERSION 6
#define THREADX_MINOR_VERSION 1
#define THREADX_PATCH_VERSION 1
#define THREADX_PATCH_VERSION 5
/* Define the following symbol for backward compatibility */
#define EL_PRODUCT_THREADX
@@ -129,7 +137,7 @@ extern "C" {
#define TX_READY ((UINT) 0)
#define TX_COMPLETED ((UINT) 1)
#define TX_TERMINATED ((UINT) 2)
#define TX_SUSPENDED ((UINT) 3)
#define TX_SUSPENDED ((UINT) 3)
#define TX_SLEEP ((UINT) 4)
#define TX_QUEUE_SUSP ((UINT) 5)
#define TX_SEMAPHORE_SUSP ((UINT) 6)
@@ -147,7 +155,6 @@ extern "C" {
#define TX_SUCCESS ((UINT) 0x00)
#define TX_DELETED ((UINT) 0x01)
#define TX_NO_MEMORY ((UINT) 0x10)
#define TX_POOL_ERROR ((UINT) 0x02)
#define TX_PTR_ERROR ((UINT) 0x03)
#define TX_WAIT_ERROR ((UINT) 0x04)
@@ -162,6 +169,7 @@ extern "C" {
#define TX_NO_INSTANCE ((UINT) 0x0D)
#define TX_THREAD_ERROR ((UINT) 0x0E)
#define TX_PRIORITY_ERROR ((UINT) 0x0F)
#define TX_NO_MEMORY ((UINT) 0x10)
#define TX_START_ERROR ((UINT) 0x10)
#define TX_DELETE_ERROR ((UINT) 0x11)
#define TX_RESUME_ERROR ((UINT) 0x12)
@@ -188,7 +196,7 @@ extern "C" {
value is 10ms, but may be replaced by a port specific version in tx_port.h or by the user
as a compilation option. */
#ifndef TX_TIMER_TICKS_PER_SECOND
#ifndef TX_TIMER_TICKS_PER_SECOND
#define TX_TIMER_TICKS_PER_SECOND ((ULONG) 100)
#endif
@@ -205,25 +213,25 @@ extern "C" {
TX_TRACE_USER_EVENT_START and TX_TRACE_USER_EVENT_END, respectively. User events should be based
on these constants in case the user event number assignment is changed in future releases. */
#define TX_TRACE_USER_EVENT_START 4096 /* I1, I2, I3, I4 are user defined */
#define TX_TRACE_USER_EVENT_END 65535 /* I1, I2, I3, I4 are user defined */
#define TX_TRACE_USER_EVENT_START 4096 /* I1, I2, I3, I4 are user defined */
#define TX_TRACE_USER_EVENT_END 65535 /* I1, I2, I3, I4 are user defined */
/* Define event filters that can be used to selectively disable certain events or groups of events. */
#define TX_TRACE_ALL_EVENTS 0x000007FF /* All ThreadX events */
#define TX_TRACE_INTERNAL_EVENTS 0x00000001 /* ThreadX internal events */
#define TX_TRACE_BLOCK_POOL_EVENTS 0x00000002 /* ThreadX Block Pool events */
#define TX_TRACE_BYTE_POOL_EVENTS 0x00000004 /* ThreadX Byte Pool events */
#define TX_TRACE_EVENT_FLAGS_EVENTS 0x00000008 /* ThreadX Event Flags events */
#define TX_TRACE_INTERRUPT_CONTROL_EVENT 0x00000010 /* ThreadX Interrupt Control events */
#define TX_TRACE_MUTEX_EVENTS 0x00000020 /* ThreadX Mutex events */
#define TX_TRACE_QUEUE_EVENTS 0x00000040 /* ThreadX Queue events */
#define TX_TRACE_INTERNAL_EVENTS 0x00000001 /* ThreadX internal events */
#define TX_TRACE_BLOCK_POOL_EVENTS 0x00000002 /* ThreadX Block Pool events */
#define TX_TRACE_BYTE_POOL_EVENTS 0x00000004 /* ThreadX Byte Pool events */
#define TX_TRACE_EVENT_FLAGS_EVENTS 0x00000008 /* ThreadX Event Flags events */
#define TX_TRACE_INTERRUPT_CONTROL_EVENT 0x00000010 /* ThreadX Interrupt Control events */
#define TX_TRACE_MUTEX_EVENTS 0x00000020 /* ThreadX Mutex events */
#define TX_TRACE_QUEUE_EVENTS 0x00000040 /* ThreadX Queue events */
#define TX_TRACE_SEMAPHORE_EVENTS 0x00000080 /* ThreadX Semaphore events */
#define TX_TRACE_THREAD_EVENTS 0x00000100 /* ThreadX Thread events */
#define TX_TRACE_TIME_EVENTS 0x00000200 /* ThreadX Time events */
#define TX_TRACE_TIMER_EVENTS 0x00000400 /* ThreadX Timer events */
#define TX_TRACE_USER_EVENTS 0x80000000UL /* ThreadX User Events */
#define TX_TRACE_THREAD_EVENTS 0x00000100 /* ThreadX Thread events */
#define TX_TRACE_TIME_EVENTS 0x00000200 /* ThreadX Time events */
#define TX_TRACE_TIMER_EVENTS 0x00000400 /* ThreadX Timer events */
#define TX_TRACE_USER_EVENTS 0x80000000UL /* ThreadX User Events */
/* Define basic alignment type used in block and byte pool operations. This data type must
@@ -309,7 +317,7 @@ typedef struct TX_TIMER_STRUCT
TX_TIMER_INTERNAL tx_timer_internal;
/* Define the pointers for the created list. */
struct TX_TIMER_STRUCT
struct TX_TIMER_STRUCT
*tx_timer_created_next,
*tx_timer_created_previous;
@@ -365,12 +373,12 @@ typedef struct TX_THREAD_STRUCT
ULONG tx_thread_time_slice; /* Current time-slice */
ULONG tx_thread_new_time_slice; /* New time-slice */
/* Define pointers to the next and previous ready threads. */
struct TX_THREAD_STRUCT
*tx_thread_ready_next,
/* Define pointers to the next and previous ready threads. */
struct TX_THREAD_STRUCT
*tx_thread_ready_next,
*tx_thread_ready_previous;
/***************************************************************/
/***************************************************************/
/* Define the first port extension in the thread control block. This
is typically defined to whitespace or a pointer type in tx_port.h. */
@@ -421,8 +429,8 @@ typedef struct TX_THREAD_STRUCT
/* Define pointers to the next and previous threads in the
created list. */
struct TX_THREAD_STRUCT
*tx_thread_created_next,
struct TX_THREAD_STRUCT
*tx_thread_created_next,
*tx_thread_created_previous;
/************* Define ThreadX SMP thread control block extensions. *************/
@@ -446,13 +454,15 @@ typedef struct TX_THREAD_STRUCT
/************* End of ThreadX SMP thread control block extensions. *************/
/* Define a pointer type for FileX extensions. */
#ifndef TX_NO_FILEX_POINTER
VOID *tx_thread_filex_ptr;
#endif
/* Define the priority inheritance variables. These will be used
to manage priority inheritance changes applied to this thread
as a result of mutex get operations. */
UINT tx_thread_user_priority;
UINT tx_thread_user_preempt_threshold;
UINT tx_thread_user_priority;
UINT tx_thread_user_preempt_threshold;
UINT tx_thread_inherit_priority;
/* Define the owned mutex count and list head pointer. */
@@ -480,7 +490,7 @@ typedef struct TX_THREAD_STRUCT
ULONG tx_thread_performance_priority_inversion_count;
/* Define the last thread pointer to preempt this thread. */
struct TX_THREAD_STRUCT
struct TX_THREAD_STRUCT
*tx_thread_performance_last_preempting_thread;
/* Define the total number of times this thread was time-sliced. */
@@ -556,13 +566,13 @@ typedef struct TX_BLOCK_POOL_STRUCT
/* Define the block pool suspension list head along with a count of
how many threads are suspended. */
struct TX_THREAD_STRUCT
struct TX_THREAD_STRUCT
*tx_block_pool_suspension_list;
UINT tx_block_pool_suspended_count;
/* Define the created list next and previous pointers. */
struct TX_BLOCK_POOL_STRUCT
*tx_block_pool_created_next,
struct TX_BLOCK_POOL_STRUCT
*tx_block_pool_created_next,
*tx_block_pool_created_previous;
#ifdef TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO
@@ -636,18 +646,18 @@ typedef struct TX_BYTE_POOL_STRUCT
/* This is used to mark the owner of the byte memory pool during
a search. If this value changes during the search, the local search
pointer must be reset. */
struct TX_THREAD_STRUCT
struct TX_THREAD_STRUCT
*tx_byte_pool_owner;
/* Define the byte pool suspension list head along with a count of
how many threads are suspended. */
struct TX_THREAD_STRUCT
struct TX_THREAD_STRUCT
*tx_byte_pool_suspension_list;
UINT tx_byte_pool_suspended_count;
/* Define the created list next and previous pointers. */
struct TX_BYTE_POOL_STRUCT
*tx_byte_pool_created_next,
struct TX_BYTE_POOL_STRUCT
*tx_byte_pool_created_next,
*tx_byte_pool_created_previous;
#ifdef TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO
@@ -703,13 +713,13 @@ typedef struct TX_EVENT_FLAGS_GROUP_STRUCT
/* Define the event flags group suspension list head along with a count of
how many threads are suspended. */
struct TX_THREAD_STRUCT
struct TX_THREAD_STRUCT
*tx_event_flags_group_suspension_list;
UINT tx_event_flags_group_suspended_count;
/* Define the created list next and previous pointers. */
struct TX_EVENT_FLAGS_GROUP_STRUCT
*tx_event_flags_group_created_next,
struct TX_EVENT_FLAGS_GROUP_STRUCT
*tx_event_flags_group_created_next,
*tx_event_flags_group_created_previous;
/* Define the delayed clearing event flags. */
@@ -795,13 +805,13 @@ typedef struct TX_MUTEX_STRUCT
/* Define the mutex suspension list head along with a count of
how many threads are suspended. */
struct TX_THREAD_STRUCT
struct TX_THREAD_STRUCT
*tx_mutex_suspension_list;
UINT tx_mutex_suspended_count;
/* Define the created list next and previous pointers. */
struct TX_MUTEX_STRUCT
*tx_mutex_created_next,
struct TX_MUTEX_STRUCT
*tx_mutex_created_next,
*tx_mutex_created_previous;
/* Define the priority of the highest priority thread waiting for
@@ -809,8 +819,8 @@ typedef struct TX_MUTEX_STRUCT
UINT tx_mutex_highest_priority_waiting;
/* Define the owned list next and previous pointers. */
struct TX_MUTEX_STRUCT
*tx_mutex_owned_next,
struct TX_MUTEX_STRUCT
*tx_mutex_owned_next,
*tx_mutex_owned_previous;
#ifdef TX_MUTEX_ENABLE_PERFORMANCE_INFO
@@ -875,13 +885,13 @@ typedef struct TX_QUEUE_STRUCT
/* Define the queue suspension list head along with a count of
how many threads are suspended. */
struct TX_THREAD_STRUCT
struct TX_THREAD_STRUCT
*tx_queue_suspension_list;
UINT tx_queue_suspended_count;
/* Define the created list next and previous pointers. */
struct TX_QUEUE_STRUCT
*tx_queue_created_next,
struct TX_QUEUE_STRUCT
*tx_queue_created_next,
*tx_queue_created_previous;
#ifdef TX_QUEUE_ENABLE_PERFORMANCE_INFO
@@ -937,13 +947,13 @@ typedef struct TX_SEMAPHORE_STRUCT
/* Define the semaphore suspension list head along with a count of
how many threads are suspended. */
struct TX_THREAD_STRUCT
struct TX_THREAD_STRUCT
*tx_semaphore_suspension_list;
UINT tx_semaphore_suspended_count;
/* Define the created list next and previous pointers. */
struct TX_SEMAPHORE_STRUCT
*tx_semaphore_created_next,
struct TX_SEMAPHORE_STRUCT
*tx_semaphore_created_next,
*tx_semaphore_created_previous;
#ifdef TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO
@@ -1181,7 +1191,6 @@ UINT _tx_el_interrupt_control(UINT new_posture);
#ifdef TX_ENABLE_MULTI_ERROR_CHECKING
/* Services with MULTI runtime error checking ThreadX. */
#define tx_block_allocate _txr_block_allocate
@@ -1739,7 +1748,6 @@ UINT _tx_trace_user_event_insert(ULONG event_id, ULONG info_field_1, ULON
UINT _tx_trace_interrupt_control(UINT new_posture);
/* Add a default macro that can be re-defined in tx_port.h to add default processing when a thread starts. Common usage
would be for enabling floating point for a thread by default, however, the additional processing could be anything
defined in tx_port.h. */
@@ -1787,15 +1795,15 @@ VOID _tx_misra_user_timer_pointer_get(TX_TIMER_INTERNAL *inte
VOID _tx_misra_thread_stack_check(TX_THREAD *thread_ptr, VOID **highest_stack);
VOID _tx_misra_trace_event_insert(ULONG event_id, VOID *info_field_1, ULONG info_field_2, ULONG info_field_3, ULONG info_field_4, ULONG filter, ULONG time_stamp);
UINT _tx_misra_always_true(void);
UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **pointer);
UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer);
UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool);
UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **pointer);
UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer);
UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool);
TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer);
UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer);
UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer);
TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer);
UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer);
TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer);
UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool);
UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool);
ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer);
TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer);
TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer);
@@ -1924,7 +1932,7 @@ VOID _tx_misra_thread_entry_exit_notify_not_used(VOID (*threa
#define TX_TIMER_INDIRECT_TO_VOID_POINTER_CONVERT(a) ((VOID *) (a))
#endif
#ifndef TX_TIMER_INITIALIZE_EXTENSION
#define TX_TIMER_INITIALIZE_EXTENSION(a)
#define TX_TIMER_INITIALIZE_EXTENSION(a)
#endif
#define TX_CONST_CHAR_TO_CHAR_POINTER_CONVERT(a) ((CHAR *) ((VOID *) (a)))
#define TX_VOID_TO_THREAD_POINTER_CONVERT(a) ((TX_THREAD *) ((VOID *) (a)))
@@ -2076,7 +2084,7 @@ VOID _tx_misra_thread_entry_exit_notify_not_used(VOID (*threa
#error "TX_THREAD_ENABLE_PERFORMANCE_INFO must not be defined."
#endif
/* Ensure timer performance info enable is not defined. */
/* Ensure timer performance info enable is not defined. */
#ifdef TX_TIMER_ENABLE_PERFORMANCE_INFO
#error "TX_TIMER_ENABLE_PERFORMANCE_INFO must not be defined."
#endif

67
common_smp/inc/tx_user_sample.h
View File

@@ -12,7 +12,7 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** */
/** ThreadX Component */
/** */
/** User Specific */
@@ -21,30 +21,34 @@
/**************************************************************************/
/**************************************************************************/
/* */
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_user.h PORTABLE C */
/* 6.1 */
/**************************************************************************/
/* */
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_user.h PORTABLE C */
/* 6.1.5 */
/* */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This file contains user defines for configuring ThreadX in specific */
/* ways. This file will have an effect only if the application and */
/* ThreadX library are built with TX_INCLUDE_USER_DEFINE_FILE defined. */
/* Note that all the defines in this file may also be made on the */
/* command line when building ThreadX library and application objects. */
/* */
/* RELEASE HISTORY */
/* */
/* */
/* This file contains user defines for configuring ThreadX in specific */
/* ways. This file will have an effect only if the application and */
/* ThreadX library are built with TX_INCLUDE_USER_DEFINE_FILE defined. */
/* Note that all the defines in this file may also be made on the */
/* command line when building ThreadX library and application objects. */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 03-02-2021 Scott Larson Modified comment(s), */
/* added option to remove */
/* FileX pointer, */
/* resulting in version 6.1.5 */
/* */
/**************************************************************************/
@@ -58,7 +62,7 @@
For maximum speed, the following should be defined:
TX_MAX_PRIORITIES 32
TX_MAX_PRIORITIES 32
TX_DISABLE_PREEMPTION_THRESHOLD
TX_DISABLE_REDUNDANT_CLEARING
TX_DISABLE_NOTIFY_CALLBACKS
@@ -70,10 +74,11 @@
For minimum size, the following should be defined:
TX_MAX_PRIORITIES 32
TX_MAX_PRIORITIES 32
TX_DISABLE_PREEMPTION_THRESHOLD
TX_DISABLE_REDUNDANT_CLEARING
TX_DISABLE_NOTIFY_CALLBACKS
TX_NO_FILEX_POINTER
TX_NOT_INTERRUPTABLE
TX_TIMER_PROCESS_IN_ISR
@@ -89,13 +94,23 @@
to tx_port.h for descriptions on each of these options. */
/*
#define TX_MAX_PRIORITIES 32
#define TX_MINIMUM_STACK ????
#define TX_MAX_PRIORITIES 32
#define TX_MINIMUM_STACK ????
#define TX_THREAD_USER_EXTENSION ????
#define TX_TIMER_THREAD_STACK_SIZE ????
#define TX_TIMER_THREAD_PRIORITY ????
*/
/* Determine if there is a FileX pointer in the thread control block.
By default, the pointer is there for legacy/backwards compatibility.
The pointer must also be there for applications using FileX.
Define this to save space in the thread control block.
*/
/*
#define TX_NO_FILEX_POINTER
*/
/* Determine if timer expirations (application timers, timeouts, and tx_thread_sleep calls
should be processed within the a system timer thread or directly in the timer ISR.
By default, the timer thread is used. When the following is defined, the timer expiration
@@ -109,10 +124,10 @@
/* Determine if in-line timer reactivation should be used within the timer expiration processing.
By default, this is disabled and a function call is used. When the following is defined,
reactivating is performed in-line resulting in faster timer processing but slightly larger
code size. */
code size. */
/*
#define TX_REACTIVATE_INLINE
#define TX_REACTIVATE_INLINE
*/
/* Determine is stack filling is enabled. By default, ThreadX stack filling is enabled,
@@ -120,7 +135,7 @@
debuggers with ThreadX-awareness and by the ThreadX run-time stack checking feature. */
/*
#define TX_DISABLE_STACK_FILLING
#define TX_DISABLE_STACK_FILLING
*/
/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is
@@ -153,9 +168,9 @@
processing when not needed. The user will also have to comment out the call to
tx_timer_interrupt, which is typically made from assembly language in
tx_initialize_low_level. Note: if TX_NO_TIMER is used, the define TX_TIMER_PROCESS_IN_ISR
must also be used. */
must also be used and tx_timer_initialize must be removed from ThreadX library. */
/*
/*
#define TX_NO_TIMER
#ifndef TX_TIMER_PROCESS_IN_ISR
#define TX_TIMER_PROCESS_IN_ISR

111
common_smp/src/tx_thread_create.c
View File

@@ -12,8 +12,8 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
@@ -32,58 +32,61 @@
#include "tx_initialize.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_create PORTABLE SMP */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_create PORTABLE SMP */
/* 6.1.3 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function creates a thread and places it on the list of created */
/* threads. */
/* */
/* INPUT */
/* */
/* thread_ptr Thread control block pointer */
/* name_ptr Pointer to thread name string */
/* entry_function Entry function of the thread */
/* entry_input 32-bit input value to thread */
/* stack_start Pointer to start of stack */
/* stack_size Stack size in bytes */
/* priority Priority of thread (0-31) */
/* */
/* This function creates a thread and places it on the list of created */
/* threads. */
/* */
/* INPUT */
/* */
/* thread_ptr Thread control block pointer */
/* name_ptr Pointer to thread name string */
/* entry_function Entry function of the thread */
/* entry_input 32-bit input value to thread */
/* stack_start Pointer to start of stack */
/* stack_size Stack size in bytes */
/* priority Priority of thread (0-31) */
/* preempt_threshold Preemption threshold */
/* time_slice Thread time-slice value */
/* auto_start Automatic start selection */
/* */
/* OUTPUT */
/* */
/* return status Thread create return status */
/* */
/* CALLS */
/* */
/* _tx_thread_smp_rebalance_execute_list Rebalance execution list */
/* _tx_thread_stack_build Build initial thread stack */
/* _tx_thread_system_resume Resume automatic start thread */
/* _tx_thread_system_ni_resume Noninterruptable resume thread*/
/* */
/* CALLED BY */
/* */
/* Application Code */
/* _tx_timer_initialize Create system timer thread */
/* */
/* RELEASE HISTORY */
/* */
/* time_slice Thread time-slice value */
/* auto_start Automatic start selection */
/* */
/* OUTPUT */
/* */
/* return status Thread create return status */
/* */
/* CALLS */
/* */
/* _tx_thread_smp_rebalance_execute_list Rebalance execution list */
/* _tx_thread_stack_build Build initial thread stack */
/* _tx_thread_system_resume Resume automatic start thread */
/* _tx_thread_system_ni_resume Noninterruptable resume thread*/
/* */
/* CALLED BY */
/* */
/* Application Code */
/* _tx_timer_initialize Create system timer thread */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 12-31-2020 Andres Mlinar Modified comment(s), */
/* resulting in version 6.1.3 */
/* */
/**************************************************************************/
UINT _tx_thread_create(TX_THREAD *thread_ptr, CHAR *name_ptr, VOID (*entry_function)(ULONG id), ULONG entry_input,
UINT _tx_thread_create(TX_THREAD *thread_ptr, CHAR *name_ptr,
VOID (*entry_function)(ULONG id), ULONG entry_input,
VOID *stack_start, ULONG stack_size, UINT priority, UINT preempt_threshold,
ULONG time_slice, UINT auto_start)
{
@@ -135,7 +138,7 @@ ALIGN_TYPE updated_stack_start;
list. */
/* Initialize thread control block to all zeros. */
TX_MEMSET(thread_ptr, 0, (sizeof(TX_THREAD)));
TX_MEMSET(thread_ptr, 0, sizeof(TX_THREAD));
/* Place the supplied parameters into the thread's control block. */
thread_ptr -> tx_thread_name = name_ptr;
@@ -190,7 +193,7 @@ ALIGN_TYPE updated_stack_start;
disable all preemption. */
thread_ptr -> tx_thread_preempt_threshold = ((UINT) 0);
thread_ptr -> tx_thread_user_preempt_threshold = ((UINT) 0);
}
}
else
{
@@ -207,7 +210,7 @@ ALIGN_TYPE updated_stack_start;
TX_THREAD_CREATE_TIMEOUT_SETUP(thread_ptr)
/* Perform any additional thread setup activities for tool or user purpose. */
TX_THREAD_CREATE_INTERNAL_EXTENSION(thread_ptr)
TX_THREAD_CREATE_INTERNAL_EXTENSION(thread_ptr)
/* Call the target specific stack frame building routine to build the
thread's initial stack and to setup the actual stack pointer in the
@@ -249,7 +252,7 @@ ALIGN_TYPE updated_stack_start;
/* Setup this thread's created links. */
thread_ptr -> tx_thread_created_previous = previous_thread;
thread_ptr -> tx_thread_created_next = next_thread;
thread_ptr -> tx_thread_created_next = next_thread;
}
/* Increment the thread created count. */
@@ -272,7 +275,7 @@ ALIGN_TYPE updated_stack_start;
/* Temporarily disable preemption. */
_tx_thread_preempt_disable++;
#endif
/* Determine if an automatic start was requested. If so, call the resume
thread function and then check for a preemption condition. */
if (auto_start == TX_AUTO_START)
@@ -294,13 +297,13 @@ ALIGN_TYPE updated_stack_start;
/* Perform any additional activities for tool or user purpose. */
TX_THREAD_CREATE_EXTENSION(thread_ptr)
/* Call the resume thread function to make this thread ready. */
/* Call the resume thread function to make this thread ready. */
_tx_thread_system_resume(thread_ptr);
/* Disable interrupts again. */
TX_DISABLE
#endif
/* Determine if the execution list needs to be re-evaluated. */
if (_tx_thread_smp_current_state_get() >= TX_INITIALIZE_IN_PROGRESS)
{
@@ -325,7 +328,7 @@ ALIGN_TYPE updated_stack_start;
/* Debug entry. */
_tx_thread_smp_debug_entry_insert(12, 0, thread_ptr);
#endif
/* Get the core index. */
core_index = TX_SMP_CORE_ID;
@@ -337,7 +340,7 @@ ALIGN_TYPE updated_stack_start;
/* Debug entry. */
_tx_thread_smp_debug_entry_insert(13, 0, thread_ptr);
#endif
}
}
#ifndef TX_NOT_INTERRUPTABLE
@@ -377,7 +380,7 @@ ALIGN_TYPE updated_stack_start;
#endif
}
/* Always return a success. */
/* Return success. */
return(TX_SUCCESS);
}

8
common_smp/src/tx_thread_smp_high_level_initialize.c
View File

@@ -38,7 +38,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_high_level_initialize PORTABLE SMP */
/* 6.1 */
/* 6.1.3 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -69,6 +69,10 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 12-31-2020 William E. Lamie Modified comments, added */
/* cast to address a MISRA */
/* compliant issue, */
/* resulting in version 6.1.3 */
/* */
/**************************************************************************/
void _tx_thread_smp_high_level_initialize(void)
@@ -95,7 +99,7 @@ void _tx_thread_smp_high_level_initialize(void)
TX_MEMSET(&_tx_thread_smp_protect_wait_list[0], 0xff, sizeof(_tx_thread_smp_protect_wait_list));
/* Set the wait list size so we can access it from assembly functions. */
_tx_thread_smp_protect_wait_list_size = TX_THREAD_SMP_PROTECT_WAIT_LIST_SIZE;
_tx_thread_smp_protect_wait_list_size = ((ULONG) TX_THREAD_SMP_PROTECT_WAIT_LIST_SIZE);
#ifndef TX_THREAD_SMP_DYNAMIC_CORE_MAX

64
common_smp/src/tx_time_get.c
View File

@@ -12,8 +12,8 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Timer */
/** */
@@ -26,47 +26,48 @@
/* Include necessary system files. */
#include "tx_api.h"
#ifdef TX_MISRA_ENABLE
#include "tx_trace.h"
#include "tx_timer.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_time_get PORTABLE C */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_time_get PORTABLE C */
/* 6.1.3 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function retrieves the internal, free-running, system clock */
/* and returns it to the caller. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* _tx_timer_system_clock Returns the system clock value */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* Application Code */
/* */
/* RELEASE HISTORY */
/* */
/* */
/* This function retrieves the internal, free-running, system clock */
/* and returns it to the caller. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* _tx_timer_system_clock Returns the system clock value */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* Application Code */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 12-31-2020 Andres Mlinar Modified comment(s), */
/* resulting in version 6.1.3 */
/* */
/**************************************************************************/
ULONG _tx_time_get(VOID)
@@ -98,5 +99,4 @@ ULONG temp_time;
/* Return the time. */
return(temp_time);
}
#endif /* TX_MISRA_ENABLE */

7
ports/arc_em/metaware/src/tx_timer_interrupt.s
View File

@@ -35,7 +35,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_timer_interrupt ARCv2_EM/MetaWare */
;/* 6.1 */
;/* 6.1.3 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -72,6 +72,10 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 12-31-2020 Scott Larson Modified comment(s), remove */
;/* unneeded load of */
;/* _tx_thread_preempt_disable, */
;/* resulting in version 6.1.3 */
;/* */
;/**************************************************************************/
;VOID _tx_timer_interrupt(VOID)
@@ -187,7 +191,6 @@ __tx_something_expired:
; {
;
ld r2, [gp, _tx_timer_expired@sda] ; Pickup timer expired flag
ld r4, [gp, _tx_thread_preempt_disable@sda] ; Pickup preempt disable
breq r2, 0, __tx_timer_dont_activate ; If not set, skip expiration processing
;
; /* Process the timer expiration. */

7
ports/arc_hs/metaware/src/tx_timer_interrupt.s
View File

@@ -35,7 +35,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_timer_interrupt ARC_HS/MetaWare */
;/* 6.1 */
;/* 6.1.3 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -72,6 +72,10 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 12-31-2020 Scott Larson Modified comment(s), remove */
;/* unneeded load of */
;/* _tx_thread_preempt_disable, */
;/* resulting in version 6.1.3 */
;/* */
;/**************************************************************************/
;VOID _tx_timer_interrupt(VOID)
@@ -187,7 +191,6 @@ __tx_something_expired:
; {
;
ld r2, [gp, _tx_timer_expired@sda] ; Pickup timer expired flag
ld r4, [gp, _tx_thread_preempt_disable@sda] ; Pickup preempt disable
breq r2, 0, __tx_timer_dont_activate ; If not set, skip expiration processing
;
; /* Process the timer expiration. */

351
ports/c667x/ccs/example_build/tx/Release/makefile Normal file
View File

@@ -0,0 +1,351 @@
################################################################################
# Automatically-generated file. Do not edit!
################################################################################
SHELL = cmd.exe
CG_TOOL_ROOT := C:/ti/ccsv8/tools/compiler/ti-cgt-c6000_8.2.4
GEN_OPTS__FLAG :=
GEN_CMDS__FLAG :=
ORDERED_OBJS += \
"./tx_block_allocate.obj" \
"./tx_block_pool_cleanup.obj" \
"./tx_block_pool_create.obj" \
"./tx_block_pool_delete.obj" \
"./tx_block_pool_info_get.obj" \
"./tx_block_pool_initialize.obj" \
"./tx_block_pool_performance_info_get.obj" \
"./tx_block_pool_performance_system_info_get.obj" \
"./tx_block_pool_prioritize.obj" \
"./tx_block_release.obj" \
"./tx_byte_allocate.obj" \
"./tx_byte_pool_cleanup.obj" \
"./tx_byte_pool_create.obj" \
"./tx_byte_pool_delete.obj" \
"./tx_byte_pool_info_get.obj" \
"./tx_byte_pool_initialize.obj" \
"./tx_byte_pool_performance_info_get.obj" \
"./tx_byte_pool_performance_system_info_get.obj" \
"./tx_byte_pool_prioritize.obj" \
"./tx_byte_pool_search.obj" \
"./tx_byte_release.obj" \
"./tx_event_flags_cleanup.obj" \
"./tx_event_flags_create.obj" \
"./tx_event_flags_delete.obj" \
"./tx_event_flags_get.obj" \
"./tx_event_flags_info_get.obj" \
"./tx_event_flags_initialize.obj" \
"./tx_event_flags_performance_info_get.obj" \
"./tx_event_flags_performance_system_info_get.obj" \
"./tx_event_flags_set.obj" \
"./tx_event_flags_set_notify.obj" \
"./tx_initialize_high_level.obj" \
"./tx_initialize_kernel_enter.obj" \
"./tx_initialize_kernel_setup.obj" \
"./tx_mutex_cleanup.obj" \
"./tx_mutex_create.obj" \
"./tx_mutex_delete.obj" \
"./tx_mutex_get.obj" \
"./tx_mutex_info_get.obj" \
"./tx_mutex_initialize.obj" \
"./tx_mutex_performance_info_get.obj" \
"./tx_mutex_performance_system_info_get.obj" \
"./tx_mutex_prioritize.obj" \
"./tx_mutex_priority_change.obj" \
"./tx_mutex_put.obj" \
"./tx_queue_cleanup.obj" \
"./tx_queue_create.obj" \
"./tx_queue_delete.obj" \
"./tx_queue_flush.obj" \
"./tx_queue_front_send.obj" \
"./tx_queue_info_get.obj" \
"./tx_queue_initialize.obj" \
"./tx_queue_performance_info_get.obj" \
"./tx_queue_performance_system_info_get.obj" \
"./tx_queue_prioritize.obj" \
"./tx_queue_receive.obj" \
"./tx_queue_send.obj" \
"./tx_queue_send_notify.obj" \
"./tx_semaphore_ceiling_put.obj" \
"./tx_semaphore_cleanup.obj" \
"./tx_semaphore_create.obj" \
"./tx_semaphore_delete.obj" \
"./tx_semaphore_get.obj" \
"./tx_semaphore_info_get.obj" \
"./tx_semaphore_initialize.obj" \
"./tx_semaphore_performance_info_get.obj" \
"./tx_semaphore_performance_system_info_get.obj" \
"./tx_semaphore_prioritize.obj" \
"./tx_semaphore_put.obj" \
"./tx_semaphore_put_notify.obj" \
"./tx_thread_context_restore.obj" \
"./tx_thread_context_save.obj" \
"./tx_thread_create.obj" \
"./tx_thread_delete.obj" \
"./tx_thread_entry_exit_notify.obj" \
"./tx_thread_identify.obj" \
"./tx_thread_info_get.obj" \
"./tx_thread_initialize.obj" \
"./tx_thread_interrupt_control.obj" \
"./tx_thread_performance_info_get.obj" \
"./tx_thread_performance_system_info_get.obj" \
"./tx_thread_preemption_change.obj" \
"./tx_thread_priority_change.obj" \
"./tx_thread_relinquish.obj" \
"./tx_thread_reset.obj" \
"./tx_thread_resume.obj" \
"./tx_thread_schedule.obj" \
"./tx_thread_shell_entry.obj" \
"./tx_thread_sleep.obj" \
"./tx_thread_stack_analyze.obj" \
"./tx_thread_stack_build.obj" \
"./tx_thread_stack_error_handler.obj" \
"./tx_thread_stack_error_notify.obj" \
"./tx_thread_suspend.obj" \
"./tx_thread_system_preempt_check.obj" \
"./tx_thread_system_resume.obj" \
"./tx_thread_system_return.obj" \
"./tx_thread_system_suspend.obj" \
"./tx_thread_terminate.obj" \
"./tx_thread_time_slice.obj" \
"./tx_thread_time_slice_change.obj" \
"./tx_thread_timeout.obj" \
"./tx_thread_wait_abort.obj" \
"./tx_time_get.obj" \
"./tx_time_set.obj" \
"./tx_timer_activate.obj" \
"./tx_timer_change.obj" \
"./tx_timer_create.obj" \
"./tx_timer_deactivate.obj" \
"./tx_timer_delete.obj" \
"./tx_timer_expiration_process.obj" \
"./tx_timer_info_get.obj" \
"./tx_timer_initialize.obj" \
"./tx_timer_interrupt.obj" \
"./tx_timer_performance_info_get.obj" \
"./tx_timer_performance_system_info_get.obj" \
"./tx_timer_system_activate.obj" \
"./tx_timer_system_deactivate.obj" \
"./tx_timer_thread_entry.obj" \
"./tx_trace_buffer_full_notify.obj" \
"./tx_trace_disable.obj" \
"./tx_trace_enable.obj" \
"./tx_trace_event_filter.obj" \
"./tx_trace_event_unfilter.obj" \
"./tx_trace_initialize.obj" \
"./tx_trace_interrupt_control.obj" \
"./tx_trace_isr_enter_insert.obj" \
"./tx_trace_isr_exit_insert.obj" \
"./tx_trace_object_register.obj" \
"./tx_trace_object_unregister.obj" \
"./tx_trace_user_event_insert.obj" \
"./txe_block_allocate.obj" \
"./txe_block_pool_create.obj" \
"./txe_block_pool_delete.obj" \
"./txe_block_pool_info_get.obj" \
"./txe_block_pool_prioritize.obj" \
"./txe_block_release.obj" \
"./txe_byte_allocate.obj" \
"./txe_byte_pool_create.obj" \
"./txe_byte_pool_delete.obj" \
"./txe_byte_pool_info_get.obj" \
"./txe_byte_pool_prioritize.obj" \
"./txe_byte_release.obj" \
"./txe_event_flags_create.obj" \
"./txe_event_flags_delete.obj" \
"./txe_event_flags_get.obj" \
"./txe_event_flags_info_get.obj" \
"./txe_event_flags_set.obj" \
"./txe_event_flags_set_notify.obj" \
"./txe_mutex_create.obj" \
"./txe_mutex_delete.obj" \
"./txe_mutex_get.obj" \
"./txe_mutex_info_get.obj" \
"./txe_mutex_prioritize.obj" \
"./txe_mutex_put.obj" \
"./txe_queue_create.obj" \
"./txe_queue_delete.obj" \
"./txe_queue_flush.obj" \
"./txe_queue_front_send.obj" \
"./txe_queue_info_get.obj" \
"./txe_queue_prioritize.obj" \
"./txe_queue_receive.obj" \
"./txe_queue_send.obj" \
"./txe_queue_send_notify.obj" \
"./txe_semaphore_ceiling_put.obj" \
"./txe_semaphore_create.obj" \
"./txe_semaphore_delete.obj" \
"./txe_semaphore_get.obj" \
"./txe_semaphore_info_get.obj" \
"./txe_semaphore_prioritize.obj" \
"./txe_semaphore_put.obj" \
"./txe_semaphore_put_notify.obj" \
"./txe_thread_create.obj" \
"./txe_thread_delete.obj" \
"./txe_thread_entry_exit_notify.obj" \
"./txe_thread_info_get.obj" \
"./txe_thread_preemption_change.obj" \
"./txe_thread_priority_change.obj" \
"./txe_thread_relinquish.obj" \
"./txe_thread_reset.obj" \
"./txe_thread_resume.obj" \
"./txe_thread_suspend.obj" \
"./txe_thread_terminate.obj" \
"./txe_thread_time_slice_change.obj" \
"./txe_thread_wait_abort.obj" \
"./txe_timer_activate.obj" \
"./txe_timer_change.obj" \
"./txe_timer_create.obj" \
"./txe_timer_deactivate.obj" \
"./txe_timer_delete.obj" \
"./txe_timer_info_get.obj" \
-include ../makefile.init
RM := DEL /F
RMDIR := RMDIR /S/Q
# All of the sources participating in the build are defined here
-include sources.mk
-include subdir_vars.mk
-include subdir_rules.mk
-include objects.mk
ifneq ($(MAKECMDGOALS),clean)
ifneq ($(strip $(C55_DEPS)),)
-include $(C55_DEPS)
endif
ifneq ($(strip $(C_UPPER_DEPS)),)
-include $(C_UPPER_DEPS)
endif
ifneq ($(strip $(S67_DEPS)),)
-include $(S67_DEPS)
endif
ifneq ($(strip $(S62_DEPS)),)
-include $(S62_DEPS)
endif
ifneq ($(strip $(S_DEPS)),)
-include $(S_DEPS)
endif
ifneq ($(strip $(OPT_DEPS)),)
-include $(OPT_DEPS)
endif
ifneq ($(strip $(C??_DEPS)),)
-include $(C??_DEPS)
endif
ifneq ($(strip $(ASM_UPPER_DEPS)),)
-include $(ASM_UPPER_DEPS)
endif
ifneq ($(strip $(S??_DEPS)),)
-include $(S??_DEPS)
endif
ifneq ($(strip $(C64_DEPS)),)
-include $(C64_DEPS)
endif
ifneq ($(strip $(CXX_DEPS)),)
-include $(CXX_DEPS)
endif
ifneq ($(strip $(S64_DEPS)),)
-include $(S64_DEPS)
endif
ifneq ($(strip $(INO_DEPS)),)
-include $(INO_DEPS)
endif
ifneq ($(strip $(CLA_DEPS)),)
-include $(CLA_DEPS)
endif
ifneq ($(strip $(S55_DEPS)),)
-include $(S55_DEPS)
endif
ifneq ($(strip $(SV7A_DEPS)),)
-include $(SV7A_DEPS)
endif
ifneq ($(strip $(C62_DEPS)),)
-include $(C62_DEPS)
endif
ifneq ($(strip $(C67_DEPS)),)
-include $(C67_DEPS)
endif
ifneq ($(strip $(PDE_DEPS)),)
-include $(PDE_DEPS)
endif
ifneq ($(strip $(K_DEPS)),)
-include $(K_DEPS)
endif
ifneq ($(strip $(C_DEPS)),)
-include $(C_DEPS)
endif
ifneq ($(strip $(CC_DEPS)),)
-include $(CC_DEPS)
endif
ifneq ($(strip $(C++_DEPS)),)
-include $(C++_DEPS)
endif
ifneq ($(strip $(C43_DEPS)),)
-include $(C43_DEPS)
endif
ifneq ($(strip $(S43_DEPS)),)
-include $(S43_DEPS)
endif
ifneq ($(strip $(ASM_DEPS)),)
-include $(ASM_DEPS)
endif
ifneq ($(strip $(S_UPPER_DEPS)),)
-include $(S_UPPER_DEPS)
endif
ifneq ($(strip $(CPP_DEPS)),)
-include $(CPP_DEPS)
endif
ifneq ($(strip $(SA_DEPS)),)
-include $(SA_DEPS)
endif
endif
-include ../makefile.defs
# Add inputs and outputs from these tool invocations to the build variables
LIB_OUTPUTS += \
tx.lib \
LIB_OUTPUTS__QUOTED += \
"tx.lib" \
# All Target
all: tx.lib
# Tool invocations
tx.lib: $(OBJS) $(OBJ_SRCS) $(LIB_SRCS)
ifneq ($(strip $(ORDERED_OBJS)),)
@echo 'Building target: "$@"'
@echo 'Invoking: C6000 Archiver'
"C:/ti/ccsv8/tools/compiler/ti-cgt-c6000_8.2.4/bin/ar6x" r "tx.lib" $(ORDERED_OBJS)
@echo 'Finished building target: "$@"'
@echo ' '
endif
# Other Targets
clean:
-$(RM) $(LIB_OUTPUTS__QUOTED)
-$(RM) "tx_block_allocate.obj" "tx_block_pool_cleanup.obj" "tx_block_pool_create.obj" "tx_block_pool_delete.obj" "tx_block_pool_info_get.obj" "tx_block_pool_initialize.obj" "tx_block_pool_performance_info_get.obj" "tx_block_pool_performance_system_info_get.obj" "tx_block_pool_prioritize.obj" "tx_block_release.obj" "tx_byte_allocate.obj" "tx_byte_pool_cleanup.obj" "tx_byte_pool_create.obj" "tx_byte_pool_delete.obj" "tx_byte_pool_info_get.obj" "tx_byte_pool_initialize.obj" "tx_byte_pool_performance_info_get.obj" "tx_byte_pool_performance_system_info_get.obj" "tx_byte_pool_prioritize.obj" "tx_byte_pool_search.obj" "tx_byte_release.obj" "tx_event_flags_cleanup.obj" "tx_event_flags_create.obj" "tx_event_flags_delete.obj" "tx_event_flags_get.obj" "tx_event_flags_info_get.obj" "tx_event_flags_initialize.obj" "tx_event_flags_performance_info_get.obj" "tx_event_flags_performance_system_info_get.obj" "tx_event_flags_set.obj" "tx_event_flags_set_notify.obj" "tx_initialize_high_level.obj" "tx_initialize_kernel_enter.obj"
-$(RM) "tx_initialize_kernel_setup.obj" "tx_mutex_cleanup.obj" "tx_mutex_create.obj" "tx_mutex_delete.obj" "tx_mutex_get.obj" "tx_mutex_info_get.obj" "tx_mutex_initialize.obj" "tx_mutex_performance_info_get.obj" "tx_mutex_performance_system_info_get.obj" "tx_mutex_prioritize.obj" "tx_mutex_priority_change.obj" "tx_mutex_put.obj" "tx_queue_cleanup.obj" "tx_queue_create.obj" "tx_queue_delete.obj" "tx_queue_flush.obj" "tx_queue_front_send.obj" "tx_queue_info_get.obj" "tx_queue_initialize.obj" "tx_queue_performance_info_get.obj" "tx_queue_performance_system_info_get.obj" "tx_queue_prioritize.obj" "tx_queue_receive.obj" "tx_queue_send.obj" "tx_queue_send_notify.obj" "tx_semaphore_ceiling_put.obj" "tx_semaphore_cleanup.obj" "tx_semaphore_create.obj" "tx_semaphore_delete.obj" "tx_semaphore_get.obj" "tx_semaphore_info_get.obj" "tx_semaphore_initialize.obj" "tx_semaphore_performance_info_get.obj" "tx_semaphore_performance_system_info_get.obj" "tx_semaphore_prioritize.obj" "tx_semaphore_put.obj" "tx_semaphore_put_notify.obj"
-$(RM) "tx_thread_context_restore.obj" "tx_thread_context_save.obj" "tx_thread_create.obj" "tx_thread_delete.obj" "tx_thread_entry_exit_notify.obj" "tx_thread_identify.obj" "tx_thread_info_get.obj" "tx_thread_initialize.obj" "tx_thread_interrupt_control.obj" "tx_thread_performance_info_get.obj" "tx_thread_performance_system_info_get.obj" "tx_thread_preemption_change.obj" "tx_thread_priority_change.obj" "tx_thread_relinquish.obj" "tx_thread_reset.obj" "tx_thread_resume.obj" "tx_thread_schedule.obj" "tx_thread_shell_entry.obj" "tx_thread_sleep.obj" "tx_thread_stack_analyze.obj" "tx_thread_stack_build.obj" "tx_thread_stack_error_handler.obj" "tx_thread_stack_error_notify.obj" "tx_thread_suspend.obj" "tx_thread_system_preempt_check.obj" "tx_thread_system_resume.obj" "tx_thread_system_return.obj" "tx_thread_system_suspend.obj" "tx_thread_terminate.obj" "tx_thread_time_slice.obj" "tx_thread_time_slice_change.obj" "tx_thread_timeout.obj" "tx_thread_wait_abort.obj" "tx_time_get.obj" "tx_time_set.obj"
-$(RM) "tx_timer_activate.obj" "tx_timer_change.obj" "tx_timer_create.obj" "tx_timer_deactivate.obj" "tx_timer_delete.obj" "tx_timer_expiration_process.obj" "tx_timer_info_get.obj" "tx_timer_initialize.obj" "tx_timer_interrupt.obj" "tx_timer_performance_info_get.obj" "tx_timer_performance_system_info_get.obj" "tx_timer_system_activate.obj" "tx_timer_system_deactivate.obj" "tx_timer_thread_entry.obj" "tx_trace_buffer_full_notify.obj" "tx_trace_disable.obj" "tx_trace_enable.obj" "tx_trace_event_filter.obj" "tx_trace_event_unfilter.obj" "tx_trace_initialize.obj" "tx_trace_interrupt_control.obj" "tx_trace_isr_enter_insert.obj" "tx_trace_isr_exit_insert.obj" "tx_trace_object_register.obj" "tx_trace_object_unregister.obj" "tx_trace_user_event_insert.obj" "txe_block_allocate.obj" "txe_block_pool_create.obj" "txe_block_pool_delete.obj" "txe_block_pool_info_get.obj" "txe_block_pool_prioritize.obj" "txe_block_release.obj" "txe_byte_allocate.obj" "txe_byte_pool_create.obj" "txe_byte_pool_delete.obj" "txe_byte_pool_info_get.obj"
-$(RM) "txe_byte_pool_prioritize.obj" "txe_byte_release.obj" "txe_event_flags_create.obj" "txe_event_flags_delete.obj" "txe_event_flags_get.obj" "txe_event_flags_info_get.obj" "txe_event_flags_set.obj" "txe_event_flags_set_notify.obj" "txe_mutex_create.obj" "txe_mutex_delete.obj" "txe_mutex_get.obj" "txe_mutex_info_get.obj" "txe_mutex_prioritize.obj" "txe_mutex_put.obj" "txe_queue_create.obj" "txe_queue_delete.obj" "txe_queue_flush.obj" "txe_queue_front_send.obj" "txe_queue_info_get.obj" "txe_queue_prioritize.obj" "txe_queue_receive.obj" "txe_queue_send.obj" "txe_queue_send_notify.obj" "txe_semaphore_ceiling_put.obj" "txe_semaphore_create.obj" "txe_semaphore_delete.obj" "txe_semaphore_get.obj" "txe_semaphore_info_get.obj" "txe_semaphore_prioritize.obj" "txe_semaphore_put.obj" "txe_semaphore_put_notify.obj" "txe_thread_create.obj" "txe_thread_delete.obj" "txe_thread_entry_exit_notify.obj" "txe_thread_info_get.obj" "txe_thread_preemption_change.obj" "txe_thread_priority_change.obj" "txe_thread_relinquish.obj"
-$(RM) "txe_thread_reset.obj" "txe_thread_resume.obj" "txe_thread_suspend.obj" "txe_thread_terminate.obj" "txe_thread_time_slice_change.obj" "txe_thread_wait_abort.obj" "txe_timer_activate.obj" "txe_timer_change.obj" "txe_timer_create.obj" "txe_timer_deactivate.obj" "txe_timer_delete.obj" "txe_timer_info_get.obj"
-$(RM) "tx_block_allocate.d" "tx_block_pool_cleanup.d" "tx_block_pool_create.d" "tx_block_pool_delete.d" "tx_block_pool_info_get.d" "tx_block_pool_initialize.d" "tx_block_pool_performance_info_get.d" "tx_block_pool_performance_system_info_get.d" "tx_block_pool_prioritize.d" "tx_block_release.d" "tx_byte_allocate.d" "tx_byte_pool_cleanup.d" "tx_byte_pool_create.d" "tx_byte_pool_delete.d" "tx_byte_pool_info_get.d" "tx_byte_pool_initialize.d" "tx_byte_pool_performance_info_get.d" "tx_byte_pool_performance_system_info_get.d" "tx_byte_pool_prioritize.d" "tx_byte_pool_search.d" "tx_byte_release.d" "tx_event_flags_cleanup.d" "tx_event_flags_create.d" "tx_event_flags_delete.d" "tx_event_flags_get.d" "tx_event_flags_info_get.d" "tx_event_flags_initialize.d" "tx_event_flags_performance_info_get.d" "tx_event_flags_performance_system_info_get.d" "tx_event_flags_set.d" "tx_event_flags_set_notify.d" "tx_initialize_high_level.d" "tx_initialize_kernel_enter.d" "tx_initialize_kernel_setup.d" "tx_mutex_cleanup.d"
-$(RM) "tx_mutex_create.d" "tx_mutex_delete.d" "tx_mutex_get.d" "tx_mutex_info_get.d" "tx_mutex_initialize.d" "tx_mutex_performance_info_get.d" "tx_mutex_performance_system_info_get.d" "tx_mutex_prioritize.d" "tx_mutex_priority_change.d" "tx_mutex_put.d" "tx_queue_cleanup.d" "tx_queue_create.d" "tx_queue_delete.d" "tx_queue_flush.d" "tx_queue_front_send.d" "tx_queue_info_get.d" "tx_queue_initialize.d" "tx_queue_performance_info_get.d" "tx_queue_performance_system_info_get.d" "tx_queue_prioritize.d" "tx_queue_receive.d" "tx_queue_send.d" "tx_queue_send_notify.d" "tx_semaphore_ceiling_put.d" "tx_semaphore_cleanup.d" "tx_semaphore_create.d" "tx_semaphore_delete.d" "tx_semaphore_get.d" "tx_semaphore_info_get.d" "tx_semaphore_initialize.d" "tx_semaphore_performance_info_get.d" "tx_semaphore_performance_system_info_get.d" "tx_semaphore_prioritize.d" "tx_semaphore_put.d" "tx_semaphore_put_notify.d" "tx_thread_create.d" "tx_thread_delete.d" "tx_thread_entry_exit_notify.d" "tx_thread_identify.d" "tx_thread_info_get.d"
-$(RM) "tx_thread_initialize.d" "tx_thread_performance_info_get.d" "tx_thread_performance_system_info_get.d" "tx_thread_preemption_change.d" "tx_thread_priority_change.d" "tx_thread_relinquish.d" "tx_thread_reset.d" "tx_thread_resume.d" "tx_thread_shell_entry.d" "tx_thread_sleep.d" "tx_thread_stack_analyze.d" "tx_thread_stack_error_handler.d" "tx_thread_stack_error_notify.d" "tx_thread_suspend.d" "tx_thread_system_preempt_check.d" "tx_thread_system_resume.d" "tx_thread_system_suspend.d" "tx_thread_terminate.d" "tx_thread_time_slice.d" "tx_thread_time_slice_change.d" "tx_thread_timeout.d" "tx_thread_wait_abort.d" "tx_time_get.d" "tx_time_set.d" "tx_timer_activate.d" "tx_timer_change.d" "tx_timer_create.d" "tx_timer_deactivate.d" "tx_timer_delete.d" "tx_timer_expiration_process.d" "tx_timer_info_get.d" "tx_timer_initialize.d" "tx_timer_performance_info_get.d" "tx_timer_performance_system_info_get.d" "tx_timer_system_activate.d" "tx_timer_system_deactivate.d" "tx_timer_thread_entry.d" "tx_trace_buffer_full_notify.d"
-$(RM) "tx_trace_disable.d" "tx_trace_enable.d" "tx_trace_event_filter.d" "tx_trace_event_unfilter.d" "tx_trace_initialize.d" "tx_trace_interrupt_control.d" "tx_trace_isr_enter_insert.d" "tx_trace_isr_exit_insert.d" "tx_trace_object_register.d" "tx_trace_object_unregister.d" "tx_trace_user_event_insert.d" "txe_block_allocate.d" "txe_block_pool_create.d" "txe_block_pool_delete.d" "txe_block_pool_info_get.d" "txe_block_pool_prioritize.d" "txe_block_release.d" "txe_byte_allocate.d" "txe_byte_pool_create.d" "txe_byte_pool_delete.d" "txe_byte_pool_info_get.d" "txe_byte_pool_prioritize.d" "txe_byte_release.d" "txe_event_flags_create.d" "txe_event_flags_delete.d" "txe_event_flags_get.d" "txe_event_flags_info_get.d" "txe_event_flags_set.d" "txe_event_flags_set_notify.d" "txe_mutex_create.d" "txe_mutex_delete.d" "txe_mutex_get.d" "txe_mutex_info_get.d" "txe_mutex_prioritize.d" "txe_mutex_put.d" "txe_queue_create.d" "txe_queue_delete.d" "txe_queue_flush.d" "txe_queue_front_send.d" "txe_queue_info_get.d"
-$(RM) "txe_queue_prioritize.d" "txe_queue_receive.d" "txe_queue_send.d" "txe_queue_send_notify.d" "txe_semaphore_ceiling_put.d" "txe_semaphore_create.d" "txe_semaphore_delete.d" "txe_semaphore_get.d" "txe_semaphore_info_get.d" "txe_semaphore_prioritize.d" "txe_semaphore_put.d" "txe_semaphore_put_notify.d" "txe_thread_create.d" "txe_thread_delete.d" "txe_thread_entry_exit_notify.d" "txe_thread_info_get.d" "txe_thread_preemption_change.d" "txe_thread_priority_change.d" "txe_thread_relinquish.d" "txe_thread_reset.d" "txe_thread_resume.d" "txe_thread_suspend.d" "txe_thread_terminate.d" "txe_thread_time_slice_change.d" "txe_thread_wait_abort.d" "txe_timer_activate.d" "txe_timer_change.d" "txe_timer_create.d" "txe_timer_deactivate.d" "txe_timer_delete.d" "txe_timer_info_get.d"
-$(RM) "tx_thread_context_restore.d" "tx_thread_context_save.d" "tx_thread_interrupt_control.d" "tx_thread_schedule.d" "tx_thread_stack_build.d" "tx_thread_system_return.d" "tx_timer_interrupt.d"
-@echo 'Finished clean'
-@echo ' '
.PHONY: all clean dependents
.SECONDARY:
-include ../makefile.targets

48
ports/cortex_a35/ac6/example_build/sample_threadx/.settings/language.settings.xml
View File

@@ -1,48 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project>
<configuration id="com.arm.eclipse.build.config.v6.exe.debug.base.515451048" name="Debug">
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
<provider class="com.arm.eclipse.builder.armcc.discovery.ArmCompiler6LanguageSettingsProvider" console="false" env-hash="-890320463837788586" id="com.arm.eclipse.builder.armcc.v6.langprovider" keep-relative-paths="false" name="Arm Compiler 6 Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
<language-scope id="com.arm.eclipse.builder.armcc.lang.c.ac6"/>
<language-scope id="com.arm.eclipse.builder.armcc.lang.cpp.ac6"/>
</provider>
</extension>
</configuration>
<configuration id="com.arm.eclipse.build.config.v6.exe.release.base.262471578" name="Release">
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
<provider class="com.arm.eclipse.builder.armcc.discovery.ArmCompiler6LanguageSettingsProvider" console="false" env-hash="-936373864897685072" id="com.arm.eclipse.builder.armcc.v6.langprovider" keep-relative-paths="false" name="Arm Compiler 6 Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
<language-scope id="com.arm.eclipse.builder.armcc.lang.c.ac6"/>
<language-scope id="com.arm.eclipse.builder.armcc.lang.cpp.ac6"/>
</provider>
</extension>
</configuration>
</project>

48
ports/cortex_a35/ac6/example_build/tx/.settings/language.settings.xml
View File

@@ -1,48 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project>
<configuration id="com.arm.eclipse.build.config.v6.lib.debug.base.332565915" name="Debug">
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
<provider class="com.arm.eclipse.builder.armcc.discovery.ArmCompiler6LanguageSettingsProvider" console="false" env-hash="-890320463837788586" id="com.arm.eclipse.builder.armcc.v6.langprovider" keep-relative-paths="false" name="Arm Compiler 6 Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
<language-scope id="com.arm.eclipse.builder.armcc.lang.c.ac6"/>
<language-scope id="com.arm.eclipse.builder.armcc.lang.cpp.ac6"/>
</provider>
</extension>
</configuration>
<configuration id="com.arm.eclipse.build.config.v6.lib.release.base.979090268" name="Release">
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
<provider class="com.arm.eclipse.builder.armcc.discovery.ArmCompiler6LanguageSettingsProvider" console="false" env-hash="-936373864897685072" id="com.arm.eclipse.builder.armcc.v6.langprovider" keep-relative-paths="false" name="Arm Compiler 6 Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
<language-scope id="com.arm.eclipse.builder.armcc.lang.c.ac6"/>
<language-scope id="com.arm.eclipse.builder.armcc.lang.cpp.ac6"/>
</provider>
</extension>
</configuration>
</project>

25
ports/cortex_m0/ac5/src/tx_thread_schedule.s
View File

@@ -30,6 +30,10 @@
IMPORT _tx_execution_thread_enter
IMPORT _tx_execution_thread_exit
ENDIF
IF :DEF:TX_LOW_POWER
IMPORT tx_low_power_enter
IMPORT tx_low_power_exit
ENDIF
;
;
AREA ||.text||, CODE, READONLY
@@ -39,7 +43,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M0/AC5 */
;/* 6.1 */
;/* 6.1.5 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -72,7 +76,10 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 03-02-2021 Scott Larson Modified comment(s), add */
;/* low power code, */
;/* resulting in version 6.1.5 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -240,11 +247,23 @@ __tx_ts_wait
STR r1, [r0] ; Store it in the current pointer
CMP r1, #0 ; If non-NULL, a new thread is ready!
BNE __tx_ts_ready ;
IF :DEF:TX_ENABLE_WFI
IF:DEF:TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter ; Possibly enter low power mode
POP {r0-r3}
ENDIF
IF:DEF:TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
ENDIF
IF:DEF:TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit ; Exit low power mode
POP {r0-r3}
ENDIF
__tx_ts_ISB
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting

25
ports/cortex_m0/ac6/src/tx_thread_schedule.S
View File

@@ -25,6 +25,10 @@
.global _tx_thread_execute_ptr
.global _tx_timer_time_slice
.global _tx_thread_system_stack_ptr
#ifdef TX_LOW_POWER
.global tx_low_power_enter
.global tx_low_power_exit
#endif
@
@
.text
@@ -35,7 +39,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_schedule Cortex-M0/AC6 */
@/* 6.1 */
@/* 6.1.5 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -68,7 +72,10 @@
@/* */
@/* DATE NAME DESCRIPTION */
@/* */
@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
@/* 03-02-2021 Scott Larson Modified comment(s), add */
@/* low power code, */
@/* resulting in version 6.1.5 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_schedule(VOID)
@@ -244,11 +251,25 @@ __tx_ts_wait:
STR r1, [r0] @ Store it in the current pointer
CMP r1, #0 @ If non-NULL, a new thread is ready!
BNE __tx_ts_ready @
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter @ Possibly enter low power mode
POP {r0-r3}
#endif
#ifdef TX_ENABLE_WFI
DSB @ Ensure no outstanding memory transactions
WFI @ Wait for interrupt
ISB @ Ensure pipeline is flushed
#endif
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit @ Exit low power mode
POP {r0-r3}
#endif
CPSIE i @ Enable interrupts
B __tx_ts_wait @ Loop to continue waiting
@

0
ports/cortex_m0/gnu/CMakeLists.txt Normal file → Executable file
View File

0
ports/cortex_m0/gnu/src/tx_thread_context_restore.S Executable file → Normal file
View File

0
ports/cortex_m0/gnu/src/tx_thread_context_save.S Executable file → Normal file
View File

0
ports/cortex_m0/gnu/src/tx_thread_interrupt_control.S Executable file → Normal file
View File

0
ports/cortex_m0/gnu/src/tx_thread_interrupt_disable.S Executable file → Normal file
View File

0
ports/cortex_m0/gnu/src/tx_thread_interrupt_restore.S Executable file → Normal file
View File

27
ports/cortex_m0/gnu/src/tx_thread_schedule.S Executable file → Normal file
View File

@@ -27,6 +27,10 @@
.global _tx_thread_system_stack_ptr
.global _tx_execution_thread_enter
.global _tx_execution_thread_exit
#ifdef TX_LOW_POWER
.global tx_low_power_enter
.global tx_low_power_exit
#endif
@
@
.text
@@ -37,7 +41,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_schedule Cortex-M0/GNU */
@/* 6.1 */
@/* 6.1.5 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -70,9 +74,12 @@
@/* */
@/* DATE NAME DESCRIPTION */
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 09-30-2020 William E. Lamie Modified comment(s), */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 09-30-2020 William E. Lamie Modified comment(s), */
@/* resulting in version 6.1 */
@/* 03-02-2021 Scott Larson Modified comment(s), add */
@/* low power code, */
@/* resulting in version 6.1.5 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_schedule(VOID)
@@ -248,11 +255,25 @@ __tx_ts_wait:
STR r1, [r0] @ Store it in the current pointer
CMP r1, #0 @ If non-NULL, a new thread is ready!
BNE __tx_ts_ready @
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter @ Possibly enter low power mode
POP {r0-r3}
#endif
#ifdef TX_ENABLE_WFI
DSB @ Ensure no outstanding memory transactions
WFI @ Wait for interrupt
ISB @ Ensure pipeline is flushed
#endif
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit @ Exit low power mode
POP {r0-r3}
#endif
CPSIE i @ Enable interrupts
B __tx_ts_wait @ Loop to continue waiting
@

0
ports/cortex_m0/gnu/src/tx_thread_stack_build.S Executable file → Normal file
View File

0
ports/cortex_m0/gnu/src/tx_thread_system_return.S Executable file → Normal file
View File

0
ports/cortex_m0/gnu/src/tx_timer_interrupt.S Executable file → Normal file
View File

25
ports/cortex_m0/iar/src/tx_thread_schedule.s
View File

@@ -28,6 +28,10 @@
EXTERN _tx_thread_preempt_disable
EXTERN _tx_execution_thread_enter
EXTERN _tx_execution_thread_exit
#ifdef TX_LOW_POWER
EXTERN tx_low_power_enter
EXTERN tx_low_power_exit
#endif
;
;
SECTION `.text`:CODE:NOROOT(2)
@@ -37,7 +41,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M0/IAR */
;/* 6.1 */
;/* 6.1.5 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -70,7 +74,10 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 03-02-2021 Scott Larson Modified comment(s), add */
;/* low power code, */
;/* resulting in version 6.1.5 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -238,11 +245,25 @@ __tx_ts_wait:
STR r1, [r0] ; Store it in the current pointer
CMP r1, #0 ; If non-NULL, a new thread is ready!
BNE __tx_ts_ready ;
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter ; Possibly enter low power mode
POP {r0-r3}
#endif
#ifdef TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
#endif
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit ; Exit low power mode
POP {r0-r3}
#endif
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;

27
ports/cortex_m0/keil/src/tx_thread_schedule.s
View File

@@ -30,6 +30,10 @@
IMPORT _tx_execution_thread_enter
IMPORT _tx_execution_thread_exit
ENDIF
IF :DEF:TX_LOW_POWER
IMPORT tx_low_power_enter
IMPORT tx_low_power_exit
ENDIF
;
;
AREA ||.text||, CODE, READONLY
@@ -39,7 +43,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M0/AC5 */
;/* 6.1 */
;/* 6.1.5 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -72,7 +76,10 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 03-02-2021 Scott Larson Modified comment(s), add */
;/* low power code, */
;/* resulting in version 6.1.5 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -241,11 +248,25 @@ __tx_ts_wait
STR r1, [r0] ; Store it in the current pointer
CMP r1, #0 ; If non-NULL, a new thread is ready!
BNE __tx_ts_ready ;
IF :DEF:TX_ENABLE_WFI
IF:DEF:TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter ; Possibly enter low power mode
POP {r0-r3}
ENDIF
IF:DEF:TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
ENDIF
IF:DEF:TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit ; Exit low power mode
POP {r0-r3}
ENDIF
__tx_ts_ISB
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting

8
ports/cortex_m23/ac6/inc/tx_port.h
View File

@@ -26,7 +26,7 @@
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h Cortex-M23/AC6 */
/* 6.1 */
/* 6.1.5 */
/* */
/* AUTHOR */
/* */
@@ -47,7 +47,10 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 03-02-2021 Scott Larson Modified comment(s), added */
/* ULONG64_DEFINED, */
/* resulting in version 6.1.5 */
/* */
/**************************************************************************/
@@ -82,6 +85,7 @@ typedef unsigned long ULONG;
typedef unsigned long long ULONG64;
typedef short SHORT;
typedef unsigned short USHORT;
#define ULONG64_DEFINED
/* Function prototypes for this port. */
struct TX_THREAD_STRUCT;

2
ports/cortex_m23/ac6/readme_threadx.txt
View File

@@ -15,6 +15,8 @@ Building the ThreadX library is easy; simply set the ThreadX_Library project
as active, then then build the library. You should now observe the compilation
and assembly of the ThreadX library. This project build produces the ThreadX
library file ThreadX_Library.lib.
Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c
replace the common files of the same name.
3. Demonstration System

235
ports/cortex_m23/gnu/example_build/build_threadx.bat Normal file
View File

@@ -0,0 +1,235 @@
del tx.a
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE ../src/tx_initialize_low_level.S
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE ../src/tx_thread_context_restore.S
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE ../src/tx_thread_context_save.S
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE ../src/tx_thread_interrupt_control.S
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE ../src/tx_thread_interrupt_disable.S
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE ../src/tx_thread_interrupt_restore.S
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE ../src/tx_thread_schedule.S
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE ../src/tx_thread_secure_stack_allocate.S
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE ../src/tx_thread_secure_stack_free.S
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE ../src/tx_thread_stack_build.S
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE ../src/tx_thread_system_return.S
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE ../src/tx_timer_interrupt.S
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../src/txe_thread_secure_stack_allocate.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../src/txe_thread_secure_stack_free.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../src/tx_thread_stack_error_handler.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../src/tx_thread_stack_error_notify.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_block_allocate.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_cleanup.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_create.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_delete.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_info_get.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_initialize.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_info_get.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_system_info_get.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_prioritize.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_block_release.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_allocate.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_cleanup.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_create.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_delete.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_info_get.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_initialize.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_info_get.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_prioritize.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_search.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_release.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_cleanup.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_create.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_delete.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_get.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_info_get.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_initialize.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_info_get.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_system_info_get.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set_notify.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_high_level.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_enter.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_setup.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_cleanup.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_create.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_delete.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_get.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_info_get.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_initialize.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_info_get.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_system_info_get.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_prioritize.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_priority_change.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_put.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_cleanup.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_create.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_delete.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_flush.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_front_send.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_info_get.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_initialize.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_info_get.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_system_info_get.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_prioritize.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_receive.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send_notify.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_ceiling_put.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_cleanup.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_create.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_delete.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_get.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_info_get.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_initialize.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_info_get.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_system_info_get.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_prioritize.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put_notify.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_create.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_delete.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_entry_exit_notify.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_identify.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_info_get.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_initialize.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_info_get.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_system_info_get.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_preemption_change.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_priority_change.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_relinquish.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_reset.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_resume.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_shell_entry.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_sleep.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_analyze.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_suspend.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_preempt_check.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_resume.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_suspend.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_terminate.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice_change.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_timeout.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_wait_abort.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_time_get.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_time_set.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_activate.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_change.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_create.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_deactivate.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_delete.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_expiration_process.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_info_get.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_initialize.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_info_get.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_system_info_get.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_activate.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_deactivate.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_thread_entry.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_enable.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_disable.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_initialize.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_interrupt_control.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_enter_insert.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_exit_insert.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_register.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_unregister.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_user_event_insert.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_buffer_full_notify.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_filter.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_unfilter.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_block_allocate.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_create.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_delete.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_info_get.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_prioritize.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_block_release.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_allocate.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_create.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_delete.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_info_get.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_prioritize.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_release.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_create.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_delete.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_get.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_info_get.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set_notify.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_create.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_delete.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_get.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_info_get.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_prioritize.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_put.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_create.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_delete.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_flush.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_front_send.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_info_get.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_prioritize.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_receive.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send_notify.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_ceiling_put.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_create.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_delete.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_get.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_info_get.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_prioritize.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put_notify.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_create.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_delete.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_entry_exit_notify.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_info_get.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_preemption_change.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_priority_change.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_relinquish.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_reset.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_resume.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_suspend.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_terminate.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_time_slice_change.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_wait_abort.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_activate.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_change.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_create.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_deactivate.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_delete.c
arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -DTX_SINGLE_MODE_NON_SECURE -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_info_get.c
arm-none-eabi-ar -r tx.a tx_thread_secure_stack_allocate.o txe_thread_secure_stack_allocate.o tx_thread_secure_stack_free.o txe_thread_secure_stack_free.o
arm-none-eabi-ar -r tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o
arm-none-eabi-ar -r tx.a tx_thread_interrupt_disable.o tx_thread_interrupt_restore.o tx_initialize_low_level.o
arm-none-eabi-ar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o
arm-none-eabi-ar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o
arm-none-eabi-ar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o
arm-none-eabi-ar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o
arm-none-eabi-ar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o
arm-none-eabi-ar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o
arm-none-eabi-ar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o
arm-none-eabi-ar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o
arm-none-eabi-ar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o
arm-none-eabi-ar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o
arm-none-eabi-ar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o
arm-none-eabi-ar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o
arm-none-eabi-ar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o
arm-none-eabi-ar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o
arm-none-eabi-ar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o
arm-none-eabi-ar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o
arm-none-eabi-ar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o
arm-none-eabi-ar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o
arm-none-eabi-ar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o
arm-none-eabi-ar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o
arm-none-eabi-ar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o
arm-none-eabi-ar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o
arm-none-eabi-ar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o
arm-none-eabi-ar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o
arm-none-eabi-ar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o
arm-none-eabi-ar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o
arm-none-eabi-ar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o
arm-none-eabi-ar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o
arm-none-eabi-ar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o
arm-none-eabi-ar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o
arm-none-eabi-ar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o
arm-none-eabi-ar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o
arm-none-eabi-ar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o

96
ports/cortex_m23/gnu/inc/tx_port.h
View File

@@ -26,7 +26,7 @@
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h Cortex-M23/GNU */
/* 6.1 */
/* 6.1.3 */
/* */
/* AUTHOR */
/* */
@@ -47,7 +47,12 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 03-02-2021 Scott Larson Modified comment(s), */
/* remove unneeded headers, */
/* use builtins, added */
/* ULONG64_DEFINED, */
/* resulting in version 6.1.5 */
/* */
/**************************************************************************/
@@ -67,8 +72,6 @@
#include <stdlib.h>
#include <string.h>
#include <arm_compat.h>
#include "ARMCM23_TZ.h" /* For intrinsic functions. */
/* Define ThreadX basic types for this port. */
@@ -82,6 +85,7 @@ typedef unsigned long ULONG;
typedef unsigned long long ULONG64;
typedef short SHORT;
typedef unsigned short USHORT;
#define ULONG64_DEFINED
/* Function prototypes for this port. */
struct TX_THREAD_STRUCT;
@@ -275,8 +279,6 @@ ULONG _tx_misra_time_stamp_get(VOID);
#ifndef TX_MISRA_ENABLE
//register unsigned int _ipsr __asm ("MRS %[result], ipsr" : [result] "=r" (_ipsr) : );
inline static unsigned int _get_ipsr(void);
inline static unsigned int _get_ipsr(void)
{
unsigned int _ipsr;
@@ -352,7 +354,7 @@ extern void _tx_thread_secure_stack_initialize(void);
#ifndef TX_DISABLE_INLINE
#define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m)));
#define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __builtin_ctz(m);
#endif
@@ -364,41 +366,73 @@ extern void _tx_thread_secure_stack_initialize(void);
is used to define a local function save area for the disable and restore
macros. */
#ifdef TX_DISABLE_INLINE
#ifndef TX_DISABLE_INLINE
UINT _tx_thread_interrupt_disable(VOID);
VOID _tx_thread_interrupt_restore(UINT previous_posture);
/* Define GNU specific macros, with in-line assembly for performance. */
#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save;
__attribute__( ( always_inline ) ) static inline unsigned int __disable_interrupts(void)
{
#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable();
unsigned int primask_value;
#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save);
__asm__ volatile (" MRS %0,PRIMASK ": "=r" (primask_value) );
__asm__ volatile (" CPSID i" : : : "memory" );
return(primask_value);
}
#else
__attribute__( ( always_inline ) ) static inline void __restore_interrupts(unsigned int primask_value)
{
#define TX_INTERRUPT_SAVE_AREA unsigned int was_masked;
#define TX_DISABLE was_masked = __disable_irq();
#define TX_RESTORE if (was_masked == 0) __enable_irq();
__asm__ volatile (" MSR PRIMASK,%0": : "r" (primask_value): "memory" );
}
__attribute__( ( always_inline ) ) static inline unsigned int __get_primask_value(void)
{
unsigned int primask_value;
__asm__ volatile (" MRS %0,PRIMASK ": "=r" (primask_value) );
return(primask_value);
}
__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void)
{
__asm__ volatile (" CPSIE i": : : "memory" );
}
__attribute__( ( always_inline ) ) static inline void _tx_thread_system_return_inline(void)
{
unsigned int interrupt_save;
*((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
if (_get_ipsr() == 0)
{
interrupt_save = __get_primask_value();
__enable_interrupts();
__restore_interrupts(interrupt_save);
}
}
#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save;
#define TX_DISABLE interrupt_save = __disable_interrupts();
#define TX_RESTORE __restore_interrupts(interrupt_save);
/* Redefine _tx_thread_system_return for improved performance. */
#define _tx_thread_system_return _tx_thread_system_return_inline
static void _tx_thread_system_return_inline(void)
{
unsigned int was_masked;
#else
#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save;
/* Set PendSV to invoke ThreadX scheduler. */
*((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
if (_get_ipsr() == 0)
{
was_masked = __disable_irq();
__enable_irq();
if (was_masked != 0)
__disable_irq();
}
}
#define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE);
#define TX_RESTORE _tx_thread_interrupt_control(interrupt_save);
#endif
@@ -406,7 +440,7 @@ unsigned int was_masked;
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/GNU Version 6.1 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/GNU Version 6.1.3 *";
#else
#ifdef TX_MISRA_ENABLE
extern CHAR _tx_version_id[100];

19
ports/cortex_m23/gnu/readme_threadx.txt
View File

@@ -5,12 +5,13 @@
1. Building the ThreadX run-time Library
An example .bat file is in the example_build directory.
Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c
replace the common files of the same name.
2. Demonstration System
No demonstration example is provided.
3. System Initialization
@@ -127,6 +128,18 @@ For generic code revision information, please refer to the readme_threadx_generi
file, which is included in your distribution. The following details the revision
information associated with this specific port of ThreadX:
12-31-2020 The following files were
changed/added for port specific version 6.1.3:
tx_port.h Remove unneeded include files,
use builtin functions,
modified comments.
tx_thread_secure_stack.c Remove unneeded include file,
use inline get/set functions,
modified comments.
09-30-2020 Initial ThreadX 6.1 version for Cortex-M23 using GNU tools.

98
ports/cortex_m23/gnu/src/tx_thread_secure_stack.c
View File

@@ -29,7 +29,6 @@
#define TX_SOURCE_CODE
#include "ARMCM23_TZ.h" /* For intrinsic functions. */
#include "tx_secure_interface.h" /* Interface for NS code. */
/* Minimum size of secure stack. */
@@ -63,7 +62,7 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT
/* FUNCTION RELEASE */
/* */
/* _tx_thread_secure_stack_initialize Cortex-M23/GNU */
/* 6.1.1 */
/* 6.1.3 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -82,10 +81,7 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT
/* */
/* CALLS */
/* */
/* __get_CONTROL Intrinsic to get CONTROL */
/* __set_CONTROL Intrinsic to set CONTROL */
/* __set_PSPLIM Intrinsic to set PSP limit */
/* __set_PSP Intrinsic to set PSP */
/* None */
/* */
/* CALLED BY */
/* */
@@ -98,19 +94,25 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-16-2020 Scott Larson Modified comment(s), */
/* resulting in version 6.1.1 */
/* 12-31-2020 Scott Larson Modified comment(s), and */
/* fixed M23 GCC build, */
/* resulting in version 6.1.3 */
/* */
/**************************************************************************/
__attribute__((cmse_nonsecure_entry))
void _tx_thread_secure_stack_initialize(void)
{
ULONG control;
/* Set secure mode to use PSP. */
__set_CONTROL(__get_CONTROL() | 2);
asm volatile("MRS %0, CONTROL" : "=r" (control)); /* Get CONTROL register. */
control |= 2; /* Use PSP. */
asm volatile("MSR CONTROL, %0" :: "r" (control)); /* Set CONTROL register. */
/* Set process stack pointer and stack limit to 0 to throw exception when a thread
without a secure stack calls a secure function that tries to use secure stack. */
__set_PSPLIM(0);
__set_PSP(0);
asm volatile("MSR PSPLIM, %0" :: "r" (0));
asm volatile("MSR PSP, %0" :: "r" (0));
return;
}
@@ -122,7 +124,7 @@ void _tx_thread_secure_stack_initialize(void)
/* FUNCTION RELEASE */
/* */
/* _tx_thread_secure_mode_stack_allocate Cortex-M23/GNU */
/* 6.1.1 */
/* 6.1.3 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -145,13 +147,9 @@ void _tx_thread_secure_stack_initialize(void)
/* */
/* CALLS */
/* */
/* __get_IPSR Intrinsic to get IPSR */
/* calloc Compiler's calloc function */
/* malloc Compiler's malloc function */
/* free Compiler's free() function */
/* __set_PSPLIM Intrinsic to set PSP limit */
/* __set_PSP Intrinsic to set PSP */
/* __TZ_get_PSPLIM_NS Intrinsic to get NS PSP */
/* */
/* CALLED BY */
/* */
@@ -165,6 +163,10 @@ void _tx_thread_secure_stack_initialize(void)
/* 10-16-2020 Scott Larson Modified comment(s), */
/* added stack sealing, */
/* resulting in version 6.1.1 */
/* 12-31-2020 Scott Larson Modified comment(s), and */
/* fixed M23 GCC build, */
/* resulting in version 6.1.3 */
/* */
/**************************************************************************/
__attribute__((cmse_nonsecure_entry))
@@ -173,12 +175,14 @@ UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack
UINT status;
TX_THREAD_SECURE_STACK_INFO *info_ptr;
UCHAR *stack_mem;
ULONG sp;
ULONG ipsr;
ULONG psplim_ns;
status = TX_SUCCESS;
/* Make sure function is called from interrupt (threads should not call). */
if (__get_IPSR() == 0)
asm volatile("MRS %0, IPSR" : "=r" (ipsr)); /* Get IPSR register. */
if (ipsr == 0)
{
status = TX_CALLER_ERROR;
}
@@ -217,14 +221,13 @@ ULONG sp;
/* Save info pointer in thread. */
thread_ptr -> tx_thread_secure_stack_context = info_ptr;
/* Check if this thread is running by looking at PSP_NS and seeing if it is within
the stack_start and stack_end range. */
sp = __TZ_get_PSP_NS();
if(sp > ((ULONG) thread_ptr -> tx_thread_stack_start) && sp < ((ULONG) thread_ptr -> tx_thread_stack_end))
/* Check if this thread is running by looking at its stack start and PSPLIM_NS */
asm volatile("MRS %0, PSPLIM_NS" : "=r" (psplim_ns)); /* Get PSPLIM_NS register. */
if(((ULONG) thread_ptr -> tx_thread_stack_start & 0xFFFFFFF8) == psplim_ns)
{
/* If this thread is running, set Secure PSP and PSPLIM. */
__set_PSPLIM((ULONG)(info_ptr -> tx_thread_secure_stack_limit));
__set_PSP((ULONG)(info_ptr -> tx_thread_secure_stack_ptr));
asm volatile("MSR PSPLIM, %0" :: "r" ((ULONG)(info_ptr -> tx_thread_secure_stack_limit)));
asm volatile("MSR PSP, %0" :: "r" ((ULONG)(info_ptr -> tx_thread_secure_stack_ptr)));
}
}
@@ -252,7 +255,7 @@ ULONG sp;
/* FUNCTION RELEASE */
/* */
/* _tx_thread_secure_mode_stack_free Cortex-M23/GNU */
/* 6.1.1 */
/* 6.1.3 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -273,7 +276,6 @@ ULONG sp;
/* */
/* CALLS */
/* */
/* __get_IPSR Intrinsic to get IPSR */
/* free Compiler's free() function */
/* */
/* CALLED BY */
@@ -287,6 +289,9 @@ ULONG sp;
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-16-2020 Scott Larson Modified comment(s), */
/* resulting in version 6.1.1 */
/* 12-31-2020 Scott Larson Modified comment(s), and */
/* fixed M23 GCC build, */
/* resulting in version 6.1.3 */
/* */
/**************************************************************************/
__attribute__((cmse_nonsecure_entry))
@@ -294,14 +299,16 @@ UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr)
{
UINT status;
TX_THREAD_SECURE_STACK_INFO *info_ptr;
ULONG ipsr;
status = TX_SUCCESS;
/* Pickup stack info from thread. */
info_ptr = thread_ptr -> tx_thread_secure_stack_context;
/* Make sure function is called from interrupt (threads should not call). */
if (__get_IPSR() == 0)
asm volatile("MRS %0, IPSR" : "=r" (ipsr)); /* Get IPSR register. */
if (ipsr == 0)
{
status = TX_CALLER_ERROR;
}
@@ -335,7 +342,7 @@ TX_THREAD_SECURE_STACK_INFO *info_ptr;
/* FUNCTION RELEASE */
/* */
/* _tx_thread_secure_stack_context_save Cortex-M23/GNU */
/* 6.1.1 */
/* 6.1.3 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -354,10 +361,7 @@ TX_THREAD_SECURE_STACK_INFO *info_ptr;
/* */
/* CALLS */
/* */
/* __get_IPSR Intrinsic to get IPSR */
/* __get_PSP Intrinsic to get PSP */
/* __set_PSPLIM Intrinsic to set PSP limit */
/* __set_PSP Intrinsic to set PSP */
/* None */
/* */
/* CALLED BY */
/* */
@@ -370,6 +374,9 @@ TX_THREAD_SECURE_STACK_INFO *info_ptr;
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-16-2020 Scott Larson Modified comment(s), */
/* resulting in version 6.1.1 */
/* 12-31-2020 Scott Larson Modified comment(s), and */
/* fixed M23 GCC build, */
/* resulting in version 6.1.3 */
/* */
/**************************************************************************/
__attribute__((cmse_nonsecure_entry))
@@ -377,9 +384,11 @@ void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr)
{
TX_THREAD_SECURE_STACK_INFO *info_ptr;
ULONG sp;
ULONG ipsr;
/* This function should be called from scheduler only. */
if (__get_IPSR() == 0)
asm volatile("MRS %0, IPSR" : "=r" (ipsr)); /* Get IPSR register. */
if (ipsr == 0)
{
return;
}
@@ -394,7 +403,7 @@ ULONG sp;
}
/* Check that stack pointer is in range */
sp = __get_PSP();
asm volatile("MRS %0, PSP" : "=r" (sp)); /* Get PSP register. */
if ((sp < (ULONG)info_ptr -> tx_thread_secure_stack_limit) ||
(sp > (ULONG)info_ptr -> tx_thread_secure_stack_start))
{
@@ -406,8 +415,8 @@ ULONG sp;
/* Set process stack pointer and stack limit to 0 to throw exception when a thread
without a secure stack calls a secure function that tries to use secure stack. */
__set_PSPLIM(0);
__set_PSP(0);
asm volatile("MSR PSPLIM, %0" :: "r" (0));
asm volatile("MSR PSP, %0" :: "r" (0));
return;
}
@@ -419,7 +428,7 @@ ULONG sp;
/* FUNCTION RELEASE */
/* */
/* _tx_thread_secure_stack_context_restore Cortex-M23/GNU */
/* 6.1.1 */
/* 6.1.3 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
@@ -438,9 +447,7 @@ ULONG sp;
/* */
/* CALLS */
/* */
/* __get_IPSR Intrinsic to get IPSR */
/* __set_PSPLIM Intrinsic to set PSP limit */
/* __set_PSP Intrinsic to set PSP */
/* None */
/* */
/* CALLED BY */
/* */
@@ -453,15 +460,20 @@ ULONG sp;
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 10-16-2020 Scott Larson Modified comment(s), */
/* resulting in version 6.1.1 */
/* 12-31-2020 Scott Larson Modified comment(s), and */
/* fixed M23 GCC build, */
/* resulting in version 6.1.3 */
/* */
/**************************************************************************/
__attribute__((cmse_nonsecure_entry))
void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr)
{
TX_THREAD_SECURE_STACK_INFO *info_ptr;
ULONG ipsr;
/* This function should be called from scheduler only. */
if (__get_IPSR() == 0)
asm volatile("MRS %0, IPSR" : "=r" (ipsr)); /* Get IPSR register. */
if (ipsr == 0)
{
return;
}
@@ -476,8 +488,8 @@ TX_THREAD_SECURE_STACK_INFO *info_ptr;
}
/* Set stack pointer and limit. */
__set_PSPLIM((ULONG)info_ptr -> tx_thread_secure_stack_limit);
__set_PSP ((ULONG)info_ptr -> tx_thread_secure_stack_ptr);
asm volatile("MSR PSPLIM, %0" :: "r" ((ULONG)info_ptr -> tx_thread_secure_stack_limit));
asm volatile("MSR PSP, %0" :: "r" ((ULONG)info_ptr -> tx_thread_secure_stack_ptr));
return;
}

8
ports/cortex_m23/iar/inc/tx_port.h
View File

@@ -26,7 +26,7 @@
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h Cortex-M23/IAR */
/* 6.1 */
/* 6.1.5 */
/* */
/* AUTHOR */
/* */
@@ -47,7 +47,10 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 03-02-2021 Scott Larson Modified comment(s), added */
/* ULONG64_DEFINED, */
/* resulting in version 6.1.5 */
/* */
/**************************************************************************/
@@ -85,6 +88,7 @@ typedef unsigned long ULONG;
typedef unsigned long long ULONG64;
typedef short SHORT;
typedef unsigned short USHORT;
#define ULONG64_DEFINED
/* Function prototypes for this port. */
struct TX_THREAD_STRUCT;

3
ports/cortex_m23/iar/readme_threadx.txt
View File

@@ -9,7 +9,8 @@ Import all ThreadX common and port-specific source files into an IAR project.
Configure the project to build a library rather than an executable. This
results in the ThreadX run-time library file tx.a, which is needed by
the application.
Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c
replace the common files of the same name.
2. Demonstration System

27
ports/cortex_m3/ac5/src/tx_thread_schedule.s
View File

@@ -30,6 +30,10 @@
IMPORT _tx_execution_thread_enter
IMPORT _tx_execution_thread_exit
ENDIF
IF :DEF:TX_LOW_POWER
IMPORT tx_low_power_enter
IMPORT tx_low_power_exit
ENDIF
;
;
AREA ||.text||, CODE, READONLY
@@ -39,7 +43,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M3/AC5 */
;/* 6.1 */
;/* 6.1.5 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -72,7 +76,10 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 03-02-2021 Scott Larson Modified comment(s), add */
;/* low power code, */
;/* resulting in version 6.1.5 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -217,11 +224,25 @@ __tx_ts_wait
LDR r1, [r2] ; Pickup the next thread to execute pointer
STR r1, [r0] ; Store it in the current pointer
CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready!
IF :DEF:TX_ENABLE_WFI
IF:DEF:TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter ; Possibly enter low power mode
POP {r0-r3}
ENDIF
IF:DEF:TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
ENDIF
IF:DEF:TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit ; Exit low power mode
POP {r0-r3}
ENDIF
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;

26
ports/cortex_m3/ac6/src/tx_thread_schedule.S
View File

@@ -25,6 +25,11 @@
.global _tx_thread_execute_ptr
.global _tx_timer_time_slice
.global _tx_thread_system_stack_ptr
#ifdef TX_LOW_POWER
.global tx_low_power_enter
.global tx_low_power_exit
#endif
@
@
.text
@@ -35,7 +40,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_schedule Cortex-M3/AC6 */
@/* 6.1 */
@/* 6.1.5 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -68,7 +73,10 @@
@/* */
@/* DATE NAME DESCRIPTION */
@/* */
@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
@/* 03-02-2021 Scott Larson Modified comment(s), add */
@/* low power code, */
@/* resulting in version 6.1.5 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_schedule(VOID)
@@ -218,11 +226,25 @@ __tx_ts_wait:
LDR r1, [r2] @ Pickup the next thread to execute pointer
STR r1, [r0] @ Store it in the current pointer
CBNZ r1, __tx_ts_ready @ If non-NULL, a new thread is ready!
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter @ Possibly enter low power mode
POP {r0-r3}
#endif
#ifdef TX_ENABLE_WFI
DSB @ Ensure no outstanding memory transactions
WFI @ Wait for interrupt
ISB @ Ensure pipeline is flushed
#endif
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit @ Exit low power mode
POP {r0-r3}
#endif
CPSIE i @ Enable interrupts
B __tx_ts_wait @ Loop to continue waiting
@

21
ports/cortex_m3/ghs/src/tx_thread_schedule.arm
View File

@@ -28,7 +28,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M3/GHS */
;/* 6.1 */
;/* 6.1.5 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -61,7 +61,10 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 03-02-2021 Scott Larson Modified comment(s), add */
;/* low power code, */
;/* resulting in version 6.1.5 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -210,11 +213,25 @@ __tx_ts_wait:
LDR r1, [r2] ; Pickup the next thread to execute pointer
STR r1, [r0] ; Store it in the current pointer
CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready!
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter ; Possibly enter low power mode
POP {r0-r3}
#endif
#ifdef TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
#endif
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit ; Exit low power mode
POP {r0-r3}
#endif
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;

0
ports/cortex_m3/gnu/CMakeLists.txt Normal file → Executable file
View File

29
ports/cortex_m3/gnu/src/tx_thread_schedule.S
View File

@@ -27,6 +27,10 @@
.global _tx_thread_system_stack_ptr
.global _tx_execution_thread_enter
.global _tx_execution_thread_exit
#ifdef TX_LOW_POWER
.global tx_low_power_enter
.global tx_low_power_exit
#endif
@
@
.text
@@ -37,7 +41,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_schedule Cortex-M3/GNU */
@/* 6.1 */
@/* 6.1.5 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -70,9 +74,12 @@
@/* */
@/* DATE NAME DESCRIPTION */
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 09-30-2020 William E. Lamie Modified comment(s), */
@/* resulting in version 6.1 */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 09-30-2020 William E. Lamie Modified comment(s), */
@/* resulting in version 6.1 */
@/* 03-02-2021 Scott Larson Modified comment(s), add */
@/* low power code, */
@/* resulting in version 6.1.5 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_schedule(VOID)
@@ -222,11 +229,25 @@ __tx_ts_wait:
LDR r1, [r2] @ Pickup the next thread to execute pointer
STR r1, [r0] @ Store it in the current pointer
CBNZ r1, __tx_ts_ready @ If non-NULL, a new thread is ready!
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter @ Possibly enter low power mode
POP {r0-r3}
#endif
#ifdef TX_ENABLE_WFI
DSB @ Ensure no outstanding memory transactions
WFI @ Wait for interrupt
ISB @ Ensure pipeline is flushed
#endif
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit @ Exit low power mode
POP {r0-r3}
#endif
CPSIE i @ Enable interrupts
B __tx_ts_wait @ Loop to continue waiting
@

25
ports/cortex_m3/iar/src/tx_thread_schedule.s
View File

@@ -28,6 +28,10 @@
EXTERN _tx_execution_thread_enter
EXTERN _tx_execution_thread_exit
EXTERN _tx_thread_preempt_disable
#ifdef TX_LOW_POWER
EXTERN tx_low_power_enter
EXTERN tx_low_power_exit
#endif
;
;
SECTION `.text`:CODE:NOROOT(2)
@@ -37,7 +41,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M3/IAR */
;/* 6.1 */
;/* 6.1.5 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -70,7 +74,10 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 03-02-2021 Scott Larson Modified comment(s), add */
;/* low power code, */
;/* resulting in version 6.1.5 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -216,11 +223,25 @@ __tx_ts_wait:
LDR r1, [r2] ; Pickup the next thread to execute pointer
STR r1, [r0] ; Store it in the current pointer
CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready!
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter ; Possibly enter low power mode
POP {r0-r3}
#endif
#ifdef TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
#endif
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit ; Exit low power mode
POP {r0-r3}
#endif
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;

27
ports/cortex_m3/keil/src/tx_thread_schedule.s
View File

@@ -30,6 +30,10 @@
IMPORT _tx_execution_thread_enter
IMPORT _tx_execution_thread_exit
ENDIF
IF :DEF:TX_LOW_POWER
IMPORT tx_low_power_enter
IMPORT tx_low_power_exit
ENDIF
;
;
AREA ||.text||, CODE, READONLY
@@ -39,7 +43,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M3/AC5 */
;/* 6.1 */
;/* 6.1.5 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -72,7 +76,10 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 03-02-2021 Scott Larson Modified comment(s), add */
;/* low power code, */
;/* resulting in version 6.1.5 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -217,11 +224,25 @@ __tx_ts_wait
LDR r1, [r2] ; Pickup the next thread to execute pointer
STR r1, [r0] ; Store it in the current pointer
CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready!
IF :DEF:TX_ENABLE_WFI
IF:DEF:TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter ; Possibly enter low power mode
POP {r0-r3}
ENDIF
IF:DEF:TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
ENDIF
IF:DEF:TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit ; Exit low power mode
POP {r0-r3}
ENDIF
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;

138
ports/cortex_m33/ac5/readme_threadx.txt
View File

@@ -53,80 +53,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD.
Non-FPU Stack Frame:
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 (Hardware stack starts here!!)
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4 Software stacked GP registers
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 Hardware stacked registers
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
FPU Stack Frame (only interrupted thread with FPU enabled):
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s0
0x08 s1
0x0C s2
0x10 s3
0x14 s4
0x18 s5
0x1C s6
0x20 s7
0x24 s8
0x28 s9
0x2C s10
0x30 s11
0x34 s12
0x38 s13
0x3C s14
0x40 s15
0x44 s16
0x48 s17
0x4C s18
0x50 s19
0x54 s20
0x58 s21
0x5C s22
0x60 s23
0x64 s24
0x68 s25
0x6C s26
0x70 s27
0x74 s28
0x78 s29
0x7C s30
0x80 s31
0x84 fpscr
0x88 r4
0x8C r5
0x90 r6
0x94 r7
0x98 r8
0x9C r9
0xA0 r10
0xA4 r11
0xA8 r0 (Hardware stack starts here!!)
0xAC r1
0xB0 r2
0xB4 r3
0xB8 r12
0xBC lr
0xC0 pc
0xC4 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s16 Software stacked FPU registers
0x08 s17
0x0C s18
0x10 s19
0x14 s20
0x18 s21
0x1C s22
0x20 s23
0x24 s24
0x28 s25
0x2C s26
0x30 s27
0x34 s28
0x38 s29
0x3C s30
0x40 s31
0x44 r4 Software stacked registers
0x48 r5
0x4C r6
0x50 r7
0x54 r8
0x58 r9
0x5C r10
0x60 r11
0x64 r0 Hardware stacked registers
0x68 r1
0x6C r2
0x70 r3
0x74 r12
0x78 lr
0x7C pc
0x80 xPSR
0x84 s0 Hardware stacked FPU registers
0x88 s1
0x8C s2
0x90 s3
0x94 s4
0x98 s5
0x9C s6
0xA0 s7
0xA4 s8
0xA8 s9
0xAC s10
0xB0 s11
0xB4 s12
0xB8 s13
0xBC s14
0xC0 s15
0xC4 fpscr
6. Improving Performance

8
ports/cortex_m33/ac6/inc/tx_port.h
View File

@@ -26,7 +26,7 @@
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h Cortex-M33/AC6 */
/* 6.1 */
/* 6.1.5 */
/* */
/* AUTHOR */
/* */
@@ -47,7 +47,10 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 03-02-2021 Scott Larson Modified comment(s), added */
/* ULONG64_DEFINED, */
/* resulting in version 6.1.5 */
/* */
/**************************************************************************/
@@ -82,6 +85,7 @@ typedef unsigned long ULONG;
typedef unsigned long long ULONG64;
typedef short SHORT;
typedef unsigned short USHORT;
#define ULONG64_DEFINED
/* Function prototypes for this port. */
struct TX_THREAD_STRUCT;

141
ports/cortex_m33/ac6/readme_threadx.txt
View File

@@ -15,7 +15,8 @@ Building the ThreadX library is easy; simply set the ThreadX_Library project
as active, then then build the library. You should now observe the compilation
and assembly of the ThreadX library. This project build produces the ThreadX
library file ThreadX_Library.lib.
Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c
replace the common files of the same name.
3. Demonstration System
@@ -53,80 +54,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD.
Non-FPU Stack Frame:
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 (Hardware stack starts here!!)
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4 Software stacked GP registers
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 Hardware stacked registers
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
FPU Stack Frame (only interrupted thread with FPU enabled):
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s0
0x08 s1
0x0C s2
0x10 s3
0x14 s4
0x18 s5
0x1C s6
0x20 s7
0x24 s8
0x28 s9
0x2C s10
0x30 s11
0x34 s12
0x38 s13
0x3C s14
0x40 s15
0x44 s16
0x48 s17
0x4C s18
0x50 s19
0x54 s20
0x58 s21
0x5C s22
0x60 s23
0x64 s24
0x68 s25
0x6C s26
0x70 s27
0x74 s28
0x78 s29
0x7C s30
0x80 s31
0x84 fpscr
0x88 r4
0x8C r5
0x90 r6
0x94 r7
0x98 r8
0x9C r9
0xA0 r10
0xA4 r11
0xA8 r0 (Hardware stack starts here!!)
0xAC r1
0xB0 r2
0xB4 r3
0xB8 r12
0xBC lr
0xC0 pc
0xC4 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s16 Software stacked FPU registers
0x08 s17
0x0C s18
0x10 s19
0x14 s20
0x18 s21
0x1C s22
0x20 s23
0x24 s24
0x28 s25
0x2C s26
0x30 s27
0x34 s28
0x38 s29
0x3C s30
0x40 s31
0x44 r4 Software stacked registers
0x48 r5
0x4C r6
0x50 r7
0x54 r8
0x58 r9
0x5C r10
0x60 r11
0x64 r0 Hardware stacked registers
0x68 r1
0x6C r2
0x70 r3
0x74 r12
0x78 lr
0x7C pc
0x80 xPSR
0x84 s0 Hardware stacked FPU registers
0x88 s1
0x8C s2
0x90 s3
0x94 s4
0x98 s5
0x9C s6
0xA0 s7
0xA4 s8
0xA8 s9
0xAC s10
0xB0 s11
0xB4 s12
0xB8 s13
0xBC s14
0xC0 s15
0xC4 fpscr
6. Improving Performance

8
ports/cortex_m33/gnu/inc/tx_port.h
View File

@@ -26,7 +26,7 @@
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h Cortex-M33/GNU */
/* 6.1 */
/* 6.1.5 */
/* */
/* AUTHOR */
/* */
@@ -47,7 +47,10 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 03-02-2021 Scott Larson Modified comment(s), added */
/* ULONG64_DEFINED, */
/* resulting in version 6.1.5 */
/* */
/**************************************************************************/
@@ -80,6 +83,7 @@ typedef unsigned long ULONG;
typedef unsigned long long ULONG64;
typedef short SHORT;
typedef unsigned short USHORT;
#define ULONG64_DEFINED
/* Function prototypes for this port. */
struct TX_THREAD_STRUCT;

141
ports/cortex_m33/gnu/readme_threadx.txt
View File

@@ -8,7 +8,8 @@ Import all ThreadX common and port-specific source files into a GNU project.
Configure the project to build a library rather than an executable. This
results in the ThreadX run-time library file tx.a, which is needed by
the application.
Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c
replace the common files of the same name.
2. Demonstration System
@@ -39,80 +40,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD.
Non-FPU Stack Frame:
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 (Hardware stack starts here!!)
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4 Software stacked GP registers
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 Hardware stacked registers
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
FPU Stack Frame (only interrupted thread with FPU enabled):
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s0
0x08 s1
0x0C s2
0x10 s3
0x14 s4
0x18 s5
0x1C s6
0x20 s7
0x24 s8
0x28 s9
0x2C s10
0x30 s11
0x34 s12
0x38 s13
0x3C s14
0x40 s15
0x44 s16
0x48 s17
0x4C s18
0x50 s19
0x54 s20
0x58 s21
0x5C s22
0x60 s23
0x64 s24
0x68 s25
0x6C s26
0x70 s27
0x74 s28
0x78 s29
0x7C s30
0x80 s31
0x84 fpscr
0x88 r4
0x8C r5
0x90 r6
0x94 r7
0x98 r8
0x9C r9
0xA0 r10
0xA4 r11
0xA8 r0 (Hardware stack starts here!!)
0xAC r1
0xB0 r2
0xB4 r3
0xB8 r12
0xBC lr
0xC0 pc
0xC4 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s16 Software stacked FPU registers
0x08 s17
0x0C s18
0x10 s19
0x14 s20
0x18 s21
0x1C s22
0x20 s23
0x24 s24
0x28 s25
0x2C s26
0x30 s27
0x34 s28
0x38 s29
0x3C s30
0x40 s31
0x44 r4 Software stacked registers
0x48 r5
0x4C r6
0x50 r7
0x54 r8
0x58 r9
0x5C r10
0x60 r11
0x64 r0 Hardware stacked registers
0x68 r1
0x6C r2
0x70 r3
0x74 r12
0x78 lr
0x7C pc
0x80 xPSR
0x84 s0 Hardware stacked FPU registers
0x88 s1
0x8C s2
0x90 s3
0x94 s4
0x98 s5
0x9C s6
0xA0 s7
0xA4 s8
0xA8 s9
0xAC s10
0xB0 s11
0xB4 s12
0xB8 s13
0xBC s14
0xC0 s15
0xC4 fpscr
5. Improving Performance

8
ports/cortex_m33/iar/inc/tx_port.h
View File

@@ -26,7 +26,7 @@
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h Cortex-M33/IAR */
/* 6.1 */
/* 6.1.5 */
/* */
/* AUTHOR */
/* */
@@ -47,7 +47,10 @@
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 09-30-2020 Scott Larson Initial Version 6.1 */
/* 03-02-2021 Scott Larson Modified comment(s), added */
/* ULONG64_DEFINED, */
/* resulting in version 6.1.5 */
/* */
/**************************************************************************/
@@ -85,6 +88,7 @@ typedef unsigned long ULONG;
typedef unsigned long long ULONG64;
typedef short SHORT;
typedef unsigned short USHORT;
#define ULONG64_DEFINED
/* Function prototypes for this port. */
struct TX_THREAD_STRUCT;

141
ports/cortex_m33/iar/readme_threadx.txt
View File

@@ -9,7 +9,8 @@ Import all ThreadX common and port-specific source files into an IAR project.
Configure the project to build a library rather than an executable. This
results in the ThreadX run-time library file tx.a, which is needed by
the application.
Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c
replace the common files of the same name.
2. Demonstration System
@@ -45,80 +46,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD.
Non-FPU Stack Frame:
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 (Hardware stack starts here!!)
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4 Software stacked GP registers
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 Hardware stacked registers
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
FPU Stack Frame (only interrupted thread with FPU enabled):
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s0
0x08 s1
0x0C s2
0x10 s3
0x14 s4
0x18 s5
0x1C s6
0x20 s7
0x24 s8
0x28 s9
0x2C s10
0x30 s11
0x34 s12
0x38 s13
0x3C s14
0x40 s15
0x44 s16
0x48 s17
0x4C s18
0x50 s19
0x54 s20
0x58 s21
0x5C s22
0x60 s23
0x64 s24
0x68 s25
0x6C s26
0x70 s27
0x74 s28
0x78 s29
0x7C s30
0x80 s31
0x84 fpscr
0x88 r4
0x8C r5
0x90 r6
0x94 r7
0x98 r8
0x9C r9
0xA0 r10
0xA4 r11
0xA8 r0 (Hardware stack starts here!!)
0xAC r1
0xB0 r2
0xB4 r3
0xB8 r12
0xBC lr
0xC0 pc
0xC4 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s16 Software stacked FPU registers
0x08 s17
0x0C s18
0x10 s19
0x14 s20
0x18 s21
0x1C s22
0x20 s23
0x24 s24
0x28 s25
0x2C s26
0x30 s27
0x34 s28
0x38 s29
0x3C s30
0x40 s31
0x44 r4 Software stacked registers
0x48 r5
0x4C r6
0x50 r7
0x54 r8
0x58 r9
0x5C r10
0x60 r11
0x64 r0 Hardware stacked registers
0x68 r1
0x6C r2
0x70 r3
0x74 r12
0x78 lr
0x7C pc
0x80 xPSR
0x84 s0 Hardware stacked FPU registers
0x88 s1
0x8C s2
0x90 s3
0x94 s4
0x98 s5
0x9C s6
0xA0 s7
0xA4 s8
0xA8 s9
0xAC s10
0xB0 s11
0xB4 s12
0xB8 s13
0xBC s14
0xC0 s15
0xC4 fpscr
5. Improving Performance

136
ports/cortex_m4/ac5/readme_threadx.txt
View File

@@ -56,78 +56,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD.
Non-FPU Stack Frame:
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 r4
0x04 r5
0x08 r6
0x0C r7
0x10 r8
0x14 r9
0x18 r10
0x1C r11
0x20 r0 (Hardware stack starts here!!)
0x24 r1
0x28 r2
0x2C r3
0x30 r12
0x34 lr
0x38 pc
0x3C xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4 Software stacked GP registers
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 Hardware stacked registers
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
FPU Stack Frame (only interrupted thread with FPU enabled):
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 s0
0x04 s1
0x08 s2
0x0C s3
0x10 s4
0x14 s5
0x18 s6
0x1C s7
0x20 s8
0x24 s9
0x28 s10
0x2C s11
0x30 s12
0x34 s13
0x38 s14
0x3C s15
0x40 s16
0x44 s17
0x48 s18
0x4C s19
0x50 s20
0x54 s21
0x58 s22
0x5C s23
0x60 s24
0x64 s25
0x68 s26
0x6C s27
0x70 s28
0x74 s29
0x78 s30
0x7C s31
0x80 fpscr
0x84 r4
0x88 r5
0x8C r6
0x90 r7
0x94 r8
0x98 r9
0x9C r10
0xA0 r11
0xA4 r0 (Hardware stack starts here!!)
0xA8 r1
0xAC r2
0xB0 r3
0xB4 r12
0xB8 lr
0xBC pc
0xC0 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s16 Software stacked FPU registers
0x08 s17
0x0C s18
0x10 s19
0x14 s20
0x18 s21
0x1C s22
0x20 s23
0x24 s24
0x28 s25
0x2C s26
0x30 s27
0x34 s28
0x38 s29
0x3C s30
0x40 s31
0x44 r4 Software stacked registers
0x48 r5
0x4C r6
0x50 r7
0x54 r8
0x58 r9
0x5C r10
0x60 r11
0x64 r0 Hardware stacked registers
0x68 r1
0x6C r2
0x70 r3
0x74 r12
0x78 lr
0x7C pc
0x80 xPSR
0x84 s0 Hardware stacked FPU registers
0x88 s1
0x8C s2
0x90 s3
0x94 s4
0x98 s5
0x9C s6
0xA0 s7
0xA4 s8
0xA8 s9
0xAC s10
0xB0 s11
0xB4 s12
0xB8 s13
0xBC s14
0xC0 s15
0xC4 fpscr
5. Improving Performance

27
ports/cortex_m4/ac5/src/tx_thread_schedule.s
View File

@@ -30,6 +30,10 @@
IMPORT _tx_execution_thread_enter
IMPORT _tx_execution_thread_exit
ENDIF
IF :DEF:TX_LOW_POWER
IMPORT tx_low_power_enter
IMPORT tx_low_power_exit
ENDIF
;
;
AREA ||.text||, CODE, READONLY
@@ -39,7 +43,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M4/AC5 */
;/* 6.1 */
;/* 6.1.5 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -72,7 +76,10 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 03-02-2021 Scott Larson Modified comment(s), add */
;/* low power code, */
;/* resulting in version 6.1.5 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -237,11 +244,25 @@ __tx_ts_wait
LDR r1, [r2] ; Pickup the next thread to execute pointer
STR r1, [r0] ; Store it in the current pointer
CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready!
IF :DEF:TX_ENABLE_WFI
IF:DEF:TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter ; Possibly enter low power mode
POP {r0-r3}
ENDIF
IF:DEF:TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
ENDIF
IF:DEF:TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit ; Exit low power mode
POP {r0-r3}
ENDIF
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;

138
ports/cortex_m4/ac6/readme_threadx.txt
View File

@@ -56,80 +56,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD.
Non-FPU Stack Frame:
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 (Hardware stack starts here!!)
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4 Software stacked GP registers
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 Hardware stacked registers
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
FPU Stack Frame (only interrupted thread with FPU enabled):
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s0
0x08 s1
0x0C s2
0x10 s3
0x14 s4
0x18 s5
0x1C s6
0x20 s7
0x24 s8
0x28 s9
0x2C s10
0x30 s11
0x34 s12
0x38 s13
0x3C s14
0x40 s15
0x44 s16
0x48 s17
0x4C s18
0x50 s19
0x54 s20
0x58 s21
0x5C s22
0x60 s23
0x64 s24
0x68 s25
0x6C s26
0x70 s27
0x74 s28
0x78 s29
0x7C s30
0x80 s31
0x84 fpscr
0x88 r4
0x8C r5
0x90 r6
0x94 r7
0x98 r8
0x9C r9
0xA0 r10 (sl)
0xA4 r11
0xA8 r0 (Hardware stack starts here!!)
0xAC r1
0xB0 r2
0xB4 r3
0xB8 r12
0xBC lr
0xC0 pc
0xC4 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s16 Software stacked FPU registers
0x08 s17
0x0C s18
0x10 s19
0x14 s20
0x18 s21
0x1C s22
0x20 s23
0x24 s24
0x28 s25
0x2C s26
0x30 s27
0x34 s28
0x38 s29
0x3C s30
0x40 s31
0x44 r4 Software stacked registers
0x48 r5
0x4C r6
0x50 r7
0x54 r8
0x58 r9
0x5C r10
0x60 r11
0x64 r0 Hardware stacked registers
0x68 r1
0x6C r2
0x70 r3
0x74 r12
0x78 lr
0x7C pc
0x80 xPSR
0x84 s0 Hardware stacked FPU registers
0x88 s1
0x8C s2
0x90 s3
0x94 s4
0x98 s5
0x9C s6
0xA0 s7
0xA4 s8
0xA8 s9
0xAC s10
0xB0 s11
0xB4 s12
0xB8 s13
0xBC s14
0xC0 s15
0xC4 fpscr
6. Improving Performance

26
ports/cortex_m4/ac6/src/tx_thread_schedule.S
View File

@@ -25,6 +25,11 @@
.global _tx_thread_execute_ptr
.global _tx_timer_time_slice
.global _tx_thread_system_stack_ptr
#ifdef TX_LOW_POWER
.global tx_low_power_enter
.global tx_low_power_exit
#endif
@
@
.text
@@ -35,7 +40,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_schedule Cortex-M4/AC6 */
@/* 6.1 */
@/* 6.1.5 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -68,7 +73,10 @@
@/* */
@/* DATE NAME DESCRIPTION */
@/* */
@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
@/* 03-02-2021 Scott Larson Modified comment(s), add */
@/* low power code, */
@/* resulting in version 6.1.5 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_schedule(VOID)
@@ -238,11 +246,25 @@ __tx_ts_wait:
LDR r1, [r2] @ Pickup the next thread to execute pointer
STR r1, [r0] @ Store it in the current pointer
CBNZ r1, __tx_ts_ready @ If non-NULL, a new thread is ready!
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter @ Possibly enter low power mode
POP {r0-r3}
#endif
#ifdef TX_ENABLE_WFI
DSB @ Ensure no outstanding memory transactions
WFI @ Wait for interrupt
ISB @ Ensure pipeline is flushed
#endif
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit @ Exit low power mode
POP {r0-r3}
#endif
CPSIE i @ Enable interrupts
B __tx_ts_wait @ Loop to continue waiting
@

136
ports/cortex_m4/ghs/readme_threadx.txt
View File

@@ -81,78 +81,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD.
Non-FPU Stack Frame:
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 r4
0x04 r5
0x08 r6
0x0C r7
0x10 r8
0x14 r9
0x18 r10
0x1C r11
0x20 r0 (Hardware stack starts here!!)
0x24 r1
0x28 r2
0x2C r3
0x30 r12
0x34 lr
0x38 pc
0x3C xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4 Software stacked GP registers
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 Hardware stacked registers
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
FPU Stack Frame (only interrupted thread with FPU enabled):
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 s0
0x04 s1
0x08 s2
0x0C s3
0x10 s4
0x14 s5
0x18 s6
0x1C s7
0x20 s8
0x24 s9
0x28 s10
0x2C s11
0x30 s12
0x34 s13
0x38 s14
0x3C s15
0x40 s16
0x44 s17
0x48 s18
0x4C s19
0x50 s20
0x54 s21
0x58 s22
0x5C s23
0x60 s24
0x64 s25
0x68 s26
0x6C s27
0x70 s28
0x74 s29
0x78 s30
0x7C s31
0x80 fpscr
0x84 r4
0x88 r5
0x8C r6
0x90 r7
0x94 r8
0x98 r9
0x9C r10 (sl)
0xA0 r11
0xA4 r0 (Hardware stack starts here!!)
0xA8 r1
0xAC r2
0xB0 r3
0xB4 r12
0xB8 lr
0xBC pc
0xC0 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s16 Software stacked FPU registers
0x08 s17
0x0C s18
0x10 s19
0x14 s20
0x18 s21
0x1C s22
0x20 s23
0x24 s24
0x28 s25
0x2C s26
0x30 s27
0x34 s28
0x38 s29
0x3C s30
0x40 s31
0x44 r4 Software stacked registers
0x48 r5
0x4C r6
0x50 r7
0x54 r8
0x58 r9
0x5C r10
0x60 r11
0x64 r0 Hardware stacked registers
0x68 r1
0x6C r2
0x70 r3
0x74 r12
0x78 lr
0x7C pc
0x80 xPSR
0x84 s0 Hardware stacked FPU registers
0x88 s1
0x8C s2
0x90 s3
0x94 s4
0x98 s5
0x9C s6
0xA0 s7
0xA4 s8
0xA8 s9
0xAC s10
0xB0 s11
0xB4 s12
0xB8 s13
0xBC s14
0xC0 s15
0xC4 fpscr
7. Improving Performance

21
ports/cortex_m4/ghs/src/tx_thread_schedule.arm
View File

@@ -28,7 +28,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M4/GHS */
;/* 6.1 */
;/* 6.1.5 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -61,7 +61,10 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 03-02-2021 Scott Larson Modified comment(s), add */
;/* low power code, */
;/* resulting in version 6.1.5 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -230,11 +233,25 @@ __tx_ts_wait:
LDR r1, [r2] ; Pickup the next thread to execute pointer
STR r1, [r0] ; Store it in the current pointer
CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready!
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter ; Possibly enter low power mode
POP {r0-r3}
#endif
#ifdef TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
#endif
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit ; Exit low power mode
POP {r0-r3}
#endif
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;

0
ports/cortex_m4/gnu/CMakeLists.txt Normal file → Executable file
View File

138
ports/cortex_m4/gnu/readme_threadx.txt
View File

@@ -53,80 +53,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD.
Non-FPU Stack Frame:
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 (Hardware stack starts here!!)
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4 Software stacked GP registers
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 Hardware stacked registers
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
FPU Stack Frame (only interrupted thread with FPU enabled):
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s0
0x08 s1
0x0C s2
0x10 s3
0x14 s4
0x18 s5
0x1C s6
0x20 s7
0x24 s8
0x28 s9
0x2C s10
0x30 s11
0x34 s12
0x38 s13
0x3C s14
0x40 s15
0x44 s16
0x48 s17
0x4C s18
0x50 s19
0x54 s20
0x58 s21
0x5C s22
0x60 s23
0x64 s24
0x68 s25
0x6C s26
0x70 s27
0x74 s28
0x78 s29
0x7C s30
0x80 s31
0x84 fpscr
0x88 r4
0x8C r5
0x90 r6
0x94 r7
0x98 r8
0x9C r9
0xA0 r10 (sl)
0xA4 r11
0xA8 r0 (Hardware stack starts here!!)
0xAC r1
0xB0 r2
0xB4 r3
0xB8 r12
0xBC lr
0xC0 pc
0xC4 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s16 Software stacked FPU registers
0x08 s17
0x0C s18
0x10 s19
0x14 s20
0x18 s21
0x1C s22
0x20 s23
0x24 s24
0x28 s25
0x2C s26
0x30 s27
0x34 s28
0x38 s29
0x3C s30
0x40 s31
0x44 r4 Software stacked registers
0x48 r5
0x4C r6
0x50 r7
0x54 r8
0x58 r9
0x5C r10
0x60 r11
0x64 r0 Hardware stacked registers
0x68 r1
0x6C r2
0x70 r3
0x74 r12
0x78 lr
0x7C pc
0x80 xPSR
0x84 s0 Hardware stacked FPU registers
0x88 s1
0x8C s2
0x90 s3
0x94 s4
0x98 s5
0x9C s6
0xA0 s7
0xA4 s8
0xA8 s9
0xAC s10
0xB0 s11
0xB4 s12
0xB8 s13
0xBC s14
0xC0 s15
0xC4 fpscr
5. Improving Performance

29
ports/cortex_m4/gnu/src/tx_thread_schedule.S
View File

@@ -27,6 +27,10 @@
.global _tx_thread_system_stack_ptr
.global _tx_execution_thread_enter
.global _tx_execution_thread_exit
#ifdef TX_LOW_POWER
.global tx_low_power_enter
.global tx_low_power_exit
#endif
@
@
.text
@@ -37,7 +41,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_schedule Cortex-M4/GNU */
@/* 6.1 */
@/* 6.1.5 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -70,9 +74,12 @@
@/* */
@/* DATE NAME DESCRIPTION */
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 09-30-2020 William E. Lamie Modified comment(s), */
@/* resulting in version 6.1 */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 09-30-2020 William E. Lamie Modified comment(s), */
@/* resulting in version 6.1 */
@/* 03-02-2021 Scott Larson Modified comment(s), add */
@/* low power code, */
@/* resulting in version 6.1.5 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_schedule(VOID)
@@ -242,11 +249,25 @@ __tx_ts_wait:
LDR r1, [r2] @ Pickup the next thread to execute pointer
STR r1, [r0] @ Store it in the current pointer
CBNZ r1, __tx_ts_ready @ If non-NULL, a new thread is ready!
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter @ Possibly enter low power mode
POP {r0-r3}
#endif
#ifdef TX_ENABLE_WFI
DSB @ Ensure no outstanding memory transactions
WFI @ Wait for interrupt
ISB @ Ensure pipeline is flushed
#endif
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit @ Exit low power mode
POP {r0-r3}
#endif
CPSIE i @ Enable interrupts
B __tx_ts_wait @ Loop to continue waiting
@

138
ports/cortex_m4/iar/readme_threadx.txt
View File

@@ -58,80 +58,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD.
Non-FPU Stack Frame:
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10 (sl)
0x20 r11
0x24 r0 (Hardware stack starts here!!)
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4 Software stacked GP registers
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 Hardware stacked registers
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
FPU Stack Frame (only interrupted thread with FPU enabled):
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s0
0x08 s1
0x0C s2
0x10 s3
0x14 s4
0x18 s5
0x1C s6
0x20 s7
0x24 s8
0x28 s9
0x2C s10
0x30 s11
0x34 s12
0x38 s13
0x3C s14
0x40 s15
0x44 s16
0x48 s17
0x4C s18
0x50 s19
0x54 s20
0x58 s21
0x5C s22
0x60 s23
0x64 s24
0x68 s25
0x6C s26
0x70 s27
0x74 s28
0x78 s29
0x7C s30
0x80 s31
0x84 fpscr
0x88 r4
0x8C r5
0x90 r6
0x94 r7
0x98 r8
0x9C r9
0xA0 r10 (sl)
0xA4 r11
0xA8 r0 (Hardware stack starts here!!)
0xAC r1
0xB0 r2
0xB4 r3
0xB8 r12
0xBC lr
0xC0 pc
0xC4 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s16 Software stacked FPU registers
0x08 s17
0x0C s18
0x10 s19
0x14 s20
0x18 s21
0x1C s22
0x20 s23
0x24 s24
0x28 s25
0x2C s26
0x30 s27
0x34 s28
0x38 s29
0x3C s30
0x40 s31
0x44 r4 Software stacked registers
0x48 r5
0x4C r6
0x50 r7
0x54 r8
0x58 r9
0x5C r10
0x60 r11
0x64 r0 Hardware stacked registers
0x68 r1
0x6C r2
0x70 r3
0x74 r12
0x78 lr
0x7C pc
0x80 xPSR
0x84 s0 Hardware stacked FPU registers
0x88 s1
0x8C s2
0x90 s3
0x94 s4
0x98 s5
0x9C s6
0xA0 s7
0xA4 s8
0xA8 s9
0xAC s10
0xB0 s11
0xB4 s12
0xB8 s13
0xBC s14
0xC0 s15
0xC4 fpscr
5. Improving Performance

25
ports/cortex_m4/iar/src/tx_thread_schedule.s
View File

@@ -28,6 +28,10 @@
EXTERN _tx_execution_thread_enter
EXTERN _tx_execution_thread_exit
EXTERN _tx_thread_preempt_disable
#ifdef TX_LOW_POWER
EXTERN tx_low_power_enter
EXTERN tx_low_power_exit
#endif
;
;
SECTION `.text`:CODE:NOROOT(2)
@@ -37,7 +41,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M4/IAR */
;/* 6.1 */
;/* 6.1.5 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -70,7 +74,10 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 03-02-2021 Scott Larson Modified comment(s), add */
;/* low power code, */
;/* resulting in version 6.1.5 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -236,11 +243,25 @@ __tx_ts_wait:
LDR r1, [r2] ; Pickup the next thread to execute pointer
STR r1, [r0] ; Store it in the current pointer
CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready!
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter ; Possibly enter low power mode
POP {r0-r3}
#endif
#ifdef TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
#endif
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit ; Exit low power mode
POP {r0-r3}
#endif
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;

136
ports/cortex_m4/keil/readme_threadx.txt
View File

@@ -57,78 +57,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD.
Non-FPU Stack Frame:
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 r4
0x04 r5
0x08 r6
0x0C r7
0x10 r8
0x14 r9
0x18 r10
0x1C r11
0x20 r0 (Hardware stack starts here!!)
0x24 r1
0x28 r2
0x2C r3
0x30 r12
0x34 lr
0x38 pc
0x3C xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4 Software stacked GP registers
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 Hardware stacked registers
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
FPU Stack Frame (only interrupted thread with FPU enabled):
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 s0
0x04 s1
0x08 s2
0x0C s3
0x10 s4
0x14 s5
0x18 s6
0x1C s7
0x20 s8
0x24 s9
0x28 s10
0x2C s11
0x30 s12
0x34 s13
0x38 s14
0x3C s15
0x40 s16
0x44 s17
0x48 s18
0x4C s19
0x50 s20
0x54 s21
0x58 s22
0x5C s23
0x60 s24
0x64 s25
0x68 s26
0x6C s27
0x70 s28
0x74 s29
0x78 s30
0x7C s31
0x80 fpscr
0x84 r4
0x88 r5
0x8C r6
0x90 r7
0x94 r8
0x98 r9
0x9C r10 (sl)
0xA0 r11
0xA4 r0 (Hardware stack starts here!!)
0xA8 r1
0xAC r2
0xB0 r3
0xB4 r12
0xB8 lr
0xBC pc
0xC0 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s16 Software stacked FPU registers
0x08 s17
0x0C s18
0x10 s19
0x14 s20
0x18 s21
0x1C s22
0x20 s23
0x24 s24
0x28 s25
0x2C s26
0x30 s27
0x34 s28
0x38 s29
0x3C s30
0x40 s31
0x44 r4 Software stacked registers
0x48 r5
0x4C r6
0x50 r7
0x54 r8
0x58 r9
0x5C r10
0x60 r11
0x64 r0 Hardware stacked registers
0x68 r1
0x6C r2
0x70 r3
0x74 r12
0x78 lr
0x7C pc
0x80 xPSR
0x84 s0 Hardware stacked FPU registers
0x88 s1
0x8C s2
0x90 s3
0x94 s4
0x98 s5
0x9C s6
0xA0 s7
0xA4 s8
0xA8 s9
0xAC s10
0xB0 s11
0xB4 s12
0xB8 s13
0xBC s14
0xC0 s15
0xC4 fpscr
5. Improving Performance

27
ports/cortex_m4/keil/src/tx_thread_schedule.s
View File

@@ -30,6 +30,10 @@
IMPORT _tx_execution_thread_enter
IMPORT _tx_execution_thread_exit
ENDIF
IF :DEF:TX_LOW_POWER
IMPORT tx_low_power_enter
IMPORT tx_low_power_exit
ENDIF
;
;
AREA ||.text||, CODE, READONLY
@@ -39,7 +43,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M4/AC5 */
;/* 6.1 */
;/* 6.1.5 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -72,7 +76,10 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 03-02-2021 Scott Larson Modified comment(s), add */
;/* low power code, */
;/* resulting in version 6.1.5 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -237,11 +244,25 @@ __tx_ts_wait
LDR r1, [r2] ; Pickup the next thread to execute pointer
STR r1, [r0] ; Store it in the current pointer
CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready!
IF :DEF:TX_ENABLE_WFI
IF:DEF:TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter ; Possibly enter low power mode
POP {r0-r3}
ENDIF
IF:DEF:TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
ENDIF
IF:DEF:TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit ; Exit low power mode
POP {r0-r3}
ENDIF
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;

136
ports/cortex_m7/ac5/readme_threadx.txt
View File

@@ -57,78 +57,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD.
Non-FPU Stack Frame:
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 r4
0x04 r5
0x08 r6
0x0C r7
0x10 r8
0x14 r9
0x18 r10
0x1C r11
0x20 r0 (Hardware stack starts here!!)
0x24 r1
0x28 r2
0x2C r3
0x30 r12
0x34 lr
0x38 pc
0x3C xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4 Software stacked GP registers
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 Hardware stacked registers
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
FPU Stack Frame (only interrupted thread with FPU enabled):
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 s0
0x04 s1
0x08 s2
0x0C s3
0x10 s4
0x14 s5
0x18 s6
0x1C s7
0x20 s8
0x24 s9
0x28 s10
0x2C s11
0x30 s12
0x34 s13
0x38 s14
0x3C s15
0x40 s16
0x44 s17
0x48 s18
0x4C s19
0x50 s20
0x54 s21
0x58 s22
0x5C s23
0x60 s24
0x64 s25
0x68 s26
0x6C s27
0x70 s28
0x74 s29
0x78 s30
0x7C s31
0x80 fpscr
0x84 r4
0x88 r5
0x8C r6
0x90 r7
0x94 r8
0x98 r9
0x9C r10 (sl)
0xA0 r11
0xA4 r0 (Hardware stack starts here!!)
0xA8 r1
0xAC r2
0xB0 r3
0xB4 r12
0xB8 lr
0xBC pc
0xC0 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s16 Software stacked FPU registers
0x08 s17
0x0C s18
0x10 s19
0x14 s20
0x18 s21
0x1C s22
0x20 s23
0x24 s24
0x28 s25
0x2C s26
0x30 s27
0x34 s28
0x38 s29
0x3C s30
0x40 s31
0x44 r4 Software stacked registers
0x48 r5
0x4C r6
0x50 r7
0x54 r8
0x58 r9
0x5C r10
0x60 r11
0x64 r0 Hardware stacked registers
0x68 r1
0x6C r2
0x70 r3
0x74 r12
0x78 lr
0x7C pc
0x80 xPSR
0x84 s0 Hardware stacked FPU registers
0x88 s1
0x8C s2
0x90 s3
0x94 s4
0x98 s5
0x9C s6
0xA0 s7
0xA4 s8
0xA8 s9
0xAC s10
0xB0 s11
0xB4 s12
0xB8 s13
0xBC s14
0xC0 s15
0xC4 fpscr
5. Improving Performance

27
ports/cortex_m7/ac5/src/tx_thread_schedule.s
View File

@@ -30,6 +30,10 @@
IMPORT _tx_execution_thread_enter
IMPORT _tx_execution_thread_exit
ENDIF
IF :DEF:TX_LOW_POWER
IMPORT tx_low_power_enter
IMPORT tx_low_power_exit
ENDIF
;
;
AREA ||.text||, CODE, READONLY
@@ -39,7 +43,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M7/AC5 */
;/* 6.1 */
;/* 6.1.5 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -72,7 +76,10 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 03-02-2021 Scott Larson Modified comment(s), add */
;/* low power code, */
;/* resulting in version 6.1.5 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -237,11 +244,25 @@ __tx_ts_wait
LDR r1, [r2] ; Pickup the next thread to execute pointer
STR r1, [r0] ; Store it in the current pointer
CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready!
IF :DEF:TX_ENABLE_WFI
IF:DEF:TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter ; Possibly enter low power mode
POP {r0-r3}
ENDIF
IF:DEF:TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
ENDIF
IF:DEF:TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit ; Exit low power mode
POP {r0-r3}
ENDIF
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;

92
ports/cortex_m7/ac6/readme_threadx.txt
View File

@@ -55,24 +55,82 @@ ThreadX. The top of the suspended thread's stack is pointed to by
tx_thread_stack_ptr in the associated thread control block TX_THREAD.
Stack Offset Stack Contents
Non-FPU Stack Frame:
0x00 r4
0x04 r5
0x08 r6
0x0C r7
0x10 r8
0x14 r9
0x18 r10
0x1C r11
0x20 r0 (Hardware stack starts here!!)
0x24 r1
0x28 r2
0x2C r3
0x30 r12
0x34 lr
0x38 pc
0x3C xPSR
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4 Software stacked GP registers
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 Hardware stacked registers
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
FPU Stack Frame (only interrupted thread with FPU enabled):
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s16 Software stacked FPU registers
0x08 s17
0x0C s18
0x10 s19
0x14 s20
0x18 s21
0x1C s22
0x20 s23
0x24 s24
0x28 s25
0x2C s26
0x30 s27
0x34 s28
0x38 s29
0x3C s30
0x40 s31
0x44 r4 Software stacked registers
0x48 r5
0x4C r6
0x50 r7
0x54 r8
0x58 r9
0x5C r10
0x60 r11
0x64 r0 Hardware stacked registers
0x68 r1
0x6C r2
0x70 r3
0x74 r12
0x78 lr
0x7C pc
0x80 xPSR
0x84 s0 Hardware stacked FPU registers
0x88 s1
0x8C s2
0x90 s3
0x94 s4
0x98 s5
0x9C s6
0xA0 s7
0xA4 s8
0xA8 s9
0xAC s10
0xB0 s11
0xB4 s12
0xB8 s13
0xBC s14
0xC0 s15
0xC4 fpscr
6. Improving Performance

26
ports/cortex_m7/ac6/src/tx_thread_schedule.S
View File

@@ -25,6 +25,11 @@
.global _tx_thread_execute_ptr
.global _tx_timer_time_slice
.global _tx_thread_system_stack_ptr
#ifdef TX_LOW_POWER
.global tx_low_power_enter
.global tx_low_power_exit
#endif
@
@
.text
@@ -35,7 +40,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_schedule Cortex-M7/AC6 */
@/* 6.1 */
@/* 6.1.5 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -68,7 +73,10 @@
@/* */
@/* DATE NAME DESCRIPTION */
@/* */
@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
@/* 03-02-2021 Scott Larson Modified comment(s), add */
@/* low power code, */
@/* resulting in version 6.1.5 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_schedule(VOID)
@@ -237,11 +245,25 @@ __tx_ts_wait:
LDR r1, [r2] @ Pickup the next thread to execute pointer
STR r1, [r0] @ Store it in the current pointer
CBNZ r1, __tx_ts_ready @ If non-NULL, a new thread is ready!
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter @ Possibly enter low power mode
POP {r0-r3}
#endif
#ifdef TX_ENABLE_WFI
DSB @ Ensure no outstanding memory transactions
WFI @ Wait for interrupt
ISB @ Ensure pipeline is flushed
#endif
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit @ Exit low power mode
POP {r0-r3}
#endif
CPSIE i @ Enable interrupts
B __tx_ts_wait @ Loop to continue waiting
@

136
ports/cortex_m7/ghs/readme_threadx.txt
View File

@@ -81,78 +81,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD.
Non-FPU Stack Frame:
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 r4
0x04 r5
0x08 r6
0x0C r7
0x10 r8
0x14 r9
0x18 r10
0x1C r11
0x20 r0 (Hardware stack starts here!!)
0x24 r1
0x28 r2
0x2C r3
0x30 r12
0x34 lr
0x38 pc
0x3C xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4 Software stacked GP registers
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 Hardware stacked registers
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
FPU Stack Frame (only interrupted thread with FPU enabled):
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 s0
0x04 s1
0x08 s2
0x0C s3
0x10 s4
0x14 s5
0x18 s6
0x1C s7
0x20 s8
0x24 s9
0x28 s10
0x2C s11
0x30 s12
0x34 s13
0x38 s14
0x3C s15
0x40 s16
0x44 s17
0x48 s18
0x4C s19
0x50 s20
0x54 s21
0x58 s22
0x5C s23
0x60 s24
0x64 s25
0x68 s26
0x6C s27
0x70 s28
0x74 s29
0x78 s30
0x7C s31
0x80 fpscr
0x84 r4
0x88 r5
0x8C r6
0x90 r7
0x94 r8
0x98 r9
0x9C r10 (sl)
0xA0 r11
0xA4 r0 (Hardware stack starts here!!)
0xA8 r1
0xAC r2
0xB0 r3
0xB4 r12
0xB8 lr
0xBC pc
0xC0 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s16 Software stacked FPU registers
0x08 s17
0x0C s18
0x10 s19
0x14 s20
0x18 s21
0x1C s22
0x20 s23
0x24 s24
0x28 s25
0x2C s26
0x30 s27
0x34 s28
0x38 s29
0x3C s30
0x40 s31
0x44 r4 Software stacked registers
0x48 r5
0x4C r6
0x50 r7
0x54 r8
0x58 r9
0x5C r10
0x60 r11
0x64 r0 Hardware stacked registers
0x68 r1
0x6C r2
0x70 r3
0x74 r12
0x78 lr
0x7C pc
0x80 xPSR
0x84 s0 Hardware stacked FPU registers
0x88 s1
0x8C s2
0x90 s3
0x94 s4
0x98 s5
0x9C s6
0xA0 s7
0xA4 s8
0xA8 s9
0xAC s10
0xB0 s11
0xB4 s12
0xB8 s13
0xBC s14
0xC0 s15
0xC4 fpscr
7. Improving Performance

21
ports/cortex_m7/ghs/src/tx_thread_schedule.arm
View File

@@ -28,7 +28,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M7/GHS */
;/* 6.1 */
;/* 6.1.5 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -61,7 +61,10 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 03-02-2021 Scott Larson Modified comment(s), add */
;/* low power code, */
;/* resulting in version 6.1.5 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -230,11 +233,25 @@ __tx_ts_wait:
LDR r1, [r2] ; Pickup the next thread to execute pointer
STR r1, [r0] ; Store it in the current pointer
CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready!
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter ; Possibly enter low power mode
POP {r0-r3}
#endif
#ifdef TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
#endif
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit ; Exit low power mode
POP {r0-r3}
#endif
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;

0
ports/cortex_m7/gnu/CMakeLists.txt Normal file → Executable file
View File

92
ports/cortex_m7/gnu/readme_threadx.txt
View File

@@ -52,24 +52,82 @@ ThreadX. The top of the suspended thread's stack is pointed to by
tx_thread_stack_ptr in the associated thread control block TX_THREAD.
Stack Offset Stack Contents
Non-FPU Stack Frame:
0x00 r4
0x04 r5
0x08 r6
0x0C r7
0x10 r8
0x14 r9
0x18 r10
0x1C r11
0x20 r0 (Hardware stack starts here!!)
0x24 r1
0x28 r2
0x2C r3
0x30 r12
0x34 lr
0x38 pc
0x3C xPSR
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4 Software stacked GP registers
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 Hardware stacked registers
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
FPU Stack Frame (only interrupted thread with FPU enabled):
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s16 Software stacked FPU registers
0x08 s17
0x0C s18
0x10 s19
0x14 s20
0x18 s21
0x1C s22
0x20 s23
0x24 s24
0x28 s25
0x2C s26
0x30 s27
0x34 s28
0x38 s29
0x3C s30
0x40 s31
0x44 r4 Software stacked registers
0x48 r5
0x4C r6
0x50 r7
0x54 r8
0x58 r9
0x5C r10
0x60 r11
0x64 r0 Hardware stacked registers
0x68 r1
0x6C r2
0x70 r3
0x74 r12
0x78 lr
0x7C pc
0x80 xPSR
0x84 s0 Hardware stacked FPU registers
0x88 s1
0x8C s2
0x90 s3
0x94 s4
0x98 s5
0x9C s6
0xA0 s7
0xA4 s8
0xA8 s9
0xAC s10
0xB0 s11
0xB4 s12
0xB8 s13
0xBC s14
0xC0 s15
0xC4 fpscr
5. Improving Performance

0
ports/cortex_m7/gnu/src/tx_thread_context_restore.S Executable file → Normal file
View File

0
ports/cortex_m7/gnu/src/tx_thread_context_save.S Executable file → Normal file
View File

0
ports/cortex_m7/gnu/src/tx_thread_interrupt_control.S Executable file → Normal file
View File

29
ports/cortex_m7/gnu/src/tx_thread_schedule.S Executable file → Normal file
View File

@@ -27,6 +27,10 @@
.global _tx_thread_system_stack_ptr
.global _tx_execution_thread_enter
.global _tx_execution_thread_exit
#ifdef TX_LOW_POWER
.global tx_low_power_enter
.global tx_low_power_exit
#endif
@
@
.text
@@ -37,7 +41,7 @@
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_schedule Cortex-M7/GNU */
@/* 6.1 */
@/* 6.1.5 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@@ -70,9 +74,12 @@
@/* */
@/* DATE NAME DESCRIPTION */
@/* */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 09-30-2020 William E. Lamie Modified comment(s), */
@/* resulting in version 6.1 */
@/* 05-19-2020 William E. Lamie Initial Version 6.0 */
@/* 09-30-2020 William E. Lamie Modified comment(s), */
@/* resulting in version 6.1 */
@/* 03-02-2021 Scott Larson Modified comment(s), add */
@/* low power code, */
@/* resulting in version 6.1.5 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_schedule(VOID)
@@ -241,11 +248,25 @@ __tx_ts_wait:
LDR r1, [r2] @ Pickup the next thread to execute pointer
STR r1, [r0] @ Store it in the current pointer
CBNZ r1, __tx_ts_ready @ If non-NULL, a new thread is ready!
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter @ Possibly enter low power mode
POP {r0-r3}
#endif
#ifdef TX_ENABLE_WFI
DSB @ Ensure no outstanding memory transactions
WFI @ Wait for interrupt
ISB @ Ensure pipeline is flushed
#endif
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit @ Exit low power mode
POP {r0-r3}
#endif
CPSIE i @ Enable interrupts
B __tx_ts_wait @ Loop to continue waiting
@

0
ports/cortex_m7/gnu/src/tx_thread_stack_build.S Executable file → Normal file
View File

0
ports/cortex_m7/gnu/src/tx_thread_system_return.S Executable file → Normal file
View File

0
ports/cortex_m7/gnu/src/tx_timer_interrupt.S Executable file → Normal file
View File

138
ports/cortex_m7/iar/readme_threadx.txt
View File

@@ -58,80 +58,80 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD.
Non-FPU Stack Frame:
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10 (sl)
0x20 r11
0x24 r0 (Hardware stack starts here!!)
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 r4 Software stacked GP registers
0x08 r5
0x0C r6
0x10 r7
0x14 r8
0x18 r9
0x1C r10
0x20 r11
0x24 r0 Hardware stacked registers
0x28 r1
0x2C r2
0x30 r3
0x34 r12
0x38 lr
0x3C pc
0x40 xPSR
FPU Stack Frame (only interrupted thread with FPU enabled):
Stack Offset Stack Contents
Stack Offset Stack Contents
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s0
0x08 s1
0x0C s2
0x10 s3
0x14 s4
0x18 s5
0x1C s6
0x20 s7
0x24 s8
0x28 s9
0x2C s10
0x30 s11
0x34 s12
0x38 s13
0x3C s14
0x40 s15
0x44 s16
0x48 s17
0x4C s18
0x50 s19
0x54 s20
0x58 s21
0x5C s22
0x60 s23
0x64 s24
0x68 s25
0x6C s26
0x70 s27
0x74 s28
0x78 s29
0x7C s30
0x80 s31
0x84 fpscr
0x88 r4
0x8C r5
0x90 r6
0x94 r7
0x98 r8
0x9C r9
0xA0 r10 (sl)
0xA4 r11
0xA8 r0 (Hardware stack starts here!!)
0xAC r1
0xB0 r2
0xB4 r3
0xB8 r12
0xBC lr
0xC0 pc
0xC4 xPSR
0x00 LR Interrupted LR (LR at time of PENDSV)
0x04 s16 Software stacked FPU registers
0x08 s17
0x0C s18
0x10 s19
0x14 s20
0x18 s21
0x1C s22
0x20 s23
0x24 s24
0x28 s25
0x2C s26
0x30 s27
0x34 s28
0x38 s29
0x3C s30
0x40 s31
0x44 r4 Software stacked registers
0x48 r5
0x4C r6
0x50 r7
0x54 r8
0x58 r9
0x5C r10
0x60 r11
0x64 r0 Hardware stacked registers
0x68 r1
0x6C r2
0x70 r3
0x74 r12
0x78 lr
0x7C pc
0x80 xPSR
0x84 s0 Hardware stacked FPU registers
0x88 s1
0x8C s2
0x90 s3
0x94 s4
0x98 s5
0x9C s6
0xA0 s7
0xA4 s8
0xA8 s9
0xAC s10
0xB0 s11
0xB4 s12
0xB8 s13
0xBC s14
0xC0 s15
0xC4 fpscr
5. Improving Performance

25
ports/cortex_m7/iar/src/tx_thread_schedule.s
View File

@@ -28,6 +28,10 @@
EXTERN _tx_execution_thread_enter
EXTERN _tx_execution_thread_exit
EXTERN _tx_thread_preempt_disable
#ifdef TX_LOW_POWER
EXTERN tx_low_power_enter
EXTERN tx_low_power_exit
#endif
;
;
SECTION `.text`:CODE:NOROOT(2)
@@ -37,7 +41,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M7/IAR */
;/* 6.1 */
;/* 6.1.5 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -70,7 +74,10 @@
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 03-02-2021 Scott Larson Modified comment(s), add */
;/* low power code, */
;/* resulting in version 6.1.5 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -236,11 +243,25 @@ __tx_ts_wait:
LDR r1, [r2] ; Pickup the next thread to execute pointer
STR r1, [r0] ; Store it in the current pointer
CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready!
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_enter ; Possibly enter low power mode
POP {r0-r3}
#endif
#ifdef TX_ENABLE_WFI
DSB ; Ensure no outstanding memory transactions
WFI ; Wait for interrupt
ISB ; Ensure pipeline is flushed
#endif
#ifdef TX_LOW_POWER
PUSH {r0-r3}
BL tx_low_power_exit ; Exit low power mode
POP {r0-r3}
#endif
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;

281
ports/rxv2/ccrx/inc/tx_port.h Normal file
View File

@@ -0,0 +1,281 @@
/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Port Specific */
/** */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/* */
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h RXv2/CCRX */
/* 6.1.3 */
/* */
/* AUTHOR */
/* */
/* William E. Lamie, Express Logic, Inc. */
/* */
/* DESCRIPTION */
/* */
/* This file contains data type definitions that make the ThreadX */
/* real-time kernel function identically on a variety of different */
/* processor architectures. For example, the size or number of bits */
/* in an "int" data type vary between microprocessor architectures and */
/* even C compilers for the same microprocessor. ThreadX does not */
/* directly use native C data types. Instead, ThreadX creates its */
/* own special types that can be mapped to actual data types by this */
/* file to guarantee consistency in the interface and functionality. */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */
/* */
/**************************************************************************/
#ifndef TX_PORT_H
#define TX_PORT_H
/* Determine if the optional ThreadX user define file should be used. */
#ifdef TX_INCLUDE_USER_DEFINE_FILE
/* Yes, include the user defines in tx_user.h. The defines in this file may
alternately be defined on the command line. */
#include "tx_user.h"
#endif
/* Define ThreadX basic types for this port. */
#define VOID void
typedef char CHAR;
typedef unsigned char UCHAR;
typedef int INT;
typedef unsigned int UINT;
typedef long LONG;
typedef unsigned long ULONG;
typedef short SHORT;
typedef unsigned short USHORT;
/* Define the priority levels for ThreadX. Legal values range
from 32 to 1024 and MUST be evenly divisible by 32. */
#ifndef TX_MAX_PRIORITIES
#define TX_MAX_PRIORITIES 32
#endif
/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during
thread creation is less than this value, the thread create call will return an error. */
#ifndef TX_MINIMUM_STACK
#define TX_MINIMUM_STACK 256 /* Minimum stack size for this port */
#endif
/* Define the system timer thread's default stack size and priority. These are only applicable
if TX_TIMER_PROCESS_IN_ISR is not defined. */
#ifndef TX_TIMER_THREAD_STACK_SIZE
#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */
#endif
#ifndef TX_TIMER_THREAD_PRIORITY
#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */
#endif
#ifndef TX_TRACE_TIME_SOURCE
#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time
#endif
#ifndef TX_TRACE_TIME_MASK
#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL
#endif
/* Define the port specific options for the _tx_build_options variable. This variable indicates
how the ThreadX library was built. */
#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0
/* Define the in-line initialization constant so that modules with in-line
initialization capabilities can prevent their initialization from being
a function call. */
#define TX_INLINE_INITIALIZATION
/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is
disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack
checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
define is negated, thereby forcing the stack fill which is necessary for the stack checking
logic. */
#ifdef TX_ENABLE_STACK_CHECKING
#undef TX_DISABLE_STACK_FILLING
#endif
/* Define the TX_THREAD control block extensions for this port. The main reason
for the multiple macros is so that backward compatibility can be maintained with
existing ThreadX kernel awareness modules. */
#define TX_THREAD_EXTENSION_0
#define TX_THREAD_EXTENSION_1
#define TX_THREAD_EXTENSION_2
#define TX_THREAD_EXTENSION_3
/* Define the port extensions of the remaining ThreadX objects. */
#define TX_BLOCK_POOL_EXTENSION
#define TX_BYTE_POOL_EXTENSION
#define TX_EVENT_FLAGS_GROUP_EXTENSION
#define TX_MUTEX_EXTENSION
#define TX_QUEUE_EXTENSION
#define TX_SEMAPHORE_EXTENSION
#define TX_TIMER_EXTENSION
/* Define the user extension field of the thread control block. Nothing
additional is needed for this port so it is defined as white space. */
#ifndef TX_THREAD_USER_EXTENSION
#define TX_THREAD_USER_EXTENSION
#endif
/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete,
tx_thread_shell_entry, and tx_thread_terminate. */
#define TX_THREAD_CREATE_EXTENSION(thread_ptr)
#define TX_THREAD_DELETE_EXTENSION(thread_ptr)
#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)
/* Define the ThreadX object creation extensions for the remaining objects. */
#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr)
#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr)
#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr)
#define TX_QUEUE_CREATE_EXTENSION(queue_ptr)
#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr)
#define TX_TIMER_CREATE_EXTENSION(timer_ptr)
/* Define the ThreadX object deletion extensions for the remaining objects. */
#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)
#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)
#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)
#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr)
#define TX_QUEUE_DELETE_EXTENSION(queue_ptr)
#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
/* Define ThreadX interrupt lockout and restore macros for protection on
access of critical kernel information. The restore interrupt macro must
restore the interrupt posture of the running thread prior to the value
present prior to the disable macro. In most cases, the save area macro
is used to define a local function save area for the disable and restore
macros. */
/* UINT _tx_thread_interrupt_control(UINT new_posture); */
#pragma inline_asm _tx_thread_interrupt_disable
static UINT _tx_thread_interrupt_disable(void){
MVFC PSW,R1 ;
CLRPSW I ;
}
#pragma inline_asm _tx_thread_interrupt_restore
static void _tx_thread_interrupt_restore(UINT old_posture){
MVFC PSW, R2 ;
BTST #16,r1 ;
BMC #16,r2 ;
MVTC r2,PSW ;
}
#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save;
#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable();
#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save);
#define _tx_thread_system_return _tx_thread_system_return_inline
static void _tx_thread_system_return_inline(void)
{
UINT interrupt_save;
interrupt_save = _tx_thread_interrupt_disable();
*((volatile UCHAR *)(0x872E0u)) = 1u;
_tx_thread_interrupt_restore(interrupt_save);
}
#ifndef TX_THREAD_GET_SYSTEM_STATE
#pragma inline_asm _get_psw
static UINT _get_psw(void){
MVFC PSW,R1 ;
}
extern volatile ULONG _tx_thread_system_state;
#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | ((~_get_psw()) & (1u << 17u)))
#endif
/* Define the interrupt lockout macros for each ThreadX object. */
#define TX_BLOCK_POOL_DISABLE TX_DISABLE
#define TX_BYTE_POOL_DISABLE TX_DISABLE
#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE
#define TX_MUTEX_DISABLE TX_DISABLE
#define TX_QUEUE_DISABLE TX_DISABLE
#define TX_SEMAPHORE_DISABLE TX_DISABLE
/* Define the version ID of ThreadX. This may be utilized by the application. */
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RXv2/CCRX Version 6.1.3 *";
#else
extern CHAR _tx_version_id[];
#endif
#endif

175
ports/rxv2/ccrx/readme_threadx.txt Normal file
View File

@@ -0,0 +1,175 @@
Microsoft's Azure RTOS ThreadX for Renesas RXv2
Using the CC-RX Tools
1. Building the ThreadX run-time Library
Please see the Samples repository on GitHub for the Azure RTOS demonstrations
for the RXv2.
2. Demonstration System
Please see the Samples repository on GitHub for the Azure RTOS demonstrations
for the RXv2
3. System Initialization
The system entry point using Renesas tools is at the label _PowerON_Reset_PC.
Use the resetprg.c file that comes with your release. Most notable is that Threadx
applications run in supervisor mode and do not use user mode. Hence switching to
user mode has been commented out.
The vector area is set up using either intprg.c or in the file tx_initialize_low_level.src.
The file tx_initialize_low_level.src is responsible for setting up various system data
structures, interrupt vectors, and a periodic timer. This is the ideal place add
application specific hardware initialization code.
ThreadX utilizes CMT0 as a periodic timer interrupt source. The CMT0 interrupt is
typically setup for 10ms periodic interrupts and the interrupt priority level is set to
level 7. You may change any of the timer parameters to suit your needs.
In addition, _tx_initialize_low_level determines the first available address for use by
the application, which is supplied as the sole input parameter to your application
definition function, tx_application_define(). The mechanism is implemented by creating the
FREEMEM section, this section should be linked last in the RAM area. tx_initialize_low_level
will pick up the starting label of this section and put it in the global variable:
_tx_initialize_unused_memory
4. Context Switch, Register Usage and Stack Frames
The RXv2 port for ThreadX uses the first software interrupt, SWINT, i.e., interrupt #17,
to perform context switch. This ISR is thus reserved when using ThreadX and the SWINT
should not be manipulated in any way by the application. The port will setup the
interrupt within _tx_initialize_low_level and the compiler will automatically install
the necessary interrupt vector. As such no additional initialization is necessary by the
application.
The following defines the saved context stack frame used by the ThreadX port. The
state of the CPU registers at the time of a context switch is saved on the running
thread's stack The top of the suspended thread's stack is pointed to by
tx_thread_stack_ptr in the associated thread control block TX_THREAD.
Offset Interrupted Stack Frame
0x00 1
0x04 ACC0
0x08 ACC1
0x0C R6
0x10 R7
0x14 R8
0x18 R9
0x1C R10
0x20 R11
0x24 R12
0x28 R13
0x2C FPSW
0x30 R14
0x34 R15
0x38 R3
0x3C R4
0x40 R5
0x44 R1
0x48 R2
0x4C PC - return address
0x50 PSW
Note: By default ccrx does not save the state of the accumulator registers ACC0 and ACC1
when entering an ISR. This means that if the ISR uses any of the DSP instructions the
content of those registers could be corrupted. Saving and restoring of the acummulators
can be enabled by adding the -save_acc command line option.
5. Improving Performance
The distribution version of ThreadX is built without any compiler
optimizations. This makes it easy to debug because you can trace or set
breakpoints inside of ThreadX itself. Of course, this costs some
performance. To make ThreadX run faster, you can change the ThreadX Library
project to disable debug information and enable the desired optimizations.
In addition, you can eliminate the ThreadX basic API error checking by
compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING
defined before tx_api.h is included.
6. Timer Processing
Timer processign is performed by calling __tx_timer_interrupt(). This should usually be done
from within the callback of a periodic timer with a period of 100Hz. In the sample projects
a Renesas Fit CMT periodic timer module (rx_cmt) is used as the timer source.
7. Interrupt Handling
Interrupt handling is unaffected by the ThreadX port as such user interrupts can be
written according to the toolchain's documentation. It is recommended not to use interrupt
priority 15 as this is the priority of the context switch interrupt. However using interrupt
priority 15 won't cause any negative side effectd but doing so may may slightly reduce
performance. Please refer to the toolchain documentation for additional details on how to
define interupt service routines.
8. Execution Profiling
The RX port adds support for the Execution Profiling Kit (EPK). The EPK consists
of the files tx_execution_profile.c and tx_execution_profile.h. See the documentation
of the EPK for generic usage details.
To add the EPK to your RXv2 release make the following modifications:
* Enable the following define for both the Threadx library and the application
TX_ENABLE_EXECUTION_CHANGE_NOTIFY
* in tx_port.h, change around line 183
change #define TX_THREAD_EXTENSION_3
into #include "tx_execution_profile.h"
* Setup CMT1 as a free running 16 bit timer.
* In tx_execution_profile.h, change following around line 74:
#ifdef TX_EXECUTION_64BIT_TIME
typedef unsigned long long EXECUTION_TIME;
#define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \
unsigned long long tx_thread_execution_time_last_start;
#define TX_EXECUTION_MAX_TIME_SOURCE 0xFFFFFFFFFFFFFFFF
#else
typedef unsigned long EXECUTION_TIME;
#define TX_THREAD_EXTENSION_3 unsigned long tx_thread_execution_time_total; \
unsigned long tx_thread_execution_time_last_start;
#define TX_EXECUTION_MAX_TIME_SOURCE 0xFFFF
#endif
/* Define basic constants for the execution profile kit. */
#define TX_EXECUTION_TIME_SOURCE (EXECUTION_TIME) *((USHORT *) 0x8800A)
Rebuild the Threadx library and the application.
Refer to the EPK documentation how to interpret the results.
9. Revision History
For generic code revision information, please refer to the readme_threadx_generic.txt
file, which is included in your distribution. The following details the revision
information associated with this specific port of ThreadX:
For generic code revision information, please refer to the readme_threadx_generic.txt
file, which is included in your distribution. The following details the revision
information associated with this specific port of ThreadX:
12-31-2020 Initial ThreadX release for the RXv2 using CC-RXX tools, version 6.1.3
Copyright(c) 1996-2020 Microsoft Corporation
https://azure.com/rtos
www.expresslogic.com

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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Initialize */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
.GLB __tx_initialize_unused_memory
IPR03 .EQU 87303H
IEN03 .EQU 87203H
.SECTION P,CODE
;
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_initialize_low_level RXv2/CCRX */
;/* 6.1.3 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is responsible for any low-level processor */
;/* initialization, including setting up interrupt vectors, setting */
;/* up a periodic timer interrupt source, saving the system stack */
;/* pointer for use in ISR processing later, and finding the first */
;/* available RAM memory address for tx_application_define. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* _tx_initialize_kernel_enter ThreadX entry function */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */
;/* */
;/**************************************************************************/
.GLB __tx_initialize_low_level
__tx_initialize_low_level:
;
; /* Save the first available memory address. */
; _tx_initialize_unused_memory = (VOID_PTR) &free_mem_start;
;
MOV.L #free_mem_start, R1 ; Pickup unused memory address
MOV.L #__tx_initialize_unused_memory,R2
MOV.L R1,[R2] ; Save first free memory address
; /* Set priority of SWINT to 1. */
MOV.L #IPR03, r1
MOV.L #1, r2
MOV.B r2, [r1]
; /* Enable SWINT. */
MOV.L #IEN03,r1
MOV.B [r1], r2
OR #(1 << 3), r2
MOV.B r2, [r1]
RTS
.SECTION FREEMEM ,DATA, ALIGN=4
free_mem_start:
.BLKL 8 ; this section is last in the link map so we can access the end of RAM memory
.END

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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
.GLB __tx_thread_system_state
.GLB __tx_thread_current_ptr
.GLB __tx_thread_system_stack_ptr
.GLB __tx_thread_execute_ptr
.GLB __tx_timer_time_slice
.GLB __tx_thread_schedule
.GLB __tx_thread_preempt_disable
;
.SECTION P,CODE
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_restore RXv2/CCRX */
;/* 6.1.3 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function restores the interrupt context if it is processing a */
;/* nested interrupt. If not, it returns to the interrupt thread if no */
;/* preemption is necessary. Otherwise, if preemption is necessary or */
;/* if no thread was running, the function returns to the scheduler. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* _tx_thread_schedule Thread scheduling routine */
;/* */
;/* CALLED BY */
;/* */
;/* ISRs Interrupt Service Routines */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_context_restore(VOID)
;{
.GLB __tx_thread_context_restore
__tx_thread_context_restore:
;
; /* Lockout interrupts. */
CLRPSW I ; disable interrupts
; /* Determine if interrupts are nested. */
; if (--_tx_thread_system_state)
; {
MOV.L #__tx_thread_system_state, R1
MOV.L [R1], R2
SUB #1, R2
MOV.L R2,[R1]
BEQ __tx_thread_not_nested_restore
;
; /* Interrupts are nested. */
;
; /* Recover the saved registers from the interrupt stack
; and return to the point of interrupt. */
;
__tx_thread_nested_restore:
POPC FPSW ; restore FPU status
POPM R14-R15 ; restore R14-R15
POPM R3-R5 ; restore R3-R5
POPM R1-R2 ; restore R1-R2
RTE ; return to point of interrupt, restore PSW including IPL
; }
__tx_thread_not_nested_restore:
;
; /* Determine if a thread was interrupted and no preemption is required. */
; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)
; || (_tx_thread_preempt_disable))
; {
MOV.L #__tx_thread_current_ptr, R1 ; Pickup current thread ptr address
MOV.L [R1], R2
CMP #0, R2
BEQ __tx_thread_idle_system_restore
MOV.L #__tx_thread_preempt_disable, R3 ; pick up preempt disable flag
MOV.L [R3], R3
CMP #0, R3
BNE __tx_thread_no_preempt_restore ; if pre-empt disable flag set, we simply return to the original point of interrupt regardless
MOV.L #__tx_thread_execute_ptr, R3 ; (_tx_thread_current_ptr != _tx_thread_execute_ptr)
CMP [R3], R2
BNE __tx_thread_preempt_restore ; jump to pre-empt restoring
;
__tx_thread_no_preempt_restore:
SETPSW U ; user stack
POPC FPSW ; restore FPU status
POPM R14-R15 ; restore R14-R15
POPM R3-R5 ; restore R3-R5
POPM R1-R2 ; restore R1-R2
RTE ; return to point of interrupt, restore PSW including IPL
; }
; else
; {
__tx_thread_preempt_restore:
; /* Save the remaining time-slice and disable it. */
; if (_tx_timer_time_slice)
; {
MOV.L #__tx_timer_time_slice, R3 ; Pickup time-slice address
MOV.L [R3],R4 ; Pickup actual time-slice
CMP #0, R4
BEQ __tx_thread_dont_save_ts ; no time slice to save
;
; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice;
; _tx_timer_time_slice = 0;
;
MOV.L R4,24[R2] ; Save thread's time slice
MOV.L #0,R4 ; Clear value
MOV.L R4,[R3] ; Disable global time slice flag
; }
__tx_thread_dont_save_ts:
;
; /* Now store the remaining registers! */
SETPSW U ; user stack
PUSHM R6-R13
MVFACGU #0, A1, R4 ; Save accumulators.
MVFACHI #0, A1, R5
MVFACLO #0, A1, R6
PUSHM R4-R6
MVFACGU #0, A0, R4
MVFACHI #0, A0, R5
MVFACLO #0, A0, R6
PUSHM R4-R6
MOV.L #1, R3 ; indicate interrupt stack frame
PUSH.L R3
;
; /* Clear the current task pointer. */
; _tx_thread_current_ptr = TX_NULL;
; R1 -> _tx_thread_current_ptr
; R2 -> *_tx_thread_current_ptr
MOV.L R0,8[R2] ; Save thread's stack pointer in thread control block
MOV.L #0,R2 ; Build NULL value
MOV.L R2,[R1] ; Set current thread to NULL
; /* Return to the scheduler. */
; _tx_thread_schedule();
__tx_thread_idle_system_restore:
MVTC #0, PSW ; reset interrupt priority level to 0
BRA __tx_thread_schedule ; jump to scheduler
; }
;
;}
;
.END

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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
.GLB __tx_thread_system_state
.GLB __tx_thread_current_ptr
.GLB __tx_thread_system_stack_ptr
.SECTION P,CODE
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_save RXv2/CCRX */
;/* 6.1.3 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function saves the context of an executing thread in the */
;/* beginning of interrupt processing. The function also ensures that */
;/* the system stack is used upon return to the calling ISR. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* ISRs */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_context_save(VOID)
;{
.GLB __tx_thread_context_save
__tx_thread_context_save:
;
; /* Upon entry to this routine, it is assumed that interrupts are locked
; out and the (interrupt) stack frame looks like the following:
;
; (lower address) SP -> [return address of this call]
; SP+4 -> Saved R1
; SP+8 -> Saved R2
; SP+12-> Interrupted PC
; SP+16-> Interrupted PSW
;
; /* Check for a nested interrupt condition. */
; if (_tx_thread_system_state++)
; {
;
MOV.L #__tx_thread_system_state, R1 ; pick up address of system state
MOV.L [R1], R2 ; pick up system state
CMP #0, R2 ; 0 -> no nesting
BEQ __tx_thread_not_nested_save
;
; /* Nested interrupt condition. */
;
ADD #1, r2 ; _tx_thread_system_state++
MOV.L r2, [r1]
;
; /* Save the rest of the scratch registers on the interrupt stack and return to the
; calling ISR. */
POP R1 ; recuperate return address from stack
PUSHM R3-R5
PUSHM R14-R15
PUSHC FPSW ; (top) FPSW, R14, R15, R3, R4, R5, R1, R2, PC, PSW (bottom)
JMP R1 ; return address was preserved in R1
;
__tx_thread_not_nested_save:
; }
;
; /* Otherwise, not nested, check to see if a thread was running. */
; else if (_tx_thread_current_ptr)
; {
;
ADD #1, R2 ; _tx_thread_system_state++
MOV.L R2, [R1]
MOV.L #__tx_thread_current_ptr, R2 ; Pickup current thread pointer
MOV.L [R2], R2
CMP #0,R2 ; Is it NULL?
BEQ __tx_thread_idle_system_save ; Yes, idle system is running - idle restore
;
; /* Move stack frame over to the current threads stack. */
; /* complete stack frame with registers not saved yet (R3-R5, R14-R15, FPSW) */
;
MVFC USP, R1 ; pick up user stack pointer
MOV.L 16[R0], R2
MOV.L R2, [-R1] ; save PSW on thread stack
MOV.L 12[R0], R2
MOV.L R2, [-R1] ; save PC on thread stack
MOV.L 8[R0], R2
MOV.L R2, [-R1] ; save R2 on thread stack
MOV.L 4[R0], R2
MOV.L R2, [-R1] ; save R1 on thread stack
MOV.L R5, [-R1] ; save R5 on thread stack
MOV.L R4, [-R1] ; save R4 on thread stack
MOV.L R3, [-R1] ; save R3 on thread stack
MOV.L R15, [-R1] ; save R15 on thread stack
MOV.L R14, [-R1] ; save R14 on thread stack
MVFC FPSW, R3
MOV.L R3, [-R1] ; save FPSW on thread stack
POP R2 ; pick up return address from interrupt stack
ADD #16, R0, R0 ; correct interrupt stack pointer back to the bottom
MVTC R1, USP ; set user/thread stack pointer
JMP R2 ; return to ISR
; }
; else
; {
;
__tx_thread_idle_system_save:
;
; /* Interrupt occurred in the scheduling loop. */
;
POP R1 ; pick up return address
ADD #16, R0, R0 ; correct interrupt stack pointer back to the bottom (PC), don't care about saved registers
JMP R1 ; return to caller
;
; }
;}
.END

96
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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
.SECTION P,CODE
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_control RXv2/CCRX */
;/* 6.1.3 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is responsible for changing the interrupt lockout */
;/* posture of the system. */
;/* */
;/* INPUT */
;/* */
;/* new_posture New interrupt lockout posture */
;/* */
;/* OUTPUT */
;/* */
;/* old_posture Old interrupt lockout posture */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* Application Code */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */
;/* */
;/**************************************************************************/
;UINT _tx_thread_interrupt_control(UINT new_posture)
;{
.GLB __tx_thread_interrupt_control
__tx_thread_interrupt_control:
;
; /* Pickup current interrupt lockout posture. */
;
MVFC PSW, R2 ; Save PSW to R2
MOV.L R2, R3 ; Make a copy of PSW in r3
;
; /* Apply the new interrupt posture. */
;
BTST #16, R1 ; test I bit of PSW of "new posture"
BMNE #16, R2 ; conditionally set I bit of intermediate posture
MVTC R2, PSW ; save intermediate posture to PSW
MOV.L R3,R1 ; Get original SR
RTS ; Return to caller
;}
.END

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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
.GLB __tx_thread_execute_ptr
.GLB __tx_thread_current_ptr
.GLB __tx_timer_time_slice
;
.SECTION P,CODE
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule RXv2/CCRX */
;/* 6.1.3 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function waits for a thread control block pointer to appear in */
;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */
;/* in the variable, the corresponding thread is resumed. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* _tx_initialize_kernel_enter ThreadX entry function */
;/* _tx_thread_system_return Return to system from thread */
;/* _tx_thread_context_restore Restore thread's context */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
;{
.GLB __tx_thread_schedule
__tx_thread_schedule:
;
; /* Enable interrupts. */
;
SETPSW I
;
; /* Wait for a thread to execute. */
; do
; {
MOV.L #__tx_thread_execute_ptr, R1 ; Address of thread to executer ptr
__tx_thread_schedule_loop:
MOV.L [R1],R2 ; Pickup next thread to execute
CMP #0,R2 ; Is it NULL?
BEQ __tx_thread_schedule_loop ; Yes, idle system, keep checking
;
; }
; while(_tx_thread_execute_ptr == TX_NULL);
;
; /* Yes! We have a thread to execute. Lockout interrupts and
; transfer control to it. */
;
CLRPSW I ; disable interrupts
;
; /* Setup the current thread pointer. */
; _tx_thread_current_ptr = _tx_thread_execute_ptr;
;
MOV.L #__tx_thread_current_ptr, R3
MOV.L R2,[R3] ; Setup current thread pointer
;
; /* Increment the run count for this thread. */
; _tx_thread_current_ptr -> tx_thread_run_count++;
;
MOV.L 4[R2],R3 ; Pickup run count
ADD #1,R3 ; Increment run counter
MOV.L R3,4[R2] ; Store it back in control block
;
; /* Setup time-slice, if present. */
; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice;
;
MOV.L 24[R2],R3 ; Pickup thread time-slice
MOV.L #__tx_timer_time_slice,R4 ; Pickup pointer to time-slice
MOV.L R3, [R4] ; Setup time-slice
;
; /* Switch to the thread's stack. */
; SP = _tx_thread_execute_ptr -> tx_thread_stack_ptr;
SETPSW U ; user stack mode
MOV.L 8[R2],R0 ; Pickup stack pointer
;
; /* Determine if an interrupt frame or a synchronous task suspension frame
; is present. */
;
POP R1 ; Pickup stack type
CMP #1, R1 ; Is it an interrupt stack?
BNE __tx_thread_synch_return ; No, a synchronous return frame is present.
POPM R1-R3 ; Restore accumulators.
MVTACLO R3, A0
MVTACHI R2, A0
MVTACGU R1, A0
POPM R1-R3
MVTACLO R3, A1
MVTACHI R2, A1
MVTACGU R1, A1
POPM R6-R13 ; Recover interrupt stack frame
POPC FPSW
POPM R14-R15
POPM R3-R5
POPM R1-R2
RTE ; return to point of interrupt, this restores PC and PSW
__tx_thread_synch_return:
POPC PSW
POPM R6-R13 ; Recover solicited stack frame
RTS
;
;}
.GLB __tx_thread_context_save
.GLB __tx_thread_context_restore
; Software triggered interrupt used to perform context switches.
; The priority of this interrupt is set to the lowest priority within
; tx_initialize_low_level() and triggered by ThreadX when calling
; _tx_thread_system_return().
.RVECTOR 27, _tx_software_interrupt_entry
.GLB _tx_software_interrupt_entry
_tx_software_interrupt_entry:
PUSHM R1-R2
BSR __tx_thread_context_save
BRA __tx_thread_context_restore
.END

155
ports/rxv2/ccrx/src/tx_thread_stack_build.src Normal file
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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
.SECTION P,CODE
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_stack_build RXv2/CCRX */
;/* 6.1.3 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function builds a stack frame on the supplied thread's stack. */
;/* The stack frame results in a fake interrupt return to the supplied */
;/* function pointer. */
;/* */
;/* INPUT */
;/* */
;/* thread_ptr Pointer to thread control blk */
;/* function_ptr Pointer to return function */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* _tx_thread_create Create thread service */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
;{
.GLB __tx_thread_stack_build
__tx_thread_stack_build:
;
;
; /* Build an interrupt frame. The form of the fake interrupt stack
; on the Renesas RX should look like the following after it is built:
;
; Stack Top: 1 Interrupt stack frame type
; ACC0
; ACC1
; R6
; R7
; R8
; R9
; R10
; R11
; R12
; R13
; FPSW
; R14
; R15
; R3
; R4
; R5
; R1
; R2
; PC
; PSW
;
; Stack Bottom: (higher memory address) */
;
MOV.L 16[R1],R3 ; Pickup end of stack area
BCLR #0, R3 ; mask for 4-byte alignment
BCLR #1, R3
;
; /* Build the stack frame. */
;
MOV.L #30000h, R4
MOV.L R4, [-R3] ; initial PSW (SVC mode, U flag set)
MOV.L R2, [-R3] ; initial PC
MOV.L #0, R4
MOV.L R4,[-R3] ; initial R2 ...
MOV.L R4,[-R3] ; initial R1 ...
MOV.L R4,[-R3] ; initial R5 ...
MOV.L R4,[-R3] ; initial R4 ...
MOV.L R4,[-R3] ; initial R3 ...
MOV.L R4,[-R3] ; initial R15 ...
MOV.L R4,[-R3] ; initial R14 ...
MVFC FPSW, r4
MOV.L R4, [-R3] ; initial FPSW
MOV.L #0, R4
MOV.L R4,[-R3] ; initial R13 ...
MOV.L R4,[-R3] ; initial R12 ...
MOV.L R4,[-R3] ; initial R11 ...
MOV.L R4,[-R3] ; initial R10 ...
MOV.L R4,[-R3] ; initial R9 ...
MOV.L R4,[-R3] ; initial R8 ...
MOV.L R4,[-R3] ; initial R7 ...
MOV.L R4,[-R3] ; initial R6 ...
MOV.L R4,[-R3] ; Accumulator 1
MOV.L R4,[-R3]
MOV.L R4,[-R3]
MOV.L R4,[-R3] ; Accumulator 0
MOV.L R4,[-R3]
MOV.L R4,[-R3]
MOV.L #1, R4
MOV.L R4,[-R3] ; indicate interrupt stack frame
; /* Setup stack pointer. */
; thread_ptr -> tx_thread_stack_ptr = R1;
MOV.L R3, 8[R1]
; store initial SP in thread control block
RTS
;}
.END

127
ports/rxv2/ccrx/src/tx_thread_system_return.src Normal file
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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
.GLB __tx_thread_current_ptr
.GLB __tx_timer_time_slice
.GLB __tx_thread_schedule
.SECTION P,CODE
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_system_return RXv2/CCRX */
;/* 6.1.3 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is target processor specific. It is used to transfer */
;/* control from a thread back to the system. Only a minimal context */
;/* is saved since the compiler assumes temp registers are going to get */
;/* slicked by a function call anyway. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* _tx_thread_schedule Thread scheduling loop */
;/* */
;/* CALLED BY */
;/* */
;/* ThreadX components */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_system_return(VOID)
;{
.GLB __tx_thread_system_return
__tx_thread_system_return:
;
; /* Save call save registers on the stack. */
;
PUSHM R6-R13
PUSHC PSW
MOV.L #0, R1
PUSH.L R1 ; solicited stack frame
;
; /* Lockout interrupts. */
;
CLRPSW I ; Lockout interrupts
;
; /* Save current stack in current Thread controle block. */
; _tx_thread_current_ptr -> tx_thread_stack_ptr = SP;
MOV.L #__tx_thread_current_ptr, R2
MOV.L [R2], R3
MOV.L R0, 8[R3]
MOV.L #__tx_timer_time_slice, R4
MOV.L [R4], R5
; /* Determine if the time-slice is active. */
; if (_tx_timer_time_slice)
; {
;
CMP #0,R5 ; Is a time-slice present?
BEQ __tx_thread_dont_save_ts ; No, don't save the time-slice
;
; /* Save time-slice for the thread and clear the current time-slice. */
; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice;
MOV.L R5,24[R3]
; _tx_timer_time_slice = 0;
;
MOV.L R1, [R4] ; Disable the time-slice
;
; }
__tx_thread_dont_save_ts:
;
; /* Clear the current thread pointer. */
; _tx_thread_current_ptr = TX_NULL;
;
MOV.L R1, [R2]
BRA __tx_thread_schedule
;}
.END

251
ports/rxv2/ccrx/src/tx_timer_interrupt.src Normal file
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@@ -0,0 +1,251 @@
;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Timer */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_timer.h"
;#include "tx_thread.h"
;
;
;Define Assembly language external references...
;
.GLB __tx_timer_time_slice
.GLB __tx_timer_system_clock
.GLB __tx_timer_current_ptr
.GLB __tx_timer_list_start
.GLB __tx_timer_list_end
.GLB __tx_timer_expired_time_slice
.GLB __tx_timer_expired
.GLB __tx_timer_expiration_process
.GLB __tx_thread_context_save
.GLB __tx_thread_time_slice
.GLB __tx_thread_context_restore
;
.SECTION P,CODE
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_timer_interrupt RXv2/CCRX */
;/* 6.1.3 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function processes the hardware timer interrupt. This */
;/* processing includes incrementing the system clock and checking for */
;/* time slice and/or timer expiration. If either is found, the */
;/* interrupt context save/restore functions are called along with the */
;/* expiration functions. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* _tx_thread_context_save Save interrupted context */
;/* _tx_timer_expiration_process Timer expiration processing */
;/* _tx_thread_time_slice Time slice interrupted thread */
;/* _tx_thread_context_restore Restore interrupted context */
;/* */
;/* CALLED BY */
;/* */
;/* interrupt vector */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */
;/* */
;/**************************************************************************/
;VOID _tx_timer_interrupt(VOID)
;{
.GLB __tx_timer_interrupt
__tx_timer_interrupt:
;
; /* Upon entry to this routine, it is assumed that all interrupts are locked
; out and the stack looks like the following:
; SP+4 -> Interrupted PC
; SP+8-> Interrupted SR
; */
;
; /* Increment the system clock. */
; _tx_timer_system_clock++;
;
PUSHM R14-R15
PUSHM R1-R5
MOV.L #__tx_timer_system_clock, R1 ; Pickup address of system clock
MOV.L [R1], R2 ; Pickup system clock
ADD #1, R2 ; Increment system clock
MOV.L R2,[R1] ; Store new system clock
;
; /* Test for time-slice expiration. */
; if (_tx_timer_time_slice)
; {
;
MOV.L #__tx_timer_time_slice, R1 ; Pickup address of time slice
MOV.L [R1], R2 ; Pickup the current time slice
CMP #0, R2 ; Is a time slice active?
BEQ __tx_timer_no_time_slice ; No, skip timer slice processing
;
; /* Decrement the time_slice. */
; _tx_timer_time_slice--;
;
SUB #1, R2 ; Decrement the time-slice
MOV.L R2, [R1] ; Store time-slice
;
; /* Check for expiration. */
; if (__tx_timer_time_slice == 0)
;
CMP #0, R2 ; Has it expired?
BNE __tx_timer_no_time_slice ; No, time-slice has not expired
;
; /* Set the time-slice expired flag. */
; _tx_timer_expired_time_slice = TX_TRUE;
;
MOV.L #__tx_timer_expired_time_slice, R1 ; Pickup address of expired time-slice
MOV.L #1, R2 ; Build expired value
MOV.L R2, [R1] ; Set expired time slice variable
; }
;
__tx_timer_no_time_slice:
;
; /* Test for timer expiration. */
; if (*_tx_timer_current_ptr)
; {
;
MOV.L #__tx_timer_current_ptr, R1 ; Pickup address of current timer ptr
MOV.L [R1], R2 ; Pickup current pointer
MOV.L [R2+], R1 ; pickup timer list entry, _tx_timer_current_ptr++
CMP #0, R1 ; Is timer pointer NULL?
BEQ __tx_timer_no_timer ; Yes, no timer has expired
;
; /* Set expiration flag. */
; _tx_timer_expired = TX_TRUE;
;
MOV.L #__tx_timer_expired,R2 ; Build address of expired flag
MOV.L #1, R1 ; Build expired value
MOV.L R1, [R2]
BRA __tx_timer_done ; Finished with timer processing
;
; }
; else
; {
__tx_timer_no_timer:
;
; /* No timer expired, increment the timer pointer. */
; _tx_timer_current_ptr++;
;
; /* R2 already contains __tx_timer_current_ptr++ */
;
; /* Check for wrap-around. */
; if (_tx_timer_current_ptr == _tx_timer_list_end)
;
MOV.L #__tx_timer_list_end, R1 ; Pickup the timer list end ptr
MOV.L [R1], R1 ; Pickup actual timer list end
CMP R1, R2 ; Are we at list end?
BNE __tx_timer_skip_wrap ; No, don't move pointer to the
; top of the list
;
; /* Wrap to beginning of list. */
; _tx_timer_current_ptr = _tx_timer_list_start;
;
MOV.L #__tx_timer_list_start, R2 ; Pickup the timer list start ptr
MOV.L [R2], R2 ; Pickup the start of the list
; }
;
__tx_timer_skip_wrap:
MOV.L #__tx_timer_current_ptr,R1
MOV.L R2, [R1] ; store in updated pointer in _tx_timer_current_ptr
__tx_timer_done:
;
; /* See if anything has expired. */
; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired))
; {
;
MOV.L #__tx_timer_expired_time_slice, R1 ; Pickup expired time slice addr
MOV.L [R1], R1 ; Pickup expired time slice
MOV.L #__tx_timer_expired, R2 ; Pickup expired timer flag address
MOV.L [R2], R2 ; Pickup actual flag
OR R1, R2 ; Or flags together
BEQ __tx_timer_nothing_expired ; If Z set, nothing has expired
__tx_something_expired:
; /* Did a timer expire? */
; if (_tx_timer_expired)
; {
MOV.L #__tx_timer_expired,R1 ; Pickup expired flag address
MOV.L [R1], R1 ; Pickup expired flag
CMP #0,R1 ; Is the expired timer flag set?
BEQ __tx_timer_dont_activate ; No, skip timer activation
;
; /* Process timer expiration. */
; _tx_timer_expiration_process();
;
BSR __tx_timer_expiration_process ; Call the timer expiration handling routine
;
; }
__tx_timer_dont_activate:
;
; /* Did time slice expire? */
; if (_tx_timer_expired_time_slice)
; {
;
MOV.L #__tx_timer_expired_time_slice, R1 ; Pickup time-slice expired flag addr
MOV.L [R1], R1 ; Pickup actual flag
CMP #0,R1 ; Has time-slice expired?
BEQ __tx_timer_not_ts_expiration ; No, skip time-slice expiration
;
; /* Time slice interrupted thread. */
; _tx_thread_time_slice();
BSR __tx_thread_time_slice ; Call time-slice processing
; }
;
__tx_timer_not_ts_expiration:
__tx_timer_nothing_expired:
POPM R1-R5
POPM R14-R15
;
RTS ; return to point of interrupt
;
;}
.END

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