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add SMP, Modules, and more processor/tools releases

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This commit is contained in:
Scott Larson
2020-08-07 16:56:45 -07:00
parent 49e3c27f3f
commit 6f61053f2a
1858 changed files with 617131 additions and 4 deletions
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<?xml version="1.0" encoding="UTF-8"?>
<section name="Workbench">
<item value="" key="org.eclipse.cdt.codan.internal.ui.preferences.CodanPreferencePage.selection"/>
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*** SESSION Sep 28, 2015 16:00:26.42 -------------------------------------------
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*** SESSION Jun 18, 2020 12:57:01.25 -------------------------------------------

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<cHelpSettings>
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<provider id="org.eclipse.cdt.ui.provider1"/>
</project>
</cHelpSettings>

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<?xml version="1.0" encoding="UTF-8"?>
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<item value="180" key="size.height"/>
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/**************************************************************************/
/* */
/* Copyright (c) 1996-2017 by Express Logic Inc. */
/* */
/* This software is copyrighted by and is the sole property of Express */
/* Logic, Inc. All rights, title, ownership, or other interests */
/* in the software remain the property of Express Logic, Inc. This */
/* software may only be used in accordance with the corresponding */
/* license agreement. Any unauthorized use, duplication, transmission, */
/* distribution, or disclosure of this software is expressly forbidden. */
/* */
/* This Copyright notice may not be removed or modified without prior */
/* written consent of Express Logic, Inc. */
/* */
/* Express Logic, Inc. reserves the right to modify this software */
/* without notice. */
/* */
/* Express Logic, Inc. info@expresslogic.com */
/* 11423 West Bernardo Court http://www.expresslogic.com */
/* San Diego, CA 92127 */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Port Specific */
/** */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/* */
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h SMP/ARC_HS/MetaWare */
/* 5.0 */
/* */
/* AUTHOR */
/* */
/* William E. Lamie, Express Logic, Inc. */
/* */
/* DESCRIPTION */
/* */
/* This file contains data type definitions that make the ThreadX */
/* real-time kernel function identically on a variety of different */
/* processor architectures. For example, the size or number of bits */
/* in an "int" data type vary between microprocessor architectures and */
/* even C compilers for the same microprocessor. ThreadX does not */
/* directly use native C data types. Instead, ThreadX creates its */
/* own special types that can be mapped to actual data types by this */
/* file to guarantee consistency in the interface and functionality. */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* xx-xx-2017 William E. Lamie Initial SMP/ARC HS/MetaWare */
/* Support Version 5.0 */
/* */
/**************************************************************************/
#ifndef TX_PORT_H
#define TX_PORT_H
/* Remove volatile for ThreadX source on the ARC. This is because the ARC
compiler generates different non-cache r/w access when using volatile
that is different from the assembly language access of the same
global variables in ThreadX. */
#ifdef TX_SOURCE_CODE
#define volatile
#else
#ifdef NX_SOURCE_CODE
#define volatile
#else
#ifdef FX_SOURCE_CODE
#define volatile
#else
#ifdef UX_SOURCE_CODE
#define volatile
#endif
#endif
#endif
#endif
/************* Define ThreadX SMP constants. *************/
/* Define the ThreadX SMP maximum number of cores. */
#ifndef TX_THREAD_SMP_MAX_CORES
#define TX_THREAD_SMP_MAX_CORES 2
#endif
/* Define the ThreadX SMP core mask. */
#ifndef TX_THREAD_SMP_CORE_MASK
#define TX_THREAD_SMP_CORE_MASK 0x3 /* Where bit 0 represents Core 0, bit 1 represents Core 1, etc. */
#endif
/* Define INLINE_DECLARE to whitespace for MetaWare compiler. */
#define INLINE_DECLARE
/* Define dynamic number of cores option. When commented out, the number of cores is static. */
/* #define TX_THREAD_SMP_DYNAMIC_CORE_MAX */
/* Define ThreadX SMP initialization macro. */
#define TX_PORT_SPECIFIC_PRE_INITIALIZATION
/* Define ThreadX SMP pre-scheduler initialization. */
#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION
/* Enable the inter-core interrupt logic. */
#define TX_THREAD_SMP_INTER_CORE_INTERRUPT
/* Determine if there is customer-specific wakeup logic needed. */
#ifdef TX_THREAD_SMP_WAKEUP_LOGIC
/* Include customer-specific wakeup code. */
#include "tx_thread_smp_core_wakeup.h"
#else
#ifdef TX_THREAD_SMP_DEFAULT_WAKEUP_LOGIC
/* Default wakeup code. */
#define TX_THREAD_SMP_WAKEUP_LOGIC
#define TX_THREAD_SMP_WAKEUP(i) _tx_thread_smp_core_preempt(i)
#endif
#endif
/* Ensure that the in-line resume/suspend define is not allowed. */
#ifdef TX_INLINE_THREAD_RESUME_SUSPEND
#undef TX_INLINE_THREAD_RESUME_SUSPEND
#endif
/************* End ThreadX SMP constants. *************/
/* Determine if the optional ThreadX user define file should be used. */
#ifdef TX_INCLUDE_USER_DEFINE_FILE
/* Yes, include the user defines in tx_user.h. The defines in this file may
alternately be defined on the command line. */
#include "tx_user.h"
#endif
/* Define compiler library include files. */
#include <stdlib.h>
#include <string.h>
/* Define ThreadX basic types for this port. */
#define VOID void
typedef char CHAR;
typedef unsigned char UCHAR;
typedef int INT;
typedef unsigned int UINT;
typedef long LONG;
typedef unsigned long ULONG;
typedef short SHORT;
typedef unsigned short USHORT;
/* Define the priority levels for ThreadX. Legal values range
from 32 to 1024 and MUST be evenly divisible by 32. */
#ifndef TX_MAX_PRIORITIES
#define TX_MAX_PRIORITIES 32
#endif
/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during
thread creation is less than this value, the thread create call will return an error. */
#ifndef TX_MINIMUM_STACK
#define TX_MINIMUM_STACK 800 /* Minimum stack size for this port */
#endif
/* Define the system timer thread's default stack size and priority. These are only applicable
if TX_TIMER_PROCESS_IN_ISR is not defined. */
#ifndef TX_TIMER_THREAD_STACK_SIZE
#define TX_TIMER_THREAD_STACK_SIZE 2048 /* Default timer thread stack size */
#endif
#ifndef TX_TIMER_THREAD_PRIORITY
#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */
#endif
/* Define various constants for the ThreadX ARC HS port. */
#define TX_INT_ENABLE 0x0000001F /* Enable all interrupts */
#define TX_INT_DISABLE_MASK 0x00000000 /* Disable all interrupts */
/* Define the clock source for trace event entry time stamp. The following two item are port specific.
For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock
source constants would be:
#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024)
#define TX_TRACE_TIME_MASK 0x0000FFFFUL
*/
#ifndef TX_TRACE_TIME_SOURCE
#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time
#endif
#ifndef TX_TRACE_TIME_MASK
#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL
#endif
/* Define the port specific options for the _tx_build_options variable. This variable indicates
how the ThreadX library was built. */
#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0
/* Define the in-line initialization constant so that modules with in-line
initialization capabilities can prevent their initialization from being
a function call. */
#define TX_INLINE_INITIALIZATION
/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is
disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack
checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
define is negated, thereby forcing the stack fill which is necessary for the stack checking
logic. */
#ifdef TX_ENABLE_STACK_CHECKING
#undef TX_DISABLE_STACK_FILLING
#endif
/* Define the TX_THREAD control block extensions for this port. The main reason
for the multiple macros is so that backward compatibility can be maintained with
existing ThreadX kernel awareness modules. */
#define TX_THREAD_EXTENSION_0 VOID *__mw_threadx_tls; \
int __mw_errnum; \
VOID (*__mw_thread_exit)(struct TX_THREAD_STRUCT *);
#define TX_THREAD_EXTENSION_1
#define TX_THREAD_EXTENSION_2
#define TX_THREAD_EXTENSION_3
/* Define the port extensions of the remaining ThreadX objects. */
#define TX_BLOCK_POOL_EXTENSION
#define TX_BYTE_POOL_EXTENSION
#define TX_EVENT_FLAGS_GROUP_EXTENSION
#define TX_MUTEX_EXTENSION
#define TX_QUEUE_EXTENSION
#define TX_SEMAPHORE_EXTENSION
#define TX_TIMER_EXTENSION
/* Define the user extension field of the thread control block. Nothing
additional is needed for this port so it is defined as white space. */
#ifndef TX_THREAD_USER_EXTENSION
#define TX_THREAD_USER_EXTENSION
#endif
/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete,
tx_thread_shell_entry, and tx_thread_terminate. */
#if __HIGHC__
/* The MetaWare thread safe C/C++ runtime library needs space to
store thread specific information. In addition, a function pointer
is also supplied so that certain thread-specific resources may be
released upon thread termination and/or thread completion. */
#define TX_THREAD_CREATE_EXTENSION(thread_ptr) \
thread_ptr -> __mw_threadx_tls = 0; \
thread_ptr -> __mw_errnum = 0; \
thread_ptr -> __mw_thread_exit = TX_NULL;
#define TX_THREAD_DELETE_EXTENSION(thread_ptr)
#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) \
if (thread_ptr -> __mw_thread_exit) \
(thread_ptr -> __mw_thread_exit) (thread_ptr);
#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) \
if (thread_ptr -> __mw_thread_exit) \
(thread_ptr -> __mw_thread_exit) (thread_ptr);
#else
#define TX_THREAD_CREATE_EXTENSION(thread_ptr)
#define TX_THREAD_DELETE_EXTENSION(thread_ptr)
#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)
#endif
/* Define the ThreadX object creation extensions for the remaining objects. */
#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr)
#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr)
#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr)
#define TX_QUEUE_CREATE_EXTENSION(queue_ptr)
#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr)
#define TX_TIMER_CREATE_EXTENSION(timer_ptr)
/* Define the ThreadX object deletion extensions for the remaining objects. */
#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)
#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)
#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)
#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr)
#define TX_QUEUE_DELETE_EXTENSION(queue_ptr)
#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
/************* Define ThreadX SMP data types and function prototypes. *************/
struct TX_THREAD_STRUCT;
/* Define the ThreadX SMP protection structure. */
typedef struct TX_THREAD_SMP_PROTECT_STRUCT
{
ULONG tx_thread_smp_protect_in_force;
struct TX_THREAD_STRUCT *
tx_thread_smp_protect_thread;
ULONG tx_thread_smp_protect_core;
ULONG tx_thread_smp_protect_count;
/* Implementation specific information follows. */
ULONG tx_thread_smp_protect_get_caller;
ULONG tx_thread_smp_protect_status32;
ULONG tx_thread_smp_protect_release_caller;
} TX_THREAD_SMP_PROTECT;
/* Define ThreadX SMP low-level assembly routines. */
struct TX_THREAD_STRUCT * _tx_thread_smp_current_thread_get(void);
UINT _tx_thread_smp_protect(void);
void _tx_thread_smp_unprotect(UINT interrupt_save);
ULONG _tx_thread_smp_current_state_get(void);
ULONG _tx_thread_smp_time_get(void);
/* Determine if SMP Debug is selected. If so, the function prototype is setup. Otherwise, the debug call is
simply mapped to whitespace. */
#ifdef TX_THREAD_SMP_DEBUG_ENABLE
void _tx_thread_smp_debug_entry_insert(ULONG id, ULONG suspend, VOID *thread_ptr);
#else
#define _tx_thread_smp_debug_entry_insert(a, b, c)
#endif
/* Define the get thread macro. */
#define TX_THREAD_GET_CURRENT(a) a = (TX_THREAD *) _tx_thread_smp_current_thread_get();
/* Define the get core ID macro. */
#define TX_SMP_CORE_ID _tx_thread_smp_core_get()
/* Define ThreadX interrupt lockout and restore macros for protection on
access of critical kernel information. The restore interrupt macro must
restore the interrupt posture of the running thread prior to the value
present prior to the disable macro. In most cases, the save area macro
is used to define a local function save area for the disable and restore
macros. */
#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save;
#define TX_DISABLE interrupt_save = _tx_thread_smp_protect();
#define TX_RESTORE _tx_thread_smp_unprotect(interrupt_save);
/************* End ThreadX SMP data type and function prototype definitions. *************/
/* Define the interrupt lockout macros for each ThreadX object. */
#define TX_BLOCK_POOL_DISABLE TX_DISABLE
#define TX_BYTE_POOL_DISABLE TX_DISABLE
#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE
#define TX_MUTEX_DISABLE TX_DISABLE
#define TX_QUEUE_DISABLE TX_DISABLE
#define TX_SEMAPHORE_DISABLE TX_DISABLE
/* Define the version ID of ThreadX. This may be utilized by the application. */
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
"Copyright (c) 1996-YYYY Express Logic Inc. * ThreadX SMP/ARC_HS/MetaWare Version GVVVV.5.0 SN: ZZZZ *";
#else
extern CHAR _tx_version_id[];
#endif
#endif

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eclipse.preferences.version=1
macros/workspace=<?xml version\="1.0" encoding\="UTF-8" standalone\="no"?>\r\n<macros/>\r\n

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eclipse.preferences.version=1
indexer/preferenceScope=0

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eclipse.preferences.version=1
indexer/preferenceScope=0

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eclipse.preferences.version=1
org.eclipse.cdt.debug.core.cDebug.default_source_containers=<?xml version\="1.0" encoding\="UTF-8" standalone\="no"?>\r\n<sourceLookupDirector>\r\n<sourceContainers duplicates\="false">\r\n<container memento\="AbsolutePath" typeId\="org.eclipse.cdt.debug.core.containerType.absolutePath"/>\r\n<container memento\="programRelativePath" typeId\="org.eclipse.cdt.debug.core.containerType.programRelativePath"/>\r\n<container memento\="&lt;?xml version\=&quot;1.0&quot; encoding\=&quot;UTF-8&quot; standalone\=&quot;no&quot;?&gt;&\#13;&\#10;&lt;project referencedProjects\=&quot;true&quot;/&gt;&\#13;&\#10;" typeId\="org.eclipse.cdt.debug.core.containerType.project"/>\r\n</sourceContainers>\r\n</sourceLookupDirector>\r\n
org.eclipse.cdt.debug.corecDebug.Disassembly.instructionStepOn=true

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columnOrderKeyEXE=0,1,2,3,4,5
columnOrderKeySF=0,1,2,3,4,5
columnSortDirectionKeyEXE=128
columnSortDirectionKeySF=128
eclipse.preferences.version=1
visibleColumnsKeyEXE=1,1,1,0,0,0
visibleColumnsKeySF=1,1,0,0,0,0

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activeConfigDesc=sample_threadx Debug.org.eclipse.cdt.launchbar.core.descriptor.default
configDescList=[sample_threadx Debug.org.eclipse.cdt.launchbar.core.descriptor.default]
sample_threadx\ Debug.org.eclipse.cdt.launchbar.core.descriptor.default/activeLaunchMode=debug
sample_threadx\ Debug.org.eclipse.cdt.launchbar.core.descriptor.default/activeLaunchTarget=org.eclipse.cdt.launchbar.core.target.local
eclipse.preferences.version=1

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eclipse.preferences.version=1
properties/sample_threadx.com.arc.cdt.toolchain.arc.av2hs.exeProject.1700533761/com.arc.cdt.toolchain.av2hs.exeDebugConfig.585788724=av2hs.exe.debug.exeCompilerDebug.1743110770\=rebuildState\\\=false\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.exeDebugConfig.585788724\=rcState\\\=0\\r\\nrebuildState\\\=false\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.asmDebugExe.1483523628\=rebuildState\\\=false\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.exeToolChainDebug.1358823635\=rebuildState\\\=false\\r\\n\r\ncom.arc.cdt.toolchain.arc.archiver.886382681\=rebuildState\\\=false\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.exeLinkerDebug.672502322\=rebuildState\\\=false\\r\\n\r\n
properties/sample_threadx.com.arc.cdt.toolchain.arc.av2hs.exeProject.1700533761/com.arc.cdt.toolchain.av2hs.exeReleaseConfig.2024992869=com.arc.cdt.toolchain.av2hs.exelinkerRelease.934772409\=rebuildState\\\=true\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.asmReleaseExe.813382130\=rebuildState\\\=true\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.exeReleaseToolChain.202924782\=rebuildState\\\=true\\r\\n\r\ncom.arc.cdt.toolchain.arc.archiver.990750758\=rebuildState\\\=true\\r\\n\r\narc.cdt.toolchain.av2hs.exeCompilerRelease.1463268267\=rebuildState\\\=true\\r\\n\r\n
properties/tx.com.arc.cdt.toolchain.arc.av2hs.libProject.1128858457/com.arc.cdt.toolchain.av2hs.libDebugConfig.2063275274=com.arc.cdt.toolchain.av2hs.libDebugAsm.1626881776\=rebuildState\\\=false\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.ArDebug.178841002\=rebuildState\\\=true\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.libDebugConfig.2063275274\=rcState\\\=0\\r\\nrebuildState\\\=false\\r\\n\r\nav2hs.lib.debug.libCompiler.46227008\=rebuildState\\\=true\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.ArDebug.1591578035\=rebuildState\\\=false\\r\\n\r\nav2hs.lib.debug.libCompiler.2145942775\=rebuildState\\\=false\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.libDebugToolChain.22686690\=rebuildState\\\=true\\r\\n\r\ncom.arc.cdt.toolchain.arc.Linker.141619666\=rebuildState\\\=true\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.libDebugToolChain.1385404397\=rebuildState\\\=false\\r\\n\r\ncom.arc.cdt.toolchain.arc.Linker.41800372\=rebuildState\\\=false\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.libDebugAsm.262854485\=rebuildState\\\=true\\r\\n\r\n
properties/tx.com.arc.cdt.toolchain.arc.av2hs.libProject.1128858457/com.arc.cdt.toolchain.av2hs.libReleaseConfig.1202427021=com.arc.cdt.toolchain.av2hs.libCompilerRelease.1920721386\=rebuildState\\\=true\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.libReleaseAsm.1207600374\=rebuildState\\\=true\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.ArRelease.217147730\=rebuildState\\\=true\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.libReleaseToolChain.1456119623\=rebuildState\\\=true\\r\\n\r\ncom.arc.cdt.toolchain.arc.Linker.1382145468\=rebuildState\\\=true\\r\\n\r\n

4
ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prefs Normal file
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eclipse.preferences.version=1
spelling_locale_initialized=true
useAnnotationsPrefPage=true
useQuickDiffPrefPage=true

3
ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prj-sample_threadx.prefs Normal file
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@@ -0,0 +1,3 @@
buildConsole/keepLog=false
buildConsole/logLocation=C\:\\arc_hs_smp\\.metadata\\.plugins\\org.eclipse.cdt.ui\\sample_threadx.build.log
eclipse.preferences.version=1

3
ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prj-tx.prefs Normal file
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@@ -0,0 +1,3 @@
buildConsole/keepLog=false
buildConsole/logLocation=C\:\\arc_hs_smp\\.metadata\\.plugins\\org.eclipse.cdt.ui\\tx.build.log
eclipse.preferences.version=1

2
ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs Normal file
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@@ -0,0 +1,2 @@
eclipse.preferences.version=1
version=1

5
ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs Normal file
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@@ -0,0 +1,5 @@
//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.attachLaunchType=org.eclipse.cdt.dsf.gdb.launch.attachCLaunch,debug,;
//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.localCLaunch=org.eclipse.cdt.cdi.launch.localCLaunch,run,;
//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.postmortemLaunchType=org.eclipse.cdt.dsf.gdb.launch.coreCLaunch,debug,;
eclipse.preferences.version=1
prefWatchExpressions=<?xml version\="1.0" encoding\="UTF-8" standalone\="no"?>\r\n<watchExpressions/>\r\n

9
ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs Normal file
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@@ -0,0 +1,9 @@
eclipse.preferences.version=1
org.eclipse.debug.ui.PREF_LAUNCH_PERSPECTIVES=<?xml version\="1.0" encoding\="UTF-8" standalone\="no"?>\r\n<launchPerspectives/>\r\n
org.eclipse.debug.ui.user_view_bindings=<?xml version\="1.0" encoding\="UTF-8" standalone\="no"?>\r\n<viewBindings>\r\n<view id\="org.eclipse.cdt.debug.ui.RegisterView">\r\n<perspective id\="org.eclipse.debug.ui.DebugPerspective" userAction\="closed"/>\r\n</view>\r\n<view id\="org.eclipse.debug.ui.ModuleView">\r\n<perspective id\="org.eclipse.debug.ui.DebugPerspective" userAction\="opened"/>\r\n</view>\r\n<view id\="org.eclipse.debug.ui.VariableView">\r\n<perspective id\="org.eclipse.debug.ui.DebugPerspective" userAction\="opened"/>\r\n</view>\r\n<view id\="org.eclipse.debug.ui.DebugView">\r\n<perspective id\="org.eclipse.debug.ui.DebugPerspective" userAction\="closed"/>\r\n</view>\r\n<view id\="org.eclipse.debug.ui.BreakpointView">\r\n<perspective id\="org.eclipse.debug.ui.DebugPerspective" userAction\="opened"/>\r\n</view>\r\n<view id\="org.eclipse.ui.console.ConsoleView">\r\n<perspective id\="org.eclipse.debug.ui.DebugPerspective" userAction\="closed"/>\r\n</view>\r\n</viewBindings>\r\n
pref_state_memento.org.eclipse.debug.ui.BreakpointView=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<VariablesViewMemento org.eclipse.debug.ui.SASH_DETAILS_PART\="315" org.eclipse.debug.ui.SASH_VIEW_PART\="684">\r\n<PRESENTATION_CONTEXT_PROPERTIES IMemento.internal.id\="org.eclipse.debug.ui.BreakpointView">\r\n<BOOLEAN BOOLEAN\="true" IMemento.internal.id\="org.eclipse.debug.ui.check"/>\r\n</PRESENTATION_CONTEXT_PROPERTIES>\r\n</VariablesViewMemento>
pref_state_memento.org.eclipse.debug.ui.DebugVieworg.eclipse.debug.ui.DebugView=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<DebugViewMemento org.eclipse.debug.ui.BREADCRUMB_DROPDOWN_AUTO_EXPAND\="false"/>
pref_state_memento.org.eclipse.debug.ui.ModuleView=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<VariablesViewMemento org.eclipse.debug.ui.SASH_DETAILS_PART\="315" org.eclipse.debug.ui.SASH_VIEW_PART\="684"/>
pref_state_memento.org.eclipse.debug.ui.VariableView=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<VariablesViewMemento org.eclipse.debug.ui.SASH_DETAILS_PART\="315" org.eclipse.debug.ui.SASH_VIEW_PART\="684"/>
preferredDetailPanes=DefaultDetailPane\:DefaultDetailPane|
preferredTargets=org.eclipse.cdt.debug.ui.toggleCBreakpointTarget\:org.eclipse.cdt.debug.ui.toggleCBreakpointTarget|org.eclipse.cdt.debug.ui.toggleCBreakpointTarget,org.eclipse.cdt.debug.ui.toggleCDynamicPrintfTarget\:org.eclipse.cdt.debug.ui.toggleCBreakpointTarget|

2
ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.editors.prefs Normal file
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@@ -0,0 +1,2 @@
eclipse.preferences.version=1
overviewRuler_migration=migrated_3.1

5
ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs Normal file
View File

@@ -0,0 +1,5 @@
PROBLEMS_FILTERS_MIGRATE=true
eclipse.preferences.version=1
platformState=1590536495337
quickStart=true
tipsAndTricks=true

2
ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.prefs Normal file
View File

@@ -0,0 +1,2 @@
eclipse.preferences.version=1
showIntro=false

3
ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs Normal file
View File

@@ -0,0 +1,3 @@
//org.eclipse.ui.commands/state/org.eclipse.ui.navigator.resources.nested.changeProjectPresentation/org.eclipse.ui.commands.radioState=false
UIActivities.org.eclipse.cdt.debug.cdigdbActivity=true
eclipse.preferences.version=1

476
ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.debug.core/.launches/sample_threadx Debug.launch Normal file
View File

@@ -0,0 +1,476 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<launchConfiguration type="org.eclipse.cdt.launch.localCLaunch">
<stringAttribute key="SeeCodeDisplay.break.profilingColumns" value="0"/>
<mapAttribute key="SeeCodeDisplay.break.valueUpdates"/>
<stringAttribute key="SeeCodeDisplay.disasm.profilingColumns" value="0.ARCV2HS"/>
<mapAttribute key="SeeCodeDisplay.disasm.valueUpdates"/>
<stringAttribute key="SeeCodeDisplay.expr.profilingColumns" value="0"/>
<mapAttribute key="SeeCodeDisplay.expr.valueUpdates"/>
<stringAttribute key="SeeCodeDisplay.mem.profilingColumns" value="0"/>
<mapAttribute key="SeeCodeDisplay.mem.valueUpdates">
<mapEntry key="data_addr_eval" value="0x80003530"/>
</mapAttribute>
<stringAttribute key="com.arc.cdt.debug.seecode.core.CPU" value="ac"/>
<mapAttribute key="com.arc.cdt.debug.seecode.core.GUIHILI_PROPS">
<mapEntry key="$cache_feature_id" value="2"/>
<mapEntry key="$enable_triggers_encountered$" value="1"/>
<mapEntry key="A6_dpfp" value="false"/>
<mapEntry key="A6_dpfpfast" value="false"/>
<mapEntry key="A6_spfp" value="false"/>
<mapEntry key="A6_spfpfast" value="false"/>
<mapEntry key="A7_ATB" value="false"/>
<mapEntry key="A7_MX" value="false"/>
<mapEntry key="A7_MX2" value="false"/>
<mapEntry key="A7_MX_audio" value="false"/>
<mapEntry key="A7_MX_video" value="false"/>
<mapEntry key="A7_SCQ" value="false"/>
<mapEntry key="A7_evec_init" value="1"/>
<mapEntry key="A7_exceptions" value="false"/>
<mapEntry key="A7_memsplit" value="false"/>
<mapEntry key="A7_recur" value="1"/>
<mapEntry key="A7_user_brk" value="1"/>
<mapEntry key="A7_vree" value="false"/>
<mapEntry key="A7_vrme" value="false"/>
<mapEntry key="AC600_dcache" value="1"/>
<mapEntry key="AC600_dcache_line_size" value="32"/>
<mapEntry key="AC600_dcache_repalg" value="Round_robin"/>
<mapEntry key="AC600_dcache_size" value="16384"/>
<mapEntry key="AC600_dcache_ways" value="2"/>
<mapEntry key="AC600_icache" value="1"/>
<mapEntry key="AC600_icache_line_size" value="64"/>
<mapEntry key="AC600_icache_repalg" value="Round_robin"/>
<mapEntry key="AC600_icache_size" value="16384"/>
<mapEntry key="AC600_icache_ways" value="2"/>
<mapEntry key="ACTION" value="{&quot;-c \&quot;sysprop command_processor include_local_symbols=1\&quot;&quot; }"/>
<mapEntry key="AC_chipinit" value="false"/>
<mapEntry key="AC_dcache" value="1"/>
<mapEntry key="AC_dcache_line_size" value="32"/>
<mapEntry key="AC_dcache_repalg" value="Random"/>
<mapEntry key="AC_dcache_size" value="16384"/>
<mapEntry key="AC_dcache_ways" value="2"/>
<mapEntry key="AC_icache" value="1"/>
<mapEntry key="AC_icache_line_size" value="64"/>
<mapEntry key="AC_icache_repalg" value="Random"/>
<mapEntry key="AC_icache_size" value="16384"/>
<mapEntry key="AC_icache_ways" value="2"/>
<mapEntry key="ARC4_CAS_DLL" value="casseia.dll"/>
<mapEntry key="ARC5_Core_Version" value="3"/>
<mapEntry key="ARC600_CAS_DLL" value="arc600cas.dll"/>
<mapEntry key="ARC600_CAS_DLL_systemc" value="arc600cas.dll"/>
<mapEntry key="ARC600_XY_banks" value="1"/>
<mapEntry key="ARC600_XY_size" value="512"/>
<mapEntry key="ARC600_config" value="config"/>
<mapEntry key="ARC600_config_already" value="config"/>
<mapEntry key="ARC600_crc" value="false"/>
<mapEntry key="ARC600_ea" value="false"/>
<mapEntry key="ARC600_fast_loads" value="false"/>
<mapEntry key="ARC600_fast_xmac_wb" value="false"/>
<mapEntry key="ARC600_mem_bus_width" value="32"/>
<mapEntry key="ARC600_mult32" value="false"/>
<mapEntry key="ARC600_norm" value="false"/>
<mapEntry key="ARC600_reg4" value="false"/>
<mapEntry key="ARC600_timer0" value="false"/>
<mapEntry key="ARC600_timer1" value="false"/>
<mapEntry key="ARC600_xmac_24" value="false"/>
<mapEntry key="ARC600_xmac_32x16d16" value="false"/>
<mapEntry key="ARC600_xmac_acc_shortcut" value="false"/>
<mapEntry key="ARC600_xmac_d16" value="false"/>
<mapEntry key="ARC600_xy" value="false"/>
<mapEntry key="ARC600_xy_modulo_addr" value="false"/>
<mapEntry key="ARC6_Core_Version" value="1"/>
<mapEntry key="ARC700_CAS_DLL" value="arc700cas.dll"/>
<mapEntry key="ARC700_XY_banks" value="1"/>
<mapEntry key="ARC700_XY_size" value="4096"/>
<mapEntry key="ARC700_config" value="config"/>
<mapEntry key="ARC700_crc" value="false"/>
<mapEntry key="ARC700_dvbf" value="false"/>
<mapEntry key="ARC700_logfile" value="cas_trace.txt"/>
<mapEntry key="ARC700_mem_bus_width" value="32"/>
<mapEntry key="ARC700_mul32x16" value="false"/>
<mapEntry key="ARC700_xmac_24" value="false"/>
<mapEntry key="ARC700_xmac_d16" value="false"/>
<mapEntry key="ARC700_xy" value="false"/>
<mapEntry key="ARC700_xy_modulo_addr" value="false"/>
<mapEntry key="ARC7_Core_Version" value="2"/>
<mapEntry key="ARC_DSP_memory" value="ARC_nodsp"/>
<mapEntry key="ARC_MX2_SCM_size" value="5120"/>
<mapEntry key="ARC_MX2_SCQ_size" value="256"/>
<mapEntry key="ARC_MX2_VRF_size" value="24"/>
<mapEntry key="ARC_MX_SCM_size" value="5120"/>
<mapEntry key="ARC_MX_SCQ_size" value="256"/>
<mapEntry key="ARC_MX_SDM_size" value="32768"/>
<mapEntry key="ARC_MX_VRF_size" value="24"/>
<mapEntry key="ARC_Timeout" value="100"/>
<mapEntry key="ARC_addr_size" value="32"/>
<mapEntry key="ARC_agu" value="-Xagu_small"/>
<mapEntry key="ARC_atomic" value="0"/>
<mapEntry key="ARC_bad_instr_intr" value="false"/>
<mapEntry key="ARC_bad_instr_intr7" value="false"/>
<mapEntry key="ARC_bad_instr_intr_NSIM" value="1"/>
<mapEntry key="ARC_bad_instr_intr_NSIM7" value="1"/>
<mapEntry key="ARC_barrel_shifter" value="0"/>
<mapEntry key="ARC_bitstream" value="false"/>
<mapEntry key="ARC_blast_spec" value="false"/>
<mapEntry key="ARC_cache_rams" value="false"/>
<mapEntry key="ARC_code_density" value="0"/>
<mapEntry key="ARC_code_protect" value="0000"/>
<mapEntry key="ARC_crc" value="false"/>
<mapEntry key="ARC_cycle_spec" value="1"/>
<mapEntry key="ARC_cycles" value="0"/>
<mapEntry key="ARC_dcache_feature" value="2"/>
<mapEntry key="ARC_dcache_mem_cycles" value="2"/>
<mapEntry key="ARC_deadbeef" value="1"/>
<mapEntry key="ARC_default_ext_interrupts" value="0"/>
<mapEntry key="ARC_default_interrupts" value="0"/>
<mapEntry key="ARC_dma" value="false"/>
<mapEntry key="ARC_dmulpf" value="false"/>
<mapEntry key="ARC_dsp" value="false"/>
<mapEntry key="ARC_dsp2" value="false"/>
<mapEntry key="ARC_dsp_accshift" value="full"/>
<mapEntry key="ARC_dsp_complex" value="false"/>
<mapEntry key="ARC_dsp_divsqrt" value="radix2"/>
<mapEntry key="ARC_dsp_itu" value="false"/>
<mapEntry key="ARC_dvbf" value="false"/>
<mapEntry key="ARC_ea" value="false"/>
<mapEntry key="ARC_ext_interrupt_num" value="0"/>
<mapEntry key="ARC_fpuda" value="false"/>
<mapEntry key="ARC_fsfpus_div" value="Slow"/>
<mapEntry key="ARC_fsfpus_mpy" value="Fast"/>
<mapEntry key="ARC_fujitsu_if" value="false"/>
<mapEntry key="ARC_hardware_selection" value="ARC_raw"/>
<mapEntry key="ARC_icache_feature" value="2"/>
<mapEntry key="ARC_interrupt_baseaddr" value="0x0"/>
<mapEntry key="ARC_interrupt_num" value="0"/>
<mapEntry key="ARC_interrupt_priorities_LIST" value="{&quot;1&quot; &quot;2&quot; &quot;3&quot; &quot;4&quot; &quot;5&quot; &quot;6&quot; &quot;7&quot; &quot;8&quot; &quot;9&quot; &quot;10&quot; &quot;11&quot; &quot;12&quot; &quot;13&quot; &quot;14&quot; &quot;15&quot; &quot;16&quot; }"/>
<mapEntry key="ARC_interrupt_vector_count" value="(default)"/>
<mapEntry key="ARC_isa_counters" value="false"/>
<mapEntry key="ARC_ldst_ram_base" value="(none)"/>
<mapEntry key="ARC_ldst_ram_size" value="(none)"/>
<mapEntry key="ARC_ll64" value="0"/>
<mapEntry key="ARC_lpc_width" value="32"/>
<mapEntry key="ARC_mac" value="0"/>
<mapEntry key="ARC_macd" value="0"/>
<mapEntry key="ARC_mcip" value="false"/>
<mapEntry key="ARC_mcip_bsu" value="false"/>
<mapEntry key="ARC_mcip_cirqnum" value="8"/>
<mapEntry key="ARC_mcip_dvfs" value="false"/>
<mapEntry key="ARC_mcip_grtc" value="false"/>
<mapEntry key="ARC_mcip_ici" value="false"/>
<mapEntry key="ARC_mcip_ics" value="false"/>
<mapEntry key="ARC_mcip_idu" value="false"/>
<mapEntry key="ARC_mcip_llm" value="false"/>
<mapEntry key="ARC_mcip_llm_base" value="0"/>
<mapEntry key="ARC_mcip_llm_size" value="128K"/>
<mapEntry key="ARC_mcip_mcd" value="false"/>
<mapEntry key="ARC_mcip_mps" value="false"/>
<mapEntry key="ARC_mcip_numsemas" value="16"/>
<mapEntry key="ARC_mcip_pmu" value="false"/>
<mapEntry key="ARC_mcip_sram_size" value="512"/>
<mapEntry key="ARC_mcip_version" value="3"/>
<mapEntry key="ARC_mem_bus_width" value="32"/>
<mapEntry key="ARC_mem_exc_intr" value="false"/>
<mapEntry key="ARC_mem_exc_intr7" value="false"/>
<mapEntry key="ARC_mem_exc_intr_NSIM" value="1"/>
<mapEntry key="ARC_mem_exc_intr_NSIM7" value="1"/>
<mapEntry key="ARC_memsize" value="(none)"/>
<mapEntry key="ARC_mpy" value="0"/>
<mapEntry key="ARC_mpy16" value="0"/>
<mapEntry key="ARC_mul32x16" value="false"/>
<mapEntry key="ARC_mult32" value="0"/>
<mapEntry key="ARC_norm" value="0"/>
<mapEntry key="ARC_opellaXD_DLL" value="c:/AshlingOpellaXDforARC/opxdarc"/>
<mapEntry key="ARC_opella_DLL" value="c:/AshlingOpellaforARC/opellarc"/>
<mapEntry key="ARC_parallel_port_address" value="0x378"/>
<mapEntry key="ARC_pc_width" value="32"/>
<mapEntry key="ARC_pmu" value="false"/>
<mapEntry key="ARC_qmpyh" value="0"/>
<mapEntry key="ARC_replay_file" value="replay.bin"/>
<mapEntry key="ARC_reset_on_restart" value="false"/>
<mapEntry key="ARC_rgf_num_wr_ports" value="2"/>
<mapEntry key="ARC_shift_assist" value="0"/>
<mapEntry key="ARC_sliding_pointers" value="false"/>
<mapEntry key="ARC_swap" value="0"/>
<mapEntry key="ARC_target" value="ARCSIM"/>
<mapEntry key="ARC_timer0" value="1"/>
<mapEntry key="ARC_timer1" value="1"/>
<mapEntry key="ARC_uart_0" value="false"/>
<mapEntry key="ARC_uart_1" value="false"/>
<mapEntry key="ARC_uart_2" value="false"/>
<mapEntry key="ARC_ultraXD_DLL" value="C:/AshlingUltra-XDforARC/uxdarc.dll"/>
<mapEntry key="ARC_unalighned_NA" value="1"/>
<mapEntry key="ARC_unaligned" value="0"/>
<mapEntry key="ARC_vmac_0" value="false"/>
<mapEntry key="ARC_vmac_1" value="false"/>
<mapEntry key="ARC_vmac_2" value="false"/>
<mapEntry key="ARC_xlib" value="0"/>
<mapEntry key="ARC_xmac_24" value="false"/>
<mapEntry key="ARC_xmac_d16" value="false"/>
<mapEntry key="ARC_xy" value="false"/>
<mapEntry key="ARG_ACTION" value="{&quot;-targs=AC&quot; &quot;-toggle=include_local_symbols=1&quot; &quot;-profile&quot; &quot;-nsim&quot; &quot;-Xrtc&quot; &quot;-toggle=deadbeef=1&quot; &quot;-interrupt_priorities=16&quot; &quot;-firq&quot; &quot;-rgf_num_banks=4&quot; }"/>
<mapEntry key="Dont_download" value="false"/>
<mapEntry key="EIA_path" value="path_to_eia/lib"/>
<mapEntry key="IDE_ARC_DSP_memory" value="ARC_nodsp"/>
<mapEntry key="IDE_ARC_crc" value="0"/>
<mapEntry key="IDE_ARC_dmulpf" value="0"/>
<mapEntry key="IDE_ARC_dvbf" value="0"/>
<mapEntry key="IDE_ARC_ea" value="0"/>
<mapEntry key="IDE_ARC_mul32x16" value="0"/>
<mapEntry key="IDE_ARC_timer0" value="1"/>
<mapEntry key="IDE_ARC_timer1" value="1"/>
<mapEntry key="IDE_ARC_xmac_24" value="0"/>
<mapEntry key="IDE_ARC_xmac_d16" value="0"/>
<mapEntry key="Local_symbols" value="1"/>
<mapEntry key="MX_ARC_speed" value="1"/>
<mapEntry key="MX_DMA_speed" value="1"/>
<mapEntry key="MX_SIMD_speed" value="1"/>
<mapEntry key="MX_perfres" value="10000"/>
<mapEntry key="MX_system_speed" value="1"/>
<mapEntry key="NA_BPU_BC_ENTRIES" value="512"/>
<mapEntry key="NA_BPU_BC_FULL_TAG" value="0"/>
<mapEntry key="NA_BPU_BC_TAG_SIZE" value="4"/>
<mapEntry key="NA_BPU_BT_ENTRIES" value="8192"/>
<mapEntry key="NA_BPU_FB_ENTRIES" value="2"/>
<mapEntry key="NA_BPU_RS_ENTRIES" value="4"/>
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11
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7
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<?xml version="1.0" encoding="UTF-8"?>
<section name="Workbench">
<section name="org.eclipse.ui.internal.QuickAccess">
<item value="790" key="dialogHeight"/>
<item value="1440" key="dialogWidth"/>
<list key="textEntries">
</list>
<list key="orderedElements">
</list>
<list key="orderedProviders">
</list>
<list key="textArray">
</list>
</section>
<section name="ImportExportAction">
<item value="org.eclipse.ui.wizards.import.ExternalProject" key="ImportExportPage.STORE_SELECTED_IMPORT_WIZARD_ID"/>
<list key="ImportExportPage.STORE_EXPANDED_IMPORT_CATEGORIES">
<item value="org.eclipse.ui.Basic"/>
</list>
</section>
<section name="FileSystemImportWizard">
<item value="false" key="WizardFileSystemResourceImportPage1.STORE_CREATE_CONTAINER_STRUCTURE_ID"/>
<item value="false" key="WizardFileSystemResourceImportPage1.STORE_OVERWRITE_EXISTING_RESOURCES_ID"/>
<list key="WizardFileSystemResourceImportPage1.STORE_SOURCE_NAMES_ID">
<item value="C:\arc_hs_smp"/>
<item value="C:\temp1663\tx_source\demo"/>
<item value="C:\temp1663\tx_source"/>
<item value="C:\temp1663\threadx\tx"/>
</list>
</section>
</section>

4
ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<workingSetManager>
<workingSet aggregate="true" factoryID="org.eclipse.ui.internal.WorkingSetFactory" id="1443482690877_0" label="Window Working Set" name="Aggregate for window 1443482690877"/>
</workingSetManager>

3
ports_smp/arc_hs_smp/metaware/example_build/.metadata/version.ini Normal file
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#Thu Jun 18 13:20:39 PDT 2020
org.eclipse.core.runtime=2
org.eclipse.platform=4.6.3.v20170301-0400

6
ports_smp/arc_hs_smp/metaware/example_build/.sc.project/.multi Normal file
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read ".sc.project/.sc.args.Core1.multi"
read ".sc.project/.sc.args.Core2.multi"
select
load
nohist readq .scrc
nohist nolog gui E> ok_to_load_windows

10
ports_smp/arc_hs_smp/metaware/example_build/.sc.project/.sc.args.Core1.multi Normal file
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// ARGS: -pset=1 -psetname=Core1 sample_threadx\Debug\sample_threadx.elf -arconnect -connect_ici -av2hs -Xatomic -Xunaligned -core3 -Xmpy_option=mpy -Xtimer0 -Xtimer1 -nooptions -interrupts=32 -ext_interrupts=3 -prop=nsim_isa_num_actionpoints=8 -off=prefer_soft_bp -nogoifmain
macro multi_Core1
nocomment prop DLL)=^C:\MWLite\MetaWare\arc/../../nSIM/lib/libsim^
nocomment prop cpunum=$cid timer0_regs=1 timer1_regs=1 cloneable=1 icnts=1 killeds=1 delay_killeds=1 trace_enabled=1 semint)=^C:\MWLite\MetaWare\arc/bin/archw^ semint)=^C:\MWLite\MetaWare\arc/bin/prof.dll^ semint)=^C:\MWLite\MetaWare\arc/bin/profmm.dll^ nsim_isa_family=av2hs nsim_isa_core=3 arcver=83 nsim_isa_atomic_option=1 nsim_isa_shift_option=3 nsim_isa_code_density_option=2 nsim_isa_swap_option=1 nsim_isa_bitscan_option=1 nsim_isa_enable_timer_0=1 nsim_isa_enable_timer_1=1 nsim_isa_number_of_interrupts=32 nsim_isa_number_of_external_interrupts=3 nsim_isa_has_interrupts=1 nsim_connect=2 nsim_connect_ici=2 nsim_isa_unaligned_option=1 nsim_isa_mpy_option=6 nsim_isa_num_actionpoints=8 port=0x378 include_local_symbols=1 prefer_soft_bp=0 flush_pipe=0 prompt=mdb dname=MetaWare sys_cmpd=1
endm
defclass name=class_multi_Core1 newsys=multi_Core1 clone_noprops=1 system1=ARC_DLL system2=BRC_DLL
defset Core1 [1]
newcmd [Core1] class_multi_Core1
[Core1] defargs sample_threadx\Debug\sample_threadx.elf

10
ports_smp/arc_hs_smp/metaware/example_build/.sc.project/.sc.args.Core2.multi Normal file
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// ARGS: -pset=2 -psetname=Core2 sample_threadx\Debug\sample_threadx.elf -arconnect -connect_ici -av2hs -Xatomic -Xunaligned -core3 -Xmpy_option=mpy -Xtimer0 -Xtimer1 -nooptions -interrupts=32 -ext_interrupts=3 -prop=nsim_isa_num_actionpoints=8 -off=prefer_soft_bp -nogoifmain
macro multi_Core2
nocomment prop DLL)=^C:\MWLite\MetaWare\arc/../../nSIM/lib/libsim^
nocomment prop cpunum=$cid timer0_regs=1 timer1_regs=1 cloneable=1 icnts=1 killeds=1 delay_killeds=1 trace_enabled=1 semint)=^C:\MWLite\MetaWare\arc/bin/archw^ semint)=^C:\MWLite\MetaWare\arc/bin/prof.dll^ semint)=^C:\MWLite\MetaWare\arc/bin/profmm.dll^ nsim_isa_family=av2hs nsim_isa_core=3 arcver=83 nsim_isa_atomic_option=1 nsim_isa_shift_option=3 nsim_isa_code_density_option=2 nsim_isa_swap_option=1 nsim_isa_bitscan_option=1 nsim_isa_enable_timer_0=1 nsim_isa_enable_timer_1=1 nsim_isa_number_of_interrupts=32 nsim_isa_number_of_external_interrupts=3 nsim_isa_has_interrupts=1 nsim_connect=2 nsim_connect_ici=2 nsim_isa_unaligned_option=1 nsim_isa_mpy_option=6 nsim_isa_num_actionpoints=8 port=0x378 include_local_symbols=1 prefer_soft_bp=0 flush_pipe=0 prompt=mdb dname=MetaWare sys_cmpd=1
endm
defclass name=class_multi_Core2 newsys=multi_Core2 clone_noprops=1 system1=ARC_DLL system2=BRC_DLL
defset Core2 [2]
newcmd [Core2] class_multi_Core2
[Core2] defargs sample_threadx\Debug\sample_threadx.elf

139
ports_smp/arc_hs_smp/metaware/example_build/.sc.project/.sc.project.windows Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<windowLayout version="3" model="sash">
<mdiFrame model="sash" x="130" y="8" width="1565" height="942">
<splitPane orientation="horizontal" divider="320">
<splitPane orientation="vertical" divider="409">
<pane>
<tabbedPanel name="locals" process="1" selected="1">
<toolBar id="0" visible="0"/>
<toolBar id="1" visible="1"/>
<toolBar id="2" visible="0"/>
</tabbedPanel>
<tabbedPanel name="locals" process="2">
<toolBar id="0" visible="0"/>
<toolBar id="1" visible="1"/>
<toolBar id="2" visible="0"/>
</tabbedPanel>
</pane>
<splitPane orientation="vertical" divider="203">
<pane>
<tabbedPanel name="stack" process="1" selected="1">
<toolBar id="0" visible="0"/>
<toolBar id="1" visible="1"/>
<toolBar id="2" visible="0"/>
</tabbedPanel>
<tabbedPanel name="stack" process="2">
<toolBar id="0" visible="0"/>
<toolBar id="1" visible="1"/>
<toolBar id="2" visible="0"/>
</tabbedPanel>
</pane>
<pane>
<tabbedPanel name="instrhist" process="2" selected="1">
<toolBar id="0" visible="0"/>
<toolBar id="1" visible="1"/>
<toolBar id="2" visible="0"/>
</tabbedPanel>
</pane>
</splitPane>
</splitPane>
<splitPane orientation="vertical" divider="478">
<splitPane orientation="vertical" divider="239">
<splitPane orientation="horizontal" divider="612">
<pane>
<tabbedPanel name="source" process="1" selected="1">
<toolBar id="0" visible="0"/>
<toolBar id="1" visible="1"/>
<toolBar id="2" visible="0"/>
<toolBar id="3" visible="0"/>
</tabbedPanel>
<tabbedPanel name="source" process="2">
<toolBar id="0" visible="0"/>
<toolBar id="1" visible="1"/>
<toolBar id="2" visible="0"/>
<toolBar id="3" visible="0"/>
</tabbedPanel>
</pane>
<pane>
<tabbedPanel name="instrhist" process="1" selected="1">
<toolBar id="0" visible="0"/>
<toolBar id="1" visible="1"/>
<toolBar id="2" visible="0"/>
</tabbedPanel>
</pane>
</splitPane>
<splitPane orientation="horizontal" divider="612">
<pane>
<tabbedPanel name="mem" process="1" selected="1">
<toolBar id="0" visible="0"/>
<toolBar id="1" visible="1"/>
<toolBar id="2" visible="0"/>
</tabbedPanel>
</pane>
<pane>
<tabbedPanel name="examine" process="1" selected="1">
<toolBar id="0" visible="0"/>
<toolBar id="1" visible="1"/>
<toolBar id="2" visible="0"/>
</tabbedPanel>
</pane>
</splitPane>
</splitPane>
<splitPane orientation="horizontal" divider="469">
<pane>
<tabbedPanel name="break" process="1">
<toolBar id="0" visible="0"/>
<toolBar id="1" visible="1"/>
<toolBar id="2" visible="0"/>
</tabbedPanel>
<tabbedPanel name="break" process="2">
<toolBar id="0" visible="0"/>
<toolBar id="1" visible="1"/>
<toolBar id="2" visible="0"/>
</tabbedPanel>
<tabbedPanel name="watchdisp" process="1" selected="1">
<toolBar id="0" visible="0"/>
<toolBar id="1" visible="1"/>
<toolBar id="2" visible="0"/>
</tabbedPanel>
<tabbedPanel name="watchdisp" process="2">
<toolBar id="0" visible="0"/>
<toolBar id="1" visible="1"/>
<toolBar id="2" visible="0"/>
</tabbedPanel>
<tabbedPanel name="command"/>
</pane>
<splitPane orientation="horizontal" divider="83">
<splitPane orientation="vertical" divider="91">
<pane>
<tabbedPanel name="processes" selected="1">
<toolBar id="0" visible="0"/>
<toolBar id="1" visible="1"/>
<toolBar id="2" visible="0"/>
</tabbedPanel>
</pane>
<pane>
<tabbedPanel name="expr" process="2" selected="1">
<toolBar id="0" visible="0"/>
<toolBar id="1" visible="1"/>
<toolBar id="2" visible="0"/>
<initState>ver 1.0;</initState>
</tabbedPanel>
</pane>
</splitPane>
<pane>
<tabbedPanel name="expr" process="1" selected="1">
<toolBar id="0" visible="0"/>
<toolBar id="1" visible="1"/>
<toolBar id="2" visible="0"/>
<valueUpdate name="id1" value="_tx_thread_system_stack_ptr"/>
<initState>ver 1.0;E:thread_0_counter:0:0;E:thread_0_counter:0:0;E:thread_1_counter:0:0;E:thread_1_counter:0:0;E:thread_2_counter:0:0;E:thread_2_counter:0:0;E:thread_3_counter:0:0;E:thread_3_counter:0:0;E:thread_4_counter:0:0;E:thread_4_counter:0:0;E:thread_5_counter:0:0;E:thread_5_counter:0:0;E:thread_6_counter:0:0;E:thread_6_counter:0:0;E:thread_7_counter:0:0;E:thread_7_counter:0:0;E:_tx_timer_system_clock:0:0;E:_tx_timer_system_clock:0:0;E:_tx_thread_execute_ptr:0:0;M:1:1:0;E:_tx_thread_execute_ptr:0:0;E:thread_1:1:0;E:thread_1:0:0;E:thread_2:0:0;E:thread_2:0:0;E:thread_0:0:0;E:thread_0:0:0;E:_tx_thread_system_stack_ptr:0:0;</initState>
</tabbedPanel>
</pane>
</splitPane>
</splitPane>
</splitPane>
</splitPane>
</mdiFrame>
</windowLayout>

5
ports_smp/arc_hs_smp/metaware/example_build/.sc.project/.sc.project.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<Config>
<CurrentWindowLayoutFile>C:\arc_hs_smp\for_intel_04-17-17\.sc.project\.sc.project.windows</CurrentWindowLayoutFile>
</Config>

25
ports_smp/arc_hs_smp/metaware/example_build/.sc.project/.sc2.Core1.properties Normal file
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ARC5_Core_Version=3
ARC6_Core_Version=3
ARC7_Core_Version=3
ARC_arconnect=1
ARC_atomic=1
ARC_connect_ici=2
ARC_default_ext_interrupts=0
ARC_default_interrupts=0
ARC_ext_interrupt_num=3
ARC_interrupt_num=32
ARC_interrupt_vector_count=32
ARC_mpy_emoption=mpy
ARC_mpy_hsoption=mpy
ARC_parallel_port_address=0x378
ARC_target=ARCSIM
ARC_timer0=1
ARC_timer1=1
ARC_unaligned=1
Execute_to_main=0
cmd_line_option=-prop\=nsim_isa_num_actionpoints\=8 -prop\=nsim_isa_num_actionpoints\=8 -prop\=nsim_isa_num_actionpoints\=8 -prop\=nsim_isa_num_actionpoints\=8 -prop\=nsim_isa_num_actionpoints\=8
prefer_sw_bp=0
program="sample_threadx\\\\Debug\\\\sample_threadx.elf"
v2em_core_version=3
v2hs_core_version=3
which_arc=ARCV2HS

25
ports_smp/arc_hs_smp/metaware/example_build/.sc.project/.sc2.Core2.properties Normal file
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ARC5_Core_Version=3
ARC6_Core_Version=3
ARC7_Core_Version=3
ARC_arconnect=1
ARC_atomic=1
ARC_connect_ici=2
ARC_default_ext_interrupts=0
ARC_default_interrupts=0
ARC_ext_interrupt_num=3
ARC_interrupt_num=32
ARC_interrupt_vector_count=32
ARC_mpy_emoption=mpy
ARC_mpy_hsoption=mpy
ARC_parallel_port_address=0x378
ARC_target=ARCSIM
ARC_timer0=1
ARC_timer1=1
ARC_unaligned=1
Execute_to_main=0
cmd_line_option=-prop\=nsim_isa_num_actionpoints\=8 -prop\=nsim_isa_num_actionpoints\=8 -prop\=nsim_isa_num_actionpoints\=8 -prop\=nsim_isa_num_actionpoints\=8 -prop\=nsim_isa_num_actionpoints\=8
prefer_sw_bp=0
program="sample_threadx\\\\Debug\\\\sample_threadx.elf"
v2em_core_version=3
v2hs_core_version=3
which_arc=ARCV2HS

3
ports_smp/arc_hs_smp/metaware/example_build/.sc.project/.sc2.properties Normal file
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ARC_parallel_port_address=0x378
Execute_to_main=1
cmd_line_option=-multifiles\=Core1,Core2 -OKN

4
ports_smp/arc_hs_smp/metaware/example_build/run_threadx_smp_demo.bat Normal file
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@@ -0,0 +1,4 @@
set NSIM_MULTICORE=1
mdb -pset=1 -psetname=Core1 sample_threadx\Debug\sample_threadx.elf -arconnect -connect_ici -av2hs -Xatomic -Xunaligned -core3 -Xmpy_option=mpy -Xtimer0 -Xtimer1 -nooptions -interrupts=32 -ext_interrupts=3 -prop=nsim_isa_num_actionpoints=8 -off=prefer_soft_bp -nogoifmain
mdb -pset=2 -psetname=Core2 sample_threadx\Debug\sample_threadx.elf -arconnect -connect_ici -av2hs -Xatomic -Xunaligned -core3 -Xmpy_option=mpy -Xtimer0 -Xtimer1 -nooptions -interrupts=32 -ext_interrupts=3 -prop=nsim_isa_num_actionpoints=8 -off=prefer_soft_bp -nogoifmain
mdb -multifiles=Core1,Core2 -OKN

3
ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/.bp.args Normal file
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location=_tx_thread_system_return
condition_enabled=0
cond=

13
ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/.bp.properties Normal file
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@@ -0,0 +1,13 @@
#Debugger engine properties
#Fri Oct 02 16:50:37 PDT 2015
ARG_ACTION={"location\=_tx_thread_system_return" "condition_enabled\=0" "cond\=" }
docTitle=break_dialog
LOCATION=_tx_thread_system_return
on_push=bpsaved
TYPE=either
TEMPORARY=false
OK_ON_ENTER=1
OK_ENABLED=1
ReadingXML=false
THREAD_SPECIFIC=false
CONDITION_ENABLED=false

188
ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/.cproject Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<cconfiguration id="com.arc.cdt.toolchain.av2hs.exeDebugConfig.585788724">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arc.cdt.toolchain.av2hs.exeDebugConfig.585788724" moduleId="org.eclipse.cdt.core.settings" name="Debug">
<externalSettings/>
<extensions>
<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.MakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="com.arc.cdt.toolchain.ARCLinkerErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="com.arc.cdt.toolchain.ARCCompilerErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="com.arc.cdt.toolchain.ARCAssemblerErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" errorParsers="com.arc.cdt.toolchain.ARCCompilerErrorParser;com.arc.cdt.toolchain.ARCLinkerErrorParser;com.arc.cdt.toolchain.ARCAssemblerErrorParser;org.eclipse.cdt.core.MakeErrorParser" id="com.arc.cdt.toolchain.av2hs.exeDebugConfig.585788724" name="Debug" parent="com.arc.cdt.toolchain.av2hs.exeDebugConfig">
<folderInfo id="com.arc.cdt.toolchain.av2hs.exeDebugConfig.585788724." name="/" resourcePath="">
<toolChain id="com.arc.cdt.toolchain.av2hs.exeToolChainDebug.1358823635" superClass="com.arc.cdt.toolchain.av2hs.exeToolChainDebug">
<targetPlatform id="hcTargetPlatform.1681683287" isAbstract="false" name="Generic platform" superClass="hcTargetPlatform"/>
<builder buildPath="${workspace_loc:/sample_threadx}/Debug" id="makeBuilder.698856797" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="makeBuilder"/>
<tool id="av2hs.exe.debug.exeCompilerDebug.1743110770" superClass="av2hs.exe.debug.exeCompilerDebug">
<option id="arc.compiler.options.target.version.1719429849" isActive="false" name="ARC Core Version" superClass="arc.compiler.options.target.version" value="arc.compiler.options.target.arcv2hs" valueType="enumerated"/>
<option id="arc.compiler.options.bs.1459483714" isActive="false" name="Barrel shifter (-Xbs/-Xbarrel_shifter)" superClass="arc.compiler.options.bs" value="true" valueType="boolean"/>
<option id="arc.compiler.options.pc_width.1230771954" isActive="false" name="PC register width (-Hpc_width=)" superClass="arc.compiler.options.pc_width" value="com.arc.cdt.toolchain.arc.pcwidth.32" valueType="enumerated"/>
<option id="arc.compiler.options.lpc_width.898161522" isActive="false" name="LP_COUNT register width (-Hlpc_width=)" superClass="arc.compiler.options.lpc_width" value="com.arc.cdt.toolchain.arc.lpcwidth.32" valueType="enumerated"/>
<option id="arc.compiler.options.include_dirs.688677620" isActive="false" isDefinedList="false" name="Include Directories (one per line)" superClass="arc.compiler.options.include_dirs" useByScannerDiscovery="false" valueType="includePath">
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/tx/inc_generic}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/tx/inc_port}&quot;"/>
</option>
<option id="arc.compiler.options.timers.timer0.92712328" isActive="false" name="Use Timer 0 (-Xtimer0)" superClass="arc.compiler.options.timers.timer0" useByScannerDiscovery="true" value="true" valueType="boolean"/>
<option id="arc.compiler.options.timers.timer1.1544799494" isActive="false" name="Use timer 1 (-Xtimer1)" superClass="arc.compiler.options.timers.timer1" useByScannerDiscovery="true" value="true" valueType="boolean"/>
<option id="arc.compiler.options.bcf.972166381" isActive="false" name="Tools Configuration File" superClass="arc.compiler.options.bcf" value="${METAWARE_ROOT}/arc/tcf/hs36.tcf" valueType="string"/>
<option id="arc.compiler.options.arcv2hscore.963577987" isActive="false" name="ARC HS Core" superClass="arc.compiler.options.arcv2hscore" useByScannerDiscovery="true" value="arc.compiler.options.arcv2hscore.core3" valueType="enumerated"/>
<option id="arc.compiler.options.sa.316338055" isActive="false" name="Shift Assist (-Xsa/-Xshift_assist)" superClass="arc.compiler.options.sa" value="true" valueType="boolean"/>
<option id="arc.compiler.options.unaligned.1554197875" isActive="false" name="Unaligned memory access (-Xunaligned)" superClass="arc.compiler.options.unaligned" useByScannerDiscovery="true" value="true" valueType="boolean"/>
<option id="arc.compiler.options.mpyHSoption.1505788200" isActive="false" name="Multiply Option -Xmpy_option=" superClass="arc.compiler.options.mpyHSoption" useByScannerDiscovery="true" value="arc.options.mpyoption.mpy" valueType="enumerated"/>
<option id="arc.compiler.options.bitscan.334538662" isActive="false" name="Bit scan instructions (-Xbitscan)" superClass="arc.compiler.options.bitscan" value="true" valueType="boolean"/>
<option id="arc.compiler.options.swap.1877987625" isActive="false" name="Swap instruction (-Xswap)" superClass="arc.compiler.options.swap" value="true" valueType="boolean"/>
<option id="arc.compiler.options.cd.415086761" isActive="false" name="Code density extension (-Xcd/-Xcode_density)" superClass="arc.compiler.options.cd" value="true" valueType="boolean"/>
<option id="arc.compiler.options.atomic.1971251451" isActive="false" name="Atomic option (-Xatomic)" superClass="arc.compiler.options.atomic" useByScannerDiscovery="true" value="true" valueType="boolean"/>
<option id="arc.compiler.options.hcl.1556432630" isActive="false" name="Compile/Link with Compact Lib (-Hcl)" superClass="arc.compiler.options.hcl" useByScannerDiscovery="true" value="true" valueType="boolean"/>
<option id="arc.compiler.options.keepasm.337838773" isActive="false" name="Preserve generated assembly files (-Hkeepasm)" superClass="arc.compiler.options.keepasm" useByScannerDiscovery="false" value="false" valueType="boolean"/>
<option id="arc.compiler.options.defines.2064476662" isActive="false" isDefinedList="false" superClass="arc.compiler.options.defines" valueType="definedSymbols">
<listOptionValue builtIn="false" value="TX_ZERO_BASED_CORE_ID"/>
</option>
<inputType id="com.arc.cdt.toolchain.arc.ccac.inputTypeCPP.1372491410" name="MetaWare C++ Input" superClass="com.arc.cdt.toolchain.arc.ccac.inputTypeCPP"/>
<inputType id="com.arc.cdt.toolchain.arc.ccac.inputTypeC.1185403415" name="MetaWare C Input" superClass="com.arc.cdt.toolchain.arc.ccac.inputTypeC"/>
<inputType id="com.arc.cdt.toolchain.arc.inputTypeCL.1235629386" name="MetaWare OpenCL" superClass="com.arc.cdt.toolchain.arc.inputTypeCL"/>
</tool>
<tool id="com.arc.cdt.toolchain.av2hs.asmDebugExe.1483523628" superClass="com.arc.cdt.toolchain.av2hs.asmDebugExe">
<option id="arc.asm.options.bs.2039952525" isActive="false" name="Barrel shifter (-Xbs/-Xbarrel_shifter)" superClass="arc.asm.options.bs" value="true" valueType="boolean"/>
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<listOptionValue builtIn="false" value="../sample_threadx.cmd"/>
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<tool id="com.arc.cdt.toolchain.arc.archiver.886382681" superClass="com.arc.cdt.toolchain.arc.archiver"/>
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<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.MakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="com.arc.cdt.toolchain.ARCLinkerErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="com.arc.cdt.toolchain.ARCCompilerErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="com.arc.cdt.toolchain.ARCAssemblerErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="rm -rf" description="" errorParsers="com.arc.cdt.toolchain.ARCCompilerErrorParser;com.arc.cdt.toolchain.ARCLinkerErrorParser;com.arc.cdt.toolchain.ARCAssemblerErrorParser;org.eclipse.cdt.core.MakeErrorParser" id="com.arc.cdt.toolchain.av2hs.exeReleaseConfig.2024992869" name="Release" parent="com.arc.cdt.toolchain.av2hs.exeReleaseConfig">
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<targetPlatform id="hcTargetPlatform.325929801" isAbstract="false" name="Generic platform" superClass="hcTargetPlatform"/>
<builder buildPath="${workspace_loc:/sample_threadx}/Release" id="makeBuilder.1770123329" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="makeBuilder"/>
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26
ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/.project Normal file
View File

@@ -0,0 +1,26 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>sample_threadx</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
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<natures>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
</natures>
</projectDescription>

35
ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/.settings/language.settings.xml Normal file
View File

@@ -0,0 +1,35 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project>
<configuration id="com.arc.cdt.toolchain.av2hs.exeDebugConfig.585788724" name="Debug">
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider copy-of="extension" id="com.arc.cdt.toolchain.arc.language.settings.providers.MccBuildCommandParser"/>
<provider class="com.arc.cdt.toolchain.arc.language.settings.providers.MccBuiltinSpecsDetector" console="false" env-hash="1695255886827884744" id="com.arc.cdt.toolchain.arc.language.settings.providers.MccBuiltinSpecsDetector" keep-relative-paths="false" name="MetaWare MCC Built-in Compiler Settings" parameter="mcc ${FLAGS} -Hbatchnotmp -Hnoobj &quot;${INPUTS}&quot;" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
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<provider class="com.arc.cdt.toolchain.arc.language.settings.providers.ClangBuildCommandParser" id="com.arc.cdt.toolchain.arc.language.settings.providers.ClangBuildCommandParser" keep-relative-paths="false" name="MetaWare CCAC Build Output Parser" parameter="ccac" prefer-non-shared="true"/>
<provider class="com.arc.cdt.toolchain.arc.language.settings.providers.ClangBuiltinSpecsDetector" console="false" env-hash="1775861871551300168" id="com.arc.cdt.toolchain.arc.language.settings.providers.ClangBuiltinSpecsDetector" keep-relative-paths="false" name="MetaWare CCAC Built-in Compiler Settings" parameter="ccac ${FLAGS} -v -dM -E &quot;${INPUTS}&quot;" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
</extension>
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<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
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<language-scope id="org.eclipse.cdt.core.gcc"/>
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<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
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<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
</extension>
</configuration>
</project>

69
ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/.settings/org.eclipse.cdt.codan.core.prefs Normal file
View File

@@ -0,0 +1,69 @@
eclipse.preferences.version=1
org.eclipse.cdt.codan.checkers.errnoreturn=Warning
org.eclipse.cdt.codan.checkers.errnoreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},implicit\=>false}
org.eclipse.cdt.codan.checkers.errreturnvalue=Error
org.eclipse.cdt.codan.checkers.errreturnvalue.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
org.eclipse.cdt.codan.checkers.noreturn=Error
org.eclipse.cdt.codan.checkers.noreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},implicit\=>false}
org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation=Error
org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem=Error
org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem=Warning
org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem=Error
org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem=Warning
org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},no_break_comment\=>"no break",last_case_param\=>false,empty_case_param\=>false}
org.eclipse.cdt.codan.internal.checkers.CatchByReference=Warning
org.eclipse.cdt.codan.internal.checkers.CatchByReference.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},unknown\=>false,exceptions\=>()}
org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem=Error
org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization=Warning
org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},skip\=>true}
org.eclipse.cdt.codan.internal.checkers.ExternalBindingProblem=Warning
org.eclipse.cdt.codan.internal.checkers.ExternalBindingProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem=Error
org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem=Error
org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
org.eclipse.cdt.codan.internal.checkers.InvalidArguments=Error
org.eclipse.cdt.codan.internal.checkers.InvalidArguments.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem=Error
org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem=Error
org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem=Error
org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem=Error
org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker=-Info
org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},pattern\=>"^[a-z]",macro\=>true,exceptions\=>()}
org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem=Warning
org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
org.eclipse.cdt.codan.internal.checkers.OverloadProblem=Error
org.eclipse.cdt.codan.internal.checkers.OverloadProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem=Error
org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem=Error
org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem=Warning
org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},macro\=>true,exceptions\=>()}
org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem=Warning
org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},paramNot\=>false}
org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem=Warning
org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},else\=>false,afterelse\=>false}
org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem=Error
org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem=Warning
org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},macro\=>true}
org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem=Warning
org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},macro\=>true}
org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem=Warning
org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},macro\=>true,exceptions\=>("@(\#)","$Id")}
org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem=Error
org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}

150
ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/arc.c Normal file
View File

@@ -0,0 +1,150 @@
/* ------------------------------------------
* Copyright (c) 2016, Synopsys, Inc. All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1) Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------- */
#include "arc.h"
/*********************************************************************
* Core Intc setup
*********************************************************************/
#define AUX_STAT32 0x00a
#define AUX_IVT_BASE 0x025
#define AUX_VOL 0x05e
#define AUX_IRQ_CTRL 0x00E
#define AUX_IRQ_SEL 0x40b
#define AUX_IRQ_PRIO 0x206
#define INTC_DEF_PRIO 1
/*********************************************************************
* Timers uses timer0
*********************************************************************/
#define AUX_TIM0_CNT 0x021
#define AUX_TIM0_CTRL 0x022
#define AUX_TIM0_LIMIT 0x023
/*********************************************************************
* Inter Core interruts
*********************************************************************/
#define AUX_MCIP_BCR 0x0d0
#define AUX_MCIP_CMD 0x600
#define AUX_MCIP_WDATA 0x601
#define AUX_MCIP_READBK 0x602
#define CMD_ICI_GENERATE_IRQ 0x1
#define CMD_ICI_GENERATE_ACK 0x2
#define CMD_ICI_READ_STATUS 0x3
#define CMD_ICI_CHECK_SOURCE 0x4
void _tx_thread_smp_initialize_wait(void);
void arc_timer_setup(unsigned int cycles);
void arc_cpu_init(void)
{
extern char VECT_TABLE_BASE[]; // from sample_threadx.lcf
_sr((unsigned int)VECT_TABLE_BASE, AUX_IVT_BASE);
/* 0xc000_0000 in uncached */
_sr(0xc0000000, AUX_VOL);
/* setup irqs to interrupt at default interruption threshhold */
_sr(IRQ_TIMER, AUX_IRQ_SEL);
_sr(INTC_DEF_PRIO, AUX_IRQ_PRIO);
_sr(IRQ_IPI, AUX_IRQ_SEL);
_sr(INTC_DEF_PRIO, AUX_IRQ_PRIO);
#ifndef TX_ZERO_BASED_CORE_ID
if (smp_processor_id() > 1)
#else
if (smp_processor_id() > 0)
#endif
_tx_thread_smp_initialize_wait();
arc_timer_setup(19999);
}
void arc_timer_setup(unsigned int cycles)
{
_sr(cycles, AUX_TIM0_LIMIT); /* interupt after CNT == @cycles */
_sr(0, AUX_TIM0_CNT); /* initial CNT */
_sr(0x3, AUX_TIM0_CTRL); /* Interrupt enable, count only when NOT halted */
}
static inline void __mcip_cmd(unsigned int cmd, unsigned int param)
{
struct mcip_cmd {
unsigned int cmd:8, param:16, pad:8;
} buf;
buf.pad = 0;
buf.cmd = cmd;
buf.param = param;
_sr(*(unsigned int *)&buf, AUX_MCIP_CMD);
}
void arc_ici_send(unsigned int cpu)
{
int ipi_pend;
__mcip_cmd(CMD_ICI_READ_STATUS, cpu);
ipi_pend = _lr(AUX_MCIP_READBK);
if (!ipi_pend)
__mcip_cmd(CMD_ICI_GENERATE_IRQ, cpu);
}
void arc_ici_handler(void)
{
unsigned int senders, c;
__mcip_cmd(CMD_ICI_CHECK_SOURCE, 0);
senders = _lr(AUX_MCIP_READBK); /* 1,2,4,8... */
/* No support interrupt coalescing yet */
c = __ffs(senders); /* 0,1,2,3 */
__mcip_cmd(CMD_ICI_GENERATE_ACK, c);
}

120
ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/arc.h Normal file
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@@ -0,0 +1,120 @@
/* ------------------------------------------
* Copyright (c) 2016, Synopsys, Inc. All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1) Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------- */
#include "arc/arc_reg.h"
/*********************************************************************
* Core Intc setup
*********************************************************************/
#ifndef __ARC_HDR__
#define __ARC_HDR__
#ifndef NULL
#define NULL 0
#endif
#define IRQ_TIMER 16
#define IRQ_IPI 19
#define CORE_PRIMARY 1
#define CORE_SECONDARY 2
#define INTERRUPT_ENABLE (1 << 4) // according ISA (SETI instruction details)
#define INTERRUPT_LEVEL(L) ((L) << 0)//simple macro for user-friendly name conversion
static inline int __ffs(unsigned long x)
{
int n;
asm volatile(
" ffs.f %0, %1 \n" /* 0..31; Z set if src 0 */
" mov.z %0, 0 \n" /* return 0 if 0 */
: "=r"(n)
: "r"(x)
: "cc");
return n;
}
#define AUX_ID 0x004
static inline int smp_processor_id()
{
unsigned int id = _lr(AUX_ID);
return (id >> 8) & 0xFF;
}
static inline void arc_halt(void)
{
asm volatile("flag 1\n");
}
/* no need for volatile */
typedef unsigned int spinlock_t;
static inline void spinlock_acquire(unsigned int *lock)
{
unsigned int val;
asm volatile(
"1: llock %[val], [%[slock]] \n"
" breq %[val], %[LOCKED], 1b \n" /* spin while LOCKED */
" scond %[LOCKED], [%[slock]] \n" /* acquire */
" bnz 1b \n"
" dmb 3 \n"
: [val] "=&r" (val)
: [slock] "r" (lock),
[LOCKED] "r" (1)
: "memory", "cc");
}
static inline void spinlock_release(unsigned int *lock)
{
__asm__ __volatile__(
" dmb 3 \n"
" st %[UNLOCKED], [%[slock]] \n"
:
: [slock] "r" (lock),
[UNLOCKED] "r" (0)
: "memory");
}
static inline void arc_enable_ints(void)
{
_seti(1);
}
extern void arc_timer_setup(unsigned int);
extern void arc_register_isr(int irq, void (*fn)(int), int arg_to_isr);
extern void arc_ici_send(unsigned int cpu);
#endif

166
ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/crt1cl.s Normal file
View File

@@ -0,0 +1,166 @@
; Copyright (c) 2000-2009 ARC International
.file "crt1cl.s"
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;; Startup
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
.text
.weak _SDA_BASE_
.macro jmpl,target
jl target ; "large" model call
.endm
.on assume_short, assume_nop_short
.define S, _s
; Indicate whether registers should be initialized with 0
; This might be desirable if executing in an environment where
; registers may contain undefined values on startup.
.define PERFORM_REGISTER_INITIALIZATION, 0
.section .text$crt00, text
.global _start
.type _start, @function
.reloc __crt_callmain, 0
_start:
.if PERFORM_REGISTER_INITIALIZATION
; Initialize the register file.
; Compiled code may generate sub r0, r1, r1, expecting to
; load 0 into r0, but in some execution environments the individual
; reads of r1 for the two source operands may return different
; (garbage) values if r1 had never been written to since reset.
.ifdef _ARC_RF16
.irep num, 1, 2, 3, 10, 11, 12, 13, 14, 15
mov r\&num, 0
.endr
.else
.irep num, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25
mov r\&num, 0
.endr
.endif
.endif
.weak __xcheck
.ifdef _PICTABLE
; under PICTABLE, r0 is assumed to contain the base of the data segment
; so must preserve it. __xcheck modifies only r0 and r1 and is
; position-independent
mov r2, r0
mov.f r0, __xcheck
beq .Linit_pic
bl __xcheck
mov r0, r2
.Linit_pic:
.weak __PICTABLE__
; In PIC mode, we assume that we were loaded by a loader and may not
; reside at the addresses that the ELF file was linked with. In
; this case, the address of where the data segment has been loaded
; is passed to _start in the r0 register. We figure out the new code
; segment base ourselves.
mov r2, __PICTABLE__
sub.f 0, r2, 0
nop ; required for -a4 -core5
beq no_pic
bl _init_pic
no_pic:
.endif
.Lsetstack:
; like smp_processor_id() from arc.h
; AUX_IDENTITY Reg [ 3 2 1 0 ]
; ^^^ => 0 for Master, !0 otherwise
; Note: this is setup for 2 cores and needs to be augmented if more than 2 cores
lr r0, [identity]
lsr r0, r0, 8
bmsk r0, r0, 7
.ifndef TX_ZERO_BASED_CORE_ID
breq r0, 2, .Lsecondary
.else
breq r0, 1, .Lsecondary
.endif
mov sp, STACK1_END ; initialize stack pointer, core 1
b .Lcontinue
.Lsecondary:
mov sp, STACK2_END ; initialize stack pointer, core 2
.Lcontinue:
mov gp, _SDA_BASE_ ; initialize small-data base register
mov fp, 0 ; initialize frame pointer
__crt_start:
; various components may get placed here by the linker:
; priority optional component command-line option
;----------------------------------------------------------------------
; 10 _init_ldi,_init_jli,_init_ei, automated
; _init_sjli
; 20 __crt_initcopy -Hcrt_initcopy
; 25 __crt_initbss -Hcrt_initbss
; 30 __crt_invcache -Hcrt_invcache
; 70 __crt_inittimer -Hcrt_inittimer
; 80 _init forced included below
; 90 __crt_callmain forced, with
; optional -Hcrt_argv
.cfa_bf _start
.section .text$crt99, text
.sectflag .text$crt99, include
; INIT CODE FALLS THROUGH TO _exit_halt
.cfa_ef
.global _exit_halt
.type _exit_halt, @function
_exit_halt:
.cfa_bf _exit_halt
flag 0x01
nop
.if ! $is_arcv2
; ARC 700 serializes on 'flag', so no way to get back to here.
nop
nop
.endif
b _exit_halt
.reloc main, 0; force main in if its in a library
.cfa_ef
.section .text$crt80, text
.sectflag .text$crt80, include
__crt_init:
bl _init
.previous
; weak versions of small data symbols normally defined by the linker.
.weak _fsbss
.weak _esbss
.set _fsbss,0
.set _esbss,0
; weak versions of BSS section symbols in case there is no .bss section
.weak _fbss
.weak _ebss
.set _fbss,0
.set _ebss,0
; weak versions of heap section boundaries. If a .heap section
; is provided, our low-level allocator "sbrk" allocates within it.
; If no .heap is provided, we allocate from _end to the end of memory.
.weak _fheap
.weak _eheap
.set _fheap,0
.set _eheap,0
; reference the beginning of the stack for debugger's stack checking
.weak _fstack
.set _fstack,0
.end

72
ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/crti.s Normal file
View File

@@ -0,0 +1,72 @@
; Copyright (c) 2002-2005 ARC International
.file "crti.s"
.option %reg
.global _init, _fini
.extern __mw_cpp_init, __mw_cpp_exit
.macro jmpl,target
.if $core_version > 5
jl target ; "large" model call
.else
lr %blink, [%status]
add %blink, %blink, 3
j target
.endif
.endm
.if $isa == "ARCompact"
.on assume_short
.endif
.section ".init",text
_init:
.if $isa == "ARC"
st %fp, [%sp, 0]
st %blink, [%sp, 4]
mov %fp, %sp
sub %sp, %sp, 16
.else
.cfa_bf _init
push %blink
.cfa_push {%blink}
.endif
.section ".init$999999", text, 1, 2, check_text_align=0
; this is now brought in by a reference generated by the compiler
; jmpl __mw_cpp_init
.if $isa == "ARC"
ld %blink, [%fp, 4]
j.d [%blink]
ld.a %fp, [%sp, 16]
.else
pop %blink
.cfa_pop {%blink}
j [%blink]
.cfa_ef
.endif
.section ".fini", text
_fini:
.if $isa == "ARC"
st %fp, [%sp, 0]
st %blink, [%sp, 4]
mov %fp, %sp
sub %sp, %sp, 16
.else
.cfa_bf _fini
push %blink
.cfa_push {%blink}
.endif
.section ".fini$999999", text, 1, 2, check_text_align=0
; jmpl __mw_cpp_exit
.if $isa == "ARC"
ld %blink, [%fp, 4]
j.d [%blink]
ld.a %fp, [%sp, 16]
.else
pop %blink
.cfa_pop {%blink}
j [%blink]
.cfa_ef
.endif
.end

374
ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/sample_threadx.c Normal file
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@@ -0,0 +1,374 @@
/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight
threads of different priorities, using a message queue, semaphore, mutex, event flags group,
byte pool, and block pool. */
#include "tx_api.h"
#define DEMO_STACK_SIZE 1024
#define DEMO_BYTE_POOL_SIZE 9120
#define DEMO_BLOCK_POOL_SIZE 100
#define DEMO_QUEUE_SIZE 100
/* Define the ThreadX object control blocks... */
TX_THREAD thread_0;
TX_THREAD thread_1;
TX_THREAD thread_2;
TX_THREAD thread_3;
TX_THREAD thread_4;
TX_THREAD thread_5;
TX_THREAD thread_6;
TX_THREAD thread_7;
TX_QUEUE queue_0;
TX_SEMAPHORE semaphore_0;
TX_MUTEX mutex_0;
TX_EVENT_FLAGS_GROUP event_flags_0;
TX_BYTE_POOL byte_pool_0;
TX_BLOCK_POOL block_pool_0;
/* Define the counters used in the demo application... */
ULONG thread_0_counter;
ULONG thread_1_counter;
ULONG thread_1_messages_sent;
ULONG thread_2_counter;
ULONG thread_2_messages_received;
ULONG thread_3_counter;
ULONG thread_4_counter;
ULONG thread_5_counter;
ULONG thread_6_counter;
ULONG thread_7_counter;
/* Define thread prototypes. */
void thread_0_entry(ULONG thread_input);
void thread_1_entry(ULONG thread_input);
void thread_2_entry(ULONG thread_input);
void thread_3_and_4_entry(ULONG thread_input);
void thread_5_entry(ULONG thread_input);
void thread_6_and_7_entry(ULONG thread_input);
void arc_cpu_init(void);
/* Define main entry point. */
int main()
{
/* ARC-specific initialization. */
arc_cpu_init();
/* Enter the ThreadX kernel. */
tx_kernel_enter();
return(0);
}
/* Define what the initial system looks like. */
void tx_application_define(void *first_unused_memory)
{
CHAR *pointer = TX_NULL;
/* Create a byte memory pool from which to allocate the thread stacks. */
tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE);
/* Put system definition stuff in here, e.g. thread creates and other assorted
create information. */
/* Allocate the stack for thread 0. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create the main thread. */
tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,
pointer, DEMO_STACK_SIZE,
1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 1. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create threads 1 and 2. These threads pass information through a ThreadX
message queue. It is also interesting to note that these threads have a time
slice. */
tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1,
pointer, DEMO_STACK_SIZE,
16, 16, 4, TX_AUTO_START);
/* Allocate the stack for thread 2. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2,
pointer, DEMO_STACK_SIZE,
16, 16, 4, TX_AUTO_START);
/* Allocate the stack for thread 3. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore.
An interesting thing here is that both threads share the same instruction area. */
tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 4. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 5. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create thread 5. This thread simply pends on an event flag which will be set
by thread_0. */
tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,
pointer, DEMO_STACK_SIZE,
4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 6. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create threads 6 and 7. These threads compete for a ThreadX mutex. */
tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 7. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the message queue. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
/* Create the message queue shared by threads 1 and 2. */
tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
/* Create the semaphore used by threads 3 and 4. */
tx_semaphore_create(&semaphore_0, "semaphore 0", 1);
/* Create the event flags group used by threads 1 and 5. */
tx_event_flags_create(&event_flags_0, "event flags 0");
/* Create the mutex used by thread 6 and 7 without priority inheritance. */
tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT);
/* Allocate the memory for a small block pool. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
/* Create a block memory pool to allocate a message buffer from. */
tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
/* Allocate a block and release the block memory. */
tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
/* Release the block back to the pool. */
tx_block_release(pointer);
}
/* Define the test threads. */
void thread_0_entry(ULONG thread_input)
{
UINT status;
/* This thread simply sits in while-forever-sleep loop. */
while(1)
{
/* Increment the thread counter. */
thread_0_counter++;
/* Sleep for 10 ticks. */
tx_thread_sleep(10);
/* Set event flag 0 to wakeup thread 5. */
status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR);
/* Check status. */
if (status != TX_SUCCESS)
break;
}
}
void thread_1_entry(ULONG thread_input)
{
UINT status;
/* This thread simply sends messages to a queue shared by thread 2. */
while(1)
{
/* Increment the thread counter. */
thread_1_counter++;
/* Send message to queue 0. */
status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
/* Check completion status. */
if (status != TX_SUCCESS)
break;
/* Increment the message sent. */
thread_1_messages_sent++;
}
}
void thread_2_entry(ULONG thread_input)
{
ULONG received_message;
UINT status;
/* This thread retrieves messages placed on the queue by thread 1. */
while(1)
{
/* Increment the thread counter. */
thread_2_counter++;
/* Retrieve a message from the queue. */
status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER);
/* Check completion status and make sure the message is what we
expected. */
if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
break;
/* Otherwise, all is okay. Increment the received message count. */
thread_2_messages_received++;
}
}
void thread_3_and_4_entry(ULONG thread_input)
{
UINT status;
/* This function is executed from thread 3 and thread 4. As the loop
below shows, these function compete for ownership of semaphore_0. */
while(1)
{
/* Increment the thread counter. */
if (thread_input == 3)
thread_3_counter++;
else
thread_4_counter++;
/* Get the semaphore with suspension. */
status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER);
/* Check status. */
if (status != TX_SUCCESS)
break;
/* Sleep for 2 ticks to hold the semaphore. */
tx_thread_sleep(2);
/* Release the semaphore. */
status = tx_semaphore_put(&semaphore_0);
/* Check status. */
if (status != TX_SUCCESS)
break;
}
}
void thread_5_entry(ULONG thread_input)
{
UINT status;
ULONG actual_flags;
/* This thread simply waits for an event in a forever loop. */
while(1)
{
/* Increment the thread counter. */
thread_5_counter++;
/* Wait for event flag 0. */
status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR,
&actual_flags, TX_WAIT_FOREVER);
/* Check status. */
if ((status != TX_SUCCESS) || (actual_flags != 0x1))
break;
}
}
void thread_6_and_7_entry(ULONG thread_input)
{
UINT status;
/* This function is executed from thread 6 and thread 7. As the loop
below shows, these function compete for ownership of mutex_0. */
while(1)
{
/* Increment the thread counter. */
if (thread_input == 6)
thread_6_counter++;
else
thread_7_counter++;
/* Get the mutex with suspension. */
status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
/* Check status. */
if (status != TX_SUCCESS)
break;
/* Get the mutex again with suspension. This shows
that an owning thread may retrieve the mutex it
owns multiple times. */
status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
/* Check status. */
if (status != TX_SUCCESS)
break;
/* Sleep for 2 ticks to hold the mutex. */
tx_thread_sleep(2);
/* Release the mutex. */
status = tx_mutex_put(&mutex_0);
/* Check status. */
if (status != TX_SUCCESS)
break;
/* Release the mutex again. This will actually
release ownership since it was obtained twice. */
status = tx_mutex_put(&mutex_0);
/* Check status. */
if (status != TX_SUCCESS)
break;
}
}

61
ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/sample_threadx.cmd Normal file
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//
// This is the linker script example (SRV3-style).
// (c) Synopsys, 2013
//
//
//number of exceptions and interrupts
NUMBER_OF_EXCEPTIONS = 16;//it is fixed (16)
NUMBER_OF_INTERRUPTS = 5;//depends on HW configuration
//define Interrupt Vector Table size
IVT_SIZE_ITEMS = (NUMBER_OF_EXCEPTIONS + NUMBER_OF_INTERRUPTS);//the total IVT size (in "items")
IVT_SIZE_BYTES = IVT_SIZE_ITEMS * 4;//in bytes
//define ICCM and DCCM locations
MEMORY {
ICCM: ORIGIN = 0x00000000, LENGTH = 128K
DCCM: ORIGIN = 0x80000000, LENGTH = 128K
}
//define sections and groups
SECTIONS {
GROUP: {
VECT_TABLE_BASE = .;
.ivt (TEXT) : # Interrupt table
{
___ivt1 = .;
* (.ivt)
___ivt2 = .;
// Make the IVT at least IVT_SIZE_BYTES
. += (___ivt2 - ___ivt1 < IVT_SIZE_BYTES) ? (IVT_SIZE_BYTES - (___ivt2 - ___ivt1)) : 0;
}
.ivh (TEXT) : // Interrupt handlers
//TEXT sections
.text? : { *('.text$crt*') }
* (TEXT): {}
//Literals
* (LIT): {}
} > ICCM
GROUP: {
//data sections
.sdata?: {}
.sbss?: {}
*(DATA): {}
*(BSS): {}
//stack
.stack ALIGN(4) SIZE(DEFINED _STACKSIZE?_STACKSIZE:4096): {}
.stack1 ALIGN(4) SIZE(4096): {}
STACK1_END = .;
.stack2 ALIGN(4) SIZE(4096): {}
STACK2_END = .;
//heap (empty)
.heap? ALIGN(4) SIZE(DEFINED _HEAPSIZE?_HEAPSIZE:0): {}
.free_memory: {}
} > DCCM
}

307
ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/tx_initialize_low_level.s Normal file
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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Initialize */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
.equ IRQ_SELECT, 0x40B
;
;
; /* Define section for placement after all linker allocated RAM memory. This
; is used to calculate the first free address that is passed to
; tx_appication_define, soley for the ThreadX application's use. */
;
.section ".free_memory","aw"
.align 4
.global _tx_first_free_address
_tx_first_free_address:
.space 4
;
;
.text
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_initialize_low_level SMP/ARC_HS/MetaWare */
;/* 6.0.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is responsible for any low-level processor */
;/* initialization, including setting up interrupt vectors, setting */
;/* up a periodic timer interrupt source, saving the system stack */
;/* pointer for use in ISR processing later, and finding the first */
;/* available RAM memory address for tx_application_define. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* _tx_initialize_kernel_enter ThreadX entry function */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* */
;/**************************************************************************/
;VOID _tx_initialize_low_level(VOID)
;{
.global _tx_initialize_low_level
.type _tx_initialize_low_level, @function
_tx_initialize_low_level:
;
; /* Save the system stack pointer. */
; _tx_thread_system_stack_ptr[0] = (VOID_PTR) (sp);
;
st sp, [gp, _tx_thread_system_stack_ptr@sda] ; Save system stack pointer
;
;
; /* Pickup the first available memory address. */
;
mov r0, _tx_first_free_address ; Pickup first free memory address
;
; /* Save the first available memory address. */
; _tx_initialize_unused_memory = (VOID_PTR) _end;
;
st r0, [gp, _tx_initialize_unused_memory@sda]
;
;
; /* Done, return to caller. */
;
j_s.d [blink] ; Return to caller
nop
;}
;
;
; /* Define default vector table entries. */
;
.global _tx_memory_error
_tx_memory_error:
flag 1
nop
nop
nop
b _tx_memory_error
.global _tx_instruction_error
_tx_instruction_error:
flag 1
nop
nop
nop
b _tx_instruction_error
.global _tx_ev_machine_check
_tx_ev_machine_check:
flag 1
nop
nop
nop
b _tx_ev_machine_check
.global _tx_ev_tblmiss_inst
_tx_ev_tblmiss_inst:
flag 1
nop
nop
nop
b _tx_ev_tblmiss_inst
.global _tx_ev_tblmiss_data
_tx_ev_tblmiss_data:
flag 1
nop
nop
nop
b _tx_ev_tblmiss_data
.global _tx_ev_protection_viol
_tx_ev_protection_viol:
flag 1
nop
nop
nop
b _tx_ev_protection_viol
.global _tx_ev_privilege_viol
_tx_ev_privilege_viol:
flag 1
nop
nop
nop
b _tx_ev_privilege_viol
.global _tx_ev_software_int
_tx_ev_software_int:
flag 1
nop
nop
nop
b _tx_ev_software_int
.global _tx_ev_trap
_tx_ev_trap:
flag 1
nop
nop
nop
b _tx_ev_trap
.global _tx_ev_extension
_tx_ev_extension:
flag 1
nop
nop
nop
b _tx_ev_extension
.global _tx_ev_divide_by_zero
_tx_ev_divide_by_zero:
flag 1
nop
nop
nop
b _tx_ev_divide_by_zero
.global _tx_ev_dc_error
_tx_ev_dc_error:
flag 1
nop
nop
nop
b _tx_ev_dc_error
.global _tx_ev_maligned
_tx_ev_maligned:
flag 1
nop
nop
nop
b _tx_ev_maligned
.global _tx_unsued_0
_tx_unsued_0:
flag 1
nop
nop
nop
b _tx_unsued_0
.global _tx_unused_1
_tx_unused_1:
flag 1
nop
nop
nop
b _tx_unused_1
.global _tx_timer_0
_tx_timer_0:
;
; /* By default, setup Timer 0 as the ThreadX timer interrupt. */
;
sub sp, sp, 160 ; Allocate an interrupt stack frame
st blink, [sp, 16] ; Save blink (blink must be saved before _tx_thread_context_save)
bl _tx_thread_context_save ; Save interrupt context
;
; /* Call ThreadX timer interrupt processing. */
;
bl.d _tx_timer_interrupt ; Call ThreadX timer processing
sub sp, sp, 16 ; Allocate stack space (delay slot)
add sp, sp, 16 ; Recover stack space
; /* Clear Timer 0 interrupt. */
;
lr r0, [CONTROL0] ; Read control register
and r0, r0, 0xFFFFFFF7 ; Clear timer 0 interrupt bit
sr r0, [CONTROL0] ; Store control register
ld r0, [sp, 16] ; Recover r0
;
b _tx_thread_context_restore ; Restore interrupt context
; flag 1
; nop
; nop
; nop
; b _tx_timer_0
.global _tx_timer_1
_tx_timer_1:
flag 1
nop
nop
nop
b _tx_timer_1
.global _tx_undefined_0
_tx_undefined_0:
flag 1
nop
nop
nop
b _tx_undefined_0
.global _tx_smp_inter_core
_tx_smp_inter_core:
;
; /* Define the inter-core interrupt. */
;
sub sp, sp, 160 ; Allocate an interrupt stack frame
st blink, [sp, 16] ; Save blink (blink must be saved before _tx_thread_context_save)
bl _tx_thread_context_save ; Save interrupt context
;
; /* Call ARC inter-core interrupt processing. */
;
bl.d arc_ici_handler ; Call ARC inter-core processing
sub sp, sp, 16 ; Allocate stack space (delay slot)
add sp, sp, 16 ; Recover stack space
;
b _tx_thread_context_restore ; Restore interrupt context
; flag 1
; nop
; nop
; nop
; b _tx_undefined_1
.global _tx_undefined_2
_tx_undefined_2:
flag 1
nop
nop
nop
b _tx_undefined_2
.end

29
ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/vectors.s Normal file
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.file "vectors.s"
.section .ivt,text
;; This directive forces this section to stay resident even if stripped out by the -zpurgetext linker option
.sectflag .ivt,include
;// handler's name type number name offset in IVT (hex/dec)
.long _start ; exception 0 program entry point offset 0x0 0
.long _tx_memory_error ; exception 1 memory_error offset 0x4 4
.long _tx_instruction_error ; exception 2 instruction_error offset 0x8 8
.long _tx_ev_machine_check ; exception 3 EV_MachineCheck offset 0xC 12
.long _tx_ev_tblmiss_inst ; exception 4 EV_TLBMissI offset 0x10 16
.long _tx_ev_tblmiss_data ; exception 5 EV_TLBMissD offset 0x14 20
.long _tx_ev_protection_viol ; exception 6 EV_ProtV offset 0x18 24
.long _tx_ev_privilege_viol ; exception 7 EV_PrivilegeV offset 0x1C 28
.long _tx_ev_software_int ; exception 8 EV_SWI offset 0x20 32
.long _tx_ev_trap ; exception 9 EV_Trap offset 0x24 36
.long _tx_ev_extension ; exception 10 EV_Extension offset 0x28 40
.long _tx_ev_divide_by_zero ; exception 11 EV_DivZero offset 0x2C 44
.long _tx_ev_dc_error ; exception 12 EV_DCError offset 0x30 48
.long _tx_ev_maligned ; exception 13 EV_Maligned offset 0x34 52
.long _tx_unsued_0 ; exception 14 unused offset 0x38 56
.long _tx_unused_1 ; exception 15 unused offset 0x3C 60
.long _tx_timer_0 ; IRQ 16 Timer 0 offset 0x40 64
.long _tx_timer_1 ; IRQ 17 Timer 1 offset 0x44 68
.long _tx_undefined_0 ; IRQ 18 offset 0x48 72
.long _tx_smp_inter_core ; IRQ 19 offset 0x4C 76
.long _tx_undefined_2 ; IRQ 20 offset 0x50 80

181
ports_smp/arc_hs_smp/metaware/example_build/tx/.cproject Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<cconfiguration id="com.arc.cdt.toolchain.av2hs.libDebugConfig.2063275274">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arc.cdt.toolchain.av2hs.libDebugConfig.2063275274" moduleId="org.eclipse.cdt.core.settings" name="Debug">
<externalSettings>
<externalSetting>
<entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/tx"/>
<entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/tx/Debug"/>
<entry flags="RESOLVED" kind="libraryFile" name="tx" srcPrefixMapping="" srcRootPath=""/>
</externalSetting>
</externalSettings>
<extensions>
<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.MakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="com.arc.cdt.toolchain.ARCLinkerErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="com.arc.cdt.toolchain.ARCCompilerErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="com.arc.cdt.toolchain.ARCAssemblerErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactExtension="a" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.staticLib" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.staticLib,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" errorParsers="com.arc.cdt.toolchain.ARCCompilerErrorParser;com.arc.cdt.toolchain.ARCLinkerErrorParser;com.arc.cdt.toolchain.ARCAssemblerErrorParser;org.eclipse.cdt.core.MakeErrorParser" id="com.arc.cdt.toolchain.av2hs.libDebugConfig.2063275274" name="Debug" parent="com.arc.cdt.toolchain.av2hs.libDebugConfig">
<folderInfo id="com.arc.cdt.toolchain.av2hs.libDebugConfig.2063275274." name="/" resourcePath="">
<toolChain id="com.arc.cdt.toolchain.av2hs.libDebugToolChain.1385404397" superClass="com.arc.cdt.toolchain.av2hs.libDebugToolChain">
<targetPlatform id="hcTargetPlatform.567731658" isAbstract="false" name="Generic platform" superClass="hcTargetPlatform"/>
<builder buildPath="${workspace_loc:/tx}/Debug" id="makeBuilder.1853351928" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="makeBuilder"/>
<tool id="av2hs.lib.debug.libCompiler.2145942775" superClass="av2hs.lib.debug.libCompiler">
<option id="arc.compiler.options.target.version.101453396" isActive="false" name="ARC Core Version" superClass="arc.compiler.options.target.version" value="arc.compiler.options.target.arcv2hs" valueType="enumerated"/>
<option id="arc.compiler.options.bs.8501396" isActive="false" name="Barrel shifter (-Xbs/-Xbarrel_shifter)" superClass="arc.compiler.options.bs" value="true" valueType="boolean"/>
<option id="arc.compiler.options.pc_width.82208768" isActive="false" name="PC register width (-Hpc_width=)" superClass="arc.compiler.options.pc_width" value="com.arc.cdt.toolchain.arc.pcwidth.32" valueType="enumerated"/>
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<extension id="com.arc.cdt.toolchain.ARCCompilerErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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</cproject>

48
ports_smp/arc_hs_smp/metaware/example_build/tx/.project Normal file
View File

@@ -0,0 +1,48 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>tx</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
</natures>
<linkedResources>
<link>
<name>inc_generic</name>
<type>2</type>
<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common_smp/inc</locationURI>
</link>
<link>
<name>inc_port</name>
<type>2</type>
<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/inc</locationURI>
</link>
<link>
<name>src_generic</name>
<type>2</type>
<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common_smp/src</locationURI>
</link>
<link>
<name>src_port</name>
<type>2</type>
<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/src</locationURI>
</link>
</linkedResources>
</projectDescription>

35
ports_smp/arc_hs_smp/metaware/example_build/tx/.settings/language.settings.xml Normal file
View File

@@ -0,0 +1,35 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project>
<configuration id="com.arc.cdt.toolchain.av2hs.libDebugConfig.2063275274" name="Debug">
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider copy-of="extension" id="com.arc.cdt.toolchain.arc.language.settings.providers.MccBuildCommandParser"/>
<provider class="com.arc.cdt.toolchain.arc.language.settings.providers.MccBuiltinSpecsDetector" console="false" env-hash="1695255886827884744" id="com.arc.cdt.toolchain.arc.language.settings.providers.MccBuiltinSpecsDetector" keep-relative-paths="false" name="MetaWare MCC Built-in Compiler Settings" parameter="mcc ${FLAGS} -Hbatchnotmp -Hnoobj &quot;${INPUTS}&quot;" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>
<provider class="com.arc.cdt.toolchain.arc.language.settings.providers.ClangBuildCommandParser" id="com.arc.cdt.toolchain.arc.language.settings.providers.ClangBuildCommandParser" keep-relative-paths="false" name="MetaWare CCAC Build Output Parser" parameter="ccac" prefer-non-shared="true"/>
<provider class="com.arc.cdt.toolchain.arc.language.settings.providers.ClangBuiltinSpecsDetector" console="false" env-hash="1775861871551300168" id="com.arc.cdt.toolchain.arc.language.settings.providers.ClangBuiltinSpecsDetector" keep-relative-paths="false" name="MetaWare CCAC Built-in Compiler Settings" parameter="ccac ${FLAGS} -v -dM -E &quot;${INPUTS}&quot;" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
</extension>
</configuration>
<configuration id="com.arc.cdt.toolchain.av2hs.libReleaseConfig.1202427021" name="Release">
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider copy-of="extension" id="com.arc.cdt.toolchain.arc.language.settings.providers.MccBuildCommandParser"/>
<provider class="com.arc.cdt.toolchain.arc.language.settings.providers.MccBuiltinSpecsDetector" console="false" env-hash="1689441029849768776" id="com.arc.cdt.toolchain.arc.language.settings.providers.MccBuiltinSpecsDetector" keep-relative-paths="false" name="MetaWare MCC Built-in Compiler Settings" parameter="mcc ${FLAGS} -Hbatchnotmp -Hnoobj &quot;${INPUTS}&quot;" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>
<provider copy-of="extension" id="com.arc.cdt.toolchain.arc.language.settings.providers.ClangBuildCommandParser"/>
<provider class="com.arc.cdt.toolchain.arc.language.settings.providers.ClangBuiltinSpecsDetector" console="false" env-hash="1767106799384934664" id="com.arc.cdt.toolchain.arc.language.settings.providers.ClangBuiltinSpecsDetector" keep-relative-paths="false" name="MetaWare CCAC Built-in Compiler Settings" parameter="ccac ${FLAGS} -v -dM -E &quot;${INPUTS}&quot;" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
</extension>
</configuration>
</project>

415
ports_smp/arc_hs_smp/metaware/inc/tx_port.h Normal file
View File

@@ -0,0 +1,415 @@
/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Port Specific */
/** */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/* */
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h SMP/ARC_HS/MetaWare */
/* 6.0.1 */
/* */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This file contains data type definitions that make the ThreadX */
/* real-time kernel function identically on a variety of different */
/* processor architectures. For example, the size or number of bits */
/* in an "int" data type vary between microprocessor architectures and */
/* even C compilers for the same microprocessor. ThreadX does not */
/* directly use native C data types. Instead, ThreadX creates its */
/* own special types that can be mapped to actual data types by this */
/* file to guarantee consistency in the interface and functionality. */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
/* */
/**************************************************************************/
#ifndef TX_PORT_H
#define TX_PORT_H
/* Remove volatile for ThreadX source on the ARC. This is because the ARC
compiler generates different non-cache r/w access when using volatile
that is different from the assembly language access of the same
global variables in ThreadX. */
#ifdef TX_SOURCE_CODE
#define volatile
#else
#ifdef NX_SOURCE_CODE
#define volatile
#else
#ifdef FX_SOURCE_CODE
#define volatile
#else
#ifdef UX_SOURCE_CODE
#define volatile
#endif
#endif
#endif
#endif
/************* Define ThreadX SMP constants. *************/
/* Define the ThreadX SMP maximum number of cores. */
#ifndef TX_THREAD_SMP_MAX_CORES
#define TX_THREAD_SMP_MAX_CORES 2
#endif
/* Define the ThreadX SMP core mask. */
#ifndef TX_THREAD_SMP_CORE_MASK
#define TX_THREAD_SMP_CORE_MASK 0x3 /* Where bit 0 represents Core 0, bit 1 represents Core 1, etc. */
#endif
/* Define INLINE_DECLARE to whitespace for MetaWare compiler. */
#define INLINE_DECLARE
/* Define dynamic number of cores option. When commented out, the number of cores is static. */
/* #define TX_THREAD_SMP_DYNAMIC_CORE_MAX */
/* Define ThreadX SMP initialization macro. */
#define TX_PORT_SPECIFIC_PRE_INITIALIZATION
/* Define ThreadX SMP pre-scheduler initialization. */
#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION
/* Enable the inter-core interrupt logic. */
#define TX_THREAD_SMP_INTER_CORE_INTERRUPT
/* Determine if there is customer-specific wakeup logic needed. */
#ifdef TX_THREAD_SMP_WAKEUP_LOGIC
/* Include customer-specific wakeup code. */
#include "tx_thread_smp_core_wakeup.h"
#else
#ifdef TX_THREAD_SMP_DEFAULT_WAKEUP_LOGIC
/* Default wakeup code. */
#define TX_THREAD_SMP_WAKEUP_LOGIC
#define TX_THREAD_SMP_WAKEUP(i) _tx_thread_smp_core_preempt(i)
#endif
#endif
/* Ensure that the in-line resume/suspend define is not allowed. */
#ifdef TX_INLINE_THREAD_RESUME_SUSPEND
#undef TX_INLINE_THREAD_RESUME_SUSPEND
#endif
/************* End ThreadX SMP constants. *************/
/* Determine if the optional ThreadX user define file should be used. */
#ifdef TX_INCLUDE_USER_DEFINE_FILE
/* Yes, include the user defines in tx_user.h. The defines in this file may
alternately be defined on the command line. */
#include "tx_user.h"
#endif
/* Define compiler library include files. */
#include <stdlib.h>
#include <string.h>
/* Define ThreadX basic types for this port. */
#define VOID void
typedef char CHAR;
typedef unsigned char UCHAR;
typedef int INT;
typedef unsigned int UINT;
typedef long LONG;
typedef unsigned long ULONG;
typedef short SHORT;
typedef unsigned short USHORT;
/* Define the priority levels for ThreadX. Legal values range
from 32 to 1024 and MUST be evenly divisible by 32. */
#ifndef TX_MAX_PRIORITIES
#define TX_MAX_PRIORITIES 32
#endif
/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during
thread creation is less than this value, the thread create call will return an error. */
#ifndef TX_MINIMUM_STACK
#define TX_MINIMUM_STACK 800 /* Minimum stack size for this port */
#endif
/* Define the system timer thread's default stack size and priority. These are only applicable
if TX_TIMER_PROCESS_IN_ISR is not defined. */
#ifndef TX_TIMER_THREAD_STACK_SIZE
#define TX_TIMER_THREAD_STACK_SIZE 2048 /* Default timer thread stack size */
#endif
#ifndef TX_TIMER_THREAD_PRIORITY
#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */
#endif
/* Define various constants for the ThreadX ARC HS port. */
#define TX_INT_ENABLE 0x0000001F /* Enable all interrupts */
#define TX_INT_DISABLE_MASK 0x00000000 /* Disable all interrupts */
/* Define the clock source for trace event entry time stamp. The following two item are port specific.
For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock
source constants would be:
#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024)
#define TX_TRACE_TIME_MASK 0x0000FFFFUL
*/
#ifndef TX_MISRA_ENABLE
#ifndef TX_TRACE_TIME_SOURCE
#define TX_TRACE_TIME_SOURCE _tx_thread_smp_time_get()
#endif
#else
#ifndef TX_TRACE_TIME_SOURCE
ULONG _tx_misra_time_stamp_get(VOID);
#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get()
#endif
#endif
#ifndef TX_TRACE_TIME_MASK
#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL
#endif
/* Define the port specific options for the _tx_build_options variable. This variable indicates
how the ThreadX library was built. */
#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0)
/* Define the in-line initialization constant so that modules with in-line
initialization capabilities can prevent their initialization from being
a function call. */
#ifdef TX_MISRA_ENABLE
#define TX_DISABLE_INLINE
#else
#define TX_INLINE_INITIALIZATION
#endif
/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is
disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack
checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
define is negated, thereby forcing the stack fill which is necessary for the stack checking
logic. */
#ifndef TX_MISRA_ENABLE
#ifdef TX_ENABLE_STACK_CHECKING
#undef TX_DISABLE_STACK_FILLING
#endif
#endif
/* Define the TX_THREAD control block extensions for this port. The main reason
for the multiple macros is so that backward compatibility can be maintained with
existing ThreadX kernel awareness modules. */
#define TX_THREAD_EXTENSION_0 VOID *__mw_threadx_tls; \
int __mw_errnum; \
VOID (*__mw_thread_exit)(struct TX_THREAD_STRUCT *);
#define TX_THREAD_EXTENSION_1
#define TX_THREAD_EXTENSION_2
#define TX_THREAD_EXTENSION_3
/* Define the port extensions of the remaining ThreadX objects. */
#define TX_BLOCK_POOL_EXTENSION
#define TX_BYTE_POOL_EXTENSION
#define TX_EVENT_FLAGS_GROUP_EXTENSION
#define TX_MUTEX_EXTENSION
#define TX_QUEUE_EXTENSION
#define TX_SEMAPHORE_EXTENSION
#define TX_TIMER_EXTENSION
/* Define the user extension field of the thread control block. Nothing
additional is needed for this port so it is defined as white space. */
#ifndef TX_THREAD_USER_EXTENSION
#define TX_THREAD_USER_EXTENSION
#endif
/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete,
tx_thread_shell_entry, and tx_thread_terminate. */
#if __HIGHC__
/* The MetaWare thread safe C/C++ runtime library needs space to
store thread specific information. In addition, a function pointer
is also supplied so that certain thread-specific resources may be
released upon thread termination and/or thread completion. */
#define TX_THREAD_CREATE_EXTENSION(thread_ptr) \
thread_ptr -> __mw_threadx_tls = 0; \
thread_ptr -> __mw_errnum = 0; \
thread_ptr -> __mw_thread_exit = TX_NULL;
#define TX_THREAD_DELETE_EXTENSION(thread_ptr)
#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) \
if (thread_ptr -> __mw_thread_exit) \
(thread_ptr -> __mw_thread_exit) (thread_ptr);
#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) \
if (thread_ptr -> __mw_thread_exit) \
(thread_ptr -> __mw_thread_exit) (thread_ptr);
#else
#define TX_THREAD_CREATE_EXTENSION(thread_ptr)
#define TX_THREAD_DELETE_EXTENSION(thread_ptr)
#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)
#endif
/* Define the ThreadX object creation extensions for the remaining objects. */
#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr)
#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr)
#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr)
#define TX_QUEUE_CREATE_EXTENSION(queue_ptr)
#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr)
#define TX_TIMER_CREATE_EXTENSION(timer_ptr)
/* Define the ThreadX object deletion extensions for the remaining objects. */
#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)
#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)
#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)
#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr)
#define TX_QUEUE_DELETE_EXTENSION(queue_ptr)
#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
/************* Define ThreadX SMP data types and function prototypes. *************/
struct TX_THREAD_STRUCT;
/* Define the ThreadX SMP protection structure. */
typedef struct TX_THREAD_SMP_PROTECT_STRUCT
{
ULONG tx_thread_smp_protect_in_force;
struct TX_THREAD_STRUCT *
tx_thread_smp_protect_thread;
ULONG tx_thread_smp_protect_core;
ULONG tx_thread_smp_protect_count;
/* Implementation specific information follows. */
ULONG tx_thread_smp_protect_get_caller;
ULONG tx_thread_smp_protect_status32;
ULONG tx_thread_smp_protect_release_caller;
} TX_THREAD_SMP_PROTECT;
/* Define ThreadX interrupt lockout and restore macros for protection on
access of critical kernel information. The restore interrupt macro must
restore the interrupt posture of the running thread prior to the value
present prior to the disable macro. In most cases, the save area macro
is used to define a local function save area for the disable and restore
macros. */
#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save;
#define TX_DISABLE interrupt_save = _tx_thread_smp_protect();
#define TX_RESTORE _tx_thread_smp_unprotect(interrupt_save);
/************* End ThreadX SMP data type and function prototype definitions. *************/
/* Define the interrupt lockout macros for each ThreadX object. */
#define TX_BLOCK_POOL_DISABLE TX_DISABLE
#define TX_BYTE_POOL_DISABLE TX_DISABLE
#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE
#define TX_MUTEX_DISABLE TX_DISABLE
#define TX_QUEUE_DISABLE TX_DISABLE
#define TX_SEMAPHORE_DISABLE TX_DISABLE
/* Define the version ID of ThreadX. This may be utilized by the application. */
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/ARC_HS/MetaWare Version 6.0.1 *";
#else
extern CHAR _tx_version_id[];
#endif
#endif

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Microsoft's Azure RTOS ThreadX SMP for ARC HS
Using the MetaWare Tools
1. Open the ThreadX SMP Workspace
In order to build the ThreadX SMP library and the ThreadX SMP demonstration
first load the Azure RTOS Workspace, which is located inside the "example_build"
directory.
2. Building the ThreadX SMP run-time Library
Building the ThreadX SMP library is easy; simply select the ThreadX library project
file "tx" and then select the build button. You should now observe the compilation
and assembly of the ThreadX SMP library. This project build produces the ThreadX SMP
library file tx.a.
3. Demonstration System
The ThreadX demonstration is designed to execute under the MetaWare ARC HS SMP
simulation. The instructions that follow describe how to get the ThreadX SMP
demonstration running.
Building the demonstration is easy; simply select the demonstration project file
"sample_threadx." At this point, select the build button and observe the
compilation, assembly, and linkage of the ThreadX SMP demonstration application.
After the demonstration is built, execute the "run_threadx_smp_demo.bat" batch file
to invoke and load the ThreadX SMP demonstration.
You are now ready to execute the ThreadX demonstration system. Select
breakpoints and data watches to observe the execution of the sample_threadx.c
SMP application.
4. System Initialization
The system entry point using the MetaWare tools is at the label _start.
This is defined within the crt1.s file supplied by MetaWare. In addition,
this is where all static and global preset C variable initialization
processing is called from.
After the MetaWare startup function completes, ThreadX initialization is
called. The main initialization function is _tx_initialize_low_level and
is located in the file tx_initialize_low_level.s. This function is
responsible for setting up various system data structures, and interrupt
vectors.
By default free memory is assumed to start at the section .free_memory
which is referenced in tx_initialize_low_level.s and located in the
linker control file after all the linker defined RAM addresses. This is
the address passed to the application definition function, tx_application_define.
5. Register Usage and Stack Frames
The ARC compiler assumes that registers r0-r12 are scratch registers for
each function. All other registers used by a C function must be preserved
by the function. ThreadX takes advantage of this in situations where a
context switch happens as a result of making a ThreadX service call (which
is itself a C function). In such cases, the saved context of a thread is
only the non-scratch registers.
The following defines the saved context stack frames for context switches
that occur as a result of interrupt handling or from thread-level API calls.
All suspended threads have one of these two types of stack frames. The top
of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the
associated thread control block TX_THREAD.
Offset Interrupted Stack Frame Non-Interrupt Stack Frame
0x00 1 0
0x04 LP_START blink
0x08 LP_END fp
0x0C LP_COUNT r26
0x10 blink r25
0x14 ilink r24
0x18 fp r23
0x1C r26 r22
0x20 r25 r21
0x24 r24 r20
0x28 r23 r19
0x2C r22 r18
0x30 r21 r17
0x34 r20 r16
0x38 r19 r15
0x3C r18 r14
0x40 r17 r13
0x44 r16 STATUS32
0x48 r15 r30
0x4C r14
0x50 r13
0x54 r12
0x58 r11
0x5C r10
0x60 r9
0x64 r8
0x68 r7
0x6C r6
0x70 r5
0x74 r4
0x78 r3
0x7C r2
0x80 r1
0x84 r0
0x88 r30
0x8C r58 - ACCL (optional)
0x90 r59 - ACCH (optional)
0x94 reserved
0x98 reserved
0x9C bta
0xA0 point of interrupt
0xA4 STATUS32
6. Improving Performance
The distribution version of ThreadX is built without any compiler
optimizations. This makes it easy to debug because you can trace or set
breakpoints inside of ThreadX itself. Of course, this costs some
performance. To make it run faster, you can change the build_threadx.bat
file to remove the -g option and enable all compiler optimizations.
In addition, you can eliminate the ThreadX basic API error checking by
compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING
defined.
7. Interrupt Handling
ThreadX provides complete and high-performance interrupt handling for the
ARC HS processor, including support for software interrupts and fast
hardware interrupts.
7.1 Software Interrupt Handling
The following template should be used for software interrupts
managed by ThreadX:
.global _tx_interrupt_x
_tx_interrupt_x:
sub sp, sp, 160 ; Allocate an interrupt stack frame
st blink, [sp, 16] ; Save blink (blink must be saved before _tx_thread_context_save)
bl _tx_thread_context_save ; Save interrupt context
;
; /* Application ISR processing goes here! Your ISR can be written in
; assembly language or in C. If it is written in C, you must allocate
; 16 bytes of stack space before it is called. This must also be
; recovered once your C ISR return. An example of this is shown below.
;
; If the ISR is written in assembly language, only the compiler scratch
; registers are available for use without saving/restoring (r0-r12).
; If use of additional registers are required they must be saved and
; restored. */
;
bl.d your_ISR_written_in_C ; Call an ISR written in C
sub sp, sp, 16 ; Allocate stack space (delay slot)
add sp, sp, 16 ; Recover stack space
;
b _tx_thread_context_restore ; Restore interrupt context
The application handles interrupts directly, which necessitates all register
preservation by the application's ISR. ISRs that do not use the ThreadX
_tx_thread_context_save and _tx_thread_context_restore routines are not
allowed access to the ThreadX API. In addition, custom application ISRs
should be higher priority than all ThreadX-managed ISRs.
8. ThreadX Timer Interrupt
ThreadX SMP requires a periodic interrupt source to manage all time-slicing,
thread sleeps, timeouts, and application timers. Without such a timer
interrupt source, these services are not functional but the remainder of
ThreadX will still run.
By default, the ThreadX timer interrupt is mapped to the ARC HS auxiliary
timer 0, which generates low priority interrupts on interrupt vector 16.
It is easy to change the timer interrupt source and priority by changing the
setup code in tx_initialize_low_level.s. In addition, the ThreadX SMP timer
is mapped to core 0. To change to another core, please edit arc.c and
_tx_timer_interrupt.s. Only one core should be used as the ThreadX SMP
periodic timer interrupt source.
9. Revision History
For generic code revision information, please refer to the readme_threadx_generic.txt
file, which is included in your distribution. The following details the revision
information associated with this specific port of ThreadX:
06/30/2020 Initial ThreadX 6.0.1 for ARC HS using MetaWare tools.
Copyright(c) 1996-2020 Microsoft Corporation
https://azure.com/rtos

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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
.equ BTA, 0x412
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_restore SMP/ARC_HS/MetaWare */
;/* 6.0.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function restores the interrupt context if it is processing a */
;/* nested interrupt. If not, it returns to the interrupt thread if no */
;/* preemption is necessary. Otherwise, if preemption is necessary or */
;/* if no thread was running, the function returns to the scheduler. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* _tx_thread_schedule Thread scheduling routine */
;/* */
;/* CALLED BY */
;/* */
;/* ISRs Interrupt Service Routines */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_context_restore(VOID)
;{
.global _tx_thread_context_restore
.type _tx_thread_context_restore, @function
_tx_thread_context_restore:
;
; /* Note: it is assumed that the stack pointer is in the same position now as
; it was after the last context save call. */
;
; /* Lockout interrupts. */
;
clri ; Disable interrupts
nop ; Delay for interrupts to really be disabled
.ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
;
; /* Call the ISR exit function to indicate an ISR is complete. */
;
bl.d _tx_execution_isr_exit ; Call the ISR exit function
sub sp, sp, 16 ; ..allocating some space on the stack
add sp, sp, 16 ; Recover the stack space
.endif
;
; /* Determine if interrupts are nested. */
; if (--_tx_thread_system_state)
; {
;
lr r3, [IDENTITY] ; Pickup core ID
xbfu r3, r3, 8, 8 ; Shift down and isolate core ID
.ifndef TX_ZERO_BASED_CORE_ID
sub r3, r3, 1 ; Subtract 1 to make 0-based
.endif
asl r3, r3, 2 ; Build index into core arrays
mov r0, _tx_thread_system_state ; Build address of system state
add r1, r0, r3 ;
ld r0, [r1] ; Pickup system state
sub r0, r0, 1 ; Decrement the system state
st r0, [r1] ; Store the new system state
breq r0, 0, __tx_thread_not_nested_restore ; If zero, not a nested interrupt
;
; /* Interrupts are nested. */
;
; /* Just recover the saved registers and return to the point of
; interrupt. */
;
__tx_thread_nested_restore:
.ifndef TX_DISABLE_LP
ld r0, [sp, 4] ; Recover LP_START
sr r0, [LP_START] ; Restore LP_START
ld r4, [sp, 8] ; Recover LP_END
sr r4, [LP_END] ; Restore LP_END
ld r2, [sp, 12] ; Recover LP_COUNT
mov LP_COUNT, r2
.endif
ld r2, [sp, 156] ; Pickup BTA
sr r2, [BTA] ; Recover BTA
.ifdef TX_ENABLE_ACC
ld r58, [sp, 140] ; Recover r58
ld r59, [sp, 144] ; Recover r59
.endif
ld blink, [sp, 16] ; Recover blink
ld r12, [sp, 84] ; Recover r12
ld r11, [sp, 88] ; Recover r11
ld r10, [sp, 92] ; Recover r10
ld r9, [sp, 96] ; Recover r9
ld r8, [sp, 100] ; Recover r8
ld r7, [sp, 104] ; Recover r7
ld r6, [sp, 108] ; Recover r6
ld r5, [sp, 112] ; Recover r5
ld r4, [sp, 116] ; Recover r4
ld r3, [sp, 120] ; Recover r3
ld r2, [sp, 124] ; Recover r2
ld r1, [sp, 128] ; Recover r1
ld r0, [sp, 132] ; Recover r0
add sp, sp, 160 ; Recover interrupt stack frame
rtie ; Return from interrupt
;
;
; }
__tx_thread_not_nested_restore:
;
; /* Determine if a thread was interrupted and no preemption is required. */
; else if (((_tx_thread_current_ptr[core]) && (_tx_thread_current_ptr[core] == _tx_thread_execute_ptr[core])
; || (_tx_thread_preempt_disable))
; {
;
mov r1, _tx_thread_current_ptr ; Build current thread pointer address
add r1, r1, r3 ;
ld r0, [r1] ; Pickup current thread pointer
mov r2, _tx_thread_smp_protection ; Build protection address
sub.f 0, r0, 0 ; Set condition codes
beq.d __tx_thread_idle_system_restore ; If NULL, idle system was interrupted
lr r4, [AUX_IRQ_ACT] ; Pickup the interrupt active register
neg r5, r4 ; Negate
and r5, r4, r5 ; See if there are any other interrupts present
brne r4, r5, __tx_thread_no_preempt_restore ; If more interrupts, just return to the point of interrupt
mov r4, _tx_thread_execute_ptr ; Build address of next thread to execute for this core
add r4, r4, r3 ;
ld r4, [r4] ; Pickup next thread to execute
ld r2, [r2, 8] ; Pickup core that has protection
breq r0, r4, __tx_thread_no_preempt_restore ; If equal, simply restore executing thread
ld r5, [gp, _tx_thread_preempt_disable@sda] ; Pickup preempt disable flag
asr r4, r3, 2 ; Shift core index back down for core ID
brne r2, r4, __tx_thread_preempt_restore ; If the core doesn't have protection, preempt thread without looking at preempt disable flag
breq r5, 0, __tx_thread_preempt_restore ; If preempt disable not set, preempt executing thread
;
;
__tx_thread_no_preempt_restore:
;
; /* Restore interrupted thread or ISR. */
;
; /* Pickup the saved stack pointer. */
; sp = _tx_thread_current_ptr[core] -> tx_thread_stack_ptr;
;
; /* Recover the saved context and return to the point of interrupt. */
;
ld sp, [r0, 8] ; Switch back to thread's stack
.ifndef TX_DISABLE_LP
ld r0, [sp, 4] ; Recover LP_START
sr r0, [LP_START] ; Restore LP_START
ld r4, [sp, 8] ; Recover LP_END
sr r4, [LP_END] ; Restore LP_END
ld r2, [sp, 12] ; Recover LP_COUNT
mov LP_COUNT, r2
.endif
ld r2, [sp, 156] ; Pickup BTA
sr r2, [BTA] ; Recover BTA
.ifdef TX_ENABLE_ACC
ld r58, [sp, 140] ; Recover r58
ld r59, [sp, 144] ; Recover r59
.endif
ld blink, [sp, 16] ; Recover blink
ld r12, [sp, 84] ; Recover r12
ld r11, [sp, 88] ; Recover r11
ld r10, [sp, 92] ; Recover r10
ld r9, [sp, 96] ; Recover r9
ld r8, [sp, 100] ; Recover r8
ld r7, [sp, 104] ; Recover r7
ld r6, [sp, 108] ; Recover r6
ld r5, [sp, 112] ; Recover r5
ld r4, [sp, 116] ; Recover r4
ld r3, [sp, 120] ; Recover r3
ld r2, [sp, 124] ; Recover r2
ld r1, [sp, 128] ; Recover r1
ld r0, [sp, 132] ; Recover r0
add sp, sp, 160 ; Recover interrupt stack frame
rtie ; Return from interrupt
;
; }
; else
; {
__tx_thread_preempt_restore:
;
ld r7, [r0, 8] ; Pickup stack pointer
mov r6, 1 ; Build interrupt stack type
st r6, [r7, 0] ; Setup interrupt stack type
st fp, [r7, 24] ; Save fp
st gp, [r7, 28] ; Save gp
st r25, [r7, 32] ; Save r25
st r24, [r7, 36] ; Save r24
st r23, [r7, 40] ; Save r23
st r22, [r7, 44] ; Save r22
st r21, [r7, 48] ; Save r21
st r20, [r7, 52] ; Save r20
st r19, [r7, 56] ; Save r19
st r18, [r7, 60] ; Save r18
st r17, [r7, 64] ; Save r17
st r16, [r7, 68] ; Save r16
st r15, [r7, 72] ; Save r15
st r14, [r7, 76] ; Save r14
st r13, [r7, 80] ; Save r13
st r30, [r7, 136] ; Save r30
__tx_preempt_save_done:
;
; /* Save the remaining time-slice and disable it. */
; if (_tx_timer_time_slice)
; {
;
mov r5, _tx_timer_time_slice ; Build time-slice address
add r5, r5, r3 ;
ld r2, [r5] ; Pickup time-slice contents
mov r7, 0 ; Build clear/NULL value
breq r2, 0, __tx_thread_dont_save_ts ; No time-slice, don't need to save it
;
; _tx_thread_current_ptr[core] -> tx_thread_time_slice = _tx_timer_time_slice[core];
; _tx_timer_time_slice = 0;
;
st r2, [r0, 24] ; If set, save remaining time-slice
st r7, [r5] ; If set, clear time slice
;
; }
__tx_thread_dont_save_ts:
;
;
; /* Clear the current thread pointer. */
; _tx_thread_current_ptr[core] = TX_NULL;
;
st r7, [r1] ; Set current thread ptr to NULL
;
; /* Set bit indicating this thread is ready for execution. */
;
dmb 3 ; Data memory barrier
st 1, [r0, 164] ; Set ready bit
sub sp, sp, 8 ; Allocate a small stack frame on the system stack
lr r0, [STATUS32] ; Pickup STATUS32
st r0, [sp, 4] ; Place on stack
mov r0, _tx_thread_schedule ; Build address of scheduler
st r0, [sp, 0] ; Write over the point of interrupt
rtie ; Return from interrupt to scheduler
;
; }
;
; /* Return to the scheduler. */
; _tx_thread_schedule();
;
__tx_thread_idle_system_restore:
lr r4, [AUX_IRQ_ACT] ; Pickup the interrupt active register
neg r5, r4 ; Negate
and r5, r4, r5 ; See if there are any other interrupts present
sub.f 0, r4, r5 ; Set condition codes
bne __tx_thread_nested_restore ; If more interrupts, just return to the point of interrupt
lr r0, [STATUS32] ; Pickup STATUS32
st r0, [sp, 4] ; Place on stack
mov r0, _tx_thread_schedule ; Build address of scheduler
st r0, [sp, 0] ; Write over the point of interrupt
rtie ; Return from interrupt to scheduler
;
;}
.end

254
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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
.equ BTA, 0x412
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_context_save SMP/ARC_HS/MetaWare */
;/* 6.0.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function saves the context of an executing thread in the */
;/* beginning of interrupt processing. The function also ensures that */
;/* the system stack is used upon return to the calling ISR. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* ISRs */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_context_save(VOID)
;{
.global _tx_thread_context_save
.type _tx_thread_context_save, @function
_tx_thread_context_save:
;
; /* Upon entry to this routine, it is assumed that an interrupt stack frame
; has already been allocated, and the interrupted blink register is already saved. */
;
clri ; Disable interrupts
st r1, [sp, 128] ; Save r1
st r0, [sp, 132] ; Save r0
st r3, [sp, 120] ; Save r3
st r2, [sp, 124] ; Save r2
;
; /* Check for a nested interrupt condition. */
; if (_tx_thread_system_state++)
; {
;
lr r3, [IDENTITY] ; Pickup core ID
xbfu r3, r3, 8, 8 ; Shift down and isolate core ID
.ifndef TX_ZERO_BASED_CORE_ID
sub r3, r3, 1 ; Subtract 1 to make 0-based
.endif
asl r3, r3, 2 ; Build index into core arrays
mov r0, _tx_thread_system_state ; Build address of system state
add r1, r0, r3 ;
ld r0, [r1] ; Pickup system state
breq r0, 0, __tx_thread_not_nested_save ; If 0, we are not in a nested
; condition
;
; /* Nested interrupt condition. */
;
add r0, r0, 1 ; Increment the nested interrupt count
st r0, [r1] ; Update system state
;
; /* Save the rest of the scratch registers on the stack and return to the
; calling ISR. */
;
__tx_thread_nested_save: ; Label is for special nested interrupt case from idle system save below
st r12, [sp, 84] ; Save r12
st r11, [sp, 88] ; Save r11
st r10, [sp, 92] ; Save r10
st r9, [sp, 96] ; Save r9
st r8, [sp, 100] ; Save r8
st r7, [sp, 104] ; Save r7
st r6, [sp, 108] ; Save r6
st r5, [sp, 112] ; Save r5
st r4, [sp, 116] ; Save r6
lr r10, [LP_START] ; Pickup LP_START
lr r9, [LP_END] ; Pickup LP_END
st LP_COUNT, [sp, 12] ; Save LP_COUNT
st r10, [sp, 4] ; Save LP_START
st r9, [sp, 8] ; Save LP_END
.ifdef TX_ENABLE_ACC
st r58, [sp, 140] ; Save r58
st r59, [sp, 144] ; Save r59
.endif
lr r0, [BTA] ; Pickup BTA
st r0, [sp, 156] ; Save BTA
;
; /* Return to the ISR. */
;
.ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
;
; /* Call the ISR enter function to indicate an ISR is executing. */
;
sub sp, sp, 32 ; Allocating some space on the stack
st blink, [sp, 16] ; Save blink
bl.d _tx_execution_isr_enter ; Call the ISR enter function
nop ; Delay slot
ld blink, [sp, 16] ; Recover blink
add sp, sp, 32 ; Recover the stack space
.endif
;
j.d [blink] ; Return to Level 1 ISR
st ilink, [sp, 20] ; Save ilink
;
__tx_thread_not_nested_save:
; }
;
; /* Otherwise, not nested, check to see if a thread was running. */
; else if (_tx_thread_current_ptr[core])
; {
;
add r0, r0, 1 ; Increment the nested interrupt count
st r0, [r1] ; Update system state
mov r2, _tx_thread_current_ptr ; Build address of current thread pointer
add r2, r2, r3 ;
ld r1, [r2] ; Pickup current thread pointer
st r12, [sp, 84] ; Save r12
st r11, [sp, 88] ; Save r11
breq r1, 0, __tx_thread_idle_system_save ; If no thread is running, idle system was
; interrupted.
;
; /* Save minimal context of interrupted thread. */
;
st r10, [sp, 92] ; Save r10
st r9, [sp, 96] ; Save r9
st r8, [sp, 100] ; Save r8
st r7, [sp, 104] ; Save r7
st r6, [sp, 108] ; Save r6
st r5, [sp, 112] ; Save r5
st r4, [sp, 116] ; Save r4
lr r10, [LP_START] ; Pickup LP_START
lr r9, [LP_END] ; Pickup LP_END
st LP_COUNT, [sp, 12] ; Save LP_COUNT
st r10, [sp, 4] ; Save LP_START
st r9, [sp, 8] ; Save LP_END
st ilink, [sp, 20] ; Save ilink
.ifdef TX_ENABLE_ACC
st r58, [sp, 140] ; Save r58
st r59, [sp, 144] ; Save r59
.endif
lr r0, [BTA] ; Pickup BTA
st r0, [sp, 156] ; Save BTA
;
; /* Save the current stack pointer in the thread's control block. */
; _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp;
;
st sp, [r1, 8] ; Save thread's stack pointer
.ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
;
; /* Call the ISR enter function to indicate an ISR is executing. */
;
sub sp, sp, 32 ; Allocating some space on the stack
st blink, [sp, 16] ; Save blink
bl.d _tx_execution_isr_enter ; Call the ISR enter function
nop ; Delay slot
ld blink, [sp, 16] ; Recover blink
add sp, sp, 32 ; Recover the stack space
.endif
;
; /* Switch to the system stack. */
; sp = _tx_thread_system_stack_ptr[core];
;
mov r1, _tx_thread_system_stack_ptr ; Build address of system stack pointer
add r1, r1, r3 ;
j_s.d [blink] ; Return to calling ISR
ld sp, [r1] ; Switch to system stack
;
; }
; else
; {
;
__tx_thread_idle_system_save:
;
; /* Interrupt occurred in the scheduling loop. */
;
.ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
;
; /* Call the ISR enter function to indicate an ISR is executing. */
;
sub sp, sp, 32 ; Allocating some space on the stack
st blink, [sp, 16] ; Save blink
bl.d _tx_execution_isr_enter ; Call the ISR enter function
nop ; Delay slot
ld blink, [sp, 16] ; Recover blink
add sp, sp, 32 ; Recover the stack space
.endif
;
; /* See if we have a special nesting condition. This happens when the higher priority
; interrupt occurs before the nested interrupt logic is valid. */
;
lr r0, [AUX_IRQ_ACT] ; Pickup the interrupt active register
neg r1, r0 ; Negate
and r1, r0, r1 ; See if there are any other interrupts present
brne r0, r1, __tx_thread_nested_save ; If more interrupts, go into the nested interrupt save logic
;
; /* Not much to do here, just adjust the stack pointer, and return to
; ISR processing. */
;
j_s.d [blink] ; Return to ISR
add sp, sp, 160 ; Recover stack space
;
; }
;}
.end

87
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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;#define TX_SOURCE_CODE
;
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;
;
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_interrupt_control SMP/ARC_HS/MetaWare */
;/* 6.0.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is responsible for changing the interrupt lockout */
;/* posture of the system. */
;/* */
;/* INPUT */
;/* */
;/* new_posture New interrupt lockout posture */
;/* */
;/* OUTPUT */
;/* */
;/* old_posture Old interrupt lockout posture */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* Application Code */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* */
;/**************************************************************************/
;UINT _tx_thread_interrupt_control(UINT new_posture)
;{
.global _tx_thread_interrupt_control
.type _tx_thread_interrupt_control, @function
_tx_thread_interrupt_control:
;
; /* Pickup current interrupt lockout posture. */
;
clri r1 ; Get current interrupt state
;
; /* Apply the new interrupt posture. */
;
seti r0 ; Set desired interrupt state
j_s.d [blink] ; Return to caller with delay slot
mov r0, r1 ; Return previous mask value. Return value is TX_INT_DISABLE or TX_INT_ENABLE.
;
;}
.end

297
ports_smp/arc_hs_smp/metaware/src/tx_thread_schedule.s Normal file
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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;
;
.equ BTA, 0x412
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h"
;
;
; /* Define the lock for the ARC simulator workaround. The ARC HS SMP
; simulator does not execute cores in a lock-step fashion, i.e., a
; core can stall for many cycles while the other core executes. This
; does not happen on actual hardware and thus the need for a schedule
; lock is not required since: 1) ThreadX SMP will not load the same
; thread into two places on the _tx_thread_execute_list, and moving
; a thread from one entry on the _tx_thread_execute_list to another
; is more than the 5 instructions executed between examination of the
; the _tx_thread_execute_list thread and clearing its ready bit in
; preparation for scheduling. */
;
.ifdef TX_ARC_SIMULATOR_WORKAROUND
.globl _tx_thread_schedule_lock
.size _tx_thread_schedule_lock, 4
.type _tx_thread_schedule_lock,@object
_tx_thread_schedule_lock:
.word 0
.endif
;
;
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule SMP/ARC_HS/MetaWare */
;/* 6.0.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function waits for a thread control block pointer to appear in */
;/* the _tx_thread_execute_ptr array. Once a thread pointer appears */
;/* in the variable, the corresponding thread is resumed. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* _tx_initialize_kernel_enter ThreadX entry function */
;/* _tx_thread_system_return Return to system from thread */
;/* _tx_thread_context_restore Restore thread's context */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
;{
.global _tx_thread_schedule_restart
_tx_thread_schedule_restart:
.ifdef TX_ARC_SIMULATOR_WORKAROUND
mov r7, _tx_thread_schedule_lock
dmb 3
mov r3, 0
st r3, [r7]
dmb 3
.endif
.global _tx_thread_schedule
.type _tx_thread_schedule, @function
_tx_thread_schedule:
;
;
; /* Enable interrupts. */
;
mov r0, 0x1F ; Build enable interrupt value
seti r0 ; Enable interrupts
;
; /* Wait for a thread to execute. */
; do
; {
;
lr r1, [IDENTITY] ; Pickup core ID
xbfu r1, r1, 8, 8 ; Shift down and isolate core ID
.ifndef TX_ZERO_BASED_CORE_ID
sub r1, r1, 1 ; Subtract 1 to make 0-based
.endif
asl r4, r1, 2 ; Build index into core arrays
mov r7, _tx_thread_execute_ptr ; Pickup base of the execute thread pointer
add r7, r7, r4 ; Build address of current thread pointer
__tx_thread_schedule_loop:
;
clri ; Lockout interrupts
nop ; Delay for interrupts to really be disabled
.ifdef TX_ARC_SIMULATOR_WORKAROUND
mov r0, _tx_thread_schedule_lock
llock r5, [r0]
breq r5, 0, _continue
b _tx_thread_schedule
_continue:
add r5, r1, 1
scond r5, [r0]
beq_s _got_lock
b _tx_thread_schedule
_got_lock:
.endif
ld r0, [r7] ; Pickup next thread to execute
breq r0, 0, _tx_thread_schedule_restart ; If NULL, keep looking
;
; }
; while(_tx_thread_execute_ptr[core] == TX_NULL);
;
;
; /* Now make sure the thread's ready bit is set. */
;
ld r5, [r0, 164] ; Pickup the ready bit for this thread to see if it can be executed
breq r5, 0, _tx_thread_schedule_restart ; If not set, start over
st 0, [r0, 164] ; Clear the ready bit now that this thread is being executed
dmb 3 ; Data memory barrier
.ifdef TX_ARC_SIMULATOR_WORKAROUND
mov r7, _tx_thread_schedule_lock
dmb 3
mov r3, 0
st r3, [r7]
dmb 3
.endif
;
; /* Yes! We have a thread to execute - transfer control to it. */
;
; /* Setup the current thread pointer. */
; _tx_thread_current_ptr[core] = _tx_thread_execute_ptr[core];
;
mov r7, _tx_thread_current_ptr ; Build address of current thread pointer
add r7, r7, r4 ;
st r0, [r7] ; Setup current thread pointer
;
; /* Increment the run count for this thread. */
; _tx_thread_current_ptr[core] -> tx_thread_run_count++;
;
ld r3, [r0, 4] ; Pickup run counter
ld r5, [r0, 24] ; Pickup time-slice for this thread
add r3, r3, 1 ; Increment run counter
st r3, [r0, 4] ; Store the new run counter
;
; /* Setup time-slice, if present. */
; _tx_timer_time_slice[core] = _tx_thread_current_ptr -> tx_thread_time_slice;
;
mov r6, _tx_timer_time_slice ; Build address of time-slice for this core
add r6, r6, r4 ;
st r5, [r6] ; Setup time-slice
;
.ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
;
; /* Call the thread entry function to indicate the thread is executing. */
;
mov r13, r0 ; Save thread control block pointer
bl.d _tx_execution_thread_enter ; Call the thread execution enter function
sub sp, sp, 16 ; ..allocating some space on the stack
add sp, sp, 16 ; Recover the stack space
mov r0, r13 ; Recover thread control block pointer
.endif
;
; /* Switch to the thread's stack. */
; sp = _tx_thread_execute_ptr[core] -> tx_thread_stack_ptr;
;
ld sp, [r0, 8] ; Switch to thread's stack
;
; /* Determine if an interrupt frame or a synchronous task suspension frame
; is present. */
;
ld r1, [sp, 0] ; Pickup the stack type
brne r1, 0, __tx_thread_schedule_int_ret ; Compare to solicited stack type. If not, thread was interrupted
ld blink, [sp, 4] ; Recover blink
ld fp, [sp, 8] ; Recover fp
ld gp, [sp, 12] ; Recover gp
ld r25, [sp, 16] ; Recover r25
ld r24, [sp, 20] ; Recover r24
ld r23, [sp, 24] ; Recover r23
ld r22, [sp, 28] ; Recover r22
ld r21, [sp, 32] ; Recover r21
ld r20, [sp, 36] ; Recover r20
ld r19, [sp, 40] ; Recover r19
ld r18, [sp, 44] ; Recover r18
ld r17, [sp, 48] ; Recover r17
ld r16, [sp, 52] ; Recover r16
ld r15, [sp, 56] ; Recover r15
ld r14, [sp, 60] ; Recover r14
ld r13, [sp, 64] ; Recover r13
ld r1, [sp, 68] ; Pickup status32
ld r30, [sp, 72] ; Recover r30
add sp, sp, 76 ; Recover solicited stack frame
j_s.d [blink] ; Return to thread and restore flags
seti r1 ; Recover STATUS32
;
__tx_thread_schedule_int_ret:
;
mov r0, 0x2 ; Pretend level 1 interrupt is returning
sr r0, [AUX_IRQ_ACT] ;
.ifndef TX_DISABLE_LP
ld r0, [sp, 4] ; Recover LP_START
sr r0, [LP_START] ; Restore LP_START
ld r1, [sp, 8] ; Recover LP_END
sr r1, [LP_END] ; Restore LP_END
ld r2, [sp, 12] ; Recover LP_COUNT
mov LP_COUNT, r2
.endif
ld r0, [sp, 156] ; Pickup saved BTA
sr r0, [BTA] ; Recover BTA
ld blink, [sp, 16] ; Recover blink
ld ilink, [sp, 20] ; Recover ilink
ld fp, [sp, 24] ; Recover fp
ld gp, [sp, 28] ; Recover gp
ld r25, [sp, 32] ; Recover r25
ld r24, [sp, 36] ; Recover r24
ld r23, [sp, 40] ; Recover r23
ld r22, [sp, 44] ; Recover r22
ld r21, [sp, 48] ; Recover r21
ld r20, [sp, 52] ; Recover r20
ld r19, [sp, 56] ; Recover r19
ld r18, [sp, 60] ; Recover r18
ld r17, [sp, 64] ; Recover r17
ld r16, [sp, 68] ; Recover r16
ld r15, [sp, 72] ; Recover r15
ld r14, [sp, 76] ; Recover r14
ld r13, [sp, 80] ; Recover r13
ld r12, [sp, 84] ; Recover r12
ld r11, [sp, 88] ; Recover r11
ld r10, [sp, 92] ; Recover r10
ld r9, [sp, 96] ; Recover r9
ld r8, [sp, 100] ; Recover r8
ld r7, [sp, 104] ; Recover r7
ld r6, [sp, 108] ; Recover r6
ld r5, [sp, 112] ; Recover r5
ld r4, [sp, 116] ; Recover r4
ld r3, [sp, 120] ; Recover r3
ld r2, [sp, 124] ; Recover r2
ld r1, [sp, 128] ; Recover r1
ld r0, [sp, 132] ; Recover r0
ld r30, [sp, 136] ; Recover r30
.ifdef TX_ENABLE_ACC
ld r58, [sp, 140] ; Recover r58
ld r59, [sp, 144] ; Recover r59
.endif
add sp, sp, 160 ; Recover interrupt stack frame
rtie ; Return to point of interrupt
;
;}
;
.end

86
ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_core_get.s Normal file
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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread - Low Level SMP Support */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;#define TX_THREAD_SMP_SOURCE_CODE
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h" */
;
;
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_smp_core_get SMP/ARC_HS/MetaWare */
;/* 6.0.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function gets the currently running core number and returns it.*/
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* Core ID */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* ThreadX Source */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* */
;/**************************************************************************/
.global _tx_thread_smp_core_get
.type _tx_thread_smp_core_get, @function
_tx_thread_smp_core_get:
;
; /* Pickup core ID. */
;
lr r0, [IDENTITY] ; Pickup core ID
xbfu r0, r0, 8, 8 ; Shift down and isolate core ID
j_s.d [blink] ; Return to caller with delay slot
.ifndef TX_ZERO_BASED_CORE_ID
sub r0, r0, 1 ; Subtract 1 to make 0-based
.else
nop ;
.endif
.end

88
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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread - Low Level SMP Support */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;#define TX_THREAD_SMP_SOURCE_CODE
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h" */
;
;
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_smp_core_preempt SMP/ARC_HS/MetaWare */
;/* 6.0.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function preempts the specified core in situations where the */
;/* thread corresponding to this core is no longer ready or when the */
;/* core must be used for a higher-priority thread. If the specified is */
;/* the current core, this processing is skipped since the will give up */
;/* control subsequently on its own. */
;/* */
;/* INPUT */
;/* */
;/* core The core to preempt */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* ThreadX Source */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* */
;/**************************************************************************/
.global _tx_thread_smp_core_preempt
.type _tx_thread_smp_core_preempt, @function
_tx_thread_smp_core_preempt:
sub sp, sp, 16 ; Allocate some stack space
st blink, [sp] ; Save return address
bl.d arc_ici_send ; Call ARC inter-core interrupt routine
sub sp, sp, 16 ; Allocate stack space (delay slot)
add sp, sp, 16 ; Recover stack space
ld blink, [sp] ; Recover return address
j_s.d [blink] ; Return to caller with delay slot
add sp, sp, 16 ; Recover stack space
.end

89
ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_current_state_get.s Normal file
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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread - Low Level SMP Support */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;#define TX_THREAD_SMP_SOURCE_CODE
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h" */
;
;
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_smp_current_state_get SMP/ARC_HS/MetaWare */
;/* 6.0.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is gets the current state of the calling core. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* ThreadX Components */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* */
;/**************************************************************************/
.global _tx_thread_smp_current_state_get
.type _tx_thread_smp_current_state_get, @function
_tx_thread_smp_current_state_get:
clri r2 ; Disable interrupts
lr r0, [IDENTITY] ; Pickup core ID
xbfu r0, r0, 8, 8 ; Shift down and isolate core ID
.ifndef TX_ZERO_BASED_CORE_ID
sub r0, r0, 1 ; Subtract 1 to make 0-based
.endif
asl r0, r0, 2 ; Build index into _tx_thread_system_state
mov r1, _tx_thread_system_state ; Build address of _tx_thread_system_state
add r1, r1, r0 ;
ld r0, [r1] ; Pickup current system state for this core
j_s.d [blink] ; Return to caller with delay slot
seti r2 ; Restore previous interrupt state
.end

90
ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_current_thread_get.s Normal file
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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread - Low Level SMP Support */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;#define TX_THREAD_SMP_SOURCE_CODE
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h" */
;
;
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_smp_current_thread_get SMP/ARC_HS/MetaWare */
;/* 6.0.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is gets the current thread of the calling core. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* ThreadX Components */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* */
;/**************************************************************************/
.global _tx_thread_smp_current_thread_get
.type _tx_thread_smp_current_thread_get, @function
_tx_thread_smp_current_thread_get:
clri r2 ; Disable interrupts
lr r0, [IDENTITY] ; Pickup core ID
xbfu r0, r0, 8, 8 ; Shift down and isolate core ID
.ifndef TX_ZERO_BASED_CORE_ID
sub r0, r0, 1 ; Subtract 1 to make 0-based
.endif
asl r0, r0, 2 ; Build index into _tx_thread_current_ptr
mov r1, _tx_thread_current_ptr ; Build address of _tx_thread_current_ptr
add r1, r1, r0 ;
ld r0, [r1] ; Pickup current thread for this core
j_s.d [blink] ; Return to caller with delay slot
seti r2 ; Restore previous interrupt state
.end

126
ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_initialize_wait.s Normal file
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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread - Low Level SMP Support */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;#define TX_THREAD_SMP_SOURCE_CODE
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h" */
;
;
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_smp_initialize_wait SMP/ARC_HS/MetaWare */
;/* 6.0.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is the place where additional cores wait until */
;/* initialization is complete before they enter the thread scheduling */
;/* loop. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* _tx_thread_schedule Thread scheduling loop */
;/* */
;/* CALLED BY */
;/* */
;/* Hardware */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* */
;/**************************************************************************/
.global _tx_thread_smp_initialize_wait
.type _tx_thread_smp_initialize_wait, @function
_tx_thread_smp_initialize_wait:
;
; /* Lockout interrupts. */
;
clri r2 ; Disable interrupts
;
; /* Pickup the CPU ID. */
;
lr r0, [IDENTITY] ; Pickup core ID
xbfu r0, r0, 8, 8 ; Shift down and isolate core ID
.ifndef TX_ZERO_BASED_CORE_ID
sub r0, r0, 1 ; Subtract 1 to make 0-based
.endif
asl r0, r0, 2 ; Build index into _tx_thread_system_state
mov r1, _tx_thread_system_stack_ptr ; Build system stack pointer address
add r1, r1, r0 ;
st sp, [r1] ; Save this core's system address
mov r1, _tx_thread_system_state ; Build system state pointer address
add r1, r1, r0 ;
mov r3, 0xF0F0F0F0 ; Build TX_INITIALIZE_IN_PROGRESS flag
wait_for_initialize:
ld r0, [r1] ; Pickup current system state for this core
; Has the TX_INITIALIZE_IN_PROGRESS flag been set yet?
brne r3, r0, wait_for_initialize ; No, simply wait here until this value is set
;
; /* Pickup the release cores flag. */
;
mov r3, 0 ; Build clear value
wait_for_release:
ld r0, [gp, _tx_thread_smp_release_cores_flag@sda] ; Pickup the release cores flag
breq r3, r0, wait_for_release ; No, simply wait here until this flag is set
;
; /* Core 0 has released this core. */
;
; /* Clear this core's system state variable. */
;
st r3, [r1] ; Clear this core's state value
;
; /* Now wait for core 0 to finish it's initialization. */
;
core_0_wait_loop:
ld r0, [gp, _tx_thread_system_state@sda] ; Pickup core 0's state value
brne r3, r0, core_0_wait_loop ; If set, continue to wait here
;
; /* Initialize is complete, enter the scheduling loop! */
;
b _tx_thread_schedule ; Return to scheduler..
.end

79
ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_low_level_initialize.s Normal file
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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread - Low Level SMP Support */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;#define TX_THREAD_SMP_SOURCE_CODE
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h" */
;
;
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_smp_low_level_initialize SMP/ARC_HS/MetaWare */
;/* 6.0.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function performs low-level initialization of the booting */
;/* core. */
;/* */
;/* INPUT */
;/* */
;/* number_of_cores Number of cores */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* _tx_initialize_high_level ThreadX high-level init */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* */
;/**************************************************************************/
.global _tx_thread_smp_low_level_initialize
.type _tx_thread_smp_low_level_initialize, @function
_tx_thread_smp_low_level_initialize:
j_s.d [blink] ; Return to caller with delay slot
nop ;
.end

117
ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_protect.s Normal file
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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread - Low Level SMP Support */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;#define TX_THREAD_SMP_SOURCE_CODE
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h" */
;
;
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_smp_protect SMP/ARC_HS/MetaWare */
;/* 6.0.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function gets protection for running inside the ThreadX */
;/* source. This is acomplished by a combination of a test-and-set */
;/* flag and periodically disabling interrupts. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* Previous Status Register */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* ThreadX Source */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* */
;/**************************************************************************/
.global _tx_thread_smp_protect
.type _tx_thread_smp_protect, @function
_tx_thread_smp_protect:
clri r0 ; Disable interrupts
lr r1, [IDENTITY] ; Pickup core ID
xbfu r1, r1, 8, 8 ; Shift down and isolate core ID
.ifndef TX_ZERO_BASED_CORE_ID
sub r1, r1, 1 ; Subtract 1 to make 0-based
.endif
mov r2, 1 ; Build protection flag
mov r3, 0 ; Build clear value
mov r4, _tx_thread_smp_protection ; Build address of the protection structure
ld r5, [r4, 8] ; Pickup the owning core
breq r1, r5, _owned ; Check if the core already owns the protection
llock r6, [r4] ; Attempt to get the inter-core lock
breq r3, r6, _continue ; If the lock is available, continue
b.d _tx_thread_smp_protect ; Attempt to get the lock again
seti r0 ; Restore original interrupt posture
_continue:
scond r2, [r4] ; Attempt to set the lock
beq_s _got_lock ; If STATUS32[Z] flag is set, we got the lock!
b.d _tx_thread_smp_protect ; Attempt to get the lock again
seti r0 ; Restore original interrupt posture
_got_lock:
dmb 3 ; Data memory barrier
st r1, [r4, 8] ; Store the owning core
.ifdef TX_SMP_DEBUG_ENABLE
asl r0, r1, 2 ; Build index into _tx_thread_system_state
mov r7, _tx_thread_current_ptr ; Pickup base of the current thread pointer
add r7, r7, r0 ; Build address of current thread pointer
ld r8, [r7] ; Pickup the current thread pointer
st r8, [r4, 4] ; Save the current thread pointer
st blink, [r4, 16] ; Save last caller's return address
st r0, [r4, 20] ; Save STATUS32
.endif
_owned:
ld r6, [r4, 12] ; Pickup ownership count
add r6, r6, 1 ; Increment ownership count
j_s.d [blink] ; Return to caller with delay slot
st r6, [r4, 12] ; Store new ownership count
.end

80
ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_time_get.s Normal file
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;/**************************************************************************/
;/* */
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
;/* */
;/* This software is licensed under the Microsoft Software License */
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
;/* and in the root directory of this software. */
;/* */
;/**************************************************************************/
;
;
;/**************************************************************************/
;/**************************************************************************/
;/** */
;/** ThreadX Component */
;/** */
;/** Thread - Low Level SMP Support */
;/** */
;/**************************************************************************/
;/**************************************************************************/
;
;
;#define TX_SOURCE_CODE
;#define TX_THREAD_SMP_SOURCE_CODE
;
;/* Include necessary system files. */
;
;#include "tx_api.h"
;#include "tx_thread.h"
;#include "tx_timer.h" */
;
;
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_smp_time_get SMP/ARC_HS/MetaWare */
;/* 6.0.1 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function gets the global time value that is used for debug */
;/* information and event tracing. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* 32-bit time stamp */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* ThreadX Source */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
;/* */
;/**************************************************************************/
.global _tx_thread_smp_time_get
.type _tx_thread_smp_time_get, @function
_tx_thread_smp_time_get:
j_s.d [blink] ; Return to caller with delay slot
lr r0, [COUNT0] ; Return count 0 value
.end

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