Add support for Star64 SBC

Signed-off-by: Ivan-Velickovic <i.velickovic@unsw.edu.au>

include/drivers/irq/riscv_plic0.h

@@ -5,7 +5,7 @@
  * SPDX-License-Identifier: GPL-2.0-only
  *
  * SiFive U54/U74 PLIC handling (HiFive Unleashed/Unmatched, Polarfire,
- * QEMU RISC-V virt)
+ * QEMU RISC-V virt, Star64)
  */
 
 #pragma once
@@ -15,7 +15,8 @@
 #if !defined(CONFIG_PLAT_HIFIVE) && \
     !defined(CONFIG_PLAT_POLARFIRE) && \
     !defined(CONFIG_PLAT_QEMU_RISCV_VIRT) && \
-    !defined(CONFIG_PLAT_ROCKETCHIP_ZCU102)
+    !defined(CONFIG_PLAT_ROCKETCHIP_ZCU102) && \
+    !defined(CONFIG_PLAT_STAR64)
 #error "Check if this platform suppots a PLIC."
 #endif
 

libsel4/sel4_plat_include/star64/sel4/plat/api/constants.h

@@ -0,0 +1,9 @@
+/*
+ * Copyright 2023, Ivan Velickovic
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+
+#pragma once
+
+#include <sel4/config.h>

src/plat/star64/config.cmake

@@ -0,0 +1,32 @@
+#
+# Copyright 2023, Ivan Velickovic
+#
+# SPDX-License-Identifier: GPL-2.0-only
+#
+
+cmake_minimum_required(VERSION 3.7.2)
+
+declare_platform(star64 KernelPlatformStar64 PLAT_STAR64 KernelArchRiscV)
+
+if(KernelPlatformStar64)
+    declare_seL4_arch(riscv64)
+    config_set(KernelRiscVPlatform RISCV_PLAT "star64")
+    # The JH7110 SoC contains the SiFive U74-MC core complex. This has four U74
+    # cores and one S7 core (which has a hart ID of 0). The first U74 core has
+    # a hart ID of 1.
+    config_set(KernelPlatformFirstHartID FIRST_HART_ID 1)
+    config_set(KernelOpenSBIPlatform OPENSBI_PLATFORM "generic")
+    # Note that by default the kernel is configured for the 4GB Star64 model.
+    list(APPEND KernelDTSList "tools/dts/star64.dts")
+    list(APPEND KernelDTSList "${CMAKE_CURRENT_LIST_DIR}/overlay-star64.dts")
+    # The value for TIMER_FREQUENCY is from the "timebase-frequency" field on
+    # the "cpus" node in the Star64 device tree.
+    # The value for PLIC_MAX_NUM_INT comes from the DTS "plic" node which says
+    # "riscv,ndev = <0x88>".
+    declare_default_headers(
+        TIMER_FREQUENCY 4000000 PLIC_MAX_NUM_INT 136
+        INTERRUPT_CONTROLLER drivers/irq/riscv_plic0.h
+    )
+else()
+    unset(KernelPlatformFirstHartID CACHE)
+endif()

src/plat/star64/overlay-star64-8gb.dts

@@ -0,0 +1,13 @@
+/*
+ * Copyright 2023, Ivan Velickovic
+ *
+ * SPDX-License-Identifier: GPL-2.0-only
+ */
+
+/ {
+    /* The Pine64 Star64 Model-A also has model with 8GB of RAM. */
+    memory@40000000 {
+        device_type = "memory";
+        reg = <0x00 0x40000000 0x02 0x00>;
+    };
+};

src/plat/star64/overlay-star64.dts

@@ -0,0 +1,24 @@
+/*
+ * Copyright 2023, Ivan Velickovic
+ *
+ * SPDX-License-Identifier: GPL-2.0-only
+ */
+
+/ {
+    chosen {
+        seL4,kernel-devices =
+            &{/soc/clint@2000000},
+            &{/soc/plic@c000000};
+    };
+
+    /*
+     * According to the StarFive JH7110 SoC manual
+     * the CLINT is mapped from 0x0200_0000 to 0x0200_FFFF.
+     */
+    soc {
+        clint@2000000 {
+            compatible = "riscv,cpu-intc";
+            reg = <0x00000000 0x2000000 0x00000000 0x000010000>;
+        };
+    };
+};