Imagelibrary/seL4
1
0
Fork 1
mirror of https://github.com/seL4/seL4.git synced 2026-04-04 22:39:54 +00:00
Code Issues Packages Projects Releases Wiki Activity

asidpools: use nASIDPools for the ASID Tables

Browse Source 
Signed-off-by: julia <git.ts@trainwit.ch>
This commit is contained in:
julia
2025-08-01 16:50:44 +10:00
committed by Indan Zupancic
parent 1c50485c9a
commit e5c3aef827
7 changed files with 7 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
include/arch/arm/arch/32/mode/model/statedata.h
View File

@@ -12,7 +12,7 @@
#include <util.h>
#include <object/structures.h>
extern asid_pool_t *armKSASIDTable[BIT(asidHighBits)] VISIBLE;
extern asid_pool_t *armKSASIDTable[nASIDPools] VISIBLE;
extern asid_t armKSHWASIDTable[BIT(hwASIDBits)] VISIBLE;
extern hw_asid_t armKSNextASID VISIBLE;

2
include/arch/arm/arch/64/mode/model/statedata.h
View File

@@ -21,7 +21,7 @@
#endif
/* The top level asid mapping table */
extern asid_pool_t *armKSASIDTable[BIT(asidHighBits)] VISIBLE;
extern asid_pool_t *armKSASIDTable[nASIDPools] VISIBLE;
/* This is the temporary userspace page table in kernel. It is required before running
* user thread to avoid speculative page table walking with the wrong page table. */

2
include/arch/riscv/arch/model/statedata.h
View File

@@ -22,7 +22,7 @@ NODE_STATE_BEGIN(archNodeState)
NODE_STATE_DECLARE(word_t, ipiReschedulePending);
NODE_STATE_END(archNodeState);
extern asid_pool_t *riscvKSASIDTable[BIT(asidHighBits)];
extern asid_pool_t *riscvKSASIDTable[nASIDPools];
/* Kernel Page Tables */
extern pte_t kernel_root_pageTable[BIT(PT_INDEX_BITS)] VISIBLE;

2
src/arch/arm/32/model/statedata.c
View File

@@ -15,7 +15,7 @@
#include <plat/machine/hardware.h>
/* The top level asid mapping table */
asid_pool_t *armKSASIDTable[BIT(asidHighBits)];
asid_pool_t *armKSASIDTable[nASIDPools];
/* The hardware ASID to virtual ASID mapping table */
asid_t armKSHWASIDTable[BIT(hwASIDBits)];

2
src/arch/arm/64/model/statedata.c
View File

@@ -18,7 +18,7 @@
#endif
asid_pool_t *armKSASIDTable[BIT(asidHighBits)];
asid_pool_t *armKSASIDTable[nASIDPools];
/* AArch64 Memory map explanation:
*

2
src/arch/riscv/model/statedata.c
View File

@@ -15,7 +15,7 @@
#include <plat/machine/hardware.h>
/* The top level asid mapping table */
asid_pool_t *riscvKSASIDTable[BIT(asidHighBits)];
asid_pool_t *riscvKSASIDTable[nASIDPools];
/* Kernel Page Tables */
pte_t kernel_root_pageTable[BIT(PT_INDEX_BITS)] ALIGN_BSS(BIT(seL4_PageTableBits));

2
src/arch/x86/model/statedata.c
View File

@@ -23,7 +23,7 @@ UP_STATE_DEFINE(interrupt_t, x86KSPendingInterrupt);
x86_arch_global_state_t x86KSGlobalState[CONFIG_MAX_NUM_NODES] ALIGN(L1_CACHE_LINE_SIZE) SKIM_BSS;
/* The top level ASID table */
asid_pool_t *x86KSASIDTable[BIT(asidHighBits)];
asid_pool_t *x86KSASIDTable[nASIDPools];
/* Current user value of the fs/gs base */
UP_STATE_DEFINE(word_t, x86KSCurrentFSBase);