Add support for the TQMa8XQP 1GiB module

TQ Group produces a system-on-module family called TQMa8Xx.

The user manual for this SoM is available here:

https://www.tq-group.com/filedownloads/files/products/embedded/manuals/arm/embedded-modul/TQ-Socket/TQMa8Xx/TQMa8Xx.UM.0104.pdf

This SoM comes in a number of different configurations.

The specific NXP SoC used, and the amount of memory are both
configurable.

The TQMa8XQP is the part number for the TQMa8Xx family configured with
the i.MX 8QuadXPlus SoC.

The datasheet for the SoC is available here:

https://www.nxp.com/docs/en/data-sheet/IMX8QXPAEC.pdf

In addition to the SoC being configurable the amount of SDRAM
on the SoM is also configurable.

The support provided in this PR is specifically for the TQMa8XQP
configured for 1GiB of memory. Note: Actual usable memory available
to the ARM application processor is 1022MiB.

System-on-modules rely on an appropriate carrier board.
Testing of this PR has been done on the MBa8Xx carrier board
that is available from TQ Group as part of their starter kit.

To the best of my knowledge there is nothing in this PR
that depends on the carrier board itself; all code is SoM
specific and should support any carrier board.

Note: This support is very specifically for the TQMa8XQP configured
with 1GiB of memory.

This may be a starting point for supporting other boards that
also have the NXP i.MX 8QuadXPlus SoC (as well as the i.MX 8DXP
and possibly other SoC in the i.MX 8 family).

Support is limited to the specific SoM due to the way in which
platform support currently works for seL4. Building a kernel
currently relies on the information from the DTS file (which is
SoM + RAM configuration specific). It would be preferable to
allow more generic support but SoC families but that is beyond
the scope of this PR.

Signed-off-by: Ben Leslie <benno@brkawy.com>

libsel4/sel4_plat_include/tqma8xqp1gb/sel4/plat/api/constants.h

@@ -0,0 +1,26 @@
+/*
+ * Copyright 2021, Breakaway Consulting Pty. Ltd.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+
+#pragma once
+
+#include <autoconf.h>
+
+/* Cortex A35 Manual Table C7.1 */
+#define seL4_NumHWBreakpoints (6)
+#define seL4_NumExclusiveBreakpoints (6)
+#define seL4_NumExclusiveWatchpoints (4)
+#ifdef CONFIG_HARDWARE_DEBUG_API
+#define seL4_FirstWatchpoint (6)
+#define seL4_NumDualFunctionMonitors (0)
+#endif
+
+#if CONFIG_ARCH_AARCH32
+/* Platform support for tqma8xqp1gb is provided for AARCH64 only, even if the
+ * Cortex-A35 supports AARCH32 also. Keep this as a build blocker as long as
+ * AARCH32 remains untested.
+ */
+#error "AARCH32 is unsupported"
+#endif /* CONFIG_ARCH_AARCH32 */

src/plat/tqma8xqp1gb/config.cmake

@@ -0,0 +1,35 @@
+#
+# Copyright 2021, Breakaway Consulting Pty. Ltd.
+#
+# SPDX-License-Identifier: GPL-2.0-only
+#
+
+cmake_minimum_required(VERSION 3.7.2)
+
+declare_platform(tqma8xqp1gb KernelPlatformTqma8xqp1gb PLAT_TQMA8XQP1GB KernelArchARM)
+
+if(KernelPlatformTqma8xqp1gb)
+    declare_seL4_arch(aarch64)
+    set(KernelArmCortexA35 ON)
+    set(KernelArchArmV8a ON)
+    config_set(KernelARMPlatform ARM_PLAT ${KernelPlatform})
+    set(KernelArmVtimerUpdateVOffset OFF)
+    set(KernelArmDisableWFIWFETraps ON)
+    list(APPEND KernelDTSList "tools/dts/${KernelPlatform}.dts")
+    list(APPEND KernelDTSList "src/plat/tqma8xqp1gb/overlay-${KernelPlatform}.dts")
+    declare_default_headers(
+        TIMER_FREQUENCY 8000000
+        MAX_IRQ 512
+        TIMER drivers/timer/arm_generic.h
+        INTERRUPT_CONTROLLER arch/machine/gic_v3.h
+        NUM_PPI 32
+        CLK_MAGIC 1llu
+        CLK_SHIFT 3u
+        KERNEL_WCET 10u
+    )
+endif()
+
+add_sources(
+    DEP "KernelPlatformTqma8xqp1gb"
+    CFILES src/arch/arm/machine/gic_v3.c src/arch/arm/machine/l2c_nop.c
+)

src/plat/tqma8xqp1gb/overlay-tqma8xqp1gb.dts

@@ -0,0 +1,29 @@
+/*
+ * Copyright 2021, Breakaway Consulting Pty. Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0-only
+ */
+
+/ {
+	chosen {
+		seL4,elfloader-devices =
+			"serial1",
+			&{/psci};
+
+		seL4,kernel-devices =
+			"serial1",
+			&{/interrupt-controller@51a00000},
+			&{/timer};
+	};
+
+	/*
+	 * The GPT is not defined in the standard Linux device tree, so it is added explicitly
+	 * here, based on chipset documentation.
+	 */
+    gpt@0x5d140000 {
+        compatible = "fsl,imx8mq-gpt\0fsl,imx7d-gpt";
+        reg = < 0x00 0x5d140000 0x00 0x10000 >;
+        interrupts = < 0x00 0x50 0x04 >;
+        status = "disabled";
+    };
+};