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riscv: use MAX_IRQ instead of PLIC_MAX_NUM_INT

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Signed-off-by: Axel Heider <axelheider@gmx.de>
This commit is contained in:
Axel Heider
2023-11-17 21:54:01 +01:00
committed by Indan Zupancic
parent a2cb6d0271
commit b59fa0ed20
10 changed files with 20 additions and 12 deletions
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2
config.cmake
View File

@@ -50,7 +50,7 @@ set_property(
if(DEFINED CALLED_declare_default_headers)
# calculate the irq cnode size based on MAX_NUM_IRQ
if("${KernelArch}" STREQUAL "riscv")
math(EXPR MAX_NUM_IRQ "${CONFIGURE_PLIC_MAX_NUM_INT} + 2")
math(EXPR MAX_NUM_IRQ "${CONFIGURE_MAX_IRQ} + 2")
else()
if(
DEFINED KernelMaxNumNodes

2
configs/seL4Config.cmake
View File

@@ -125,7 +125,7 @@ macro(declare_default_headers)
cmake_parse_arguments(
CONFIGURE
""
"TIMER_FREQUENCY;MAX_IRQ;NUM_PPI;PLIC_MAX_NUM_INT;INTERRUPT_CONTROLLER;TIMER;SMMU;CLK_SHIFT;CLK_MAGIC;KERNEL_WCET;TIMER_PRECISION;TIMER_OVERHEAD_TICKS;MAX_SID;MAX_CB"
"TIMER_FREQUENCY;MAX_IRQ;NUM_PPI;INTERRUPT_CONTROLLER;TIMER;SMMU;CLK_SHIFT;CLK_MAGIC;KERNEL_WCET;TIMER_PRECISION;TIMER_OVERHEAD_TICKS;MAX_SID;MAX_CB"
""
${ARGN}
)

2
src/arch/riscv/platform_gen.h.in
View File

@@ -28,7 +28,7 @@
*/
enum IRQConstants {
PLIC_IRQ_OFFSET = 0,
PLIC_MAX_IRQ = PLIC_IRQ_OFFSET + (@CONFIGURE_PLIC_MAX_NUM_INT@),
PLIC_MAX_IRQ = PLIC_IRQ_OFFSET + (@CONFIGURE_MAX_IRQ@),
#ifdef ENABLE_SMP_SUPPORT
INTERRUPT_IPI_0,
INTERRUPT_IPI_1,

3
src/plat/ariane/config.cmake
View File

@@ -23,7 +23,8 @@ if(KernelPlatformAriane)
# interrupts and using the dummy PLIC driver seems the best option for now
# to avoid confusion or even crashes.
declare_default_headers(
TIMER_FREQUENCY 25000000 PLIC_MAX_NUM_INT 0
TIMER_FREQUENCY 25000000
MAX_IRQ 0
INTERRUPT_CONTROLLER drivers/irq/riscv_plic_dummy.h
)
else()

3
src/plat/hifive/config.cmake
View File

@@ -18,7 +18,8 @@ if(KernelPlatformHifive)
list(APPEND KernelDTSList "tools/dts/hifive.dts")
list(APPEND KernelDTSList "src/plat/hifive/overlay-hifive.dts")
declare_default_headers(
TIMER_FREQUENCY 1000000 PLIC_MAX_NUM_INT 53
TIMER_FREQUENCY 1000000
MAX_IRQ 53
INTERRUPT_CONTROLLER drivers/irq/riscv_plic0.h
)
else()

3
src/plat/polarfire/config.cmake
View File

@@ -17,7 +17,8 @@ if(KernelPlatformPolarfire)
list(APPEND KernelDTSList "tools/dts/mpfs_icicle.dts")
list(APPEND KernelDTSList "src/plat/polarfire/overlay-polarfire.dts")
declare_default_headers(
TIMER_FREQUENCY 1000000 PLIC_MAX_NUM_INT 186
TIMER_FREQUENCY 1000000
MAX_IRQ 186
INTERRUPT_CONTROLLER drivers/irq/riscv_plic0.h
)
else()

3
src/plat/qemu-riscv-virt/config.cmake
View File

@@ -190,7 +190,8 @@ if(KernelPlatformQEMURiscVVirt)
# The CLINT timer pretends to run at 10 MHz, but this speed may not hold in
# practical measurements.
declare_default_headers(
TIMER_FREQUENCY 10000000 PLIC_MAX_NUM_INT 128
TIMER_FREQUENCY 10000000
MAX_IRQ 128
INTERRUPT_CONTROLLER drivers/irq/riscv_plic0.h
)

6
src/plat/rocketchip/config.cmake
View File

@@ -47,7 +47,8 @@ if(KernelPlatformRocketchip)
list(APPEND KernelDTSList "src/plat/rocketchip/overlay-rocketchip-zcu102.dts")
# The zcu102 instantiation supports the PLIC and external interrupts
declare_default_headers(
TIMER_FREQUENCY 10000000 PLIC_MAX_NUM_INT 128
TIMER_FREQUENCY 10000000
MAX_IRQ 128
INTERRUPT_CONTROLLER drivers/irq/riscv_plic0.h
)
else()
@@ -59,7 +60,8 @@ if(KernelPlatformRocketchip)
# interrupts and using the dummy PLIC driver seems the best option for now
# to avoid confusion or even crashes.
declare_default_headers(
TIMER_FREQUENCY 10000000 PLIC_MAX_NUM_INT 0
TIMER_FREQUENCY 10000000
MAX_IRQ 0
INTERRUPT_CONTROLLER drivers/irq/riscv_plic_dummy.h
)
endif()

3
src/plat/spike/config.cmake
View File

@@ -23,7 +23,8 @@ if(KernelPlatformSpike)
endif()
list(APPEND KernelDTSList "src/plat/spike/overlay-spike.dts")
declare_default_headers(
TIMER_FREQUENCY 10000000 PLIC_MAX_NUM_INT 0
TIMER_FREQUENCY 10000000
MAX_IRQ 0
INTERRUPT_CONTROLLER drivers/irq/riscv_plic_dummy.h
)
else()

5
src/plat/star64/config.cmake
View File

@@ -21,10 +21,11 @@ if(KernelPlatformStar64)
list(APPEND KernelDTSList "${CMAKE_CURRENT_LIST_DIR}/overlay-star64.dts")
# The value for TIMER_FREQUENCY is from the "timebase-frequency" field on
# the "cpus" node in the Star64 device tree.
# The value for PLIC_MAX_NUM_INT comes from the DTS "plic" node which says
# The value for MAX_IRQ comes from the DTS "plic" node which says
# "riscv,ndev = <0x88>".
declare_default_headers(
TIMER_FREQUENCY 4000000 PLIC_MAX_NUM_INT 136
TIMER_FREQUENCY 4000000
MAX_IRQ 136
INTERRUPT_CONTROLLER drivers/irq/riscv_plic0.h
)
else()