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[SELFOUR-1156] RISC-V Port

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Experimental release that supports both RV32 and RV64
This commit is contained in:
Hesham Almatary
2018-02-21 14:00:00 +10:00
committed by Anna Lyons
parent 511be7d91d
commit 83ba084713
136 changed files with 9803 additions and 11 deletions
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.gitignore vendored
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@@ -32,11 +32,14 @@ manual/generated
# Generated headers
libsel4/arch_include/arm/sel4/arch/invocation.h
libsel4/arch_include/ia32/sel4/arch/invocation.h
libsel4/arch_include/riscv/sel4/arch/invocation.h
libsel4/arch_include/x86/sel4/arch/invocation.h
libsel4/sel4_arch_include/aarch32/sel4/sel4_arch/invocation.h
libsel4/sel4_arch_include/aarch64/sel4/sel4_arch/invocation.h
libsel4/sel4_arch_include/ia32/sel4/sel4_arch/invocation.h
libsel4/sel4_arch_include/x86_64/sel4/sel4_arch/invocation.h
libsel4/sel4_arch_include/riscv32/sel4/sel4_arch/invocation.h
libsel4/sel4_arch_include/riscv64/sel4/sel4_arch/invocation.h
# Emacs backups
*~