Add support for SiFive Premier P550 platform

The SiFive Premier P550 [1] is a new development board from SiFive
that is based on the ESWIN EIC7700X SoC.

The platform is interesting to the seL4 community as it implements
the RISC-V hypervisor extension meaning we now have real hardware to
evaluate RISC-V hypervisor changes to seL4. It also implements the
Sscofpmf extension and so we'll be able to get more experiment with
proper profiling on RISC-V.

Unfortunately, it seems we still do not have proper ASID suppor
according to [2].

The board comes in two configurations, 16GB and 32GB of memory.
This adds support for the 16GB model.

The DTS comes from SiFive's fork of Linux [3].
No modifications were made, any extra things are in the overlay.

[1]: https://www.sifive.com/boards/hifive-premier-p550
[2]: https://forums.sifive.com/t/asid-vmid-support-in-p550-eic7700x/6887
[3]: https://github.com/sifive/riscv-linux/tree/dev/kernel/hifive-premier-p550

Signed-off-by: Ivan-Velickovic <i.velickovic@unsw.edu.au>

include/drivers/irq/riscv_plic0.h

@@ -18,7 +18,8 @@
     !defined(CONFIG_PLAT_ROCKETCHIP_ZCU102) && \
     !defined(CONFIG_PLAT_STAR64) && \
     !defined(CONFIG_PLAT_CHESHIRE) && \
-    !defined(CONFIG_PLAT_ARIANE)
+    !defined(CONFIG_PLAT_ARIANE) && \
+    !defined(CONFIG_PLAT_HIFIVE_P550)
 #error "Check if this platform supports a PLIC."
 #endif
 

libsel4/sel4_plat_include/hifive-p550/sel4/plat/api/constants.h

@@ -0,0 +1,9 @@
+/*
+ * Copyright 2025, UNSW
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+
+#pragma once
+
+#include <sel4/config.h>

src/plat/eswin/config.cmake

@@ -0,0 +1,30 @@
+#
+# Copyright 2025, UNSW
+#
+# SPDX-License-Identifier: GPL-2.0-only
+#
+
+cmake_minimum_required(VERSION 3.7.2)
+
+declare_platform(hifive-p550 KernelPlatformHifiveP550 PLAT_HIFIVE_P550 KernelArchRiscV)
+
+if(KernelPlatformHifiveP550)
+    declare_seL4_arch(riscv64)
+    config_set(KernelRiscVPlatform RISCV_PLAT ${KernelPlatform})
+    config_set(KernelPlatformFirstHartID FIRST_HART_ID 0)
+    config_set(KernelOpenSBIPlatform OPENSBI_PLATFORM "generic")
+    # Note that by default the kernel is configured for the 16GB model.
+    list(APPEND KernelDTSList "tools/dts/${KernelPlatform}.dts")
+    list(APPEND KernelDTSList "${CMAKE_CURRENT_LIST_DIR}/overlay-${KernelPlatform}.dts")
+    # The value for TIMER_FREQUENCY is from the "timebase-frequency" field on
+    # the "cpus" node in the HiFive P550 device tree.
+    # The value for MAX_IRQ comes from the DTS "interrupt-controller" node which says
+    # "riscv,ndev = <0x208>".
+    declare_default_headers(
+        TIMER_FREQUENCY 1000000
+        MAX_IRQ 520
+        INTERRUPT_CONTROLLER drivers/irq/riscv_plic0.h
+    )
+else()
+    unset(KernelPlatformFirstHartID CACHE)
+endif()

src/plat/eswin/overlay-hifive-p550.dts

@@ -0,0 +1,49 @@
+/*
+ * Copyright 2025, UNSW
+ *
+ * SPDX-License-Identifier: GPL-2.0-only
+ */
+
+/ {
+    reserved-memory {
+        /delete-node/ linux,cma;
+    };
+
+    chosen {
+        seL4,kernel-devices =
+            &{/soc/clint@2000000},
+            &{/soc/interrupt-controller@c000000};
+    };
+
+    /* 16GiB of main memory */
+    memory@80000000 {
+        reg = <0x00 0x80000000 0x04 0x00>;
+    };
+
+    /*
+     * According to the EIC7700X SoC manual the CLINT is mapped from
+     * 0x0200_0000 to 0x0200_C000.
+     */
+    soc {
+        clint@2000000 {
+            compatible = "riscv,cpu-intc";
+            reg = <0x00000000 0x2000000 0x00000000 0x00000c000>;
+        };
+    };
+
+    /* Reserve 2 MiB for SBI at the start of RAM (0x40000000 - 0x40200000). This
+     * is exactly one "megapage" in the MMU table. It leaves plenty of space for
+     * further SBI experimenting, given the known usage (as of June 2021) is:
+     * - BBL: 76 KiB (= 0x13000)
+     * - OpenSBI: 128 KiB (= 0x20000) with PMP protection
+     */
+    reserved-memory {
+        #address-cells = <0x02>;
+        #size-cells = <0x02>;
+        ranges;
+        sbi@40000000 {
+            reg = <0x0 0x80000000 0x0 0x200000>;
+            no-map;
+        };
+    };
+};