virtex4, virtex5 bsp.h: Use BSP_INTERRUPT_STACK_SIZE not user space CONFIGURE_INTERRUPT_STACK_SIZE

closes #2801.

LICENSE.WEBSERVER

@@ -1,4 +0,0 @@
-The source code in c/src/libnetworking/rtems_webserver is a port
-of the Go Ahead Software, Inc. WebServer.  Their copyright and 
-licensing terms apply.  See c/src/libnetworking/rtems_webserver/license.txt
-for details.

aclocal/enable-smp.m4

@@ -2,8 +2,8 @@ AC_DEFUN([RTEMS_ENABLE_SMP],
 [
 ## AC_BEFORE([$0], [RTEMS_CHECK_SMP])dnl
 
-AC_ARG_ENABLE(smp,
+AC_ARG_ENABLE(experimental-smp,
-[AS_HELP_STRING([--enable-smp],[enable support for symmetric multiprocessing
+[AS_HELP_STRING([--enable-experimental-smp],[enable experimental support for symmetric multiprocessing
 (SMP)])],
 [case "${enableval}" in 
   yes) case "${RTEMS_CPU}" in
@@ -13,5 +13,9 @@ AC_ARG_ENABLE(smp,
        ;;
   no) RTEMS_HAS_SMP=no ;;
   *)  AC_MSG_ERROR(bad value ${enableval} for enable-smp option) ;;
-esac],[RTEMS_HAS_SMP=no]) 
+esac],[RTEMS_HAS_SMP=no])
+AC_ARG_ENABLE(smp,
+[],
+[AC_MSG_ERROR([SMP support is experimental in RTEMS 4.11, use --enable-experimental-smp])],
+[])
 ])

ampolish3

@@ -1,4 +1,4 @@
-#! /usr/bin/perl -w
+#! /usr/bin/env perl
 #
 # Copyright (C) 2005, 2006 Ralf Corsépius, Ulm, Germany
 #

c/src/aclocal/enable-smp.m4

@@ -2,8 +2,8 @@ AC_DEFUN([RTEMS_ENABLE_SMP],
 [
 ## AC_BEFORE([$0], [RTEMS_CHECK_SMP])dnl
 
-AC_ARG_ENABLE(smp,
+AC_ARG_ENABLE(experimental-smp,
-[AS_HELP_STRING([--enable-smp],[enable support for symmetric multiprocessing
+[AS_HELP_STRING([--enable-experimental-smp],[enable experimental support for symmetric multiprocessing
 (SMP)])],
 [case "${enableval}" in 
   yes) case "${RTEMS_CPU}" in
@@ -13,5 +13,9 @@ AC_ARG_ENABLE(smp,
        ;;
   no) RTEMS_HAS_SMP=no ;;
   *)  AC_MSG_ERROR(bad value ${enableval} for enable-smp option) ;;
-esac],[RTEMS_HAS_SMP=no]) 
+esac],[RTEMS_HAS_SMP=no])
+AC_ARG_ENABLE(smp,
+[],
+[AC_MSG_ERROR([SMP support is experimental in RTEMS 4.11, use --enable-experimental-smp])],
+[])
 ])

c/src/ada-tests/support/init.c

@@ -1,17 +1,19 @@
 /*
- *  COPYRIGHT (c) 1989-2007
+ *  COPYRIGHT (c) 1989-2015
  *  On-Line Applications Research Corporation (OAR).
  */
 
 #include <bsp.h>
 #include <stdlib.h>
 
+#include <rtems/score/threadimpl.h>
+
 /*
  * This is the entry point automatically generated by GNAT.
  */
 extern int gnat_main ( int argc, char **argv, char **envp );
 
-void *POSIX_Init(
+static void *POSIX_Init(
   void *argument
 )
 {
@@ -21,28 +23,33 @@ void *POSIX_Init(
 }
 
 /*
- *  Only for sp04 and sp07
+ *  Prototypes for various test support routines. Since these are bound to
+ *  from Ada, there are no external .h files even though they must be public.
  */
-
+uint32_t milliseconds_per_tick(void);
-rtems_id tcb_to_id(
+uint32_t ticks_per_second(void);
-  Thread_Control *tcb
+uint32_t work_space_size(void);
-)
+uint32_t is_configured_multiprocessing(void);
-{
+uint32_t get_node(void);
-  return tcb->Object.id;
+rtems_id tcb_to_id(Thread_Control *tcb);
-}
-
 
 /*
  *  By putting this in brackets rather than quotes, we get the search
  *  path and can get this file from ".." in the mptests.
  */
-
 #define CONFIGURE_INIT
 #define CONFIGURE_GNAT_RTEMS
 #define CONFIGURE_MEMORY_OVERHEAD  (256)
 
 #include <config.h>
 
+rtems_id tcb_to_id(
+  Thread_Control *tcb
+)
+{
+  return tcb->Object.id; /* Only for sp04 and sp07 */
+}
+
 uint32_t milliseconds_per_tick(void)
 {
   return CONFIGURE_MICROSECONDS_PER_TICK / 1000;

c/src/lib/libbsp/arm/altera-cyclone-v/startup/linkcmds.altcycv

@@ -24,5 +24,6 @@ bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ? bsp_sectio
 bsp_vector_table_in_start_section = 1;
 
 bsp_translation_table_base = ORIGIN (RAM_MMU);
+bsp_translation_table_end = ORIGIN (RAM_MMU) + LENGTH (RAM_MMU);
 
 INCLUDE linkcmds.armv4

c/src/lib/libbsp/arm/beagle/Makefile.am

@@ -123,8 +123,9 @@ libbsp_a_SOURCES += ../../shared/clockdrv_shell.h
 
 # Cache
 libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
-libbsp_a_SOURCES += ../../../libcpu/arm/shared/include/cache_.h
+libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
-libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include
+libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
+libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
 
 ###############################################################################
 #                  Special Rules                                              #

c/src/lib/libbsp/arm/beagle/include/bsp.h

@@ -111,7 +111,13 @@ static inline void isb(void)
 /* flush data cache */
 static inline void flush_data_cache(void)
 {
-    asm volatile("mov r0, #0; mcr p15, #0, r0, c7, c10, #4" : : : "memory");
+    asm volatile(
+        "mov r0, #0\n"
+        "mcr p15, #0, r0, c7, c10, #4\n"
+        : /* No outputs */
+        : /* No inputs */
+        : "r0","memory"
+    );
 }
 
 #define __arch_getb(a)      (*(volatile unsigned char *)(a))

c/src/lib/libbsp/arm/csb336/Makefile.am

@@ -10,6 +10,7 @@ include_HEADERS = include/bsp.h
 include_HEADERS += ../../shared/include/tm27.h
 
 include_bsp_HEADERS =
+libbsp_a_CPPFLAGS =
 
 nodist_include_HEADERS = include/bspopts.h
 nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h
@@ -51,8 +52,9 @@ libbsp_a_SOURCES += ../../shared/src/irq-shell.c
 
 # Cache
 libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
-libbsp_a_SOURCES += ../../shared/include/cache_.h
+libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
-libbsp_a_CPPFLAGS = -I$(srcdir)/../../shared/include
+libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
+libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
 
 if HAS_NETWORKING
 network_CPPFLAGS = -D__INSIDE_RTEMS_BSD_TCPIP_STACK__

c/src/lib/libbsp/arm/csb337/Makefile.am

@@ -13,6 +13,7 @@ include_HEADERS += include/sed1356.h
 endif
 
 include_bsp_HEADERS =
+libbsp_a_CPPFLAGS =
 
 if ENABLE_UMON
 include_umondir = $(includedir)/umon
@@ -88,8 +89,9 @@ endif
 
 # Cache
 libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
-libbsp_a_SOURCES += ../../shared/include/cache_.h
+libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
-libbsp_a_CPPFLAGS = -I$(srcdir)/../../shared/include
+libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
+libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
 
 if HAS_NETWORKING
 network_CPPFLAGS = -D__INSIDE_RTEMS_BSD_TCPIP_STACK__

c/src/lib/libbsp/arm/lpc32xx/Makefile.am

@@ -145,8 +145,10 @@ libbsp_a_SOURCES += misc/idle-thread.c
 
 # Cache
 libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
-libbsp_a_SOURCES += ../../../libcpu/arm/shared/include/cache_.h
+libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
-libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include
+libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
+libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
+
 
 # Start hooks
 libbsp_a_SOURCES += startup/bspstarthooks.c

c/src/lib/libbsp/arm/raspberrypi/Makefile.am

@@ -45,8 +45,7 @@ include_bsp_HEADERS += include/mmu.h
 include_bsp_HEADERS += include/usart.h
 include_bsp_HEADERS += include/raspberrypi.h
 
-include_libcpu_HEADERS = ../../../libcpu/arm/shared/include/cache_.h \
+include_libcpu_HEADERS =  ../../../libcpu/arm/shared/include/arm-cp15.h
-    ../../../libcpu/arm/shared/include/arm-cp15.h
 
 ###############################################################################
 # Data                                                       #
@@ -88,6 +87,9 @@ libbsp_a_SOURCES += ../../shared/sbrk.c
 libbsp_a_SOURCES += ../../shared/src/stackalloc.c
 libbsp_a_SOURCES += ../shared/startup/bsp-start-memcpy.S
 libbsp_a_SOURCES += ../shared/arm-cp15-set-ttb-entries.c
+if BSP_START_IN_HYP_SUPPORT
+libbsp_a_SOURCES += ../shared/startup/bsp-start-in-hyp-support.S
+endif
 
 # Startup
 libbsp_a_SOURCES += ../../shared/bspreset_loop.c
@@ -125,8 +127,9 @@ libbsp_a_SOURCES += misc/timer.c
 
 # Cache
 libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
-libbsp_a_SOURCES += ../../../libcpu/arm/shared/include/cache_.h
+libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
-libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include
+libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
+libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
 
 # Start hooks
 libbsp_a_SOURCES += startup/bspstarthooks.c

c/src/lib/libbsp/arm/raspberrypi/configure.ac

@@ -24,6 +24,10 @@ AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
 RTEMS_BSPOPTS_SET([BSP_START_RESET_VECTOR],[*],[])
 RTEMS_BSPOPTS_HELP([BSP_START_RESET_VECTOR],[reset vector address for BSP start])
 
+RTEMS_BSPOPTS_SET([BSP_START_IN_HYP_SUPPORT],[*],[1])
+RTEMS_BSPOPTS_HELP([BSP_START_IN_HYP_SUPPORT], [Support start of BSP in ARM HYP mode])
+AM_CONDITIONAL(BSP_START_IN_HYP_SUPPORT,test "$BSP_START_IN_HYP_SUPPORT" = "1")
+
 # Is this a Raspberry Pi 2?
 RTEMS_BSPOPTS_SET([BSP_IS_RPI2],[raspberrypi2],[1])
 RTEMS_BSPOPTS_SET([BSP_IS_RPI2],[*],[0])

c/src/lib/libbsp/arm/raspberrypi/include/irq.h

@@ -51,20 +51,20 @@
 #define BCM2835_IRQ_ID_UART          57
 
 
+#define BCM2835_IRQ_ID_BASIC_BASE_ID 64
 #define BCM2835_IRQ_ID_TIMER_0       64
 #define BCM2835_IRQ_ID_MAILBOX_0     65
 #define BCM2835_IRQ_ID_DOORBELL_0    66
 #define BCM2835_IRQ_ID_DOORBELL_1    67
 #define BCM2835_IRQ_ID_GPU0_HALTED   68
+#define BCM2835_IRQ_ID_GPU1_HALTED   69
+#define BCM2835_IRQ_ID_ILL_ACCESS_1  70
+#define BCM2835_IRQ_ID_ILL_ACCESS_0  71
 
 #define BSP_INTERRUPT_VECTOR_MIN    (0)
 #define BSP_INTERRUPT_VECTOR_MAX    (BCM2835_INTC_TOTAL_IRQ - 1)
 
 #define BSP_IRQ_COUNT               (BCM2835_INTC_TOTAL_IRQ)
 
-
-void raspberrypi_set_exception_handler(Arm_symbolic_exception_name exception,
-                                         void (*handler)(void));
-
 #endif /* ASM */
 #endif /* LIBBSP_ARM_RASPBERRYPI_IRQ_H */

c/src/lib/libbsp/arm/raspberrypi/include/raspberrypi.h

@@ -20,6 +20,7 @@
 #ifndef LIBBSP_ARM_RASPBERRYPI_RASPBERRYPI_H
 #define LIBBSP_ARM_RASPBERRYPI_RASPBERRYPI_H
 
+#include <bspopts.h>
 #include <stdint.h>
 #include <bsp/utility.h>
 

c/src/lib/libbsp/arm/raspberrypi/irq/irq.c

@@ -1,5 +1,5 @@
 /**
- * @file
+ * @file irq.c
  *
  * @ingroup raspberrypi_interrupt
  *
@@ -7,6 +7,8 @@
  */
 
 /*
+ * Copyright (c) 2014 Andre Marques <andre.lousa.marques at gmail.com>
+ *
  * Copyright (c) 2009
  * embedded brains GmbH
  * Obere Lagerstr. 30
@@ -27,98 +29,130 @@
 #include <bsp/raspberrypi.h>
 #include <bsp/linker-symbols.h>
 #include <bsp/mmu.h>
+#include <rtems/bspIo.h>
+#include <strings.h>
 
-/*
+typedef struct {
-** This sets the main exception vectors
+  unsigned long enable_reg_addr;
-*/
+  unsigned long disable_reg_addr;
-void raspberrypi_set_exception_handler(
+} bcm2835_irq_ctrl_reg_t;
-                        Arm_symbolic_exception_name exception,
+
-                        void (*handler)(void)
+static const bcm2835_irq_ctrl_reg_t bcm2835_irq_ctrl_reg_table[] = {
-                                       )
+  { BCM2835_IRQ_ENABLE1, BCM2835_IRQ_DISABLE1 },
+  { BCM2835_IRQ_ENABLE2, BCM2835_IRQ_DISABLE2 },
+  { BCM2835_IRQ_ENABLE_BASIC, BCM2835_IRQ_DISABLE_BASIC }
+};
+
+static inline const bcm2835_irq_ctrl_reg_t *
+bsp_vector_to_reg(rtems_vector_number vector)
 {
-    if ((unsigned) exception < MAX_EXCEPTIONS)
+  return bcm2835_irq_ctrl_reg_table + (vector >> 5);
-    {
-        uint32_t *table = (uint32_t *) bsp_section_vector_begin + MAX_EXCEPTIONS;
-        table [exception] = (uint32_t) handler;
-
-    }
 }
 
+static inline uint32_t
+bsp_vector_to_mask(rtems_vector_number vector)
+{
+  return 1 << (vector & 0x1f);
+}
+
+static const int bcm2835_irq_speedup_table[] =
+{
+  /*  0 */ BCM2835_IRQ_ID_BASIC_BASE_ID +  0,
+  /*  1 */ BCM2835_IRQ_ID_BASIC_BASE_ID +  1,
+  /*  2 */ BCM2835_IRQ_ID_BASIC_BASE_ID +  2,
+  /*  3 */ BCM2835_IRQ_ID_BASIC_BASE_ID +  3,
+  /*  4 */ BCM2835_IRQ_ID_BASIC_BASE_ID +  4,
+  /*  5 */ BCM2835_IRQ_ID_BASIC_BASE_ID +  5,
+  /*  6 */ BCM2835_IRQ_ID_BASIC_BASE_ID +  6,
+  /*  7 */ BCM2835_IRQ_ID_BASIC_BASE_ID +  7,
+  /*  8 */ -1, /* One or more bits set in pending register 1 */
+  /*  9 */ -2, /* One or more bits set in pending register 2 */
+  /* 10 */  7, /* GPU IRQ 7 */
+  /* 11 */  9, /* GPU IRQ 9 */
+  /* 12 */ 10, /* GPU IRQ 10 */
+  /* 13 */ 18, /* GPU IRQ 18 */
+  /* 14 */ 19, /* GPU IRQ 19 */
+  /* 15 */ 53, /* GPU IRQ 53 */
+  /* 16 */ 54, /* GPU IRQ 54 */
+  /* 17 */ 55, /* GPU IRQ 55 */
+  /* 18 */ 56, /* GPU IRQ 56 */
+  /* 19 */ 57, /* GPU IRQ 57 */
+  /* 20 */ 62, /* GPU IRQ 62 */
+};
+
 /*
-** Determine the source of the interrupt and dispatch the correct handler.
+ * Define which basic peding register (BCM2835_IRQ_BASIC) bits
-*/
+ * should be processed through bcm2835_irq_speedup_table
+ */
+
+#define BCM2835_IRQ_BASIC_SPEEDUP_USED_BITS 0x1ffcff
+
+/*
+ * Determine the source of the interrupt and dispatch the correct handler.
+ */
 void bsp_interrupt_dispatch(void)
 {
+  unsigned int pend;
+  unsigned int pend_bit;
+
   rtems_vector_number vector = 255;
 
-  /* ARM timer */
+  pend = BCM2835_REG(BCM2835_IRQ_BASIC);
-  if (BCM2835_REG(BCM2835_IRQ_BASIC) && 0x1)
+  if ( pend & BCM2835_IRQ_BASIC_SPEEDUP_USED_BITS ) {
-  {
+    pend_bit = ffs(pend) - 1;
-      vector = BCM2835_IRQ_ID_TIMER_0;
+    vector = bcm2835_irq_speedup_table[pend_bit];
-
+  } else {
-  }
+    pend = BCM2835_REG(BCM2835_IRQ_PENDING1);
-  /* UART 0 */
+    if ( pend != 0 ) {
-  else if ( BCM2835_REG(BCM2835_IRQ_BASIC) && BCM2835_BIT(19))
+      pend_bit = ffs(pend) - 1;
-  {
+      vector = pend_bit;
-      vector = BCM2835_IRQ_ID_UART;
+    } else {
+      pend = BCM2835_REG(BCM2835_IRQ_PENDING2);
+      if ( pend != 0 ) {
+        pend_bit = ffs(pend) - 1;
+        vector = pend_bit + 32;
+      }
+    }
   }
 
   if ( vector < 255 )
   {
       bsp_interrupt_handler_dispatch(vector);
   }
-
 }
 
 rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
 {
-  rtems_interrupt_level  level;
+  if ( vector > BSP_INTERRUPT_VECTOR_MAX )
+    return RTEMS_INVALID_ID;
 
-  rtems_interrupt_disable(level);
+  BCM2835_REG(bsp_vector_to_reg(vector)->enable_reg_addr) =
-
+              bsp_vector_to_mask(vector);
-   /* ARM Timer */
-  if ( vector == BCM2835_IRQ_ID_TIMER_0 )
-  {
-      BCM2835_REG(BCM2835_IRQ_ENABLE_BASIC) = 0x1;
-  }
-  /* UART 0 */
-  else if ( vector == BCM2835_IRQ_ID_UART )
-  {
-      BCM2835_REG(BCM2835_IRQ_ENABLE2) =  BCM2835_BIT(25);
-
-  }
-  rtems_interrupt_enable(level);
 
   return RTEMS_SUCCESSFUL;
 }
 
 rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
 {
-  rtems_interrupt_level level;
+  if ( vector > BSP_INTERRUPT_VECTOR_MAX )
+    return RTEMS_INVALID_ID;
 
-  rtems_interrupt_disable(level);
+  BCM2835_REG(bsp_vector_to_reg(vector)->disable_reg_addr) =
-
+              bsp_vector_to_mask(vector);
-  if ( vector == BCM2835_IRQ_ID_TIMER_0 )
-  {
-      BCM2835_REG(BCM2835_IRQ_DISABLE_BASIC) = 0x1;
-  }
-  else if ( vector == BCM2835_IRQ_ID_UART )
-  {
-      BCM2835_REG(BCM2835_IRQ_DISABLE2) = BCM2835_BIT(25);
-  }
-  rtems_interrupt_enable(level);
 
   return RTEMS_SUCCESSFUL;
 }
 
-
 void bsp_interrupt_handler_default(rtems_vector_number vector)
 {
-    printk("spurious interrupt: %u\n", vector);
+    printk("spurious interrupt: %lu\n", vector);
 }
 
 rtems_status_code bsp_interrupt_facility_initialize(void)
 {
-   raspberrypi_set_exception_handler(ARM_EXCEPTION_IRQ, _ARMV4_Exception_interrupt);
+   BCM2835_REG(BCM2835_IRQ_DISABLE1) = 0xffffffff;
+   BCM2835_REG(BCM2835_IRQ_DISABLE2) = 0xffffffff;
+   BCM2835_REG(BCM2835_IRQ_DISABLE_BASIC) = 0xffffffff;
+   BCM2835_REG(BCM2835_IRQ_FIQ_CTRL) = 0;
    return RTEMS_SUCCESSFUL;
 }

c/src/lib/libbsp/arm/raspberrypi/misc/timer.c

@@ -16,6 +16,7 @@
  *
  */
 
+#include <bsp.h>
 #include <rtems.h>
 #include <rtems/btimer.h>
 #include <bsp/raspberrypi.h>

c/src/lib/libbsp/arm/raspberrypi/preinstall.am

@@ -130,10 +130,6 @@ $(PROJECT_INCLUDE)/bsp/raspberrypi.h: include/raspberrypi.h $(PROJECT_INCLUDE)/b
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/raspberrypi.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/raspberrypi.h
 
-$(PROJECT_INCLUDE)/libcpu/cache_.h: ../../../libcpu/arm/shared/include/cache_.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/cache_.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/cache_.h
-
 $(PROJECT_INCLUDE)/libcpu/arm-cp15.h: ../../../libcpu/arm/shared/include/arm-cp15.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/arm-cp15.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/arm-cp15.h

c/src/lib/libbsp/arm/raspberrypi/startup/bspstarthooks.c

@@ -26,11 +26,46 @@
 #include <bsp/start.h>
 #include <bsp/raspberrypi.h>
 #include <bsp/mm.h>
+#include <libcpu/arm-cp15.h>
+#include <bsp.h>
 
 void BSP_START_TEXT_SECTION bsp_start_hook_0(void)
 {
-}
+  uint32_t sctlr_val;
 
+  sctlr_val = arm_cp15_get_control();
+
+  /*
+   * Current U-boot loader seems to start kernel image
+   * with I and D caches on and MMU enabled.
+   * If RTEMS application image finds that cache is on
+   * during startup then disable caches.
+   */
+  if (sctlr_val & (ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M)) {
+    if (sctlr_val & (ARM_CP15_CTRL_C | ARM_CP15_CTRL_M)) {
+      /*
+       * If the data cache is on then ensure that it is clean
+       * before switching off to be extra carefull.
+       */
+      rtems_cache_flush_entire_data();
+      rtems_cache_invalidate_entire_data();
+    }
+    arm_cp15_flush_prefetch_buffer();
+    sctlr_val &= ~(ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M | ARM_CP15_CTRL_A);
+    arm_cp15_set_control(sctlr_val);
+  }
+  rtems_cache_invalidate_entire_data();
+  rtems_cache_invalidate_entire_instruction();
+  arm_cp15_branch_predictor_invalidate_all();
+  arm_cp15_tlb_invalidate();
+  arm_cp15_flush_prefetch_buffer();
+
+  /* Clear Translation Table Base Control Register */
+  arm_cp15_set_translation_table_base_control_register(0);
+
+  /* Clear Secure or Non-secure Vector Base Address Register */
+  arm_cp15_set_vector_base_address(0);
+}
 
 void BSP_START_TEXT_SECTION bsp_start_hook_1(void)
 {

c/src/lib/libbsp/arm/raspberrypi/startup/linkcmds

@@ -36,9 +36,9 @@
  */
 
 MEMORY {
-        VECTOR_RAM     (AIW) : ORIGIN = 0x0       , LENGTH = 0x8000
+        VECTOR_RAM     (AIW) : ORIGIN = 0x0       , LENGTH = 16k
-        RAM            (AIW) : ORIGIN = 0x00008000, LENGTH = 128M - 48K
+	RAM_MMU        (AIW) : ORIGIN = 0x00004000, LENGTH = 16k
-	RAM_MMU        (AIW) : ORIGIN = 128M - 16k, LENGTH = 16k
+        RAM            (AIW) : ORIGIN = 0x00008000, LENGTH = 128M - 32k
 }
 
 REGION_ALIAS ("REGION_START", RAM);

c/src/lib/libbsp/arm/raspberrypi/startup/mm_config_table.c

@@ -23,31 +23,44 @@
 #include <bsp.h>
 #include <bsp/arm-cp15-start.h>
 
+/*
+ * Pagetable initialization data
+ *
+ * Keep all read-only sections before read-write ones.
+ * This ensures that write is allowed if one page/region
+ * is partially filled by read-only section contentent
+ * and rest is used for writeable section
+ */
+
 const arm_cp15_start_section_config arm_cp15_start_mmu_config_table[] = {
   {
     .begin = (uint32_t) bsp_section_fast_text_begin,
     .end = (uint32_t) bsp_section_fast_text_end,
     .flags = ARMV7_MMU_CODE_CACHED
-  }, {
-    .begin = (uint32_t) bsp_section_fast_data_begin,
-    .end = (uint32_t) bsp_section_fast_data_end,
-    .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED
   }, {
     .begin = (uint32_t) bsp_section_start_begin,
     .end = (uint32_t) bsp_section_start_end,
     .flags = ARMV7_MMU_CODE_CACHED
-  }, {
-    .begin = (uint32_t) bsp_section_vector_begin,
-    .end = (uint32_t) bsp_section_vector_end,
-    .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED
   }, {
     .begin = (uint32_t) bsp_section_text_begin,
     .end = (uint32_t) bsp_section_text_end,
-    .flags = ARMV7_MMU_READ_WRITE
+    .flags = ARMV7_MMU_CODE_CACHED
   }, {
     .begin = (uint32_t) bsp_section_rodata_begin,
     .end = (uint32_t) bsp_section_rodata_end,
     .flags = ARMV7_MMU_DATA_READ_ONLY_CACHED
+  }, {
+    .begin = (uint32_t) bsp_translation_table_base,
+    .end = (uint32_t) bsp_translation_table_base + 0x4000,
+    .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED
+  }, {
+    .begin = (uint32_t) bsp_section_fast_data_begin,
+    .end = (uint32_t) bsp_section_fast_data_end,
+    .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED
+  }, {
+    .begin = (uint32_t) bsp_section_vector_begin,
+    .end = (uint32_t) bsp_section_vector_end,
+    .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED
   }, {
     .begin = (uint32_t) bsp_section_data_begin,
     .end = (uint32_t) bsp_section_data_end,

c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am

@@ -125,8 +125,9 @@ libbsp_a_SOURCES += ../shared/arm-a9mpcore-clock-config.c
 
 # Cache
 libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
-libbsp_a_SOURCES += ../../../libcpu/arm/shared/include/cache_.h
+libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
-libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include
+libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
+libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
 
 # Start hooks
 libbsp_a_SOURCES += startup/bspstarthooks.c

c/src/lib/libbsp/arm/realview-pbx-a9/startup/linkcmds.realview_pbx_a9_qemu

@@ -30,5 +30,6 @@ bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ? bsp_sectio
 bsp_vector_table_in_start_section = 1;
 
 bsp_translation_table_base = ORIGIN (RAM_MMU);
+bsp_translation_table_end = ORIGIN (RAM_MMU) + LENGTH (RAM_MMU);
 
 INCLUDE linkcmds.armv4

c/src/lib/libbsp/arm/shared/arm-cp15-set-ttb-entries.c

@@ -12,35 +12,69 @@
  * http://www.rtems.org/license/LICENSE.
  */
 
+#include <rtems.h>
 #include <libcpu/arm-cp15.h>
 
+/*
+ * Translation table modification requires to propagate
+ * information to memory and other cores.
+ *
+ * Algorithm follows example found in the section
+ *
+ * B3.10.1 General TLB maintenance requirements
+ * TLB maintenance operations and the memory order model
+ *
+ * of ARM Architecture Reference Manual
+ * ARMv7-A and ARMv7-R edition
+ * ARM DDI 0406C.b (ID072512)
+ */
+
 static uint32_t set_translation_table_entries(
   const void *begin,
   const void *end,
   uint32_t section_flags
 )
 {
-  uint32_t cl_size = arm_cp15_get_min_cache_line_size();
   uint32_t *ttb = arm_cp15_get_translation_table_base();
-  uint32_t i = ARM_MMU_SECT_GET_INDEX(begin);
+  uint32_t istart = ARM_MMU_SECT_GET_INDEX(begin);
   uint32_t iend = ARM_MMU_SECT_GET_INDEX(ARM_MMU_SECT_MVA_ALIGN_UP(end));
   uint32_t index_mask = (1U << (32 - ARM_MMU_SECT_BASE_SHIFT)) - 1U;
   uint32_t ctrl;
   uint32_t section_flags_of_first_entry;
+  uint32_t i;
+  void *first_ttb_addr;
+  void *last_ttb_end;
 
-  ctrl = arm_cp15_mmu_disable(cl_size);
+  ctrl = arm_cp15_get_control();
-  arm_cp15_tlb_invalidate();
+  section_flags_of_first_entry = ttb [istart];
-  section_flags_of_first_entry = ttb [i];
+  last_ttb_end = first_ttb_addr = ttb + istart;
 
-  while (i != iend) {
+  for ( i = istart; i != iend; i = (i + 1U) & index_mask ) {
     uint32_t addr = i << ARM_MMU_SECT_BASE_SHIFT;
 
     ttb [i] = addr | section_flags;
-
+    last_ttb_end = ttb + i + 1;
-    i = (i + 1U) & index_mask;
   }
 
-  arm_cp15_set_control(ctrl);
+  if ( ctrl & (ARM_CP15_CTRL_C | ARM_CP15_CTRL_M ) ) {
+    rtems_cache_flush_multiple_data_lines(first_ttb_addr,
+                last_ttb_end - first_ttb_addr);
+  }
+
+  _ARM_Data_synchronization_barrier();
+
+  for ( i = istart; i != iend; i = (i + 1U) & index_mask ) {
+    void *mva = (void *) (i << ARM_MMU_SECT_BASE_SHIFT);
+    #if defined(__ARM_ARCH_7A__)
+    arm_cp15_tlb_invalidate_entry_all_asids(mva);
+    #else
+    arm_cp15_tlb_instruction_invalidate_entry(mva);
+    arm_cp15_tlb_data_invalidate_entry(mva);
+    #endif
+  }
+
+  _ARM_Data_synchronization_barrier();
+  _ARM_Instruction_synchronization_barrier();
 
   return section_flags_of_first_entry;
 }
@@ -51,13 +85,5 @@ uint32_t arm_cp15_set_translation_table_entries(
   uint32_t section_flags
 )
 {
-  rtems_interrupt_level level;
+  return set_translation_table_entries(begin, end, section_flags);
-  uint32_t section_flags_of_first_entry;
-
-  rtems_interrupt_disable(level);
-  section_flags_of_first_entry =
-    set_translation_table_entries(begin, end, section_flags);
-  rtems_interrupt_enable(level);
-
-  return section_flags_of_first_entry;
 }

c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h

@@ -72,6 +72,10 @@ extern "C" {
 /* These two defines also ensure that the rtems_cache_* functions have bodies */
 #define CPU_DATA_CACHE_ALIGNMENT ARM_CACHE_L1_CPU_DATA_ALIGNMENT
 #define CPU_INSTRUCTION_CACHE_ALIGNMENT ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT
+#if defined(__ARM_ARCH_7A__)
+/* Some/many ARM Cortex-A cores have L1 data line lenght 64 bytes */
+#define CPU_MAXIMAL_CACHE_ALIGNMENT 64
+#endif
 #define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS \
   ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS
 #define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS

c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h

@@ -0,0 +1,187 @@
+/**
+ * @file
+ *
+ * @ingroup arm
+ *
+ * @brief ARM cache defines and implementation.
+ */
+
+/*
+ * Copyright (c) 2009-2011 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Obere Lagerstr. 30
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_ARMV467AR_BASIC_CACHE_H
+#define LIBBSP_ARM_ARMV467AR_BASIC_CACHE_H
+
+#include <libcpu/arm-cp15.h>
+#include "../include/arm-cache-l1.h"
+
+#define CPU_DATA_CACHE_ALIGNMENT 32
+#define CPU_INSTRUCTION_CACHE_ALIGNMENT 32
+#if defined(__ARM_ARCH_7A__)
+/* Some/many ARM Cortex-A cores have L1 data line lenght 64 bytes */
+#define CPU_MAXIMAL_CACHE_ALIGNMENT 64
+#endif
+
+#define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS \
+          ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS
+
+
+static inline void _CPU_cache_flush_1_data_line(const void *d_addr)
+{
+  arm_cache_l1_flush_1_data_line(d_addr);
+}
+
+static inline void
+_CPU_cache_flush_data_range(
+  const void *d_addr,
+  size_t      n_bytes
+)
+{
+  _ARM_Data_synchronization_barrier();
+  arm_cache_l1_flush_data_range(
+    d_addr,
+    n_bytes
+  );
+  #if !defined(__ARM_ARCH_7A__)
+  arm_cp15_drain_write_buffer();
+  #endif
+ _ARM_Data_synchronization_barrier();
+}
+
+static inline void _CPU_cache_invalidate_1_data_line(const void *d_addr)
+{
+  arm_cache_l1_invalidate_1_data_line(d_addr);
+}
+
+static inline void
+_CPU_cache_invalidate_data_range(
+  const void *addr_first,
+  size_t     n_bytes
+)
+{
+  arm_cache_l1_invalidate_data_range(
+    addr_first,
+    n_bytes
+  );
+}
+
+static inline void _CPU_cache_freeze_data(void)
+{
+  /* TODO */
+}
+
+static inline void _CPU_cache_unfreeze_data(void)
+{
+  /* TODO */
+}
+
+static inline void _CPU_cache_invalidate_1_instruction_line(const void *d_addr)
+{
+  arm_cache_l1_invalidate_1_instruction_line(d_addr);
+}
+
+static inline void
+_CPU_cache_invalidate_instruction_range( const void *i_addr, size_t n_bytes)
+{
+  arm_cache_l1_invalidate_instruction_range( i_addr, n_bytes );
+  _ARM_Instruction_synchronization_barrier();
+}
+
+static inline void _CPU_cache_freeze_instruction(void)
+{
+  /* TODO */
+}
+
+static inline void _CPU_cache_unfreeze_instruction(void)
+{
+  /* TODO */
+}
+
+static inline void _CPU_cache_flush_entire_data(void)
+{
+  _ARM_Data_synchronization_barrier();
+  #if defined(__ARM_ARCH_7A__)
+  arm_cp15_data_cache_clean_all_levels();
+  #else
+  arm_cp15_data_cache_clean_and_invalidate();
+  arm_cp15_drain_write_buffer();
+  #endif
+  _ARM_Data_synchronization_barrier();
+}
+
+static inline void _CPU_cache_invalidate_entire_data(void)
+{
+  #if defined(__ARM_ARCH_7A__)
+  arm_cp15_data_cache_invalidate_all_levels();
+  #else
+  arm_cp15_data_cache_invalidate();
+  #endif
+}
+
+static inline void _CPU_cache_enable_data(void)
+{
+  rtems_interrupt_level level;
+  uint32_t ctrl;
+
+  rtems_interrupt_local_disable(level);
+  ctrl = arm_cp15_get_control();
+  ctrl |= ARM_CP15_CTRL_C;
+  arm_cp15_set_control(ctrl);
+  rtems_interrupt_local_enable(level);
+}
+
+static inline void _CPU_cache_disable_data(void)
+{
+  rtems_interrupt_level level;
+  uint32_t ctrl;
+
+  rtems_interrupt_local_disable(level);
+  arm_cp15_data_cache_test_and_clean_and_invalidate();
+  ctrl = arm_cp15_get_control();
+  ctrl &= ~ARM_CP15_CTRL_C;
+  arm_cp15_set_control(ctrl);
+  rtems_interrupt_local_enable(level);
+}
+
+static inline void _CPU_cache_invalidate_entire_instruction(void)
+{
+  arm_cache_l1_invalidate_entire_instruction();
+  _ARM_Instruction_synchronization_barrier();
+}
+
+static inline void _CPU_cache_enable_instruction(void)
+{
+  rtems_interrupt_level level;
+  uint32_t ctrl;
+
+  rtems_interrupt_local_disable(level);
+  ctrl = arm_cp15_get_control();
+  ctrl |= ARM_CP15_CTRL_I;
+  arm_cp15_set_control(ctrl);
+  rtems_interrupt_local_enable(level);
+}
+
+static inline void _CPU_cache_disable_instruction(void)
+{
+  rtems_interrupt_level level;
+  uint32_t ctrl;
+
+  rtems_interrupt_local_disable(level);
+  ctrl = arm_cp15_get_control();
+  ctrl &= ~ARM_CP15_CTRL_I;
+  arm_cp15_set_control(ctrl);
+  rtems_interrupt_local_enable(level);
+}
+
+#endif /* LIBBSP_ARM_ARMV467AR_BASIC_CACHE_H */

c/src/lib/libbsp/arm/shared/armv7m/clock/armv7m-clock-config.c

@@ -23,7 +23,12 @@
 /* This is defined in clockdrv_shell.h */
 static void Clock_isr(void *arg);
 
-static rtems_timecounter_simple _ARMV7M_TC;
+typedef struct {
+  rtems_timecounter_simple base;
+  bool countflag;
+} ARMV7M_Timecounter;
+
+static ARMV7M_Timecounter _ARMV7M_TC;
 
 static uint32_t _ARMV7M_TC_get(rtems_timecounter_simple *tc)
 {
@@ -32,11 +37,25 @@ static uint32_t _ARMV7M_TC_get(rtems_timecounter_simple *tc)
   return systick->cvr;
 }
 
-static bool _ARMV7M_TC_is_pending(rtems_timecounter_simple *tc)
+static bool _ARMV7M_TC_is_pending(rtems_timecounter_simple *base)
 {
-  volatile ARMV7M_SCB *scb = _ARMV7M_SCB;
+  ARMV7M_Timecounter *tc = (ARMV7M_Timecounter *) base;
+  rtems_interrupt_level level;
+  bool countflag;
 
-  return ((scb->icsr & ARMV7M_SCB_ICSR_PENDSTSET) != 0);
+  rtems_interrupt_disable(level);
+
+  countflag = tc->countflag;
+  if (!countflag) {
+    volatile ARMV7M_Systick *systick = _ARMV7M_Systick;
+
+    countflag = ((systick->csr & ARMV7M_SYSTICK_CSR_COUNTFLAG) != 0);
+    tc->countflag = countflag;
+  }
+
+  rtems_interrupt_enable(level);
+
+  return countflag;
 }
 
 static uint32_t _ARMV7M_TC_get_timecount(struct timecounter *tc)
@@ -48,19 +67,26 @@ static uint32_t _ARMV7M_TC_get_timecount(struct timecounter *tc)
   );
 }
 
-static void _ARMV7M_TC_tick(void)
+static void _ARMV7M_TC_at_tick(rtems_timecounter_simple *base)
-{
-  rtems_timecounter_simple_downcounter_tick(&_ARMV7M_TC, _ARMV7M_TC_get);
-}
-
-static void _ARMV7M_Systick_at_tick(void)
 {
+  ARMV7M_Timecounter *tc = (ARMV7M_Timecounter *) base;
   volatile ARMV7M_Systick *systick = _ARMV7M_Systick;
 
+  tc->countflag = false;
+
   /* Clear COUNTFLAG */
   systick->csr;
 }
 
+static void _ARMV7M_TC_tick(void)
+{
+  rtems_timecounter_simple_downcounter_tick(
+    &_ARMV7M_TC.base,
+    _ARMV7M_TC_get,
+    _ARMV7M_TC_at_tick
+  );
+}
+
 static void _ARMV7M_Systick_handler(void)
 {
   _ARMV7M_Interrupt_service_enter();
@@ -95,7 +121,7 @@ static void _ARMV7M_Systick_initialize(void)
     | ARMV7M_SYSTICK_CSR_CLKSOURCE;
 
   rtems_timecounter_simple_install(
-    &_ARMV7M_TC,
+    &_ARMV7M_TC.base,
     freq,
     interval,
     _ARMV7M_TC_get_timecount
@@ -111,9 +137,6 @@ static void _ARMV7M_Systick_cleanup(void)
 
 #define Clock_driver_timecounter_tick() _ARMV7M_TC_tick()
 
-#define Clock_driver_support_at_tick() \
-  _ARMV7M_Systick_at_tick()
-
 #define Clock_driver_support_initialize_hardware() \
   _ARMV7M_Systick_initialize()
 

c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h

@@ -37,8 +37,10 @@ extern "C" {
 #define ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT 32
 #define ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS
 
-#define ARM_CACHE_L1_CSS_ID_DATA 0
+#define ARM_CACHE_L1_CSS_ID_DATA \
-#define ARM_CACHE_L1_CSS_ID_INSTRUCTION 1
+          (ARM_CP15_CACHE_CSS_ID_DATA | ARM_CP15_CACHE_CSS_LEVEL(0))
+#define ARM_CACHE_L1_CSS_ID_INSTRUCTION \
+          (ARM_CP15_CACHE_CSS_ID_INSTRUCTION | ARM_CP15_CACHE_CSS_LEVEL(0))
 #define ARM_CACHE_L1_DATA_LINE_MASK ( ARM_CACHE_L1_CPU_DATA_ALIGNMENT - 1 )
 #define ARM_CACHE_L1_INSTRUCTION_LINE_MASK \
   ( ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT \
@@ -52,15 +54,6 @@ static void arm_cache_l1_errata_764369_handler( void )
 #endif
 }
 
-static void arm_cache_l1_select( const uint32_t selection )
-{
-  /* select current cache level in cssr */
-  arm_cp15_set_cache_size_selection( selection );
-
-  /* isb to sych the new cssr&csidr */
-  _ARM_Instruction_synchronization_barrier();
-}
-
 /*
  * @param l1LineSize      Number of bytes in cache line expressed as power of 
  *                        2 value
@@ -69,22 +62,23 @@ static void arm_cache_l1_select( const uint32_t selection )
  * qparam liNumSets       Number of sets in cache
  * */
 
-static inline void arm_cache_l1_properties( 
+static inline void arm_cache_l1_properties_for_level(
   uint32_t *l1LineSize,
   uint32_t *l1Associativity,
-  uint32_t *l1NumSets )
+  uint32_t *l1NumSets,
+  uint32_t level_and_inst_dat
+)
 {
-  uint32_t id;
+  uint32_t ccsidr;
 
-  _ARM_Instruction_synchronization_barrier();
+  ccsidr = arm_cp15_get_cache_size_id_for_level(level_and_inst_dat);
-  id               = arm_cp15_get_cache_size_id();
 
   /* Cache line size in words + 2 -> bytes) */
-  *l1LineSize      = ( id & 0x0007U ) + 2 + 2;
+  *l1LineSize      = arm_ccsidr_get_line_power(ccsidr);
   /* Number of Ways */
-  *l1Associativity = ( ( id >> 3 ) & 0x03ffU ) + 1; 
+  *l1Associativity = arm_ccsidr_get_associativity(ccsidr);
   /* Number of Sets */
-  *l1NumSets       = ( ( id >> 13 ) & 0x7fffU ) + 1;
+  *l1NumSets       = arm_ccsidr_get_num_sets(ccsidr);
 }
 
 /*
@@ -130,8 +124,9 @@ static inline void arm_cache_l1_flush_entire_data( void )
   _ARM_Data_memory_barrier();
 
   /* Get the L1 cache properties */
-  arm_cache_l1_properties( &l1LineSize, &l1Associativity,
+  arm_cache_l1_properties_for_level( &l1LineSize,
-                                     &l1NumSets );
+                    &l1Associativity, &l1NumSets,
+                    ARM_CACHE_L1_CSS_ID_DATA);
 
   for ( w = 0; w < l1Associativity; ++w ) {
     for ( s = 0; s < l1NumSets; ++s ) {
@@ -160,8 +155,9 @@ static inline void arm_cache_l1_invalidate_entire_data( void )
   _ARM_Data_memory_barrier();
 
   /* Get the L1 cache properties */
-  arm_cache_l1_properties( &l1LineSize, &l1Associativity,
+  arm_cache_l1_properties_for_level( &l1LineSize,
-                                     &l1NumSets );
+                    &l1Associativity, &l1NumSets,
+                    ARM_CACHE_L1_CSS_ID_DATA);
 
   for ( w = 0; w < l1Associativity; ++w ) {
     for ( s = 0; s < l1NumSets; ++s ) {
@@ -191,8 +187,9 @@ static inline void arm_cache_l1_clean_and_invalidate_entire_data( void )
 
 
   /* Get the L1 cache properties */
-  arm_cache_l1_properties( &l1LineSize, &l1Associativity,
+  arm_cache_l1_properties_for_level( &l1LineSize,
-                                     &l1NumSets );
+                    &l1Associativity, &l1NumSets,
+                    ARM_CACHE_L1_CSS_ID_DATA);
 
   for ( w = 0; w < l1Associativity; ++w ) {
     for ( s = 0; s < l1NumSets; ++s ) {
@@ -332,9 +329,13 @@ static inline void arm_cache_l1_invalidate_entire_instruction( void )
   arm_cp15_instruction_cache_invalidate();
   #endif /* RTEMS_SMP */
 
-  if ( ( ctrl & ARM_CP15_CTRL_Z ) == 0 ) {
+  if ( ( ctrl & ARM_CP15_CTRL_Z ) != 0 ) {
+    #if defined(__ARM_ARCH_7A__)
     arm_cp15_branch_predictor_inner_shareable_invalidate_all();
+    #endif
+    #if defined(__ARM_ARCH_6KZ__) || defined(__ARM_ARCH_7A__)
     arm_cp15_branch_predictor_invalidate_all();
+    #endif
   }
 }
 
@@ -371,19 +372,14 @@ static inline void arm_cache_l1_disable_instruction( void )
 
 static inline size_t arm_cache_l1_get_data_cache_size( void )
 {
-  rtems_interrupt_level level;
   size_t   size;
   uint32_t line_size     = 0;
   uint32_t associativity = 0;
   uint32_t num_sets      = 0;
 
-  rtems_interrupt_disable(level);
+  arm_cache_l1_properties_for_level( &line_size,
-
+                    &associativity, &num_sets,
-  arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_DATA );
+                    ARM_CACHE_L1_CSS_ID_DATA);
-  arm_cache_l1_properties( &line_size, &associativity,
-                           &num_sets );
-
-  rtems_interrupt_enable(level);
 
   size = (1 << line_size) * associativity * num_sets;
 
@@ -392,22 +388,17 @@ static inline size_t arm_cache_l1_get_data_cache_size( void )
 
 static inline size_t arm_cache_l1_get_instruction_cache_size( void )
 {
-  rtems_interrupt_level level;
   size_t   size;
   uint32_t line_size     = 0;
   uint32_t associativity = 0;
   uint32_t num_sets      = 0;
 
-  rtems_interrupt_disable(level);
+  arm_cache_l1_properties_for_level( &line_size,
-
+                    &associativity, &num_sets,
-  arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_INSTRUCTION );
+                    ARM_CACHE_L1_CSS_ID_INSTRUCTION);
-  arm_cache_l1_properties( &line_size, &associativity,
-                           &num_sets );
-
-  rtems_interrupt_enable(level);
 
   size = (1 << line_size) * associativity * num_sets;
-  
+
   return size;
 }
 

c/src/lib/libbsp/arm/shared/include/arm-cp15-start.h

@@ -84,6 +84,10 @@ typedef struct {
     .begin = (uint32_t) bsp_section_nocache_begin, \
     .end = (uint32_t) bsp_section_nocache_end, \
     .flags = ARMV7_MMU_DEVICE \
+  }, { \
+    .begin = (uint32_t) bsp_translation_table_base, \
+    .end = (uint32_t) bsp_translation_table_end, \
+    .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED \
   }
 
 BSP_START_DATA_SECTION extern const arm_cp15_start_section_config

c/src/lib/libbsp/arm/shared/include/arm-errata.h

@@ -77,10 +77,10 @@ static bool arm_errata_is_applicable_processor_errata_764369(
     case ARM_RELEASE_ID_R2_P2:
     case ARM_RELEASE_ID_R2_P0:
       is_applicable = true;
-    break;
+      break;
     default:
       is_applicable = false;
-    break;
+      break;
   }
   
   return is_applicable;
@@ -116,9 +116,10 @@ static bool arm_errata_is_applicable_processor_errata_775420(
     case ARM_RELEASE_ID_R2_P3:
     case ARM_RELEASE_ID_R2_P2:
       is_applicable = true;
+      break;
     default:
       is_applicable = false;
-    break;
+      break;
   }
   
   return is_applicable;
@@ -129,4 +130,4 @@ static bool arm_errata_is_applicable_processor_errata_775420(
 }
 #endif /* __cplusplus */
 
-#endif /* ARM_ERRATA_H_ */
+#endif /* ARM_ERRATA_H_ */

c/src/lib/libbsp/arm/shared/include/linker-symbols.h

@@ -59,6 +59,10 @@ LINKER_SYMBOL(bsp_stack_und_begin)
 LINKER_SYMBOL(bsp_stack_und_end)
 LINKER_SYMBOL(bsp_stack_und_size)
 
+LINKER_SYMBOL(bsp_stack_hyp_begin)
+LINKER_SYMBOL(bsp_stack_hyp_end)
+LINKER_SYMBOL(bsp_stack_hyp_size)
+
 LINKER_SYMBOL(bsp_stack_svc_begin)
 LINKER_SYMBOL(bsp_stack_svc_end)
 LINKER_SYMBOL(bsp_stack_svc_size)

c/src/lib/libbsp/arm/shared/include/start.h

@@ -45,6 +45,15 @@ extern "C" {
 
 #define BSP_START_DATA_SECTION __attribute__((section(".bsp_start_data")))
 
+/*
+* Many ARM boot loaders pass arguments to loaded OS kernel
+*/
+#ifdef BSP_START_HOOKS_WITH_LOADER_ARGS
+#define BSP_START_HOOKS_LOADER_ARGS int saved_psr, int saved_machid, int saved_dtb_adr
+#else
+#define BSP_START_HOOKS_LOADER_ARGS void
+#endif
+
 /**
 * @brief System start entry.
 */
@@ -57,7 +66,7 @@ void _start(void);
 * stack pointers are initialized but before the copying of the exception
 * vectors.
 */
-void bsp_start_hook_0(void);
+void bsp_start_hook_0(BSP_START_HOOKS_LOADER_ARGS);
 
 /**
 * @brief Start entry hook 1.
@@ -65,7 +74,7 @@ void bsp_start_hook_0(void);
 * This hook will be called from the start entry code after copying of the
 * exception vectors but before the call to boot_card().
 */
-void bsp_start_hook_1(void);
+void bsp_start_hook_1(BSP_START_HOOKS_LOADER_ARGS);
 
 /**
  * @brief Similar to standard memcpy().

c/src/lib/libbsp/arm/shared/start/start.S

@@ -54,12 +54,18 @@
 	.extern bsp_start_init_registers_vfp
 #endif
 
+#ifdef BSP_START_IN_HYP_SUPPORT
+	.extern	bsp_start_arm_drop_hyp_mode
+	.globl	bsp_start_hyp_vector_table_begin
+#endif
+
 	/* Global symbols */
 	.globl	_start
 	.globl	bsp_start_vector_table_begin
 	.globl	bsp_start_vector_table_end
 	.globl	bsp_start_vector_table_size
 	.globl	bsp_vector_table_size
+	.globl	bsp_start_hook_0_done
 
 	.section	".bsp_start_text", "ax"
 
@@ -124,16 +130,56 @@ handler_addr_fiq:
 
 bsp_start_vector_table_end:
 
+#ifdef BSP_START_IN_HYP_SUPPORT
+bsp_start_hyp_vector_table_begin:
+	ldr	pc, handler_addr_hyp_reset
+	ldr	pc, handler_addr_hyp_undef
+	ldr	pc, handler_addr_hyp_swi
+	ldr	pc, handler_addr_hyp_prefetch
+	ldr	pc, handler_addr_hyp_abort
+	ldr	pc, handler_addr_hyp_hyp
+	ldr	pc, handler_addr_hyp_irq
+	ldr	pc, handler_addr_hyp_fiq
+
+handler_addr_hyp_reset:
+	.word	_ARMV4_Exception_reserved_default
+
+handler_addr_hyp_undef:
+	.word	_ARMV4_Exception_reserved_default
+
+handler_addr_hyp_swi:
+	.word	_ARMV4_Exception_reserved_default
+
+handler_addr_hyp_prefetch:
+	.word	_ARMV4_Exception_reserved_default
+
+handler_addr_hyp_abort:
+	.word	_ARMV4_Exception_reserved_default
+
+handler_addr_hyp_hyp:
+	.word	_ARMV4_Exception_reserved_default
+
+handler_addr_hyp_irq:
+	.word	_ARMV4_Exception_reserved_default
+
+handler_addr_hyp_fiq:
+	.word	_ARMV4_Exception_reserved_default
+
+bsp_start_hyp_vector_table_end:
+#endif
+
 /* Start entry */
 
 _start:
 
 	/*
 	 * We do not save the context since we do not return to the boot
-	 * loader.
+	 * loader but preserve r1 and r2 to allow access to bootloader parameters
 	 */
-
+#ifndef BSP_START_NEEDS_REGISTER_INITIALIZATION
-#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
+	mov	r5, r1		/* machine type number or ~0 for DT boot */
+	mov	r6, r2		/* physical address of ATAGs or DTB */
+#else /* BSP_START_NEEDS_REGISTER_INITIALIZATION */
 	bl bsp_start_init_registers_core
 #endif
 
@@ -147,6 +193,24 @@ _start:
 	mul	r1, r0
 #endif
 
+	mrs	r4, cpsr	/* save original procesor status value  */
+#ifdef BSP_START_IN_HYP_SUPPORT
+	orr	r0, r4, #(ARM_PSR_I | ARM_PSR_F)
+	msr	cpsr, r4
+
+	and	r0, r4, #ARM_PSR_M_MASK
+	cmp	r0, #ARM_PSR_M_HYP
+	bne	bsp_start_skip_hyp_svc_switch
+
+	/* Boot loader stats kernel in HYP mode, switch to SVC necessary */
+	ldr	sp, =bsp_stack_hyp_end
+#ifdef RTEMS_SMP
+	add	sp, r1
+#endif
+	bl	bsp_start_arm_drop_hyp_mode
+
+bsp_start_skip_hyp_svc_switch:
+#endif
 	/*
 	 * Set SVC mode, disable interrupts and enable ARM instructions.
 	 */
@@ -247,6 +311,10 @@ _start:
 
 	SWITCH_FROM_ARM_TO_THUMB	r0
 
+	mov	r0, r4		/* original cpsr value */
+	mov	r1, r5		/* machine type number or ~0 for DT boot */
+	mov	r2, r6		/* physical address of ATAGs or DTB */
+
 	b	bsp_start_hook_0
 
 bsp_start_hook_0_done:
@@ -258,6 +326,8 @@ bsp_start_hook_0_done:
 	 * vectors and the pointers to the default exception handlers.
 	 */
 
+	stmdb	sp!, {r4, r5, r6}
+
 	ldr	r0, =bsp_vector_table_begin
 	adr	r1, bsp_start_vector_table_begin
 	cmp	r0, r1
@@ -269,7 +339,9 @@ bsp_start_hook_0_done:
 
 bsp_vector_table_copy_done:
 
-	SWITCH_FROM_ARM_TO_THUMB	r0
+	ldmia	sp!, {r0, r1, r2}
+
+	SWITCH_FROM_ARM_TO_THUMB	r3
 
 	/* Branch to start hook 1 */
 	bl	bsp_start_hook_1

c/src/lib/libbsp/arm/shared/startup/bsp-start-in-hyp-support.S

@@ -0,0 +1,77 @@
+/**
+ * @file
+ *
+ * @brief Boot and system start code.
+ */
+
+ /*
+ * Copyright (c) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems/asm.h>
+#include <rtems/system.h>
+#include <rtems/score/cpu.h>
+
+#include <bspopts.h>
+#include <bsp/irq.h>
+#include <bsp/linker-symbols.h>
+
+	.extern	bsp_start_hyp_vector_table_begin
+	.globl	bsp_start_arm_drop_hyp_mode
+	.globl	bsp_arm_drop_hyp_mode_only
+
+.arm
+
+/*
+ * The routine is called from startup code and it should
+ * preserve all registers except r2 and r3. r0 can be used
+ * as pass though argument in some cases, a1 is used for
+ * CPU stack offset during startup and r4 to r6 to preserve
+ * booloader arguments
+ */
+
+bsp_start_arm_drop_hyp_mode:
+	ldr	r2, bsp_start_hyp_vector_table_begin_addr
+	mcr	p15, 4, r2, c12, c0, 0
+
+	mov	r2, #0
+	mcr	p15, 4, r2, c1, c1, 0
+	mcr	p15, 4, r2, c1, c1, 2
+	mcr	p15, 4, r2, c1, c1, 3
+/*
+ * HSCTLR.TE
+ * optional start of hypervisor handlers in Thumb mode
+ *	orr	r0, #(1 << 30)
+ */
+	mcr	p15, 4, r2, c1, c0, 0	/* HSCTLR */
+	mrc	p15, 4, r2, c1, c1, 1	/* HDCR */
+	and	r2, #0x1f		/* Preserve HPMN */
+	mcr	p15, 4, r2, c1, c1, 1	/* HDCR */
+
+bsp_arm_drop_hyp_mode_only:
+	/* Prepare SVC mode for eret */
+	mrs	r2, cpsr
+	bic	r2, r2, #ARM_PSR_M_MASK
+	orr	r2, r2, #ARM_PSR_M_SVC
+	msr	spsr_cxsf, r2
+
+	adr	r2, 1f
+	.inst 0xe12ef302	/* msr ELR_hyp, r2 */
+	mov	r2, sp
+	mov	r3, lr
+	.inst 0xe160006e	/* eret */
+1:	mov	sp, r2
+	mov	lr, r3
+	bx	lr
+
+bsp_start_hyp_vector_table_begin_addr:
+	.word	bsp_start_hyp_vector_table_begin

c/src/lib/libbsp/arm/shared/startup/linkcmds.base

@@ -53,10 +53,13 @@ bsp_stack_svc_size = ALIGN (bsp_stack_svc_size, bsp_stack_align);
 bsp_stack_und_size = DEFINED (bsp_stack_und_size) ? bsp_stack_und_size : 0;
 bsp_stack_und_size = ALIGN (bsp_stack_und_size, bsp_stack_align);
 
+bsp_stack_hyp_size = DEFINED (bsp_stack_hyp_size) ? bsp_stack_hyp_size : 0;
+bsp_stack_hyp_size = ALIGN (bsp_stack_hyp_size, bsp_stack_align);
+
 bsp_stack_main_size = DEFINED (bsp_stack_main_size) ? bsp_stack_main_size : 0;
 bsp_stack_main_size = ALIGN (bsp_stack_main_size, bsp_stack_align);
 
-bsp_stack_all_size = bsp_stack_abt_size + bsp_stack_fiq_size + bsp_stack_irq_size + bsp_stack_svc_size + bsp_stack_und_size + bsp_stack_main_size;
+bsp_stack_all_size = bsp_stack_abt_size + bsp_stack_fiq_size + bsp_stack_irq_size + bsp_stack_svc_size + bsp_stack_und_size + bsp_stack_hyp_size + bsp_stack_main_size;
 
 bsp_processor_count = DEFINED (bsp_processor_count) ? bsp_processor_count : 1;
 
@@ -312,6 +315,10 @@ SECTIONS {
 		. = . + bsp_stack_und_size;
 		bsp_stack_und_end = .;
 
+		bsp_stack_hyp_begin = .;
+		. = . + bsp_stack_hyp_size;
+		bsp_stack_hyp_end = .;
+
 		bsp_stack_abt_begin = .;
 		. = . + bsp_stack_abt_size;
 		bsp_stack_abt_end = .;

c/src/lib/libbsp/arm/smdk2410/Makefile.am

@@ -11,6 +11,7 @@ include_HEADERS += ../gp32/smc/smc.h
 include_HEADERS += ../../shared/include/tm27.h
 
 include_bsp_HEADERS =
+libbsp_a_CPPFLAGS =
 
 nodist_include_HEADERS = include/bspopts.h
 nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h
@@ -57,8 +58,9 @@ libbsp_a_SOURCES += ../gp32/smc/smc.c ../gp32/smc/smc.h
 
 # Cache
 libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
-libbsp_a_SOURCES += ../../shared/include/cache_.h
+libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
-libbsp_a_CPPFLAGS = -I$(srcdir)/../../shared/include
+libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
+libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
 
 libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/arm920.rel \
     ../../../libcpu/@RTEMS_CPU@/s3c24xx/clock.rel \

c/src/lib/libbsp/arm/tms570/Makefile.am

@@ -41,6 +41,10 @@ include_bsp_HEADERS += include/tms570-vim.h
 include_bsp_HEADERS += include/tms570-pom.h
 include_bsp_HEADERS += include/tms570-sci-driver.h
 include_bsp_HEADERS += include/system-clocks.h
+include_bsp_HEADERS += include/tms570-pinmux.h
+
+include_bsp_HEADERS += include/tms570-pins.h
+include_bsp_HEADERS += include/tms570ls3137zwt-pins.h
 
 include_bsp_ti_hercules_HEADERS = include/ti_herc/reg_adc.h
 include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_ccmsr.h
@@ -50,7 +54,7 @@ include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_dcc.h
 include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_dma.h
 include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_dmm.h
 include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_efuse.h
-include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_emac.h
+include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_emacc.h
 include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_emacm.h
 include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_emif.h
 include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_esm.h
@@ -94,6 +98,7 @@ project_lib_DATA += startup/linkcmds
 
 EXTRA_DIST =
 EXTRA_DIST += startup/linkcmds.tms570ls3137_hdk
+EXTRA_DIST += startup/linkcmds.tms570ls3137_hdk_with_loader
 EXTRA_DIST += startup/linkcmds.tms570ls3137_hdk_sdram
 EXTRA_DIST += startup/linkcmds.tms570ls3137_hdk_intram
 
@@ -151,7 +156,7 @@ libbsp_a_SOURCES += clock/benchmark_timer.c
 # RTC
 
 # GPIO
-
+libbsp_a_SOURCES += pinmux/pinmux.c
 # Timer
 
 # Benchmark Timer
@@ -166,8 +171,30 @@ libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
 libbsp_a_SOURCES += ../../../libcpu/arm/shared/include/cache_.h
 libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include
 
+if TMS570_USE_HWINIT_STARTUP
+libbsp_a_SOURCES += hwinit/tms570_sys_core.S
+libbsp_a_SOURCES += hwinit/fail_notification.c
+libbsp_a_SOURCES += hwinit/init_emif_sdram.c
+libbsp_a_SOURCES += hwinit/init_esm.c
+libbsp_a_SOURCES += hwinit/init_pinmux.c
+libbsp_a_SOURCES += hwinit/init_system.c
+libbsp_a_SOURCES += hwinit/tms570_selftest.c
+libbsp_a_SOURCES += hwinit/tms570_selftest_par_can.c
+libbsp_a_SOURCES += hwinit/tms570_selftest_par_mibspi.c
+libbsp_a_SOURCES += hwinit/tms570_selftest_par_std.c
+libbsp_a_SOURCES += hwinit/tms570_selftest_parity.c
+libbsp_a_SOURCES += hwinit/tms570_tcram_tests.c
+
+include_bsp_HEADERS += hwinit/tms570_selftest_parity.h
+include_bsp_HEADERS += hwinit/tms570_hwinit.h
+include_bsp_HEADERS += hwinit/tms570_selftest.h
+
+# Start hooks
+libbsp_a_SOURCES += hwinit/bspstarthooks-hwinit.c
+else
 # Start hooks
 libbsp_a_SOURCES += startup/bspstarthooks.c
+endif
 
 # ----------------------------
 # ------  Special Rules

c/src/lib/libbsp/arm/tms570/README

@@ -2,23 +2,35 @@ Development Board: TMS570LS31x Hercules Development Kit from TI
 
 http://www.ti.com/tool/tmds570ls31hdk
 
+Overview
+--------
+
 Drivers:
 
-	o Console
+  o Console
-	o Clock
+  o Clock
-  o Ethernet - work in progress
+  o Ethernet - external lwIP fork repository
 
 BSP variants:
   tms570ls3137_hdk_intram - place code and data into internal SRAM
   tms570ls3137_hdk_sdram - place code into external SDRAM and data to SRAM
-  tms570ls3137_hdk - variant prepared for stand-alone RTEMS application
+  tms570ls3137_hdk_with_loader - reserve 256kB at Flash start for loader
-                      stored and running directly from flash. Not working yet.
+                                 and place RTEMS application from address
+                                 0x00040000
+  tms570ls3137_hdk - variant for stand-alone RTEMS application stored
+                     and running directly from flash. This variant
+                     requires initialization of hardware to be integrated
+                     into RTEMS. RTEMS has to be configured with
+                       TMS570_USE_HWINIT_STARTUP=1
+                     and initialization code has to be included in the sources.
 
-Tool-chain
+Tool-chain used for development
-  GCC 4.9.0 + Newlib 2.1.0 + Binutils 2.24 configuration:
+-------------------------------
+
+  arm-rtems4.12-gcc (GCC) 6.1.1 20160526 + Newlib 2.4.0.20160527 + Binutils 2.26.20160125
 
   CFLAGS="-O2 -pipe" LDFLAGS=-s \
-  ../../../src/gcc-4.9/configure --target=arm-rtems4.11 --prefix=/usr \
+  ../../../src/gcc-6.1/configure --target=arm-rtems4.12 --prefix=/usr \
                --enable-languages=c,c++ \
                --disable-libstdcxx-pch \
                --with-gnu-ld \
@@ -35,33 +47,102 @@ Tool-chain
                --enable-version-specific-runtime-libs \
                --enable-newlib-iconv \
                --disable-lto \
+               --disable-lto \
+               --enable-libgomp \
+               --enable-newlib-iconv \
+               --enable-newlib-iconv-encodings="iso_8859_1,utf_8" \
 
-Patches required for Cortex-R and big-endian ARM support are already
+All patches required for Cortex-R and big-endian ARM support are already
-accepted by the mainline.
+integrated in GCC the mainline.
+
+RTEMS build configuration used for testing of self contained
+applications to run directly from Flash
+
+  ../../../src/rtems/configure  --target=arm-rtems4.12 --prefix=/opt/rtems4.12 \
+    --enable-rtems-inlines --disable-multiprocessing --enable-cxx \
+    --enable-rdbg --enable-maintainer-mode --enable-tests=samples \
+    --disable-networking --enable-posix --enable-itron --disable-ada \
+    --disable-expada --disable-multilib --disable-docs \
+    --enable-rtemsbsp="tms570ls3137_hdk" \
+    --enable-rtems-debug \
+    TMS570_USE_HWINIT_STARTUP=1
 
 Execution
+---------
 
-Currently, a bootloader is not used. For test and debug purposes, TI's
+Application build by above process can be directly programmed
-HalCoGen generated application is used to set up the board and then
+into Flash and run.
-the RTEMS application image is loaded using OpenOCD to internal
-EEC SRAM or external DRAM. The following features are
-not implemented in the BSP:
 
- + Initial complex CPU and peripheral initialization
+For test and debug purposes, TI's HalCoGen generated application
+is used to set up the board and then the RTEMS application
+image is loaded using OpenOCD to internal EEC SRAM or external SDRAM.
+This prevents wear of Flash which has limited guaranteed
+erase cycles count.
+
+The following features are implemented in the BSP only partially:
+
+ + Initial CPU and peripheral initialization
  + Cores Self-test
 
 Setup application code is available there:
           https://github.com/hornmich/tms570ls3137-hdk-sdram
 
-Howto setup TMDS570LS31HDK?
+TMDS570LS31HDK setup to use SDRAM to load and debug RTEMS applications
+-----------------------------------------------------------------------
 
-	o Unpack board.	
+  o Program SDRAM_SCI_configuration-program or another boot loader
-	o Verify that demo application runs.
+    (for example ETHERNET XCP is developed)
-  o Upload bootloader specified above
   o write BSP application either to sdram or intram and jump to RTEMS start code
 
-Additional information about the board can be found at
+ETHERNET
-  http://www.rtems.org/wiki/index.php/Tms570
+--------
+
+For ETHERNET, the lwIP port for TMS570LS3137 has been developed
+at Industrial Informatics Group of Czech Technical University
+in Prague and development versions are available on SourceForge.
+
+The RTEMS and TMS570 support is included in uLAN project lwIP
+repository for now
+
+  https://sourceforge.net/p/ulan/lwip-omk/
+
+But other place should be found when RTEMS lwIP
+integration with read, write, close etc. functions
+is implemented in future.
+
+Adapt BSP for another TMS570 based hardware
+-------------------------------------------
+
+When TMS570_USE_HWINIT_STARTUP=1 then quite complete
+initialization and selft-test code is included in TMS570
+BSP build. The support included in hwinit subdirectory
+provides version of bsp_start_hook_0 and bsp_start_hook_1
+which proceeds many self-tests functions, clocks, PLLs
+peripherals and other subsystems configuration.
+
+Complete pin multiplexer initialization according
+to the list of individual pins functions is included.
+Pins function definition can be found and altered
+in a file
+
+ rtems/c/src/lib/libbsp/arm/tms570/hwinit/init_pinmux.c
+
+Complete "database" of all possible pin functions for
+TMS570LS3137 chip is provided in a file
+
+  rtems/c/src/lib/libbsp/arm/tms570/include/tms570ls3137zwt-pins.h
+
+If another package or chip is considered then tools found
+in next repository can be used or extended to generate header
+files and pins "database"
+
+  https://github.com/AoLaD/rtems-tms570-utils
+
+Links to additional information
+-------------------------------
+
+Additional information about the BSP and board can be found at
+  https://devel.rtems.org/wiki/TBR/BSP/Tms570
 
 Additional information about the CPU can be found at
   http://www.ti.com/product/tms570ls3137

c/src/lib/libbsp/arm/tms570/clock/clock.c

@@ -85,23 +85,39 @@ static void tms570_clock_driver_support_initialize_hardware( void )
   /* Hardware specific initialize */
   TMS570_RTI.GCTRL = 0;
   TMS570_RTI.CNT[0].CPUCx = tc_prescaler - 1;
-  TMS570_RTI.TBCTRL = 2;
+  TMS570_RTI.TBCTRL = TMS570_RTI_TBCTRL_INC;
   TMS570_RTI.CAPCTRL = 0;
   TMS570_RTI.COMPCTRL = 0;
   /* set counter to zero */
   TMS570_RTI.CNT[0].UCx = 0;
   TMS570_RTI.CNT[0].FRCx = 0;
   /* clear interrupts*/
-  TMS570_RTI.CLEARINTENA = 0x00070f0f;
+  TMS570_RTI.CLEARINTENA = TMS570_RTI_CLEARINTENA_CLEAROVL1INT |
-  TMS570_RTI.INTFLAG = 0x0007000f;
+                           TMS570_RTI_CLEARINTENA_CLEAROVL0INT |
+                           TMS570_RTI_CLEARINTENA_CLEARTBINT |
+                           TMS570_RTI_CLEARINTENA_CLEARDMA3 |
+                           TMS570_RTI_CLEARINTENA_CLEARDMA2 |
+                           TMS570_RTI_CLEARINTENA_CLEARDMA1 |
+                           TMS570_RTI_CLEARINTENA_CLEARDMA0 |
+                           TMS570_RTI_CLEARINTENA_CLEARINT3 |
+                           TMS570_RTI_CLEARINTENA_CLEARINT2 |
+                           TMS570_RTI_CLEARINTENA_CLEARINT1 |
+                           TMS570_RTI_CLEARINTENA_CLEARINT0;
+  TMS570_RTI.INTFLAG = TMS570_RTI_INTFLAG_OVL1INT |
+                       TMS570_RTI_INTFLAG_OVL0INT |
+                       TMS570_RTI_INTFLAG_TBINT |
+                       TMS570_RTI_INTFLAG_INT3 |
+                       TMS570_RTI_INTFLAG_INT2 |
+                       TMS570_RTI_INTFLAG_INT1 |
+                       TMS570_RTI_INTFLAG_INT0;
   /* set timer */
   TMS570_RTI.CMP[0].COMPx = TMS570_RTI.CNT[0].FRCx + tc_increments_per_tick;
   TMS570_RTI.COMP0CLR = TMS570_RTI.CMP[0].COMPx + tc_increments_per_tick / 2;
   TMS570_RTI.CMP[0].UDCPx = tc_increments_per_tick;
   /* enable interupt */
-  TMS570_RTI.SETINTENA = 0x1;
+  TMS570_RTI.SETINTENA = TMS570_RTI_SETINTENA_SETINT0;
   /* enable timer */
-  TMS570_RTI.GCTRL = 1;
+  TMS570_RTI.GCTRL = TMS570_RTI_GCTRL_CNT0EN;
   /* set timecounter */
   tms570_rti_tc.tc_get_timecount = tms570_rti_get_timecount;
   tms570_rti_tc.tc_counter_mask = 0xffffffff;
@@ -117,7 +133,7 @@ static void tms570_clock_driver_support_initialize_hardware( void )
  */
 static void tms570_clock_driver_support_at_tick( void )
 {
-  TMS570_RTI.INTFLAG = 0x00000001;
+  TMS570_RTI.INTFLAG = TMS570_RTI_INTFLAG_INT0;
 }
 
 /**
@@ -156,7 +172,8 @@ static void tms570_clock_driver_support_install_isr(
 static void tms570_clock_driver_support_shutdown_hardware( void )
 {
   /* turn off the timer interrupts */
-  TMS570_RTI.CLEARINTENA = 0x20000;
+  TMS570_RTI.CLEARINTENA = TMS570_RTI_CLEARINTENA_CLEAROVL0INT |
+                           TMS570_RTI_CLEARINTENA_CLEARINT0;  
 }
 
 #define Clock_driver_support_initialize_hardware \

c/src/lib/libbsp/arm/tms570/configure.ac

@@ -50,6 +50,10 @@ RTEMS_BSPOPTS_HELP([TMS570_OSCILLATOR_RTC],[RTC oscillator frequency in Hz])
 RTEMS_BSPOPTS_SET([TMS570_CCLK],[*],[96000000U])
 RTEMS_BSPOPTS_HELP([TMS570_CCLK],[CPU clock in Hz])
 
+RTEMS_BSPOPTS_SET([TMS570_USE_HWINIT_STARTUP],[*],[0])
+RTEMS_BSPOPTS_HELP([TMS570_USE_HWINIT_STARTUP],[Include BSP startup code for TMS570LS3137 which allows to start RTEMS application directly after reset])
+AM_CONDITIONAL(TMS570_USE_HWINIT_STARTUP,test "$TMS570_USE_HWINIT_STARTUP" = "1")
+
 RTEMS_BSP_CLEANUP_OPTIONS(0, 1)
 RTEMS_BSP_LINKCMDS
 

c/src/lib/libbsp/arm/tms570/console/printk-support.c

@@ -41,7 +41,7 @@ static void tms570_putc(char ch)
   rtems_interrupt_level level;
 
   rtems_interrupt_disable(level);
-  while ( ( driver_context_table[0].regs->FLR & 0x100 ) == 0) {
+  while ( ( driver_context_table[0].regs->FLR & TMS570_SCI_FLR_TXRDY ) == 0) {
     rtems_interrupt_flash(level);
   }
   driver_context_table[0].regs->TD = ch;
@@ -74,7 +74,7 @@ static void tms570_uart_output(char c)
  */
 static int tms570_uart_input( void )
 {
-  if ( driver_context_table[0].regs->FLR & (1<<9) ) {
+  if ( driver_context_table[0].regs->FLR & TMS570_SCI_FLR_RXRDY ) {
       return driver_context_table[0].regs->RD;
   } else {
       return -1;

c/src/lib/libbsp/arm/tms570/console/tms570-sci.c

@@ -95,6 +95,40 @@ rtems_device_driver console_initialize(
     ++minor
   ) {
     tms570_sci_context *ctx = &driver_context_table[minor];
+    uint32_t rx_pin = 1 << 1;
+    uint32_t tx_pin = 1 << 2;
+
+    /* Resec SCI peripheral */
+    ctx->regs->GCR0 = TMS570_SCI_GCR0_RESET * 0;
+    ctx->regs->GCR0 = TMS570_SCI_GCR0_RESET * 1;
+
+    /* Clear all interrupt sources */
+    ctx->regs->CLEARINT = 0xffffffff;
+
+    /* Map all interrupts to SCI INT0 line */
+    ctx->regs->CLEARINTLVL = 0xffffffff;
+
+    ctx->regs->GCR1 = TMS570_SCI_GCR1_TXENA * 0 |
+                      TMS570_SCI_GCR1_RXENA * 0 |
+                      TMS570_SCI_GCR1_CONT * 0 | /* continue operation when debugged */
+                      TMS570_SCI_GCR1_LOOP_BACK * 0 |
+                      TMS570_SCI_GCR1_POWERDOWN * 0 |
+                      TMS570_SCI_GCR1_SLEEP * 0 |
+                      TMS570_SCI_GCR1_SWnRST * 0 | /* reset state */
+                      TMS570_SCI_GCR1_CLOCK * 1 | /* internal clock */
+                      TMS570_SCI_GCR1_TIMING_MODE * 1 |
+                      TMS570_SCI_GCR1_COMM_MODE * 0;
+
+    /* Setup connection of SCI peripheral Rx and Tx  pins */
+    ctx->regs->PIO0 = rx_pin * 1 | tx_pin * 1; /* Rx and Tx pins are not GPIO */
+    ctx->regs->PIO3 = rx_pin * 0 | tx_pin * 0; /* Default output low  */
+    ctx->regs->PIO1 = rx_pin * 0 | tx_pin * 0; /* Input when not used by SCI */
+    ctx->regs->PIO6 = rx_pin * 0 | tx_pin * 0; /* No open drain */
+    ctx->regs->PIO7 = rx_pin * 0 | tx_pin * 0; /* Pull-up/down enabled */
+    ctx->regs->PIO8 = rx_pin * 1 | tx_pin * 1; /* Select pull-up */
+
+    /* Bring device out of software reset */
+    ctx->regs->GCR1 |= TMS570_SCI_GCR1_SWnRST;
 
     /*
      * Install this device in the file system and Termios.  In order
@@ -107,7 +141,7 @@ rtems_device_driver console_initialize(
         major,
         minor,
         handler,
-	NULL,
+        NULL,
         &ctx->base
     );
     if ( sc != RTEMS_SUCCESSFUL ) {
@@ -155,7 +189,7 @@ static int tms570_sci_read_received_chars(
  */
 static void tms570_sci_enable_interrupts(tms570_sci_context * ctx)
 {
-  ctx->regs->SETINT = (1<<9);
+  ctx->regs->SETINT = TMS570_SCI_SETINT_SET_RX_INT;
 }
 
 /**
@@ -169,7 +203,7 @@ static void tms570_sci_enable_interrupts(tms570_sci_context * ctx)
  */
 static void tms570_sci_disable_interrupts(tms570_sci_context * ctx)
 {
-  ctx->regs->CLEARINT = (1<<9);
+  ctx->regs->CLEARINT = TMS570_SCI_CLEARINT_CLR_RX_INT;
 }
 
 /**
@@ -213,41 +247,64 @@ static bool tms570_sci_set_attributes(
   rtems_interrupt_lock_context lock_context;
   int32_t bauddiv;
   int32_t baudrate;
+  uint32_t flr_tx_ready = TMS570_SCI_FLR_TX_EMPTY | TMS570_SCI_FLR_TX_EMPTY;
+
+  /* Baud rate */
+  baudrate = rtems_termios_baud_to_number(cfgetospeed(t));
 
   rtems_termios_device_lock_acquire(base, &lock_context);
 
-  ctx->regs->GCR1 &= ~( (1<<7) | (1<<25) | (1<<24) );
+  while ( (ctx->regs->GCR1 & TMS570_SCI_GCR1_TXENA) &&
+          (ctx->regs->FLR & flr_tx_ready) != flr_tx_ready) {
+    /*
+     * There are pending characters in the hardware,
+     * change in the middle of the character Tx leads
+     * to disturb of the character and SCI engine
+     */
+    rtems_interval tw;
 
-  ctx->regs->GCR1 &= ~(1<<4);    /*one stop bit*/
+    rtems_termios_device_lock_release(base, &lock_context);
-  ctx->regs->FORMAT = 0x7;
+
+    tw = rtems_clock_get_ticks_per_second();
+    tw = tw * 5 / baudrate + 1;
+    rtems_task_wake_after( tw );
+
+    rtems_termios_device_lock_acquire(base, &lock_context);
+  }
+
+  ctx->regs->GCR1 &= ~( TMS570_SCI_GCR1_SWnRST | TMS570_SCI_GCR1_TXENA |
+                        TMS570_SCI_GCR1_RXENA );
+
+  ctx->regs->GCR1 &= ~TMS570_SCI_GCR1_STOP;    /*one stop bit*/
+  ctx->regs->FORMAT = TMS570_SCI_FORMAT_CHAR(0x7);
 
   switch ( t->c_cflag & ( PARENB|PARODD ) ) {
     case ( PARENB|PARODD ):
       /* Odd parity */
-      ctx->regs->GCR1 &= ~(1<<3);
+      ctx->regs->GCR1 &= ~TMS570_SCI_GCR1_PARITY;
-      ctx->regs->GCR1 |= (1<<2);
+      ctx->regs->GCR1 |= TMS570_SCI_GCR1_PARITY_ENA;
       break;
 
     case PARENB:
       /* Even parity */
-      ctx->regs->GCR1 |= (1<<3);
+      ctx->regs->GCR1 |= TMS570_SCI_GCR1_PARITY;
-      ctx->regs->GCR1 |= (1<<2);
+      ctx->regs->GCR1 |= TMS570_SCI_GCR1_PARITY_ENA;
       break;
 
     default:
     case 0:
     case PARODD:
       /* No Parity */
-      ctx->regs->GCR1 &= ~(1<<2);
+      ctx->regs->GCR1 &= ~TMS570_SCI_GCR1_PARITY_ENA;
   }
 
-  /* Baud rate */
+  /* Apply baudrate to the hardware */
-  baudrate = rtems_termios_baud_to_number(cfgetospeed(t));
   baudrate *= 2 * 16;
   bauddiv = (BSP_PLL_OUT_CLOCK + baudrate / 2) / baudrate;
   ctx->regs->BRS = bauddiv;
 
-  ctx->regs->GCR1 |= (1<<7) | (1<<25) | (1<<24);
+  ctx->regs->GCR1 |= TMS570_SCI_GCR1_SWnRST | TMS570_SCI_GCR1_TXENA |
+                     TMS570_SCI_GCR1_RXENA;
 
   rtems_termios_device_lock_release(base, &lock_context);
 
@@ -274,7 +331,7 @@ static void tms570_sci_interrupt_handler(void * arg)
   /*
    * Check if we have received something.
    */
-   if ( (ctx->regs->FLR & (1<<9) ) == (1<<9) ) {
+   if ( (ctx->regs->FLR & TMS570_SCI_FLR_RXRDY ) == TMS570_SCI_FLR_RXRDY ) {
       n = tms570_sci_read_received_chars(ctx, buf, TMS570_SCI_BUFFER_SIZE);
       if ( n > 0 ) {
         /* Hand the data over to the Termios infrastructure */
@@ -284,7 +341,7 @@ static void tms570_sci_interrupt_handler(void * arg)
   /*
    * Check if we have something transmitted.
    */
-  if ( (ctx->regs->FLR & (1<<8) ) == (1<<8) ) {
+  if ( (ctx->regs->FLR & TMS570_SCI_FLR_TXRDY ) == TMS570_SCI_FLR_TXRDY ) {
     n = tms570_sci_transmitted_chars(ctx);
     if ( n > 0 ) {
       /*
@@ -355,7 +412,7 @@ static void tms570_sci_poll_write(
   /* Write */
 
   for ( i = 0; i < n; ++i ) {
-    while ( (ctx->regs->FLR & (1<<11) ) == 0) {
+    while ( (ctx->regs->FLR & TMS570_SCI_FLR_TX_EMPTY ) == 0) {
       ;
     }
     ctx->regs->TD = buf[i];
@@ -375,7 +432,7 @@ static int TMS570_sci_can_read_char(
   tms570_sci_context * ctx
 )
 {
-  return ctx->regs->FLR & (1<<9);
+  return ctx->regs->FLR & TMS570_SCI_FLR_RXRDY;
 }
 
 /**
@@ -471,7 +528,7 @@ static bool tms570_sci_interrupt_first_open(
   if ( ret == false ) {
     return false;
   }
-  ctx->regs->SETINTLVL = 0;
+
   /* Register Interrupt handler */
   sc = rtems_interrupt_handler_install(ctx->irq,
       ctx->device_name,
@@ -523,15 +580,19 @@ static void tms570_sci_interrupt_last_close(
 {
   tms570_sci_context *ctx = (tms570_sci_context *) base;
   rtems_interrupt_lock_context lock_context;
+  rtems_interval tw;
+  int32_t baudrate;
 
   /* Turn off RX interrupts */
   rtems_termios_device_lock_acquire(base, &lock_context);
   tms570_sci_disable_interrupts(ctx);
   rtems_termios_device_lock_release(base, &lock_context);
 
-  /* Flush device */
+  tw = rtems_clock_get_ticks_per_second();
-  while ( ( ctx->regs->FLR & (1<<11) ) > 0 ) {
+  baudrate = rtems_termios_baud_to_number(cfgetospeed(&tty->termios));
-    ;/* Wait until all data has been sent */
+  tw = tw * 10 / baudrate + 1;
+  while ( ( ctx->regs->FLR & TMS570_SCI_FLR_TX_EMPTY ) == 0 ) {
+     rtems_task_wake_after(tw);
   }
 
   /* uninstall ISR */

c/src/lib/libbsp/arm/tms570/hwinit/bspstarthooks-hwinit.c

@@ -0,0 +1,422 @@
+#include <stdint.h>
+#include <bsp.h>
+#include <bsp/start.h>
+#include <bsp/tms570.h>
+
+#include "tms570_selftest.h"
+#include "tms570_selftest_parity.h"
+#include "tms570_hwinit.h"
+
+void bsp_start_hook_0_done( void );
+
+static inline
+int tms570_running_from_tcram( void )
+{
+  void *fncptr = (void*)bsp_start_hook_0;
+  return ( fncptr >= (void*)TMS570_TCRAM_START_PTR ) &&
+         ( fncptr < (void*)TMS570_TCRAM_WINDOW_END_PTR );
+}
+
+static inline
+int tms570_running_from_sdram( void )
+{
+  void *fncptr = (void*)bsp_start_hook_0;
+  return ( ( (void*)fncptr >= (void*)TMS570_SDRAM_START_PTR ) &&
+           ( (void*)fncptr < (void*)TMS570_SDRAM_WINDOW_END_PTR ) );
+}
+
+#define PBIST_March13N_SP        0x00000008U  /**< March13 N Algo for 1 Port mem */
+
+BSP_START_TEXT_SECTION void bsp_start_hook_0( void )
+{
+  /*
+   * Work Around for Errata DEVICE#140: ( Only on Rev A silicon)
+   *
+   * Errata Description:
+   *            The Core Compare Module(CCM-R4) may cause nERROR to be asserted after a cold power-on
+   * Workaround:
+   *            Clear ESM Group2 Channel 2 error in ESMSR2 and Compare error in CCMSR register
+   */
+  if ( TMS570_SYS1.DEVID == 0x802AAD05U ) {
+    _esmCcmErrorsClear_();
+  }
+
+  /* Enable CPU Event Export */
+  /* This allows the CPU to signal any single-bit or double-bit errors detected
+   * by its ECC logic for accesses to program flash or data RAM.
+   */
+  _coreEnableEventBusExport_();
+
+  /* Workaround for Errata CORTEXR4 66 */
+  _errata_CORTEXR4_66_();
+
+  /* Workaround for Errata CORTEXR4 57 */
+  _errata_CORTEXR4_57_();
+
+  /* check for power-on reset condition */
+  /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
+  if ( ( TMS570_SYS1.SYSESR & TMS570_SYS1_SYSESR_PORST ) != 0U ) {
+    /* clear all reset status flags */
+    TMS570_SYS1.SYSESR = 0xFFFFU;
+
+    /* continue with normal start-up sequence */
+  }
+  /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
+  else if ( ( TMS570_SYS1.SYSESR & TMS570_SYS1_SYSESR_OSCRST ) != 0U ) {
+    /* Reset caused due to oscillator failure.
+       Add user code here to handle oscillator failure */
+  }
+  /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
+  else if ( ( TMS570_SYS1.SYSESR & TMS570_SYS1_SYSESR_WDRST ) != 0U ) {
+    /* Reset caused due
+     *  1) windowed watchdog violation - Add user code here to handle watchdog violation.
+     *  2) ICEPICK Reset - After loading code via CCS / System Reset through CCS
+     */
+    /* Check the WatchDog Status register */
+    if ( TMS570_RTI.WDSTATUS != 0U ) {
+      /* Add user code here to handle watchdog violation. */
+      /* Clear the Watchdog reset flag in Exception Status register */
+      TMS570_SYS1.SYSESR = TMS570_SYS1_SYSESR_WDRST;
+    } else {
+      /* Clear the ICEPICK reset flag in Exception Status register */
+      TMS570_SYS1.SYSESR = TMS570_SYS1_SYSESR_WDRST;
+    }
+  }
+  /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
+  else if ( ( TMS570_SYS1.SYSESR & TMS570_SYS1_SYSESR_CPURST ) != 0U ) {
+    /* Reset caused due to CPU reset.
+       CPU reset can be caused by CPU self-test completion, or
+       by toggling the "CPU RESET" bit of the CPU Reset Control Register. */
+
+    /* clear all reset status flags */
+    TMS570_SYS1.SYSESR = TMS570_SYS1_SYSESR_CPURST;
+  }
+  /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
+  else if ( ( TMS570_SYS1.SYSESR & TMS570_SYS1_SYSESR_SWRST ) != 0U ) {
+    /* Reset caused due to software reset.
+       Add user code to handle software reset. */
+  } else {
+    /* Reset caused by nRST being driven low externally.
+       Add user code to handle external reset. */
+  }
+
+  /*
+   * Check if there were ESM group3 errors during power-up.
+   * These could occur during eFuse auto-load or during reads from flash OTP
+   * during power-up. Device operation is not reliable and not recommended
+   * in this case.
+   * An ESM group3 error only drives the nERROR pin low. An external circuit
+   * that monitors the nERROR pin must take the appropriate action to ensure that
+   * the system is placed in a safe state, as determined by the application.
+   */
+  if ( ( TMS570_ESM.SR[ 2 ] ) != 0U ) {
+    /*SAFETYMCUSW 5 C MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
+    /*SAFETYMCUSW 26 S MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
+    for (;; ) {
+    }           /* Wait */
+  }
+
+  /* Initialize System - Clock, Flash settings with Efuse self check */
+  tms570_system_hw_init();
+
+  /* Workaround for Errata PBIST#4 */
+  /* FIXME */
+  //errata_PBIST_4();
+
+  /*
+   * Run a diagnostic check on the memory self-test controller.
+   * This function chooses a RAM test algorithm and runs it on an on-chip ROM.
+   * The memory self-test is expected to fail. The function ensures that the PBIST controller
+   * is capable of detecting and indicating a memory self-test failure.
+   */
+  tms570_pbist_self_check();
+
+  /* Run PBIST on STC ROM */
+  tms570_pbist_run( (uint32_t) STC_ROM_PBIST_RAM_GROUP,
+    ( (uint32_t) PBIST_TripleReadSlow | (uint32_t) PBIST_TripleReadFast ) );
+
+  /* Wait for PBIST for STC ROM to be completed */
+  /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+  while ( tms570_pbist_is_test_completed() != TRUE ) {
+  }                                                  /* Wait */
+
+  /* Check if PBIST on STC ROM passed the self-test */
+  if ( tms570_pbist_is_test_passed() != TRUE ) {
+    /* PBIST and STC ROM failed the self-test.
+     * Need custom handler to check the memory failure
+     * and to take the appropriate next step.
+     */
+    tms570_pbist_fail();
+  }
+
+  /* Disable PBIST clocks and disable memory self-test mode */
+  tms570_pbist_stop();
+
+  /* Run PBIST on PBIST ROM */
+  tms570_pbist_run( (uint32_t) PBIST_ROM_PBIST_RAM_GROUP,
+    ( (uint32_t) PBIST_TripleReadSlow | (uint32_t) PBIST_TripleReadFast ) );
+
+  /* Wait for PBIST for PBIST ROM to be completed */
+  /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+  while ( tms570_pbist_is_test_completed() != TRUE ) {
+  }                                                  /* Wait */
+
+  /* Check if PBIST ROM passed the self-test */
+  if ( tms570_pbist_is_test_passed() != TRUE ) {
+    /* PBIST and STC ROM failed the self-test.
+     * Need custom handler to check the memory failure
+     * and to take the appropriate next step.
+     */
+    tms570_pbist_fail();
+  }
+
+  /* Disable PBIST clocks and disable memory self-test mode */
+  tms570_pbist_stop();
+
+  if ( !tms570_running_from_tcram() ) {
+    /*
+     * The next sequence tests TCRAM, main TMS570 system operation RAM area.
+     * The tests are destructive, lead the first to fill memory by 0xc5c5c5c5
+     * and then to clear it to zero. The sequence is obliviously incompatible
+     * with RTEMS image running from TCRAM area (code clears itself).
+     *
+     * But TCRAM clear leads to overwrite of stack which is used to store
+     * value of bsp_start_hook_0 call return address from link register.
+     *
+     * If the bsp_start_hook_0 by jump to bsp_start_hook_0_done
+     * then generated C code does not use any variable which
+     * is stores on stack and code works OK even that memory
+     * is cleared during bsp_start_hook_0 execution.
+     *
+     * The last assumption is a little fragile in respect to
+     * code and compiler changes.
+     */
+
+    /* Disable RAM ECC before doing PBIST for Main RAM */
+    _coreDisableRamEcc_();
+
+    /* Run PBIST on CPU RAM.
+     * The PBIST controller needs to be configured separately for single-port and dual-port SRAMs.
+     * The CPU RAM is a single-port memory. The actual "RAM Group" for all on-chip SRAMs is defined in the
+     * device datasheet.
+     */
+    tms570_pbist_run( 0x08300020U,   /* ESRAM Single Port PBIST */
+      (uint32_t) PBIST_March13N_SP );
+
+    /* Wait for PBIST for CPU RAM to be completed */
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+    while ( tms570_pbist_is_test_completed() != TRUE ) {
+    }                                                  /* Wait */
+
+    /* Check if CPU RAM passed the self-test */
+    if ( tms570_pbist_is_test_passed() != TRUE ) {
+      /* CPU RAM failed the self-test.
+       * Need custom handler to check the memory failure
+       * and to take the appropriate next step.
+       */
+      tms570_pbist_fail();
+    }
+
+    /* Disable PBIST clocks and disable memory self-test mode */
+    tms570_pbist_stop();
+
+    /*
+     * Initialize CPU RAM.
+     * This function uses the system module's hardware for auto-initialization of memories and their
+     * associated protection schemes. The CPU RAM is initialized by setting bit 0 of the MSIENA register.
+     * Hence the value 0x1 passed to the function.
+     * This function will initialize the entire CPU RAM and the corresponding ECC locations.
+     */
+    tms570_memory_init( 0x1U );
+
+    /*
+     * Enable ECC checking for TCRAM accesses.
+     * This function enables the CPU's ECC logic for accesses to B0TCM and B1TCM.
+     */
+    _coreEnableRamEcc_();
+  } /* end of the code skipped for tms570_running_from_tcram() */
+
+  /* Start PBIST on all dual-port memories */
+  /* NOTE : Please Refer DEVICE DATASHEET for the list of Supported Dual port Memories.
+     PBIST test performed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab.
+   */
+  tms570_pbist_run( (uint32_t) 0x00000000U | /* EMAC RAM */
+    (uint32_t) 0x00000000U |                 /* USB RAM */
+    (uint32_t) 0x00000800U |                 /* DMA RAM */
+    (uint32_t) 0x00000200U |                 /* VIM RAM */
+    (uint32_t) 0x00000040U |                 /* MIBSPI1 RAM */
+    (uint32_t) 0x00000080U |                 /* MIBSPI3 RAM */
+    (uint32_t) 0x00000100U |                 /* MIBSPI5 RAM */
+    (uint32_t) 0x00000004U |                 /* CAN1 RAM */
+    (uint32_t) 0x00000008U |                 /* CAN2 RAM */
+    (uint32_t) 0x00000010U |                 /* CAN3 RAM */
+    (uint32_t) 0x00000400U |                 /* ADC1 RAM */
+    (uint32_t) 0x00020000U |                 /* ADC2 RAM */
+    (uint32_t) 0x00001000U |                 /* HET1 RAM */
+    (uint32_t) 0x00040000U |                 /* HET2 RAM */
+    (uint32_t) 0x00002000U |                 /* HTU1 RAM */
+    (uint32_t) 0x00080000U |                 /* HTU2 RAM */
+    (uint32_t) 0x00004000U |                 /* RTP RAM */
+    (uint32_t) 0x00008000U,                  /* FRAY RAM */
+    (uint32_t) PBIST_March13N_DP );
+
+  if ( !tms570_running_from_tcram() ) {
+
+    /* Test the CPU ECC mechanism for RAM accesses.
+     * The checkBxRAMECC functions cause deliberate single-bit and double-bit errors in TCRAM accesses
+     * by corrupting 1 or 2 bits in the ECC. Reading from the TCRAM location with a 2-bit error
+     * in the ECC causes a data abort exception. The data abort handler is written to look for
+     * deliberately caused exception and to return the code execution to the instruction
+     * following the one that caused the abort.
+     */
+    tms570_check_tcram_ecc();
+
+    /* Wait for PBIST for CPU RAM to be completed */
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+    while ( tms570_pbist_is_test_completed() != TRUE ) {
+    }                                                  /* Wait */
+
+    /* Check if CPU RAM passed the self-test */
+    if ( tms570_pbist_is_test_passed() != TRUE ) {
+      /* CPU RAM failed the self-test.
+       * Need custom handler to check the memory failure
+       * and to take the appropriate next step.
+       */
+      tms570_pbist_fail();
+    }
+
+  } /* end of the code skipped for tms570_running_from_tcram() */
+
+  /* Disable PBIST clocks and disable memory self-test mode */
+  tms570_pbist_stop();
+
+  /* Release the MibSPI1 modules from local reset.
+   * This will cause the MibSPI1 RAMs to get initialized along with the parity memory.
+   */
+  TMS570_SPI1.GCR0 = TMS570_SPI_GCR0_nRESET;
+
+  /* Release the MibSPI3 modules from local reset.
+   * This will cause the MibSPI3 RAMs to get initialized along with the parity memory.
+   */
+  TMS570_SPI3.GCR0 = TMS570_SPI_GCR0_nRESET;
+
+  /* Release the MibSPI5 modules from local reset.
+   * This will cause the MibSPI5 RAMs to get initialized along with the parity memory.
+   */
+  TMS570_SPI5.GCR0 = TMS570_SPI_GCR0_nRESET;
+
+  /* Enable parity on selected RAMs */
+  tms570_enable_parity();
+
+  /* Initialize all on-chip SRAMs except for MibSPIx RAMs
+   * The MibSPIx modules have their own auto-initialization mechanism which is triggered
+   * as soon as the modules are brought out of local reset.
+   */
+  /* The system module auto-init will hang on the MibSPI RAM if the module is still in local reset.
+   */
+  /* NOTE : Please Refer DEVICE DATASHEET for the list of Supported Memories and their channel numbers.
+            Memory Initialization is perfomed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab.
+   */
+  tms570_memory_init( (uint32_t) ( (uint32_t) 1U << 1U ) |  /* DMA RAM */
+    (uint32_t) ( (uint32_t) 1U << 2U ) |                /* VIM RAM */
+    (uint32_t) ( (uint32_t) 1U << 5U ) |                /* CAN1 RAM */
+    (uint32_t) ( (uint32_t) 1U << 6U ) |                /* CAN2 RAM */
+    (uint32_t) ( (uint32_t) 1U << 10U ) |               /* CAN3 RAM */
+    (uint32_t) ( (uint32_t) 1U << 8U ) |                /* ADC1 RAM */
+    (uint32_t) ( (uint32_t) 1U << 14U ) |               /* ADC2 RAM */
+    (uint32_t) ( (uint32_t) 1U << 3U ) |                /* HET1 RAM */
+    (uint32_t) ( (uint32_t) 1U << 4U ) |                /* HTU1 RAM */
+    (uint32_t) ( (uint32_t) 1U << 15U ) |               /* HET2 RAM */
+    (uint32_t) ( (uint32_t) 1U << 16U )                 /* HTU2 RAM */
+  );
+
+  /* Disable parity */
+  tms570_disable_parity();
+
+  /*
+   * Test the parity protection mechanism for peripheral RAMs
+   * Refer DEVICE DATASHEET for the list of Supported Memories
+   * with parity.
+   */
+
+  tms570_selftest_par_run( tms570_selftest_par_list,
+    tms570_selftest_par_list_size );
+
+#if 0
+  /*
+   * RTEMS VIM initialization is implemented by the function
+   * bsp_interrupt_facility_initialize(). RTEMS does not
+   * gain performance from use of vectors targets provided
+   * directly by VIM. RTEMS require to route all interrupts
+   * through _ARMV4_Exception_interrupt handler.
+   *
+   * But actual RTEMS VIM initialization lefts some registers
+   * default values untouched. All registers values should be
+   * ensured/configured in future probably.
+   */
+
+  /* Enable IRQ offset via Vic controller */
+  _coreEnableIrqVicOffset_();
+
+  /* Initialize VIM table */
+  vimInit();
+#endif
+
+  /* Configure system response to error conditions signaled to the ESM group1 */
+  tms570_esm_init();
+
+#if 1
+  /*
+   * Do not depend on link register to be restored to
+   * correct value from stack. If TCRAM self test is enabled
+   * the all stack content is zeroed there.
+   */
+  bsp_start_hook_0_done();
+#endif
+}
+
+BSP_START_TEXT_SECTION void bsp_start_hook_1( void )
+{
+  /* At this point we can use objects outside the .start section  */
+#if 0
+  /* Do not run attempt to initialize MPU when code is running from SDRAM */
+  if ( !tms570_running_from_sdram() ) {
+    /*
+     * MPU background areas setting has to be overlaid
+     * if execution of code is required from external memory/SDRAM.
+     * This region is non executable by default.
+     */
+    _mpuInit_();
+  }
+#endif
+  tms570_emif_sdram_init();
+
+  bsp_start_copy_sections();
+  bsp_start_clear_bss();
+}
+
+/*
+ * Chip specific list of peripherals which should be tested
+ * for functional RAM parity reporting
+ */
+const tms570_selftest_par_desc_t *const
+tms570_selftest_par_list[] = {
+  &tms570_selftest_par_het1_desc,
+  &tms570_selftest_par_htu1_desc,
+  &tms570_selftest_par_het2_desc,
+  &tms570_selftest_par_htu2_desc,
+  &tms570_selftest_par_adc1_desc,
+  &tms570_selftest_par_adc2_desc,
+  &tms570_selftest_par_can1_desc,
+  &tms570_selftest_par_can2_desc,
+  &tms570_selftest_par_can3_desc,
+  &tms570_selftest_par_vim_desc,
+  &tms570_selftest_par_dma_desc,
+  &tms570_selftest_par_spi1_desc,
+  &tms570_selftest_par_spi3_desc,
+  &tms570_selftest_par_spi5_desc,
+};
+
+const int tms570_selftest_par_list_size =
+  RTEMS_ARRAY_SIZE( tms570_selftest_par_list );

c/src/lib/libbsp/arm/tms570/hwinit/fail_notification.c

@@ -0,0 +1,17 @@
+#include <stdint.h>
+#include <stdbool.h>
+#include <bsp/tms570.h>
+#include "tms570_selftest.h"
+
+void bsp_selftest_fail_notification( uint32_t flag )
+{
+}
+
+void tms570_memory_port0_fail_notification(
+  uint32_t groupSelect,
+  uint32_t dataSelect,
+  uint32_t address,
+  uint32_t data
+)
+{
+}

c/src/lib/libbsp/arm/tms570/hwinit/init_emif_sdram.c

@@ -0,0 +1,64 @@
+/**
+ * @file init_emif_sdram.c
+ *
+ * @ingroup tms570
+ *
+ * @brief Initialization of external memory/SDRAM interface.
+ */
+
+#include <stdint.h>
+#include <bsp/tms570.h>
+#include "tms570_hwinit.h"
+
+void tms570_emif_sdram_init( void )
+{
+  uint32_t dummy;
+  uint32_t sdtimr = 0;
+  uint32_t sdcr = 0;
+
+  /* Do not run attempt to initialize SDRAM when code is running from it */
+  if ( ( (void*)tms570_emif_sdram_init >= (void*)TMS570_SDRAM_START_PTR ) &&
+       ( (void*)tms570_emif_sdram_init <= (void*)TMS570_SDRAM_WINDOW_END_PTR ) )
+    return;
+
+  sdtimr = TMS570_EMIF_SDTIMR_T_RFC_SET( sdtimr, 6 - 1 );
+  sdtimr = TMS570_EMIF_SDTIMR_T_RP_SET( sdtimr, 2 - 1 );
+  sdtimr = TMS570_EMIF_SDTIMR_T_RCD_SET( sdtimr, 2 - 1 );
+  sdtimr = TMS570_EMIF_SDTIMR_T_WR_SET( sdtimr, 2 - 1 );
+  sdtimr = TMS570_EMIF_SDTIMR_T_RAS_SET( sdtimr, 4 - 1 );
+  sdtimr = TMS570_EMIF_SDTIMR_T_RC_SET( sdtimr, 6 - 1 );
+  sdtimr = TMS570_EMIF_SDTIMR_T_RRD_SET( sdtimr, 2 - 1 );
+
+  TMS570_EMIF.SDTIMR = sdtimr;
+
+  /* Minimum number of ECLKOUT cycles from Self-Refresh exit to any command */
+  TMS570_EMIF.SDSRETR = 5;
+  /* Define the SDRAM refresh period in terms of EMIF_CLK cycles. */
+  TMS570_EMIF.SDRCR = 2000;
+
+  /* SR - Self-Refresh mode bit. */
+  sdcr |= TMS570_EMIF_SDCR_SR * 0;
+  /* field: PD - Power Down bit controls entering and exiting of the power-down mode. */
+  sdcr |= TMS570_EMIF_SDCR_PD * 0;
+  /* PDWR - Perform refreshes during power down. */
+  sdcr |= TMS570_EMIF_SDCR_PDWR * 0;
+  /* NM - Narrow mode bit defines whether SDRAM is 16- or 32-bit-wide */
+  sdcr |= TMS570_EMIF_SDCR_NM * 1;
+  /* CL - CAS Latency. */
+  sdcr = TMS570_EMIF_SDCR_CL_SET( sdcr, 2 );
+  /* CL can only be written if BIT11_9LOCK is simultaneously written with a 1. */
+  sdcr |= TMS570_EMIF_SDCR_BIT11_9LOCK * 1;
+  /* IBANK - Internal SDRAM Bank size. */
+  sdcr = TMS570_EMIF_SDCR_IBANK_SET( sdcr, 2 ); /* 4-banks device */
+  /* Page Size. This field defines the internal page size of connected SDRAM devices. */
+  sdcr = TMS570_EMIF_SDCR_PAGESIZE_SET( sdcr, 0 ); /* elements_256 */
+
+  TMS570_EMIF.SDCR = sdcr;
+
+  dummy = *(volatile uint32_t*)TMS570_SDRAM_START_PTR;
+  (void) dummy;
+  TMS570_EMIF.SDRCR = 31;
+
+  /* Define the SDRAM refresh period in terms of EMIF_CLK cycles. */
+  TMS570_EMIF.SDRCR = 312;
+}

c/src/lib/libbsp/arm/tms570/hwinit/init_esm.c

@@ -0,0 +1,62 @@
+/**
+ * @file init_esm.c
+ *
+ * @ingroup tms570
+ *
+ * @brief Error signaling module initialization
+ */
+
+#include <stdint.h>
+#include <bsp/tms570.h>
+#include "tms570_hwinit.h"
+
+/**
+ * @brief Error signaling module initialization (HCG:esmInit)
+ *
+ */
+void tms570_esm_init( void )
+{
+  /** - Disable error pin channels */
+  TMS570_ESM.DEPAPR1 = 0xFFFFFFFFU;
+  TMS570_ESM.IEPCR4 = 0xFFFFFFFFU;
+
+  /** - Disable interrupts */
+  TMS570_ESM.IECR1 = 0xFFFFFFFFU;
+  TMS570_ESM.IECR4 = 0xFFFFFFFFU;
+
+  /** - Clear error status flags */
+  TMS570_ESM.SR[0U] = 0xFFFFFFFFU;
+  TMS570_ESM.SR[1U] = 0xFFFFFFFFU;
+  TMS570_ESM.SSR2   = 0xFFFFFFFFU;
+  TMS570_ESM.SR[2U] = 0xFFFFFFFFU;
+  TMS570_ESM.SR4    = 0xFFFFFFFFU;
+
+  /** - Setup LPC preload */
+  TMS570_ESM.LTCPR = 16384U - 1U;
+
+  /** - Reset error pin */
+  if (TMS570_ESM.EPSR == 0U) {
+    TMS570_ESM.EKR = 0x00000005U;
+  } else {
+    TMS570_ESM.EKR = 0x00000000U;
+  }
+
+  /** - Clear interrupt level */
+  TMS570_ESM.ILCR1 = 0xFFFFFFFFU;
+  TMS570_ESM.ILCR4 = 0xFFFFFFFFU;
+
+  /** - Set interrupt level */
+  TMS570_ESM.ILSR1 = 0x00000000;
+
+  TMS570_ESM.ILSR4 = 0x00000000;
+
+  /** - Enable error pin channels */
+  TMS570_ESM.EEPAPR1 = 0x00000000;
+
+  TMS570_ESM.IEPSR4 = 0x00000000;
+
+  /** - Enable interrupts */
+  TMS570_ESM.IESR1 = 0x00000000;
+
+  TMS570_ESM.IESR4 = 0x00000000;
+}

c/src/lib/libbsp/arm/tms570/hwinit/init_pinmux.c

@@ -0,0 +1,259 @@
+/**
+ * @file init_pinmux.c
+ *
+ * @ingroup tms570
+ *
+ * @brief Initialize pin multiplexers.
+ */
+/*
+ * Copyright (c) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include <stdint.h>
+#include <bsp/tms570.h>
+#include <bsp/tms570-pinmux.h>
+#include <rtems.h>
+#include "tms570_hwinit.h"
+
+/*
+ * To check that content is right generated use
+ *
+ * objdump --section=.rodata -s init_pinmux.o
+ */
+#if 0
+
+/*
+ * Test of use of the default pins configuration with one line added.
+ * This can be used to concatenate partial lists but care has to
+ * be taken to not attempt to override already defined pin.
+ * This would not work and result in two PINMMR bits set
+ * for given pine.
+ */
+
+#ifndef TMS570_PINMMR_INIT_LIST
+  #define TMS570_PINMMR_INIT_LIST(per_pin_action, common_arg) \
+     TMS570_PINMMR_DEFAULT_INIT_LIST(per_pin_action, common_arg) \
+     per_pin_action(common_arg, TMS570_BALL_E3_HET2_18)
+#endif
+
+#else
+
+/*
+ * Definition of fuctions for all pins of TMS570LS3137.
+ * This setup correctponds to TMS570LS31x HDK Kit
+ */
+
+#define TMS570_PINMMR_INIT_LIST( per_pin_action, common_arg ) \
+  per_pin_action( common_arg, TMS570_BALL_W10_GIOB_3 ) \
+  per_pin_action( common_arg, TMS570_BALL_A5_GIOA_0 ) \
+  per_pin_action( common_arg, TMS570_BALL_C3_MIBSPI3NCS_3 ) \
+  per_pin_action( common_arg, TMS570_BALL_B2_MIBSPI3NCS_2 ) \
+  per_pin_action( common_arg, TMS570_BALL_C2_GIOA_1 ) \
+  per_pin_action( common_arg, TMS570_BALL_E3_HET1_11 ) \
+  per_pin_action( common_arg, TMS570_BALL_E5_EMIF_DATA_4 ) \
+  per_pin_action( common_arg, TMS570_BALL_F5_EMIF_DATA_5 ) \
+  per_pin_action( common_arg, TMS570_BALL_C1_GIOA_2 ) \
+  per_pin_action( common_arg, TMS570_BALL_G5_EMIF_DATA_6 ) \
+  per_pin_action( common_arg, TMS570_BALL_E1_GIOA_3 ) \
+  per_pin_action( common_arg, TMS570_BALL_B5_GIOA_5 ) \
+  per_pin_action( common_arg, TMS570_BALL_K5_EMIF_DATA_7 ) \
+  per_pin_action( common_arg, TMS570_BALL_B3_HET1_22 ) \
+  per_pin_action( common_arg, TMS570_BALL_H3_GIOA_6 ) \
+  per_pin_action( common_arg, TMS570_BALL_L5_EMIF_DATA_8 ) \
+  per_pin_action( common_arg, TMS570_BALL_M1_GIOA_7 ) \
+  per_pin_action( common_arg, TMS570_BALL_M5_EMIF_DATA_9 ) \
+  per_pin_action( common_arg, TMS570_BALL_V2_HET1_01 ) \
+  per_pin_action( common_arg, TMS570_BALL_U1_HET1_03 ) \
+  per_pin_action( common_arg, TMS570_BALL_K18_HET1_00 ) \
+  per_pin_action( common_arg, TMS570_BALL_W5_HET1_02 ) \
+  per_pin_action( common_arg, TMS570_BALL_V6_HET1_05 ) \
+  per_pin_action( common_arg, TMS570_BALL_N5_EMIF_DATA_10 ) \
+  per_pin_action( common_arg, TMS570_BALL_T1_HET1_07 ) \
+  per_pin_action( common_arg, TMS570_BALL_P5_EMIF_DATA_11 ) \
+  per_pin_action( common_arg, TMS570_BALL_V7_HET1_09 ) \
+  per_pin_action( common_arg, TMS570_BALL_R5_EMIF_DATA_12 ) \
+  per_pin_action( common_arg, TMS570_BALL_R6_EMIF_DATA_13 ) \
+  per_pin_action( common_arg, TMS570_BALL_V5_MIBSPI3NCS_1 ) \
+  per_pin_action( common_arg, TMS570_BALL_W3_SCIRX ) \
+  per_pin_action( common_arg, TMS570_BALL_R7_EMIF_DATA_14 ) \
+  per_pin_action( common_arg, TMS570_BALL_N2_SCITX ) \
+  per_pin_action( common_arg, TMS570_BALL_G3_MIBSPI1NCS_2 ) \
+  per_pin_action( common_arg, TMS570_BALL_N1_HET1_15 ) \
+  per_pin_action( common_arg, TMS570_BALL_R8_EMIF_DATA_15 ) \
+  per_pin_action( common_arg, TMS570_BALL_R9_ETMTRACECLKIN ) \
+  per_pin_action( common_arg, TMS570_BALL_W9_MIBSPI3NENA ) \
+  per_pin_action( common_arg, TMS570_BALL_V10_MIBSPI3NCS_0 ) \
+  per_pin_action( common_arg, TMS570_BALL_J3_MIBSPI1NCS_3 ) \
+  per_pin_action( common_arg, TMS570_BALL_N19_AD1EVT ) \
+  per_pin_action( common_arg, TMS570_BALL_N15_EMIF_DATA_3 ) \
+  per_pin_action( common_arg, TMS570_BALL_N17_EMIF_nCS_0 ) \
+  per_pin_action( common_arg, TMS570_BALL_M15_EMIF_DATA_2 ) \
+  per_pin_action( common_arg, TMS570_BALL_K17_EMIF_nCS_3 ) \
+  per_pin_action( common_arg, TMS570_BALL_M17_EMIF_nCS_4 ) \
+  per_pin_action( common_arg, TMS570_BALL_L15_EMIF_DATA_1 ) \
+  per_pin_action( common_arg, TMS570_BALL_P1_HET1_24 ) \
+  per_pin_action( common_arg, TMS570_BALL_A14_HET1_26 ) \
+  per_pin_action( common_arg, TMS570_BALL_K15_EMIF_DATA_0 ) \
+  per_pin_action( common_arg, TMS570_BALL_G19_MIBSPI1NENA ) \
+  per_pin_action( common_arg, TMS570_BALL_H18_MIBSPI5NENA ) \
+  per_pin_action( common_arg, TMS570_BALL_J18_MIBSPI5SOMI_0 ) \
+  per_pin_action( common_arg, TMS570_BALL_J19_MIBSPI5SIMO_0 ) \
+  per_pin_action( common_arg, TMS570_BALL_H19_MIBSPI5CLK ) \
+  per_pin_action( common_arg, TMS570_BALL_R2_MIBSPI1NCS_0 ) \
+  per_pin_action( common_arg, TMS570_BALL_E18_HET1_08 ) \
+  per_pin_action( common_arg, TMS570_BALL_K19_HET1_28 ) \
+  per_pin_action( common_arg, TMS570_BALL_D17_EMIF_nWE ) \
+  per_pin_action( common_arg, TMS570_BALL_D16_EMIF_BA_1 ) \
+  per_pin_action( common_arg, TMS570_BALL_C17_EMIF_ADDR_21 ) \
+  per_pin_action( common_arg, TMS570_BALL_C16_EMIF_ADDR_20 ) \
+  per_pin_action( common_arg, TMS570_BALL_C15_EMIF_ADDR_19 ) \
+  per_pin_action( common_arg, TMS570_BALL_D15_EMIF_ADDR_18 ) \
+  per_pin_action( common_arg, TMS570_BALL_E13_EMIF_BA_0 ) \
+  per_pin_action( common_arg, TMS570_BALL_C14_EMIF_ADDR_17 ) \
+  per_pin_action( common_arg, TMS570_BALL_D14_EMIF_ADDR_16 ) \
+  per_pin_action( common_arg, TMS570_BALL_E12_EMIF_nOE ) \
+  per_pin_action( common_arg, TMS570_BALL_D19_HET1_10 ) \
+  per_pin_action( common_arg, TMS570_BALL_E11_EMIF_nDQM_1 ) \
+  per_pin_action( common_arg, TMS570_BALL_B4_HET1_12 ) \
+  per_pin_action( common_arg, TMS570_BALL_E9_EMIF_ADDR_5 ) \
+  per_pin_action( common_arg, TMS570_BALL_C13_EMIF_ADDR_15 ) \
+  per_pin_action( common_arg, TMS570_BALL_A11_HET1_14 ) \
+  per_pin_action( common_arg, TMS570_BALL_C12_EMIF_ADDR_14 ) \
+  per_pin_action( common_arg, TMS570_BALL_M2_GIOB_0 ) \
+  per_pin_action( common_arg, TMS570_BALL_E8_EMIF_ADDR_4 ) \
+  per_pin_action( common_arg, TMS570_BALL_B11_HET1_30 ) \
+  per_pin_action( common_arg, TMS570_BALL_E10_EMIF_nDQM_0 ) \
+  per_pin_action( common_arg, TMS570_BALL_E7_EMIF_ADDR_3 ) \
+  per_pin_action( common_arg, TMS570_BALL_C11_EMIF_ADDR_13 ) \
+  per_pin_action( common_arg, TMS570_BALL_C10_EMIF_ADDR_12 ) \
+  per_pin_action( common_arg, TMS570_BALL_F3_MIBSPI1NCS_1 ) \
+  per_pin_action( common_arg, TMS570_BALL_C9_EMIF_ADDR_11 ) \
+  per_pin_action( common_arg, TMS570_BALL_D5_EMIF_ADDR_1 ) \
+  per_pin_action( common_arg, TMS570_BALL_K2_GIOB_1 ) \
+  per_pin_action( common_arg, TMS570_BALL_C8_EMIF_ADDR_10 ) \
+  per_pin_action( common_arg, TMS570_BALL_C7_EMIF_ADDR_9 ) \
+  per_pin_action( common_arg, TMS570_BALL_D4_EMIF_ADDR_0 ) \
+  per_pin_action( common_arg, TMS570_BALL_C5_EMIF_ADDR_7 ) \
+  per_pin_action( common_arg, TMS570_BALL_C4_EMIF_ADDR_6 ) \
+  per_pin_action( common_arg, TMS570_BALL_E6_EMIF_ADDR_2 ) \
+  per_pin_action( common_arg, TMS570_BALL_C6_EMIF_ADDR_8 ) \
+  per_pin_action( common_arg, TMS570_MMR_SELECT_SPI4CLK ) \
+  per_pin_action( common_arg, TMS570_MMR_SELECT_SPI4SIMO ) \
+  per_pin_action( common_arg, TMS570_MMR_SELECT_SPI4SOMI ) \
+  per_pin_action( common_arg, TMS570_MMR_SELECT_SPI4NENA ) \
+  per_pin_action( common_arg, TMS570_MMR_SELECT_SPI4NCS_0 ) \
+  per_pin_action( common_arg, TMS570_BALL_A13_HET1_17 ) \
+  per_pin_action( common_arg, TMS570_BALL_B13_HET1_19 ) \
+  per_pin_action( common_arg, TMS570_BALL_H4_HET1_21 ) \
+  per_pin_action( common_arg, TMS570_BALL_J4_HET1_23 ) \
+  per_pin_action( common_arg, TMS570_BALL_M3_HET1_25 ) \
+  per_pin_action( common_arg, TMS570_BALL_A9_HET1_27 ) \
+  per_pin_action( common_arg, TMS570_BALL_A3_HET1_29 ) \
+  per_pin_action( common_arg, TMS570_BALL_J17_HET1_31 ) \
+  per_pin_action( common_arg, TMS570_BALL_W6_MIBSPI5NCS_2 ) \
+  per_pin_action( common_arg, TMS570_BALL_T12_MIBSPI5NCS_3 ) \
+  per_pin_action( common_arg, TMS570_BALL_E19_MIBSPI5NCS_0 ) \
+  per_pin_action( common_arg, TMS570_BALL_B6_MIBSPI5NCS_1 ) \
+  per_pin_action( common_arg, TMS570_BALL_E16_MIBSPI5SIMO_1 ) \
+  per_pin_action( common_arg, TMS570_BALL_H17_MIBSPI5SIMO_2 ) \
+  per_pin_action( common_arg, TMS570_BALL_G17_MIBSPI5SIMO_3 ) \
+  per_pin_action( common_arg, TMS570_BALL_E17_MIBSPI5SOMI_1 ) \
+  per_pin_action( common_arg, TMS570_BALL_H16_MIBSPI5SOMI_2 ) \
+  per_pin_action( common_arg, TMS570_BALL_G16_MIBSPI5SOMI_3 ) \
+  per_pin_action( common_arg, TMS570_BALL_D3_SPI2NENA ) \
+  per_pin_action( common_arg, \
+  TMS570_MMR_SELECT_EMIF_CLK_SEL | TMS570_PIN_CLEAR_RQ_MASK ) \
+  per_pin_action( common_arg, \
+  TMS570_BALL_F2_GIOB_2 | TMS570_PIN_CLEAR_RQ_MASK ) \
+  per_pin_action( common_arg, \
+  TMS570_MMR_SELECT_GMII_SEL | TMS570_PIN_CLEAR_RQ_MASK ) \
+  per_pin_action( common_arg, TMS570_MMR_SELECT_ADC_TRG1 ) \
+
+
+#endif
+
+/*
+ * The next construct allows to compute values for individual
+ * PINMMR registers based on the multiple processing
+ * complete pin functions list at compile time.
+ * Each line computes 32-bit value which selects function
+ * of consecutive four pins. Each pin function is defined
+ * by single byte.
+ */
+const uint32_t tms570_pinmmr_init_data[] = {
+  TMS570_PINMMR_REG_VAL( 0, TMS570_PINMMR_INIT_LIST ),
+  TMS570_PINMMR_REG_VAL( 1, TMS570_PINMMR_INIT_LIST ),
+  TMS570_PINMMR_REG_VAL( 2, TMS570_PINMMR_INIT_LIST ),
+  TMS570_PINMMR_REG_VAL( 3, TMS570_PINMMR_INIT_LIST ),
+  TMS570_PINMMR_REG_VAL( 4, TMS570_PINMMR_INIT_LIST ),
+  TMS570_PINMMR_REG_VAL( 5, TMS570_PINMMR_INIT_LIST ),
+  TMS570_PINMMR_REG_VAL( 6, TMS570_PINMMR_INIT_LIST ),
+  TMS570_PINMMR_REG_VAL( 7, TMS570_PINMMR_INIT_LIST ),
+  TMS570_PINMMR_REG_VAL( 8, TMS570_PINMMR_INIT_LIST ),
+  TMS570_PINMMR_REG_VAL( 9, TMS570_PINMMR_INIT_LIST ),
+  TMS570_PINMMR_REG_VAL( 10, TMS570_PINMMR_INIT_LIST ),
+  TMS570_PINMMR_REG_VAL( 11, TMS570_PINMMR_INIT_LIST ),
+  TMS570_PINMMR_REG_VAL( 12, TMS570_PINMMR_INIT_LIST ),
+  TMS570_PINMMR_REG_VAL( 13, TMS570_PINMMR_INIT_LIST ),
+  TMS570_PINMMR_REG_VAL( 14, TMS570_PINMMR_INIT_LIST ),
+  TMS570_PINMMR_REG_VAL( 15, TMS570_PINMMR_INIT_LIST ),
+  TMS570_PINMMR_REG_VAL( 16, TMS570_PINMMR_INIT_LIST ),
+  TMS570_PINMMR_REG_VAL( 17, TMS570_PINMMR_INIT_LIST ),
+  TMS570_PINMMR_REG_VAL( 18, TMS570_PINMMR_INIT_LIST ),
+  TMS570_PINMMR_REG_VAL( 19, TMS570_PINMMR_INIT_LIST ),
+  TMS570_PINMMR_REG_VAL( 20, TMS570_PINMMR_INIT_LIST ),
+  TMS570_PINMMR_REG_VAL( 21, TMS570_PINMMR_INIT_LIST ),
+  TMS570_PINMMR_REG_VAL( 22, TMS570_PINMMR_INIT_LIST ),
+  TMS570_PINMMR_REG_VAL( 23, TMS570_PINMMR_INIT_LIST ),
+  TMS570_PINMMR_REG_VAL( 24, TMS570_PINMMR_INIT_LIST ),
+  TMS570_PINMMR_REG_VAL( 25, TMS570_PINMMR_INIT_LIST ),
+  TMS570_PINMMR_REG_VAL( 26, TMS570_PINMMR_INIT_LIST ),
+  TMS570_PINMMR_REG_VAL( 27, TMS570_PINMMR_INIT_LIST ),
+  TMS570_PINMMR_REG_VAL( 28, TMS570_PINMMR_INIT_LIST ),
+  TMS570_PINMMR_REG_VAL( 29, TMS570_PINMMR_INIT_LIST ),
+  TMS570_PINMMR_REG_VAL( 30, TMS570_PINMMR_INIT_LIST ),
+};
+
+/**
+ * @brief setups pin multiplexer according to precomputed registers values (HCG:muxInit)
+ */
+void tms570_pinmux_init( void )
+{
+  tms570_bsp_pinmmr_config( tms570_pinmmr_init_data, 0,
+    RTEMS_ARRAY_SIZE( tms570_pinmmr_init_data ) );
+}
+
+#if 0
+
+/*
+ * Alternative option how to set function of individual pins
+ * or use list for one by one setting. This is much slower
+ * and consumes more memory to hold complete list.
+ *
+ * On the other hand this solution can be used for configuration
+ * or reconfiguration of some shorter groups of pins at runtime.
+ *
+ */
+
+const uint32_t tms570_pinmmr_init_list[] = {
+  TMS570_PINMMR_COMA_LIST( TMS570_PINMMR_INIT_LIST )
+};
+
+void tms570_pinmux_init_by_list( void )
+{
+  int pincnt = RTEMS_ARRAY_SIZE( tms570_pinmmr_init_list );
+  const uint32_t *pinfnc = tms570_pinmmr_init_list;
+
+  while ( pincnt-- )
+    tms570_bsp_pin_config_one( *(pinfnc++) );
+}
+#endif

c/src/lib/libbsp/arm/tms570/hwinit/init_system.c

@@ -0,0 +1,378 @@
+/** @file init_system.c
+
+   based on Ti HalCoGen generated file
+ */
+
+/*
+ * Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <bsp/tms570.h>
+#include <bsp/tms570-pinmux.h>
+#include "tms570_selftest.h"
+#include "tms570_hwinit.h"
+
+/**
+ * @brief Setup all system PLLs (HCG:setupPLL)
+ *
+ */
+void tms570_pll_init( void )
+{
+  uint32_t pll12_dis = 0x42;
+
+  /* Disable PLL1 and PLL2 */
+  TMS570_SYS1.CSDISSET = pll12_dis;
+
+  /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+  while ( ( TMS570_SYS1.CSDIS & pll12_dis ) != pll12_dis ) {
+    /* Wait */
+  }
+
+  /* Clear Global Status Register */
+  TMS570_SYS1.GLBSTAT = TMS570_SYS1_GLBSTAT_FBSLIP |
+                        TMS570_SYS1_GLBSTAT_RFSLIP |
+                        TMS570_SYS1_GLBSTAT_OSCFAIL;
+  /** - Configure PLL control registers */
+  /** @b Initialize @b Pll1: */
+
+  /* Setup pll control register 1 */
+  TMS570_SYS1.PLLCTL1 = TMS570_SYS1_PLLCTL1_ROS * 0 |
+                        TMS570_SYS1_PLLCTL1_MASK_SLIP( 1 ) |
+                        TMS570_SYS1_PLLCTL1_PLLDIV( 0x1f ) | /* max value */
+                        TMS570_SYS1_PLLCTL1_ROF * 0 |
+                        TMS570_SYS1_PLLCTL1_REFCLKDIV( 6 - 1 ) |
+                        TMS570_SYS1_PLLCTL1_PLLMUL( ( 120 - 1 ) << 8 );
+
+  /* Setup pll control register 2 */
+  TMS570_SYS1.PLLCTL2 = TMS570_SYS1_PLLCTL2_FMENA * 0 |
+                        TMS570_SYS1_PLLCTL2_SPREADINGRATE( 255 ) |
+                        TMS570_SYS1_PLLCTL2_MULMOD( 7 ) |
+                        TMS570_SYS1_PLLCTL2_ODPLL( 2 - 1 ) |
+                        TMS570_SYS1_PLLCTL2_SPR_AMOUNT( 61 );
+
+  /** @b Initialize @b Pll2: */
+
+  /* Setup pll2 control register */
+  TMS570_SYS2.PLLCTL3 = TMS570_SYS2_PLLCTL3_ODPLL2( 2 - 1 ) |
+                        TMS570_SYS2_PLLCTL3_PLLDIV2( 0x1F ) | /* max value */
+                        TMS570_SYS2_PLLCTL3_REFCLKDIV2( 6 - 1 ) |
+                        TMS570_SYS2_PLLCTL3_PLLMUL2( ( 120 - 1 ) << 8 );
+
+  /** - Enable PLL(s) to start up or Lock */
+  TMS570_SYS1.CSDIS = 0x00000000 | /* CLKSR0 on */
+                      0x00000000 | /* CLKSR1 on */
+                      0x00000008 | /* CLKSR3 off */
+                      0x00000000 | /* CLKSR4 on */
+                      0x00000000 | /* CLKSR5 on */
+                      0x00000000 | /* CLKSR6 on */
+                      0x00000080;  /* CLKSR7 off */
+}
+
+/**
+ * @brief Adjust Low-Frequency (LPO) oscilator (HCG:trimLPO)
+ *
+ */
+/* SourceId : SYSTEM_SourceId_002 */
+/* DesignId : SYSTEM_DesignId_002 */
+/* Requirements : HL_SR468 */
+void tms570_trim_lpo_init( void )
+{
+  /** @b Initialize Lpo: */
+  /** Load TRIM values from OTP if present else load user defined values */
+  /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
+  TMS570_SYS1.LPOMONCTL = TMS570_SYS1_LPOMONCTL_BIAS_ENABLE |
+                          TMS570_SYS1_LPOMONCTL_OSCFRQCONFIGCNT * 0 |
+                          TMS570_SYS1_LPOMONCTL_HFTRIM( 16 ) |
+                          16; /* LFTRIM  */
+}
+
+/* FIXME */
+enum tms570_flash_power_modes {
+  TMS570_FLASH_SYS_SLEEP = 0U,     /**< Alias for flash bank power mode sleep   */
+  TMS570_FLASH_SYS_STANDBY = 1U,   /**< Alias for flash bank power mode standby */
+  TMS570_FLASH_SYS_ACTIVE = 3U     /**< Alias for flash bank power mode active  */
+};
+
+enum tms570_system_clock_source {
+  TMS570_SYS_CLK_SRC_OSC = 0U,          /**< Alias for oscillator clock Source                */
+  TMS570_SYS_CLK_SRC_PLL1 = 1U,         /**< Alias for Pll1 clock Source                      */
+  TMS570_SYS_CLK_SRC_EXTERNAL1 = 3U,    /**< Alias for external clock Source                  */
+  TMS570_SYS_CLK_SRC_LPO_LOW = 4U,      /**< Alias for low power oscillator low clock Source  */
+  TMS570_SYS_CLK_SRC_LPO_HIGH = 5U,     /**< Alias for low power oscillator high clock Source */
+  TMS570_SYS_CLK_SRC_PLL2 = 6U,         /**< Alias for Pll2 clock Source                      */
+  TMS570_SYS_CLK_SRC_EXTERNAL2 = 7U,    /**< Alias for external 2 clock Source                */
+  TMS570_SYS_CLK_SRC_VCLK = 9U          /**< Alias for synchronous VCLK1 clock Source         */
+};
+
+/**
+ * @brief Setup Flash memory parameters and timing (HCG:setupFlash)
+ *
+ */
+/* SourceId : SYSTEM_SourceId_003 */
+/* DesignId : SYSTEM_DesignId_003 */
+/* Requirements : HL_SR457 */
+void tms570_flash_init( void )
+{
+  /** - Setup flash read mode, address wait states and data wait states */
+  TMS570_FLASH.FRDCNTL = TMS570_FLASH_FRDCNTL_RWAIT( 3 ) |
+                         TMS570_FLASH_FRDCNTL_ASWSTEN |
+                         TMS570_FLASH_FRDCNTL_ENPIPE;
+
+  /** - Setup flash access wait states for bank 7 */
+  TMS570_FLASH.FSMWRENA = TMS570_FLASH_FSMWRENA_WR_ENA( 0x5 );
+  TMS570_FLASH.EEPROMCONFIG = TMS570_FLASH_EEPROMCONFIG_EWAIT( 3 ) |
+                              TMS570_FLASH_EEPROMCONFIG_AUTOSUSP_EN * 0 |
+                              TMS570_FLASH_EEPROMCONFIG_AUTOSTART_GRACE( 2 );
+
+  /** - Disable write access to flash state machine registers */
+  TMS570_FLASH.FSMWRENA = TMS570_FLASH_FSMWRENA_WR_ENA( 0xA );
+
+  /** - Setup flash bank power modes */
+  TMS570_FLASH.FBFALLBACK = TMS570_FLASH_FBFALLBACK_BANKPWR7(
+    TMS570_FLASH_SYS_ACTIVE ) |
+                            TMS570_FLASH_FBFALLBACK_BANKPWR1(
+    TMS570_FLASH_SYS_ACTIVE ) |
+                            TMS570_FLASH_FBFALLBACK_BANKPWR0(
+    TMS570_FLASH_SYS_ACTIVE );
+}
+
+/**
+ * @brief Power-up all peripherals and enable their clocks (HCG:periphInit)
+ *
+ */
+/* SourceId : SYSTEM_SourceId_004 */
+/* DesignId : SYSTEM_DesignId_004 */
+/* Requirements : HL_SR470 */
+void tms570_periph_init( void )
+{
+  /** - Disable Peripherals before peripheral powerup*/
+  TMS570_SYS1.CLKCNTL &= ~TMS570_SYS1_CLKCNTL_PENA;
+
+  /** - Release peripherals from reset and enable clocks to all peripherals */
+  /** - Power-up all peripherals */
+  TMS570_PCR.PSPWRDWNCLR0 = 0xFFFFFFFFU;
+  TMS570_PCR.PSPWRDWNCLR1 = 0xFFFFFFFFU;
+  TMS570_PCR.PSPWRDWNCLR2 = 0xFFFFFFFFU;
+  TMS570_PCR.PSPWRDWNCLR3 = 0xFFFFFFFFU;
+
+  /** - Enable Peripherals */
+  TMS570_SYS1.CLKCNTL |= TMS570_SYS1_CLKCNTL_PENA;
+}
+
+/**
+ * @brief Setup chip clocks including to wait for PLLs locks (HCG:mapClocks)
+ *
+ */
+/* SourceId : SYSTEM_SourceId_005 */
+/* DesignId : SYSTEM_DesignId_005 */
+/* Requirements : HL_SR469 */
+void tms570_map_clock_init( void )
+{
+  uint32_t sys_csvstat, sys_csdis;
+
+  /** @b Initialize @b Clock @b Tree: */
+  /** - Disable / Enable clock domain */
+  TMS570_SYS1.CDDIS = ( 0U << 4U ) |  /* AVCLK 1 OFF */
+                      ( 0U << 5U ) |  /* AVCLK 2 OFF */
+                      ( 0U << 8U ) |  /* VCLK3 OFF */
+                      ( 0U << 9U ) |  /* VCLK4 OFF */
+                      ( 1U << 10U ) | /* AVCLK 3 OFF */
+                      ( 0U << 11U );  /* AVCLK 4 OFF */
+
+  /* Work Around for Errata SYS#46:
+   *
+   * Errata Description:
+   *            Clock Source Switching Not Qualified with Clock Source Enable And Clock Source Valid
+   * Workaround:
+   *            Always check the CSDIS register to make sure the clock source is turned on and check
+   * the CSVSTAT register to make sure the clock source is valid. Then write to GHVSRC to switch the clock.
+   */
+  /** - Wait for until clocks are locked */
+  sys_csvstat = TMS570_SYS1.CSVSTAT;
+  sys_csdis = TMS570_SYS1.CSDIS;
+
+  while ( ( sys_csvstat & ( ( sys_csdis ^ 0xFFU ) & 0xFFU ) ) !=
+          ( ( sys_csdis ^ 0xFFU ) & 0xFFU ) ) {
+    sys_csvstat = TMS570_SYS1.CSVSTAT;
+    sys_csdis = TMS570_SYS1.CSDIS;
+  } /* Wait */
+
+  /* Now the PLLs are locked and the PLL outputs can be sped up */
+  /* The R-divider was programmed to be 0xF. Now this divider is changed to programmed value */
+  TMS570_SYS1.PLLCTL1 =
+    ( TMS570_SYS1.PLLCTL1 & ~TMS570_SYS1_PLLCTL1_PLLDIV( 0x1F ) ) |
+    TMS570_SYS1_PLLCTL1_PLLDIV( 1 - 1 );
+  /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+  TMS570_SYS2.PLLCTL3 =
+    ( TMS570_SYS2.PLLCTL3 & ~TMS570_SYS2_PLLCTL3_PLLDIV2( 0x1F ) ) |
+    TMS570_SYS2_PLLCTL3_PLLDIV2( 1 - 1 );
+
+  /* Enable/Disable Frequency modulation */
+  TMS570_SYS1.PLLCTL2 &= ~TMS570_SYS1_PLLCTL2_FMENA;
+
+  /** - Map device clock domains to desired sources and configure top-level dividers */
+  /** - All clock domains are working off the default clock sources until now */
+  /** - The below assignments can be easily modified using the HALCoGen GUI */
+
+  /** - Setup GCLK, HCLK and VCLK clock source for normal operation, power down mode and after wakeup */
+  TMS570_SYS1.GHVSRC = TMS570_SYS1_GHVSRC_GHVWAKE( TMS570_SYS_CLK_SRC_OSC ) |
+                       TMS570_SYS1_GHVSRC_HVLPM( TMS570_SYS_CLK_SRC_OSC ) |
+                       TMS570_SYS1_GHVSRC_GHVSRC( TMS570_SYS_CLK_SRC_PLL1 );
+
+  /** - Setup synchronous peripheral clock dividers for VCLK1, VCLK2, VCLK3 */
+  TMS570_SYS1.CLKCNTL =
+    ( TMS570_SYS1.CLKCNTL & ~TMS570_SYS1_CLKCNTL_VCLK2R( 0xF ) ) |
+    TMS570_SYS1_CLKCNTL_VCLK2R( 1 );
+
+  TMS570_SYS1.CLKCNTL =
+    ( TMS570_SYS1.CLKCNTL & ~TMS570_SYS1_CLKCNTL_VCLKR( 0xF ) ) |
+    TMS570_SYS1_CLKCNTL_VCLKR( 1 );
+
+  TMS570_SYS2.CLK2CNTRL =
+    ( TMS570_SYS2.CLK2CNTRL & ~TMS570_SYS2_CLK2CNTRL_VCLK3R( 0xF ) ) |
+    TMS570_SYS2_CLK2CNTRL_VCLK3R( 1 );
+
+  TMS570_SYS2.CLK2CNTRL = ( TMS570_SYS2.CLK2CNTRL & 0xFFFFF0FFU ) |
+                          ( 1U << 8U ); /* FIXME: unknown in manual*/
+
+  /** - Setup RTICLK1 and RTICLK2 clocks */
+  TMS570_SYS1.RCLKSRC = ( 1U << 24U ) |
+                        ( TMS570_SYS_CLK_SRC_VCLK << 16U ) | /* FIXME: not in manual */
+                        TMS570_SYS1_RCLKSRC_RTI1DIV( 1 ) |
+                        TMS570_SYS1_RCLKSRC_RTI1SRC( TMS570_SYS_CLK_SRC_VCLK );
+
+  /** - Setup asynchronous peripheral clock sources for AVCLK1 and AVCLK2 */
+  TMS570_SYS1.VCLKASRC =
+    TMS570_SYS1_VCLKASRC_VCLKA2S( TMS570_SYS_CLK_SRC_VCLK ) |
+    TMS570_SYS1_VCLKASRC_VCLKA1S( TMS570_SYS_CLK_SRC_VCLK );
+
+  TMS570_SYS2.VCLKACON1 = TMS570_SYS2_VCLKACON1_VCLKA4R( 1 - 1 ) |
+                          TMS570_SYS2_VCLKACON1_VCLKA4_DIV_CDDIS * 0 |
+                          TMS570_SYS2_VCLKACON1_VCLKA4S(
+    TMS570_SYS_CLK_SRC_VCLK ) |
+                          TMS570_SYS2_VCLKACON1_VCLKA3R( 1 - 1 ) |
+                          TMS570_SYS2_VCLKACON1_VCLKA3_DIV_CDDIS * 0 |
+                          TMS570_SYS2_VCLKACON1_VCLKA3S(
+    TMS570_SYS_CLK_SRC_VCLK );
+}
+
+/**
+ * @brief TMS570 system hardware initialization (HCG:systemInit)
+ *
+ */
+/* SourceId : SYSTEM_SourceId_006 */
+/* DesignId : SYSTEM_DesignId_006 */
+/* Requirements : HL_SR471 */
+void tms570_system_hw_init( void )
+{
+  uint32_t efc_check_status;
+
+  /* Configure PLL control registers and enable PLLs.
+   * The PLL takes (127 + 1024 * NR) oscillator cycles to acquire lock.
+   * This initialization sequence performs all the tasks that are not
+   * required to be done at full application speed while the PLL locks.
+   */
+  tms570_pll_init();
+
+  /* Run eFuse controller start-up checks and start eFuse controller ECC self-test.
+   * This includes a check for the eFuse controller error outputs to be stuck-at-zero.
+   */
+  efc_check_status = tms570_efc_check();
+
+  /* Enable clocks to peripherals and release peripheral reset */
+  tms570_periph_init();
+
+  /* Configure device-level multiplexing and I/O multiplexing */
+  tms570_pinmux_init();
+
+  /* Enable external memory interface */
+  TMS570_SYS1.GPREG1 |= TMS570_SYS1_GPREG1_EMIF_FUNC;
+
+  if ( efc_check_status == 0U ) {
+    /* Wait for eFuse controller self-test to complete and check results */
+    if ( tms570_efc_check_self_test() == false ) { /* eFuse controller ECC logic self-test failed */
+      bsp_selftest_fail_notification( EFCCHECK_FAIL1 );           /* device operation is not reliable */
+    }
+  } else if ( efc_check_status == 2U ) {
+    /* Wait for eFuse controller self-test to complete and check results */
+    if ( tms570_efc_check_self_test() == false ) { /* eFuse controller ECC logic self-test failed */
+      bsp_selftest_fail_notification( EFCCHECK_FAIL1 );           /* device operation is not reliable */
+    } else {
+      bsp_selftest_fail_notification( EFCCHECK_FAIL2 );
+    }
+  } else {
+    /* Empty */
+  }
+
+  /** - Set up flash address and data wait states based on the target CPU clock frequency
+   * The number of address and data wait states for the target CPU clock frequency are specified
+   * in the specific part's datasheet.
+   */
+  tms570_flash_init();
+
+  /** - Configure the LPO such that HF LPO is as close to 10MHz as possible */
+  tms570_trim_lpo_init();
+
+  /** - Wait for PLLs to start up and map clock domains to desired clock sources */
+  tms570_map_clock_init();
+
+  /** - set ECLK pins functional mode */
+  TMS570_SYS1.SYSPC1 = 0U;
+
+  /** - set ECLK pins default output value */
+  TMS570_SYS1.SYSPC4 = 0U;
+
+  /** - set ECLK pins output direction */
+  TMS570_SYS1.SYSPC2 = 1U;
+
+  /** - set ECLK pins open drain enable */
+  TMS570_SYS1.SYSPC7 = 0U;
+
+  /** - set ECLK pins pullup/pulldown enable */
+  TMS570_SYS1.SYSPC8 = 0U;
+
+  /** - set ECLK pins pullup/pulldown select */
+  TMS570_SYS1.SYSPC9 = 1U;
+
+  /** - Setup ECLK */
+  TMS570_SYS1.ECPCNTL = TMS570_SYS1_ECPCNTL_ECPSSEL * 0 |
+                        TMS570_SYS1_ECPCNTL_ECPCOS * 0 |
+                        TMS570_SYS1_ECPCNTL_ECPDIV( 8 - 1 );
+}
+
+#if 0
+errata_PBIST_4
+vimInit
+#endif

c/src/lib/libbsp/arm/tms570/hwinit/tms570_hwinit.h

@@ -0,0 +1,31 @@
+#ifndef LIBBSP_ARM_TMS570_HWINIT_H
+#define LIBBSP_ARM_TMS570_HWINIT_H
+
+#define TMS570_TCRAM_START_PTR       ( (void *) ( 0x08000000U ) )
+#define TMS570_TCRAM_WINDOW_END_PTR  ( (void *) ( 0x08080000U ) )
+
+#define TMS570_SDRAM_START_PTR      ( (void *) ( 0x80000000U ) )
+#define TMS570_SDRAM_WINDOW_END_PTR ( (void *) ( 0xA0000000U ) )
+
+/* Ti TMS570 core setup implemented in assembly */
+void _esmCcmErrorsClear_( void );
+void _coreEnableEventBusExport_( void );
+void _errata_CORTEXR4_66_( void );
+void _errata_CORTEXR4_57_( void );
+void _coreEnableRamEcc_( void );
+void _coreDisableRamEcc_( void );
+void _mpuInit_( void );
+
+void tms570_emif_sdram_init( void );
+void tms570_memory_init( uint32_t ram );
+void tms570_system_hw_init( void );
+void tms570_pinmux_init( void );
+void tms570_pll_init( void );
+void tms570_trim_lpo_init( void );
+void tms570_flash_init( void );
+void tms570_periph_init( void );
+void tms570_map_clock_init( void );
+void tms570_system_hw_init( void );
+void tms570_esm_init( void );
+
+#endif /* LIBBSP_ARM_TMS570_HWINIT_H */

c/src/lib/libbsp/arm/tms570/hwinit/tms570_selftest.c

@@ -0,0 +1,598 @@
+/**
+ * @file tms570_selftest.c
+ *
+ * @ingroup tms570
+ *
+ * @brief TMS570 selftest support functions implementation.
+ */
+/*
+ * Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+#include <bsp/tms570.h>
+#include "tms570_selftest.h"
+#include "tms570_hwinit.h"
+
+/**
+ * @brief Checks to see if the EFUSE Stuck at zero test is completed successfully (HCG:efcStuckZeroTest).
+ /
+ * @return 1 if EFUSE Stuck at zero test completed, otherwise 0.
+ *
+ * Checks to see if the EFUSE Stuck at zero test is completed successfully.
+ */
+/* SourceId : SELFTEST_SourceId_012 */
+/* DesignId : SELFTEST_DesignId_014 */
+/* Requirements : HL_SR402 */
+bool tms570_efc_stuck_zero( void )
+{
+  uint32_t esm_estatus4, esm_estatus1;
+
+  bool result = false;
+
+  uint32_t output_enable = TMS570_EFUSE_EFCBOUND_Self_Test_Error_OE |
+                           TMS570_EFUSE_EFCBOUND_Single_Bit_Error_OE |
+                           TMS570_EFUSE_EFCBOUND_Instruction_Error_OE |
+                           TMS570_EFUSE_EFCBOUND_Autoload_Error_OE;
+
+  uint32_t error_checks = TMS570_EFUSE_EFCBOUND_EFC_Single_Bit_Error |
+                          TMS570_EFUSE_EFCBOUND_EFC_Instruction_Error |
+                          TMS570_EFUSE_EFCBOUND_EFC_Autoload_Error |
+                          TMS570_EFUSE_EFCBOUND_EFC_Self_Test_Error;
+
+  /* configure the output enable for auto load error , instruction info,
+       instruction error, and self test error using boundary register
+       and drive values one across all the errors */
+  TMS570_EFUSE.EFCBOUND = output_enable | error_checks;
+
+  /* Read from the pin register. This register holds the current values
+       of above errors. This value should be 0x5c00.If not at least one of
+       the above errors is stuck at 0. */
+  if ( ( TMS570_EFUSE.EFCPINS & 0x5C00U ) == 0x5C00U ) {
+    esm_estatus4 = TMS570_ESM.SR4;
+    esm_estatus1 = TMS570_ESM.SR[ 2U ];
+
+    /* check if the ESM group1 channel 41 is set and group3 channel 1 is set */
+    if ( ( ( esm_estatus4 & 0x200U ) == 0x200U ) &&
+         ( ( esm_estatus1 & 0x2U ) == 0x2U ) ) {
+      /* stuck-at-zero test passed */
+      result = true;
+    }
+  }
+
+  /* put the pins back low */
+  TMS570_EFUSE.EFCBOUND = output_enable;
+
+  /* clear group1 flag */
+  TMS570_ESM.SR4 = 0x200U;
+
+  /* clear group3 flag */
+  TMS570_ESM.SR[ 2U ] = 0x2U;
+
+  /* The nERROR pin will become inactive once the LTC counter expires */
+  TMS570_ESM.EKR = 0x5U;
+
+  return result;
+}
+
+/**
+ * @brief EFUSE module self check Driver (HCG:efcSelfTest)
+ *
+ * This function self checks the EFSUE module.
+ */
+/* SourceId : SELFTEST_SourceId_013 */
+/* DesignId : SELFTEST_DesignId_013 */
+/* Requirements : HL_SR402 */
+void tms570_efc_self_test( void )
+{
+  /* configure self-test cycles */
+  TMS570_EFUSE.EFC_ST_CY = 0x258U;
+
+  /* configure self-test signature */
+  TMS570_EFUSE.EFC_ST_SIG = 0x5362F97FU;
+
+  /* configure boundary register to start ECC self-test */
+  TMS570_EFUSE.EFCBOUND = 0x00002000 |
+                          TMS570_EFUSE_EFCBOUND_Input_Enable( 0xF );
+}
+
+/**
+ * @brief EFUSE module self check Driver (HCG:checkefcSelfTest)
+ *
+ * @return Returns TRUE if EFC Selftest was a PASS, else FALSE
+ *
+ * This function returns the status of efcSelfTest.
+ * Note: This function can be called only after calling efcSelfTest
+ */
+/* SourceId : SELFTEST_SourceId_014 */
+/* DesignId : SELFTEST_DesignId_015 */
+/* Requirements : HL_SR403 */
+bool tms570_efc_check_self_test( void )
+{
+  bool result = false;
+
+  uint32_t efc_pins, efc_error;
+  uint32_t esmCh40Stat, esmCh41Stat = 0U;
+
+  /* wait until EFC self-test is done */
+  /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+  while ( ( TMS570_EFUSE.EFCPINS & TMS570_EFUSE_EFCPINS_EFC_Selftest_Done ) ==
+          0U ) {
+  }                                                                               /* Wait */
+
+  /* check if EFC self-test error occurred */
+  efc_pins = TMS570_EFUSE.EFCPINS;
+  efc_error = TMS570_EFUSE.EFC_ERR_STAT;
+
+  if ( ( ( efc_pins & TMS570_EFUSE_EFCPINS_EFC_Selftest_Error ) == 0U ) &&
+       ( ( efc_error & 0x1FU ) == 0U ) ) {
+    /* check if EFC self-test error is set */
+    esmCh40Stat = TMS570_ESM.SR4 & 0x100U;
+    esmCh41Stat = TMS570_ESM.SR4 & 0x200U;
+
+    if ( ( esmCh40Stat == 0U ) && ( esmCh41Stat == 0U ) ) {
+      result = true;
+    }
+  }
+
+  return result;
+}
+
+/**
+ * @brief EFUSE module self check Driver (HCG:efcCheck)
+ * @return Returns 0 if no error was detected during autoload and Stuck At Zero Test passed
+ *                 1 if no error was detected during autoload but Stuck At Zero Test failed
+ *                 2 if there was a single-bit error detected during autoload
+ *                 3 if some other error occurred during autoload
+ *
+ *   This function self checks the EFUSE module.
+ */
+/* SourceId : SELFTEST_SourceId_011 */
+/* DesignId : SELFTEST_DesignId_012 */
+/* Requirements : HL_SR402 */
+uint32_t tms570_efc_check( void )
+{
+  uint32_t efc_status = 0U;
+  uint32_t status;
+
+  /* read the EFC Error Status Register */
+  efc_status = TMS570_EFUSE.EFC_ERR_STAT;
+
+  if ( efc_status == 0x0U ) {
+    /* run stuck-at-zero test and check if it passed */
+    if ( tms570_efc_stuck_zero() == true ) {
+      /* start EFC ECC logic self-test */
+      tms570_efc_self_test();
+      status = 0U;
+    } else {
+      /* EFC output is stuck-at-zero, device operation unreliable */
+      bsp_selftest_fail_notification( EFCCHECK_FAIL1 );
+      status = 1U;
+    }
+  }
+  /* EFC Error Register is not zero */
+  else {
+    /* one-bit error detected during autoload */
+    if ( efc_status == 0x15U ) {
+      /* start EFC ECC logic self-test */
+      tms570_efc_self_test();
+      status = 2U;
+    } else {
+      /* Some other EFC error was detected */
+      bsp_selftest_fail_notification( EFCCHECK_FAIL1 );
+      status = 3U;
+    }
+  }
+
+  return status;
+}
+
+/**
+ * @brief PBIST self test Driver (HCG:pbistSelfCheck)
+ *
+ * This function is called to perform PBIST self test.
+ */
+/* SourceId : SELFTEST_SourceId_005 */
+/* DesignId : SELFTEST_DesignId_005 */
+/* Requirements : HL_SR399 */
+void tms570_pbist_self_check( void )
+{
+  volatile uint32_t i = 0U;
+  uint32_t          PBIST_wait_done_loop = 0U;
+
+  /* Run a diagnostic check on the memory self-test controller */
+  /* First set up the PBIST ROM clock as this clock frequency is limited to 90MHz */
+
+  /* Disable PBIST clocks and ROM clock */
+  TMS570_PBIST.PACT = 0x0U;
+
+  /* PBIST ROM clock frequency = HCLK frequency /2 */
+  /* Disable memory self controller */
+  TMS570_SYS1.MSTGCR = 0x00000105U;
+
+  /* Disable Memory Initialization controller */
+  TMS570_SYS1.MINITGCR = 0x5U;
+
+  /* Enable memory self controller */
+  TMS570_SYS1.MSTGCR = 0x0000010AU;
+
+  /* Clear PBIST Done */
+  TMS570_SYS1.MSTCGSTAT = 0x1U;
+
+  /* Enable PBIST controller */
+  TMS570_SYS1.MSIENA = 0x1U;
+
+  /* wait for 32 VBUS clock cycles at least, based on HCLK to VCLK ratio */
+  /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */
+  /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */
+  for ( i = 0U; i < ( 32U + ( 32U * 1U ) ); i++ ) { /* Wait */
+  }
+
+  /* Enable PBIST clocks and ROM clock */
+  TMS570_PBIST.PACT = 0x3U;
+
+  /* CPU control of PBIST */
+  TMS570_PBIST.DLR = 0x10U;
+
+  /* Custom always fail algo, this will not use the ROM and just set a fail */
+  TMS570_PBIST.RAMT = 0x00002000U;
+  *(volatile uint32_t *) 0xFFFFE400U = 0x4C000001U;
+  *(volatile uint32_t *) 0xFFFFE440U = 0x00000075U;
+  *(volatile uint32_t *) 0xFFFFE404U = 0x4C000002U;
+  *(volatile uint32_t *) 0xFFFFE444U = 0x00000075U;
+  *(volatile uint32_t *) 0xFFFFE408U = 0x4C000003U;
+  *(volatile uint32_t *) 0xFFFFE448U = 0x00000075U;
+  *(volatile uint32_t *) 0xFFFFE40CU = 0x4C000004U;
+  *(volatile uint32_t *) 0xFFFFE44CU = 0x00000075U;
+  *(volatile uint32_t *) 0xFFFFE410U = 0x4C000005U;
+  *(volatile uint32_t *) 0xFFFFE450U = 0x00000075U;
+  *(volatile uint32_t *) 0xFFFFE414U = 0x4C000006U;
+  *(volatile uint32_t *) 0xFFFFE454U = 0x00000075U;
+  *(volatile uint32_t *) 0xFFFFE418U = 0x00000000U;
+  *(volatile uint32_t *) 0xFFFFE458U = 0x00000001U;
+
+  /* PBIST_RUN */
+  ( &TMS570_PBIST.DLR )[ 2 ] = 1;
+
+  /* wait until memory self-test done is indicated */
+  /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+  while ( ( TMS570_SYS1.MSTCGSTAT & 0x1U ) != 0x1U )
+    PBIST_wait_done_loop++;
+
+  /* Wait */
+
+  /* Check for the failure */
+  if ( ( TMS570_PBIST.FSRF0 & 0x1U ) != 0x1U ) {
+    /* No failure was indicated even if the always fail algorithm was run*/
+    bsp_selftest_fail_notification( PBISTSELFCHECK_FAIL1 );
+  } else {
+    /* Check that the algorithm executed in the expected amount of time. */
+    /* This time is dependent on the ROMCLKDIV selected above            */
+    if ( PBIST_wait_done_loop >= 2U ) {
+      bsp_selftest_fail_notification( PBISTSELFCHECK_FAIL2 );
+    }
+
+    /* Disable PBIST clocks and ROM clock */
+    TMS570_PBIST.PACT = 0x0U;
+
+    /* Disable PBIST */
+    TMS570_SYS1.MSTGCR &= 0xFFFFFFF0U;
+    TMS570_SYS1.MSTGCR |= 0x5U;
+  }
+}
+
+/**
+ * @brief CPU self test Driver (HCG:pbistRun)
+ * @param[in] raminfoL   - Select the list of RAM to be tested.
+ * @param[in] algomask   - Select the list of Algorithm to be run.
+ *
+ * This function performs Memory Built-in Self test using PBIST module.
+ */
+/* SourceId : SELFTEST_SourceId_006 */
+/* DesignId : SELFTEST_DesignId_006 */
+/* Requirements : HL_SR400 */
+void tms570_pbist_run(
+  uint32_t raminfoL,
+  uint32_t algomask
+)
+{
+  volatile uint32_t i = 0U;
+
+  /* PBIST ROM clock frequency = HCLK frequency /2 */
+  /* Disable memory self controller */
+  TMS570_SYS1.MSTGCR = 0x00000105U;
+
+  /* Disable Memory Initialization controller */
+  TMS570_SYS1.MINITGCR = 0x5U;
+
+  /* Enable PBIST controller */
+  TMS570_SYS1.MSIENA = 0x1U;
+
+  /* Enable memory self controller */
+  TMS570_SYS1.MSTGCR = 0x0000010AU;
+
+  /* wait for 32 VBUS clock cycles at least, based on HCLK to VCLK ratio */
+  /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */
+  /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */
+  for ( i = 0U; i < ( 32U + ( 32U * 1U ) ); i++ ) { /* Wait */
+  }
+
+  /* Enable PBIST clocks and ROM clock */
+  TMS570_PBIST.PACT = 0x3U;
+
+  /* Select all algorithms to be tested */
+  TMS570_PBIST.ALGO = algomask;
+
+  /* Select RAM groups */
+  TMS570_PBIST.RINFOL = raminfoL;
+
+  /* Select all RAM groups */
+  TMS570_PBIST.RINFOUL = 0x00000000U;
+
+  /* ROM contents will not override RINFOx settings */
+  TMS570_PBIST.OVER = 0x0U;
+
+  /* Algorithm code is loaded from ROM */
+  TMS570_PBIST.ROM = 0x3U;
+
+  /* Start PBIST */
+  TMS570_PBIST.DLR = 0x14U;
+}
+
+/**
+ *  @brief Routine to stop PBIST test enabled (HCG:pbistStop)
+ *
+ *  This function is called to stop PBIST after test is performed.
+ */
+/* SourceId : SELFTEST_SourceId_007 */
+/* DesignId : SELFTEST_DesignId_007 */
+/* Requirements : HL_SR523 */
+void tms570_pbist_stop( void )
+{
+  /* disable pbist clocks and ROM clock */
+  TMS570_PBIST.PACT = 0x0U;
+  TMS570_SYS1.MSTGCR &= 0xFFFFFFF0U;
+  TMS570_SYS1.MSTGCR |= 0x5U;
+}
+
+/**
+ * @brief Checks to see if the PBIST test is completed (HCG:pbistIsTestCompleted)
+ * @return 1 if PBIST test completed, otherwise 0.
+ *
+ * Checks to see if the PBIST test is completed.
+ */
+/* SourceId : SELFTEST_SourceId_008 */
+/* DesignId : SELFTEST_DesignId_008 */
+/* Requirements : HL_SR401 */
+bool tms570_pbist_is_test_completed( void )
+{
+  return ( ( TMS570_SYS1.MSTCGSTAT & 0x1U ) != 0U );
+}
+
+/**
+ * @brief Checks to see if the PBIST test is completed successfully (HCG:pbistIsTestPassed)
+ * @return 1 if PBIST test passed, otherwise 0.
+ *
+ * Checks to see if the PBIST test is completed successfully.
+ */
+/* SourceId : SELFTEST_SourceId_009 */
+/* DesignId : SELFTEST_DesignId_009 */
+/* Requirements : HL_SR401 */
+bool tms570_pbist_is_test_passed( void )
+{
+  bool status;
+
+  if ( TMS570_PBIST.FSRF0 == 0U ) {
+    status = true;
+  } else {
+    status = false;
+  }
+
+  return status;
+}
+
+/**
+ * @brief Checks to see if the PBIST Port test is completed successfully (HCG:pbistPortTestStatus)
+ * @param[in] port   - Select the port to get the status.
+ * @return 1 if PBIST Port test completed successfully, otherwise 0.
+ *
+ * Checks to see if the selected PBIST Port test is completed successfully.
+ */
+/* SourceId : SELFTEST_SourceId_010 */
+/* DesignId : SELFTEST_DesignId_010 */
+/* Requirements : HL_SR401 */
+bool tms570_pbist_port_test_status( uint32_t port )
+{
+  bool status;
+
+  if ( port == (uint32_t) PBIST_PORT0 ) {
+    status = ( TMS570_PBIST.FSRF0 == 0U );
+  } else {
+    /* Invalid Input */
+    status = false;
+  }
+
+  return status;
+}
+
+/**
+ * @brief Reaction to PBIST failure (HCG:pbistFail)
+ *
+ * @return Void.
+ */
+/* SourceId : SELFTEST_SourceId_042 */
+/* DesignId : SELFTEST_DesignId_011 */
+/* Requirements : HL_SR401 */
+void tms570_pbist_fail( void )
+{
+  uint32_t PBIST_RAMT, PBIST_FSRA0, PBIST_FSRDL0;
+
+  /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+  PBIST_RAMT = TMS570_PBIST.RAMT;
+  PBIST_FSRA0 = TMS570_PBIST.FSRA0;
+  PBIST_FSRDL0 = TMS570_PBIST.FSRDL0;
+
+  if ( tms570_pbist_port_test_status( (uint32_t) PBIST_PORT0 ) != true ) {
+    uint32_t groupSelect = ( PBIST_RAMT & 0xFF000000U ) >> 24U;
+    uint32_t dataSelect = ( PBIST_RAMT & 0x00FF0000U ) >> 16U;
+    uint32_t address = PBIST_FSRA0;
+    uint32_t data = PBIST_FSRDL0;
+    tms570_memory_port0_fail_notification( groupSelect,
+      dataSelect,
+      address,
+      data );
+  } else {
+/*SAFETYMCUSW 5 C MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
+/*SAFETYMCUSW 26 S MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
+/*SAFETYMCUSW 28 D MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
+    for (;; ) {
+    }           /* Wait */
+  }
+}
+
+/**
+ * @brief Memory Initialization Driver (HCG:memoryInit)
+ *
+ * This function is called to perform Memory initialization of selected RAM's.
+ */
+/* SourceId : SELFTEST_SourceId_002 */
+/* DesignId : SELFTEST_DesignId_004 */
+/* Requirements : HL_SR396 */
+void tms570_memory_init( uint32_t ram )
+{
+  /* Enable Memory Hardware Initialization */
+  TMS570_SYS1.MINITGCR = 0xAU;
+
+  /* Enable Memory Hardware Initialization for selected RAM's */
+  TMS570_SYS1.MSIENA = ram;
+
+  /* Wait until Memory Hardware Initialization complete */
+  /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+  while ( ( TMS570_SYS1.MSTCGSTAT & 0x00000100U ) != 0x00000100U ) {
+  }                                                              /* Wait */
+
+  /* Disable Memory Hardware Initialization */
+  TMS570_SYS1.MINITGCR = 0x5U;
+}
+
+volatile uint32_t *const
+tms570_esm_group_channel_to_sr_table[ 4 ][ 2 ] = {
+  { NULL, NULL },
+  { &TMS570_ESM.SR[ 0 ], &TMS570_ESM.SR4 },
+  { &TMS570_ESM.SR[ 1 ], NULL },
+  { &TMS570_ESM.SR[ 2 ], NULL },
+};
+
+/**
+ * @brief Routine to clear specified error channel signalling bit
+ * @param[in] grp   - ESM error channels group
+ * @param[in] chan  - ESM error channel number inside specified group
+ */
+void tms570_esm_channel_sr_clear(
+  unsigned grp,
+  unsigned chan
+)
+{
+  volatile uint32_t *sr_reg;
+
+  sr_reg = tms570_esm_group_channel_to_sr_table[ grp ][ chan >> 5 ];
+
+  if ( sr_reg != NULL )
+    *sr_reg = 1 << (chan & 0x1f);
+}
+
+/** tms570_esm_channel_sr_get
+ * @brief Routine to test is specified error channel is signalling error
+ * @param[in] grp   - ESM error channels group
+ * @param[in] chan  - ESM error channel number inside specified group
+ */
+int tms570_esm_channel_sr_get(
+  unsigned grp,
+  unsigned chan
+)
+{
+  volatile uint32_t *sr_reg;
+
+  sr_reg = tms570_esm_group_channel_to_sr_table[ grp ][ chan >> 5 ];
+
+  if ( sr_reg != NULL )
+    return *sr_reg & ( 1 << ( chan & 0x1f ) );
+  else
+    return 0;
+}
+
+/**
+ * @brief Enable peripheral RAM parity (HCG:enableParity)
+ *
+ * This function enables RAM parity for all peripherals for which RAM parity check is enabled.
+ * This function is called before memoryInit in the startup
+ *
+ */
+void tms570_enable_parity( void )
+{
+  TMS570_DMA.DMAPCR = 0xAU;                   /* Enable DMA RAM parity */
+  TMS570_VIM.PARCTL = 0xAU;                   /* Enable VIM RAM parity */
+  TMS570_DCAN1.CTL = ((uint32_t)0xAU << 10U) | 1U; /* Enable CAN1 RAM parity */
+  TMS570_DCAN2.CTL = ((uint32_t)0xAU << 10U) | 1U; /* Enable CAN2 RAM parity */
+  TMS570_DCAN3.CTL = ((uint32_t)0xAU << 10U) | 1U; /* Enable CAN3 RAM parity */
+  TMS570_ADC1.PARCR = 0xAU;                   /* Enable ADC1 RAM parity */
+  TMS570_ADC2.PARCR = 0xAU;                   /* Enable ADC2 RAM parity */
+  TMS570_NHET1.PCR  = 0xAU;                   /* Enable HET1 RAM parity */
+  TMS570_HTU1.PCR   = 0xAU;                   /* Enable HTU1 RAM parity */
+  TMS570_NHET2.PCR  = 0xAU;                   /* Enable HET2 RAM parity */
+  TMS570_HTU2.PCR   = 0xAU;                   /* Enable HTU2 RAM parity */
+}
+
+/**
+ * @brief Disable peripheral RAM parity (HCG:disableParity)
+ *
+ * This function disables RAM parity for all peripherals for which RAM parity check is enabled.
+ * This function is called after memoryInit in the startup
+ *
+ */
+void tms570_disable_parity( void )
+{
+  TMS570_DMA.DMAPCR = 0x5U;                   /* Disable DMA RAM parity */
+  TMS570_VIM.PARCTL = 0x5U;                   /* Disable VIM RAM parity */
+  TMS570_DCAN1.CTL = ((uint32_t)0x5U << 10U) | 1U; /* Disable CAN1 RAM parity */
+  TMS570_DCAN2.CTL = ((uint32_t)0x5U << 10U) | 1U; /* Disable CAN2 RAM parity */
+  TMS570_DCAN3.CTL = ((uint32_t)0x5U << 10U) | 1U; /* Disable CAN3 RAM parity */
+  TMS570_ADC1.PARCR = 0x5U;                   /* Disable ADC1 RAM parity */
+  TMS570_ADC2.PARCR = 0x5U;                   /* Disable ADC2 RAM parity */
+  TMS570_NHET1.PCR  = 0x5U;                   /* Disable HET1 RAM parity */
+  TMS570_HTU1.PCR   = 0x5U;                   /* Disable HTU1 RAM parity */
+  TMS570_NHET2.PCR  = 0x5U;                   /* Disable HET2 RAM parity */
+  TMS570_HTU2.PCR   = 0x5U;                   /* Disable HTU2 RAM parity */
+}

c/src/lib/libbsp/arm/tms570/hwinit/tms570_selftest.h

@@ -0,0 +1,214 @@
+/**
+ * @file tms570_selftest.h
+ *
+ * @ingroup tms570
+ *
+ * @brief Definition of TMS570 selftest error codes, addresses and functions.
+ */
+/*
+ * Copyright (c) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ *
+ * Algorithms are based on Ti manuals and Ti HalCoGen generated
+ * code available under following copyright.
+ */
+/*
+ * Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef LIBBSP_ARM_TMS570_SELFTEST_H
+#define LIBBSP_ARM_TMS570_SELFTEST_H
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#define CCMSELFCHECK_FAIL1           1U
+#define CCMSELFCHECK_FAIL2           2U
+#define CCMSELFCHECK_FAIL3           3U
+#define CCMSELFCHECK_FAIL4           4U
+#define PBISTSELFCHECK_FAIL1         5U
+#define EFCCHECK_FAIL1               6U
+#define EFCCHECK_FAIL2               7U
+#define FMCECCCHECK_FAIL1            8U
+#define CHECKB0RAMECC_FAIL1          9U
+#define CHECKB1RAMECC_FAIL1         10U
+#define CHECKFLASHECC_FAIL1         11U
+#define VIMPARITYCHECK_FAIL1        12U
+#define DMAPARITYCHECK_FAIL1        13U
+#define HET1PARITYCHECK_FAIL1       14U
+#define HTU1PARITYCHECK_FAIL1       15U
+#define HET2PARITYCHECK_FAIL1       16U
+#define HTU2PARITYCHECK_FAIL1       17U
+#define ADC1PARITYCHECK_FAIL1       18U
+#define ADC2PARITYCHECK_FAIL1       19U
+#define CAN1PARITYCHECK_FAIL1       20U
+#define CAN2PARITYCHECK_FAIL1       21U
+#define CAN3PARITYCHECK_FAIL1       22U
+#define MIBSPI1PARITYCHECK_FAIL1    23U
+#define MIBSPI3PARITYCHECK_FAIL1    24U
+#define MIBSPI5PARITYCHECK_FAIL1    25U
+#define CHECKRAMECC_FAIL1           26U
+#define CHECKRAMECC_FAIL2           27U
+#define CHECKCLOCKMONITOR_FAIL1     28U
+#define CHECKFLASHEEPROMECC_FAIL1   29U
+#define CHECKFLASHEEPROMECC_FAIL2   31U
+#define CHECKFLASHEEPROMECC_FAIL3   32U
+#define CHECKFLASHEEPROMECC_FAIL4   33U
+#define CHECKPLL1SLIP_FAIL1         34U
+#define CHECKRAMADDRPARITY_FAIL1    35U
+#define CHECKRAMADDRPARITY_FAIL2    36U
+#define CHECKRAMUERRTEST_FAIL1      37U
+#define CHECKRAMUERRTEST_FAIL2      38U
+#define FMCBUS1PARITYCHECK_FAIL1    39U
+#define FMCBUS1PARITYCHECK_FAIL2    40U
+#define PBISTSELFCHECK_FAIL2         41U
+#define PBISTSELFCHECK_FAIL3         42U
+
+/* PBIST and STC ROM - PBIST RAM GROUPING */
+#define PBIST_ROM_PBIST_RAM_GROUP   1U
+#define STC_ROM_PBIST_RAM_GROUP     2U
+
+#define VIMRAMLOC       (*(volatile uint32_t *)0xFFF82000U)
+#define VIMRAMPARLOC    (*(volatile uint32_t *)0xFFF82400U)
+
+#define NHET1RAMPARLOC  (*(volatile uint32_t *)0xFF462000U)
+#define NHET2RAMPARLOC  (*(volatile uint32_t *)0xFF442000U)
+#define adcPARRAM1      (*(volatile uint32_t *)(0xFF3E0000U + 0x1000U))
+#define adcPARRAM2      (*(volatile uint32_t *)(0xFF3A0000U + 0x1000U))
+#define canPARRAM1      (*(volatile uint32_t *)(0xFF1E0000U + 0x10U))
+#define canPARRAM2      (*(volatile uint32_t *)(0xFF1C0000U + 0x10U))
+#define canPARRAM3      (*(volatile uint32_t *)(0xFF1A0000U + 0x10U))
+#define HTU1PARLOC      (*(volatile uint32_t *)0xFF4E0200U)
+#define HTU2PARLOC      (*(volatile uint32_t *)0xFF4C0200U)
+
+#define NHET1RAMLOC     (*(volatile uint32_t *)0xFF460000U)
+#define NHET2RAMLOC     (*(volatile uint32_t *)0xFF440000U)
+#define HTU1RAMLOC      (*(volatile uint32_t *)0xFF4E0000U)
+#define HTU2RAMLOC      (*(volatile uint32_t *)0xFF4C0000U)
+
+#define adcRAM1 (*(volatile uint32_t *)0xFF3E0000U)
+#define adcRAM2 (*(volatile uint32_t *)0xFF3A0000U)
+#define canRAM1 (*(volatile uint32_t *)0xFF1E0000U)
+#define canRAM2 (*(volatile uint32_t *)0xFF1C0000U)
+#define canRAM3 (*(volatile uint32_t *)0xFF1A0000U)
+
+#define DMARAMPARLOC    (*(volatile uint32_t *)(0xFFF80A00U))
+#define DMARAMLOC       (*(volatile uint32_t *)(0xFFF80000U))
+
+#define MIBSPI1RAMLOC   (*(volatile uint32_t *)(0xFF0E0000U))
+#define MIBSPI3RAMLOC   (*(volatile uint32_t *)(0xFF0C0000U))
+#define MIBSPI5RAMLOC   (*(volatile uint32_t *)(0xFF0A0000U))
+
+#define mibspiPARRAM1 (*(volatile uint32_t *)(0xFF0E0000U + 0x00000400U))
+#define mibspiPARRAM3 (*(volatile uint32_t *)(0xFF0C0000U + 0x00000400U))
+#define mibspiPARRAM5 (*(volatile uint32_t *)(0xFF0A0000U + 0x00000400U))
+
+/** @enum pbistPort
+ *   @brief Alias names for pbist Port number
+ *
+ *   This enumeration is used to provide alias names for the pbist Port number
+ *     - PBIST_PORT0
+ *     - PBIST_PORT1
+ *
+ *   @Note Check the datasheet for the port avaiability
+ */
+enum pbistPort {
+  PBIST_PORT0 = 0U,   /**< Alias for PBIST Port 0 */
+  PBIST_PORT1 = 1U    /**< Alias for PBIST Port 1 < Check datasheet for Port 1 availability > */
+};
+
+enum {
+  PBIST_TripleReadSlow     = 0x00000001U,  /**<TRIPLE_READ_SLOW_READ  for PBIST and STC ROM*/
+  PBIST_TripleReadFast     = 0x00000002U,  /**<TRIPLE_READ_SLOW_READ  for PBIST and STC ROM*/
+  PBIST_March13N_DP        = 0x00000004U,  /**< March13 N Algo for 2 Port mem */
+};
+
+uint32_t tms570_efc_check( void );
+
+bool tms570_efc_check_self_test( void );
+
+void bsp_selftest_fail_notification( uint32_t flag );
+
+void tms570_memory_port0_fail_notification(
+  uint32_t groupSelect,
+  uint32_t dataSelect,
+  uint32_t address,
+  uint32_t data
+);
+
+void tms570_esm_channel_sr_clear(
+  unsigned grp,
+  unsigned chan
+);
+
+int tms570_esm_channel_sr_get(
+  unsigned grp,
+  unsigned chan
+);
+
+void tms570_pbist_self_check( void );
+
+void tms570_pbist_run(
+  uint32_t raminfoL,
+  uint32_t algomask
+);
+
+bool tms570_pbist_is_test_completed( void );
+
+bool tms570_pbist_is_test_passed( void );
+
+void tms570_pbist_fail( void );
+
+void tms570_pbist_stop( void );
+
+void tms570_enable_parity( void );
+
+void tms570_disable_parity( void );
+
+bool tms570_efc_stuck_zero( void );
+
+void tms570_efc_self_test( void );
+
+bool tms570_pbist_port_test_status( uint32_t port );
+
+void tms570_check_tcram_ecc( void );
+
+#endif /*LIBBSP_ARM_TMS570_SELFTEST_H*/

c/src/lib/libbsp/arm/tms570/hwinit/tms570_selftest_par_can.c

@@ -0,0 +1,93 @@
+/**
+ * @file tms570_selftest_par_can.c
+ *
+ * @ingroup tms570
+ *
+ * @brief Test CAN module parity based protection logic to work.
+ */
+/*
+ * Copyright (c) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ *
+ * Algorithms are based on Ti manuals and Ti HalCoGen generated
+ * code.
+ */
+
+#include <stdint.h>
+#include <stddef.h>
+#include <bsp/tms570.h>
+#include "tms570_selftest.h"
+#include "tms570_selftest_parity.h"
+
+/**
+ * @brief run test to check that parity protection works for CAN modules RAM
+ *
+ * @param[in] desc module registers addresses end ESM channels descriptor
+ *
+ * @return Void, in the case of error invokes bsp_selftest_fail_notification()
+ *
+ * The descriptor provides address of the module registers and address
+ * of internal RAM memory and corresponding parity area test access window.
+ */
+void tms570_selftest_par_check_can( const tms570_selftest_par_desc_t *desc )
+{
+  volatile uint32_t       test_read_data;
+  volatile tms570_dcan_t *can_regs = (volatile tms570_dcan_t *) desc->fnc_data;
+  uint32_t                canctl_bak = can_regs->CTL;
+  uint32_t                canctl_pmd;
+  int                     perr;
+
+  /* Set TEST mode and enable parity checking */
+  /* Disable parity, init mode, TEST mode */
+  canctl_pmd = TMS570_DCAN_CTL_PMD_SET( 0, 0x5 );
+  can_regs->CTL = canctl_pmd | TMS570_DCAN_CTL_Test | TMS570_DCAN_CTL_Init;
+
+  /* Enable RAM Direct Access mode */
+  can_regs->TEST = TMS570_DCAN_TEST_RDA;
+
+  /* flip parity bit */
+  *desc->par_loc ^= desc->par_xor;
+
+  /* Disable TEST mode */
+  canctl_pmd = TMS570_DCAN_CTL_PMD_SET( 0, 0xA );
+  can_regs->CTL = canctl_pmd | TMS570_DCAN_CTL_Test;
+
+  /* read to cause parity error */
+  test_read_data = *desc->ram_loc;
+  (void) test_read_data;
+
+  /* check if ESM channel is flagged */
+  perr = tms570_esm_channel_sr_get( desc->esm_prim_grp, desc->esm_prim_chan );
+
+  if ( !perr ) {
+    /* RAM parity error was not flagged to ESM. */
+    bsp_selftest_fail_notification( desc->fail_code );
+  } else {
+    /* clear ESM flag */
+    tms570_esm_channel_sr_clear( desc->esm_prim_grp, desc->esm_prim_chan );
+
+    /* Set TEST mode and enable parity checking */
+    canctl_pmd = TMS570_DCAN_CTL_PMD_SET( 0, 0x5 );
+    can_regs->CTL = canctl_pmd | TMS570_DCAN_CTL_Test | TMS570_DCAN_CTL_Init;
+
+    /* Revert back to correct data by flipping parity location */
+    *desc->par_loc ^= desc->par_xor;
+  }
+
+  /* Disable RAM Direct Access mode */
+  can_regs->TEST = 0x00000000U;
+
+  /* Restore CTL register */
+  can_regs->CTL = canctl_bak;
+
+  /* Read Error and Status register to clear Parity Error bit */
+  test_read_data = can_regs->ES;
+}

c/src/lib/libbsp/arm/tms570/hwinit/tms570_selftest_par_mibspi.c

@@ -0,0 +1,105 @@
+/**
+ * @file tms570_selftest_par_can.c
+ *
+ * @ingroup tms570
+ *
+ * @brief Test MibSPI module parity based protection logic to work.
+ */
+/*
+ * Copyright (c) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ *
+ * Algorithms are based on Ti manuals and Ti HalCoGen generated
+ * code.
+ */
+
+#include <stdint.h>
+#include <stddef.h>
+#include <bsp/tms570.h>
+#include "tms570_selftest.h"
+#include "tms570_selftest_parity.h"
+
+/**
+ * @brief run test to check that parity protection works for MibSPI modules RAM
+ *
+ * @param[in] desc module registers addresses end ESM channels descriptor
+ *
+ * @return Void, in the case of error invokes bsp_selftest_fail_notification()
+ *
+ * The descriptor provides address of the module registers and address
+ * of internal RAM memory and corresponding parity area test access window.
+ */
+void tms570_selftest_par_check_mibspi( const tms570_selftest_par_desc_t *desc )
+{
+  volatile uint32_t      test_read_data;
+  volatile tms570_spi_t *spi_regs = (volatile tms570_spi_t *) desc->fnc_data;
+  uint32_t               mibspie_bak;
+  uint32_t               uerrctl_bak;
+  int                    perr;
+  int                    wait_timeout = 10000;
+
+  /* wait for MibSPI RAM to complete initialization */
+  while ( ( spi_regs->FLG & TMS570_SPI_FLG_BUFINITACTIVE ) ==
+          TMS570_SPI_FLG_BUFINITACTIVE ) {
+    if ( !wait_timeout-- ) {
+      bsp_selftest_fail_notification( desc->fail_code );
+    }
+  }
+
+  /* Store previous configuration of MibSPI */
+  mibspie_bak = spi_regs->MIBSPIE;
+  uerrctl_bak = spi_regs->UERRCTRL;
+
+  /* enable multi-buffered mode */
+  spi_regs->MIBSPIE = TMS570_SPI_MIBSPIE_MSPIENA;
+
+  /* enable parity error detection */
+  spi_regs->UERRCTRL = TMS570_SPI_UERRCTRL_EDEN_SET( spi_regs->UERRCTRL,
+                                                    TMS570_SELFTEST_PAR_CR_KEY );
+
+  /* enable parity test mode */
+  spi_regs->UERRCTRL |= TMS570_SPI_UERRCTRL_PTESTEN;
+
+  /* flip parity bit */
+  *desc->par_loc ^= desc->par_xor;
+
+  /* disable parity TEST mode */
+  spi_regs->UERRCTRL &= ~TMS570_SPI_UERRCTRL_PTESTEN;
+
+  /* read to cause parity error */
+  test_read_data = *desc->ram_loc;
+  (void) test_read_data;
+
+  /* check if ESM channel is flagged */
+  perr = tms570_esm_channel_sr_get( desc->esm_prim_grp, desc->esm_prim_chan );
+
+  if ( !perr ) {
+    /* RAM parity error was not flagged to ESM. */
+    bsp_selftest_fail_notification( desc->fail_code );
+  } else {
+    /* clear parity error flags */
+    spi_regs->UERRSTAT = TMS570_SPI_UERRSTAT_EDFLG1 |
+                         TMS570_SPI_UERRSTAT_EDFLG0;
+
+    /* clear ESM flag */
+    tms570_esm_channel_sr_clear( desc->esm_prim_grp, desc->esm_prim_chan );
+
+    /* enable parity test mode */
+    spi_regs->UERRCTRL |= TMS570_SPI_UERRCTRL_PTESTEN;
+
+    /* Revert back to correct data by flipping parity location */
+    *desc->par_loc ^= desc->par_xor;
+  }
+
+  /* Restore MIBSPI control registers */
+  spi_regs->UERRCTRL = uerrctl_bak;
+  spi_regs->MIBSPIE = mibspie_bak;
+}

c/src/lib/libbsp/arm/tms570/hwinit/tms570_selftest_par_std.c

@@ -0,0 +1,90 @@
+/**
+ * @file tms570_selftest_par_std.c
+ *
+ * @ingroup tms570
+ *
+ * @brief Generic parity based protection logic check applicable to HETx, HTUx, ADC, DMA and VIM.
+ */
+/*
+ * Copyright (c) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ *
+ * Algorithms are based on Ti manuals and Ti HalCoGen generated
+ * code.
+ */
+
+#include <stdint.h>
+#include <stddef.h>
+#include <bsp/tms570.h>
+#include "tms570_selftest.h"
+#include "tms570_selftest_parity.h"
+
+/**
+ * @brief run test to check that parity protection works for modules with common setup structure.
+ *
+ * @param[in] desc module registers addresses end ESM channels descriptor
+ *
+ * @return Void, in the case of error invokes bsp_selftest_fail_notification()
+ *
+ * The descriptor provides address of the module registers and address
+ * of internal RAM memory and corresponding parity area test access window.
+ * This test function is usable for HETx, HTUx, ADC, DMA and VIM TMS570
+ * peripherals.
+ */
+void tms570_selftest_par_check_std( const tms570_selftest_par_desc_t *desc )
+{
+  volatile uint32_t test_read_data;
+  uint32_t          par_cr_bak = *desc->par_cr_reg;
+  int               perr;
+
+  /* Set TEST mode and enable parity checking */
+  *desc->par_cr_reg = desc->par_cr_test | TMS570_SELFTEST_PAR_CR_KEY;
+
+  /* flip parity bit */
+  *desc->par_loc ^= desc->par_xor;
+
+  /* Disable TEST mode */
+  *desc->par_cr_reg = TMS570_SELFTEST_PAR_CR_KEY;
+
+  /* read to cause parity error */
+  test_read_data = *desc->ram_loc;
+  (void) test_read_data;
+
+  /* check if ESM channel is flagged */
+  perr = tms570_esm_channel_sr_get( desc->esm_prim_grp, desc->esm_prim_chan );
+
+  if ( desc->esm_sec_grp )
+    perr |= tms570_esm_channel_sr_get( desc->esm_sec_grp, desc->esm_sec_chan );
+
+  if ( !perr ) {
+    /* RAM parity error was not flagged to ESM. */
+    bsp_selftest_fail_notification( desc->fail_code );
+  } else {
+    /* If periperal has it own parity status register, clear it */
+    if ( desc->par_st_reg != NULL )
+      *desc->par_st_reg = desc->par_st_clear;
+
+    /* clear ESM flag */
+    tms570_esm_channel_sr_clear( desc->esm_prim_grp, desc->esm_prim_chan );
+
+    if ( desc->esm_sec_grp )
+      tms570_esm_channel_sr_clear( desc->esm_sec_grp, desc->esm_sec_chan );
+
+    /* Set TEST mode and enable parity checking */
+    *desc->par_cr_reg = desc->par_cr_test | TMS570_SELFTEST_PAR_CR_KEY;
+
+    /* Revert back to correct data by flipping parity location */
+    *desc->par_loc ^= desc->par_xor;
+  }
+
+  /* Restore Parity comtrol register */
+  *desc->par_cr_reg = par_cr_bak;
+}

c/src/lib/libbsp/arm/tms570/hwinit/tms570_selftest_parity.c

@@ -0,0 +1,316 @@
+/**
+ * @file tms570_selftest_parity.c
+ *
+ * @ingroup tms570
+ *
+ * @brief Check of module parity based protection logic to work.
+ */
+/*
+ * Copyright (c) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include <stdint.h>
+#include <stddef.h>
+#include <bsp/tms570.h>
+#include <rtems.h>
+#include "tms570_selftest.h"
+#include "tms570_selftest_parity.h"
+
+/* HCG:het1ParityCheck */
+const tms570_selftest_par_desc_t
+  tms570_selftest_par_het1_desc = {
+  .esm_prim_grp  = 1,
+  .esm_prim_chan = 7,
+  .esm_sec_grp   = 0,
+  .esm_sec_chan  = 0,
+  .fail_code     = HET1PARITYCHECK_FAIL1,
+  .ram_loc       = &NHET1RAMLOC,
+  .par_loc       = &NHET1RAMPARLOC,
+  .par_xor       = 0x00000001,
+  .par_cr_reg    = &TMS570_NHET1.PCR,
+  .par_cr_test   = TMS570_NHET_PCR_TEST,
+  .par_st_reg    = NULL,
+  .par_st_clear  = 0,
+  .partest_fnc   = tms570_selftest_par_check_std,
+  .fnc_data      = NULL
+};
+
+/* HCG:htu1ParityCheck */
+const tms570_selftest_par_desc_t
+  tms570_selftest_par_htu1_desc = {
+  .esm_prim_grp  = 1,
+  .esm_prim_chan = 8,
+  .esm_sec_grp   = 0,
+  .esm_sec_chan  = 0,
+  .fail_code     = HTU1PARITYCHECK_FAIL1,
+  .ram_loc       = &HTU1RAMLOC,
+  .par_loc       = &HTU1PARLOC,
+  .par_xor       = 0x00000001,
+  .par_cr_reg    = &TMS570_HTU1.PCR,
+  .par_cr_test   = TMS570_HTU_PCR_TEST,
+  .par_st_reg    = &TMS570_HTU1.PAR,
+  .par_st_clear  = TMS570_HTU_PAR_PEFT,
+  .partest_fnc   = tms570_selftest_par_check_std,
+  .fnc_data      = NULL
+};
+
+/* HCG:het2ParityCheck */
+const tms570_selftest_par_desc_t
+  tms570_selftest_par_het2_desc = {
+  .esm_prim_grp  = 1,
+  .esm_prim_chan = 7,
+  .esm_sec_grp   = 1,
+  .esm_sec_chan  = 34,
+  .fail_code     = HET2PARITYCHECK_FAIL1,
+  .ram_loc       = &NHET2RAMLOC,
+  .par_loc       = &NHET2RAMPARLOC,
+  .par_xor       = 0x00000001,
+  .par_cr_reg    = &TMS570_NHET2.PCR,
+  .par_cr_test   = TMS570_NHET_PCR_TEST,
+  .par_st_reg    = NULL,
+  .par_st_clear  = 0,
+  .partest_fnc   = tms570_selftest_par_check_std,
+  .fnc_data      = NULL
+};
+
+/* HCG:htu2ParityCheck */
+const tms570_selftest_par_desc_t
+  tms570_selftest_par_htu2_desc = {
+  .esm_prim_grp  = 1,
+  .esm_prim_chan = 8,
+  .esm_sec_grp   = 0,
+  .esm_sec_chan  = 0,
+  .fail_code     = HTU2PARITYCHECK_FAIL1,
+  .ram_loc       = &HTU2RAMLOC,
+  .par_loc       = &HTU2PARLOC,
+  .par_xor       = 0x00000001,
+  .par_cr_reg    = &TMS570_HTU2.PCR,
+  .par_cr_test   = TMS570_HTU_PCR_TEST,
+  .par_st_reg    = &TMS570_HTU2.PAR,
+  .par_st_clear  = TMS570_HTU_PAR_PEFT,
+  .partest_fnc   = tms570_selftest_par_check_std,
+  .fnc_data      = NULL
+};
+
+/* HCG:adc1ParityCheck */
+const tms570_selftest_par_desc_t
+  tms570_selftest_par_adc1_desc = {
+  .esm_prim_grp  = 1,
+  .esm_prim_chan = 19,
+  .esm_sec_grp   = 0,
+  .esm_sec_chan  = 0,
+  .fail_code     = ADC1PARITYCHECK_FAIL1,
+  .ram_loc       = &adcRAM1,
+  .par_loc       = &adcPARRAM1,
+  .par_xor       = 0xffffffff,
+  .par_cr_reg    = &TMS570_ADC1.PARCR,
+  .par_cr_test   = TMS570_ADC_PARCR_TEST,
+  .par_st_reg    = NULL,
+  .par_st_clear  = 0,
+  .partest_fnc   = tms570_selftest_par_check_std,
+  .fnc_data      = NULL
+};
+
+/* HCG:adc2ParityCheck */
+const tms570_selftest_par_desc_t
+  tms570_selftest_par_adc2_desc = {
+  .esm_prim_grp  = 1,
+  .esm_prim_chan = 1,
+  .esm_sec_grp   = 0,
+  .esm_sec_chan  = 0,
+  .fail_code     = ADC2PARITYCHECK_FAIL1,
+  .ram_loc       = &adcRAM2,
+  .par_loc       = &adcPARRAM2,
+  .par_xor       = 0xffffffff,
+  .par_cr_reg    = &TMS570_ADC2.PARCR,
+  .par_cr_test   = TMS570_ADC_PARCR_TEST,
+  .par_st_reg    = NULL,
+  .par_st_clear  = 0,
+  .partest_fnc   = tms570_selftest_par_check_std,
+  .fnc_data      = NULL
+};
+
+/* HCG:can1ParityCheck */
+const tms570_selftest_par_desc_t
+  tms570_selftest_par_can1_desc = {
+  .esm_prim_grp  = 1,
+  .esm_prim_chan = 21,
+  .esm_sec_grp   = 0,
+  .esm_sec_chan  = 0,
+  .fail_code     = CAN1PARITYCHECK_FAIL1,
+  .ram_loc       = &canRAM1,
+  .par_loc       = &canPARRAM1,
+  .par_xor       = 0x00001000,
+  .par_cr_reg    = NULL,
+  .par_cr_test   = 0,
+  .par_st_reg    = NULL,
+  .par_st_clear  = 0,
+  .partest_fnc   = tms570_selftest_par_check_can,
+  .fnc_data      = &TMS570_DCAN1
+};
+
+/* HCG:can2ParityCheck */
+const tms570_selftest_par_desc_t
+  tms570_selftest_par_can2_desc = {
+  .esm_prim_grp  = 1,
+  .esm_prim_chan = 23,
+  .esm_sec_grp   = 0,
+  .esm_sec_chan  = 0,
+  .fail_code     = CAN2PARITYCHECK_FAIL1,
+  .ram_loc       = &canRAM2,
+  .par_loc       = &canPARRAM2,
+  .par_xor       = 0x00001000,
+  .par_cr_reg    = NULL,
+  .par_cr_test   = 0,
+  .par_st_reg    = NULL,
+  .par_st_clear  = 0,
+  .partest_fnc   = tms570_selftest_par_check_can,
+  .fnc_data      = &TMS570_DCAN2
+};
+
+/* HCG:can3ParityCheck */
+const tms570_selftest_par_desc_t
+  tms570_selftest_par_can3_desc = {
+  .esm_prim_grp  = 1,
+  .esm_prim_chan = 22,
+  .esm_sec_grp   = 0,
+  .esm_sec_chan  = 0,
+  .fail_code     = CAN3PARITYCHECK_FAIL1,
+  .ram_loc       = &canRAM3,
+  .par_loc       = &canPARRAM3,
+  .par_xor       = 0x00001000,
+  .par_cr_reg    = NULL,
+  .par_cr_test   = 0,
+  .par_st_reg    = NULL,
+  .par_st_clear  = 0,
+  .partest_fnc   = tms570_selftest_par_check_can,
+  .fnc_data      = &TMS570_DCAN3
+};
+
+/* HCG:vimParityCheck */
+const tms570_selftest_par_desc_t
+  tms570_selftest_par_vim_desc = {
+  .esm_prim_grp  = 1,
+  .esm_prim_chan = 15,
+  .esm_sec_grp   = 0,
+  .esm_sec_chan  = 0,
+  .fail_code     = VIMPARITYCHECK_FAIL1,
+  .ram_loc       = &VIMRAMLOC,
+  .par_loc       = &VIMRAMPARLOC,
+  .par_xor       = 0x00000001,
+  .par_cr_reg    = &TMS570_VIM.PARCTL,
+  .par_cr_test   = TMS570_VIM_PARCTL_TEST,
+  .par_st_reg    = &TMS570_VIM.PARFLG,
+  .par_st_clear  = TMS570_VIM_PARFLG_PARFLG,
+  .partest_fnc   = tms570_selftest_par_check_std,
+  .fnc_data      = NULL
+};
+
+/* HCG:dmaParityCheck */
+const tms570_selftest_par_desc_t
+  tms570_selftest_par_dma_desc = {
+  .esm_prim_grp  = 1,
+  .esm_prim_chan = 3,
+  .esm_sec_grp   = 0,
+  .esm_sec_chan  = 0,
+  .fail_code     = DMAPARITYCHECK_FAIL1,
+  .ram_loc       = &DMARAMLOC,
+  .par_loc       = &DMARAMPARLOC,
+  .par_xor       = 0x00000001,
+  .par_cr_reg    = &TMS570_DMA.DMAPCR,
+  .par_cr_test   = TMS570_DMA_DMAPCR_TEST,
+  .par_st_reg    = &TMS570_DMA.DMAPAR,
+  .par_st_clear  = TMS570_DMA_DMAPAR_EDFLAG,
+  .partest_fnc   = tms570_selftest_par_check_std,
+  .fnc_data      = NULL
+};
+
+/* HCG:mibspi1ParityCheck */
+const tms570_selftest_par_desc_t
+  tms570_selftest_par_spi1_desc = {
+  .esm_prim_grp  = 1,
+  .esm_prim_chan = 17,
+  .esm_sec_grp   = 0,
+  .esm_sec_chan  = 0,
+  .fail_code     = MIBSPI1PARITYCHECK_FAIL1,
+  .ram_loc       = &MIBSPI1RAMLOC,
+  .par_loc       = &mibspiPARRAM1,
+  .par_xor       = 0x00000001,
+  .par_cr_reg    = NULL,
+  .par_cr_test   = 0,
+  .par_st_reg    = NULL,
+  .par_st_clear  = 0,
+  .partest_fnc   = tms570_selftest_par_check_mibspi,
+  .fnc_data      = &TMS570_SPI1
+};
+
+/* HCG:mibspi3ParityCheck */
+const tms570_selftest_par_desc_t
+  tms570_selftest_par_spi3_desc = {
+  .esm_prim_grp  = 1,
+  .esm_prim_chan = 18,
+  .esm_sec_grp   = 0,
+  .esm_sec_chan  = 0,
+  .fail_code     = MIBSPI3PARITYCHECK_FAIL1,
+  .ram_loc       = &MIBSPI3RAMLOC,
+  .par_loc       = &mibspiPARRAM3,
+  .par_xor       = 0x00000001,
+  .par_cr_reg    = NULL,
+  .par_cr_test   = 0,
+  .par_st_reg    = NULL,
+  .par_st_clear  = 0,
+  .partest_fnc   = tms570_selftest_par_check_mibspi,
+  .fnc_data      = &TMS570_SPI3
+};
+
+/* HCG:mibspi5ParityCheck */
+const tms570_selftest_par_desc_t
+  tms570_selftest_par_spi5_desc = {
+  .esm_prim_grp  = 1,
+  .esm_prim_chan = 24,
+  .esm_sec_grp   = 0,
+  .esm_sec_chan  = 0,
+  .fail_code     = MIBSPI5PARITYCHECK_FAIL1,
+  .ram_loc       = &MIBSPI5RAMLOC,
+  .par_loc       = &mibspiPARRAM5,
+  .par_xor       = 0x00000001,
+  .par_cr_reg    = NULL,
+  .par_cr_test   = 0,
+  .par_st_reg    = NULL,
+  .par_st_clear  = 0,
+  .partest_fnc   = tms570_selftest_par_check_mibspi,
+  .fnc_data      = &TMS570_SPI5
+};
+
+/**
+ * @brief run parity protection mechanism check for set of modules described by list.
+ *
+ * @param[in] desc_arr array of pointers to descriptors providing addresses
+ *                     and ESM channels for individual peripherals.
+ * @param[in] desc_cnt count of pointers in the array
+ *
+ * @return Void, in the case of error invokes bsp_selftest_fail_notification()
+ */
+void tms570_selftest_par_run(
+  const tms570_selftest_par_desc_t *
+  const *desc_arr,
+  int    desc_cnt
+)
+{
+  int                              i;
+  const tms570_selftest_par_desc_t *desc;
+
+  for ( i = 0; i < desc_cnt; i++ ) {
+    desc = desc_arr[ i ];
+    desc->partest_fnc( desc );
+  }
+}

c/src/lib/libbsp/arm/tms570/hwinit/tms570_selftest_parity.h

@@ -0,0 +1,110 @@
+/**
+ * @file tms570_selftest_parity.h
+ *
+ * @ingroup tms570
+ *
+ * @brief Check of module parity based protection logic to work.
+ */
+/*
+ * Copyright (c) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_TMS570_SELFTEST_PARITY_H
+#define LIBBSP_ARM_TMS570_SELFTEST_PARITY_H
+
+#include <stdint.h>
+
+/**
+ * The magic number used to switch most of the peripherals
+ * into parity protection test mode
+ */
+#define TMS570_SELFTEST_PAR_CR_KEY 0xA
+
+typedef struct tms570_selftest_par_desc tms570_selftest_par_desc_t;
+
+typedef void tms570_selftest_par_fnc_t( const tms570_selftest_par_desc_t *desc );
+
+/**
+ * Decriptor specifying registers addresses and values used to test
+ * that parity protection is working for given hardware
+ * module/peripheral. It is used during initial chip self-tests.
+ */
+struct tms570_selftest_par_desc {
+  unsigned char esm_prim_grp;    /**< ESM primary signalling group number. */
+  unsigned char esm_prim_chan;   /**< ESM primary signalling channel number. */
+  unsigned char esm_sec_grp;     /**< ESM optional/alternative signalling group. */
+  unsigned char esm_sec_chan;    /**< ESM optional/alternative signalling channel. */
+  int fail_code;                 /**< Error code reported to
+                  bsp_selftest_fail_notification() in the case of the test failure. */
+  volatile uint32_t *ram_loc;    /**< Address of memory protected by parity. */
+  volatile uint32_t *par_loc;    /**< Address of mapping of parity bits into CPU
+                                  * address space. */
+  uint32_t par_xor;              /**< Bitmask used to alter parity to cause
+                                  * intentional parity failure. */
+  volatile uint32_t *par_cr_reg; /**< Address of module parity test control register. */
+  uint32_t par_cr_test;          /**< Mask of bit which cause switch to a test mode. */
+  volatile uint32_t *par_st_reg; /**< Optional module parity status register which. */
+  uint32_t par_st_clear;         /**< Optional value which is written to status register
+                                  * to clear error. */
+  tms570_selftest_par_fnc_t *partest_fnc; /**< Function which specialized for given kind
+                                  * of peripheral/module mechanism testing. */
+  volatile void *fnc_data;       /**< Pointer to the base of tested peripheral registers.
+                                  * It is required by some test functions (CAN and MibSPI) */
+};
+
+extern const tms570_selftest_par_desc_t
+  tms570_selftest_par_het1_desc;
+extern const tms570_selftest_par_desc_t
+  tms570_selftest_par_htu1_desc;
+extern const tms570_selftest_par_desc_t
+  tms570_selftest_par_het2_desc;
+extern const tms570_selftest_par_desc_t
+  tms570_selftest_par_htu2_desc;
+extern const tms570_selftest_par_desc_t
+  tms570_selftest_par_adc1_desc;
+extern const tms570_selftest_par_desc_t
+  tms570_selftest_par_adc2_desc;
+extern const tms570_selftest_par_desc_t
+  tms570_selftest_par_can1_desc;
+extern const tms570_selftest_par_desc_t
+  tms570_selftest_par_can2_desc;
+extern const tms570_selftest_par_desc_t
+  tms570_selftest_par_can3_desc;
+extern const tms570_selftest_par_desc_t
+  tms570_selftest_par_vim_desc;
+const tms570_selftest_par_desc_t
+  tms570_selftest_par_dma_desc;
+const tms570_selftest_par_desc_t
+  tms570_selftest_par_spi1_desc;
+const tms570_selftest_par_desc_t
+  tms570_selftest_par_spi3_desc;
+const tms570_selftest_par_desc_t
+  tms570_selftest_par_spi5_desc;
+
+extern const tms570_selftest_par_desc_t *const
+tms570_selftest_par_list[];
+
+extern const int tms570_selftest_par_list_size;
+
+void tms570_selftest_par_check_std( const tms570_selftest_par_desc_t *desc );
+
+void tms570_selftest_par_check_can( const tms570_selftest_par_desc_t *desc );
+
+void tms570_selftest_par_check_mibspi( const tms570_selftest_par_desc_t *desc );
+
+void tms570_selftest_par_run(
+  const tms570_selftest_par_desc_t *
+  const *desc_arr,
+  int    desc_cnt
+);
+
+#endif /* LIBBSP_ARM_TMS570_SELFTEST_PARITY_H */

c/src/lib/libbsp/arm/tms570/hwinit/tms570_sys_core.S

@@ -0,0 +1,575 @@
+/*--------------------------------------------------------------------------
+ tms570_sys_core.S
+
+ Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com
+
+
+  Redistribution and use in source and binary forms, with or without
+  modification, are permitted provided that the following conditions
+  are met:
+
+    Redistributions of source code must retain the above copyright
+    notice, this list of conditions and the following disclaimer.
+
+    Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions and the following disclaimer in the
+    documentation and/or other materials provided with the
+    distribution.
+
+    Neither the name of Texas Instruments Incorporated nor the names of
+    its contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+-------------------------------------------------------------------------*/
+
+    .section .text
+    .syntax unified
+    .cpu cortex-r4
+    .arm
+
+/*-------------------------------------------------------------------------------*/
+@ Initialize CPU Registers
+@ SourceId : CORE_SourceId_001
+@ DesignId : CORE_DesignId_001
+@ Requirements: HL_SR477, HL_SR476, HL_SR492
+
+    .weak _coreInitRegisters_
+    .type _coreInitRegisters_, %function
+
+_coreInitRegisters_:
+
+    @ After reset, the CPU is in the Supervisor mode (M = 10011)
+        mov r0, lr
+        mov r1, #0x0000
+        mov r2, #0x0000
+        mov r3, #0x0000
+        mov r4, #0x0000
+        mov r5, #0x0000
+        mov r6, #0x0000
+        mov r7, #0x0000
+        mov r8, #0x0000
+        mov r9, #0x0000
+        mov r10, #0x0000
+        mov r11, #0x0000
+        mov r12, #0x0000
+        mov r13, #0x0000
+        mrs r1, cpsr
+        msr spsr_cxsf, r1
+        @ Switch to FIQ mode (M = 10001)
+        cps #17
+        mov lr, r0
+        mov r8, #0x0000
+        mov r9, #0x0000
+        mov r10, #0x0000
+        mov r11, #0x0000
+        mov r12, #0x0000
+        mrs r1, cpsr
+        msr spsr_cxsf, r1
+        @ Switch to IRQ mode (M = 10010)
+        cps #18
+        mov lr, r0
+        mrs r1,cpsr
+        msr spsr_cxsf, r1             @ Switch to Abort mode (M = 10111)
+        cps #23
+        mov lr, r0
+        mrs r1,cpsr
+        msr spsr_cxsf, r1             @ Switch to Undefined Instruction Mode (M = 11011)
+        cps #27
+        mov lr, r0
+        mrs r1,cpsr
+        msr spsr_cxsf, r1             @ Switch to System Mode ( Shares User Mode registers ) (M = 11111)
+        cps #31
+        mov lr, r0
+        mrs r1,cpsr
+        msr spsr_cxsf, r1
+
+        mrc   p15,     #0x00,      r2,       c1, c0, #0x02
+        orr   r2,      r2,         #0xF00000
+        mcr   p15,     #0x00,      r2,       c1, c0, #0x02
+        mov   r2,      #0x40000000
+        fmxr  fpexc,   r2
+
+        fmdrr d0, r1, r1
+        fmdrr d1, r1, r1
+        fmdrr d2, r1, r1
+        fmdrr d3, r1, r1
+        fmdrr d4, r1, r1
+        fmdrr d5, r1, r1
+        fmdrr d6, r1, r1
+        fmdrr d7, r1, r1
+        fmdrr d8, r1, r1
+        fmdrr d9, r1, r1
+        fmdrr d10, r1, r1
+        fmdrr d11, r1, r1
+        fmdrr d12, r1, r1
+        fmdrr d13, r1, r1
+        fmdrr d14, r1, r1
+        fmdrr d15, r1, r1
+
+    bl next1
+next1:
+    bl next2
+next2:
+    bl next3
+next3:
+    bl next4
+next4:
+    bx r0
+
+/*-------------------------------------------------------------------------------*/
+@ Take CPU to IDLE state
+@ SourceId : CORE_SourceId_004
+@ DesignId : CORE_DesignId_004
+@ Requirements: HL_SR493
+
+    .weak _gotoCPUIdle_
+    .type _gotoCPUIdle_, %function
+
+_gotoCPUIdle_:
+
+        WFI
+        nop
+        nop
+        nop
+        nop
+        bx    lr
+
+/*-------------------------------------------------------------------------------*/
+@ Enable VFP Unit
+@ SourceId : CORE_SourceId_005
+@ DesignId : CORE_DesignId_006
+@ Requirements: HL_SR492, HL_SR476
+
+    .weak _coreEnableVfp_
+    .type _coreEnableVfp_, %function
+
+_coreEnableVfp_:
+
+        stmfd sp!, {r0}
+        mrc   p15,     #0x00,      r0,       c1, c0, #0x02
+        orr   r0,      r0,         #0xF00000
+        mcr   p15,     #0x00,      r0,       c1, c0, #0x02
+        mov   r0,      #0x40000000
+        fmxr  fpexc,   r0
+        ldmfd sp!, {r0}
+        bx    lr
+
+/*-------------------------------------------------------------------------------*/
+@ Enable Event Bus Export
+@ SourceId : CORE_SourceId_006
+@ DesignId : CORE_DesignId_007
+@ Requirements: HL_SR479
+
+    .weak _coreEnableEventBusExport_
+    .type _coreEnableEventBusExport_, %function
+
+_coreEnableEventBusExport_:
+
+        stmfd sp!, {r0}
+        mrc   p15, #0x00, r0,         c9, c12, #0x00
+        orr   r0,  r0,    #0x10
+        mcr   p15, #0x00, r0,         c9, c12, #0x00
+        ldmfd sp!, {r0}
+        bx    lr
+
+/*-------------------------------------------------------------------------------*/
+@ Disable Event Bus Export
+@ SourceId : CORE_SourceId_007
+@ DesignId : CORE_DesignId_008
+@ Requirements: HL_SR481
+
+    .weak _coreDisableEventBusExport_
+    .type _coreDisableEventBusExport_, %function
+
+_coreDisableEventBusExport_:
+
+        stmfd sp!, {r0}
+        mrc   p15, #0x00, r0,         c9, c12, #0x00
+        bic   r0,  r0,    #0x10
+        mcr   p15, #0x00, r0,         c9, c12, #0x00
+        ldmfd sp!, {r0}
+        bx    lr
+
+/*-------------------------------------------------------------------------------*/
+@ Enable RAM ECC Support
+@ SourceId : CORE_SourceId_008
+@ DesignId : CORE_DesignId_009
+@ Requirements: HL_SR480
+
+    .weak _coreEnableRamEcc_
+    .type _coreEnableRamEcc_, %function
+
+_coreEnableRamEcc_:
+
+        stmfd sp!, {r0}
+        mrc   p15, #0x00, r0,         c1, c0,  #0x01
+        orr   r0,  r0,    #0x0C000000
+        mcr   p15, #0x00, r0,         c1, c0,  #0x01
+        ldmfd sp!, {r0}
+        bx    lr
+
+/*-------------------------------------------------------------------------------*/
+@ Disable RAM ECC Support
+@ SourceId : CORE_SourceId_009
+@ DesignId : CORE_DesignId_010
+@ Requirements: HL_SR482
+
+    .weak _coreDisableRamEcc_
+    .type _coreDisableRamEcc_, %function
+
+_coreDisableRamEcc_:
+
+        stmfd sp!, {r0}
+        mrc   p15, #0x00, r0,         c1, c0,  #0x01
+        bic   r0,  r0,    #0x0C000000
+        mcr   p15, #0x00, r0,         c1, c0,  #0x01
+        ldmfd sp!, {r0}
+        bx    lr
+
+/*-------------------------------------------------------------------------------*/
+@ Enable Flash ECC Support
+@ SourceId : CORE_SourceId_010
+@ DesignId : CORE_DesignId_011
+@ Requirements: HL_SR480
+
+    .weak _coreEnableFlashEcc_
+    .type _coreEnableFlashEcc_, %function
+
+_coreEnableFlashEcc_:
+
+        stmfd sp!, {r0}
+        mrc   p15, #0x00, r0,         c1, c0,  #0x01
+        orr   r0,  r0,    #0x02000000
+        dmb
+        mcr   p15, #0x00, r0,         c1, c0,  #0x01
+        ldmfd sp!, {r0}
+        bx    lr
+
+/*-------------------------------------------------------------------------------*/
+@ Disable Flash ECC Support
+@ SourceId : CORE_SourceId_011
+@ DesignId : CORE_DesignId_012
+@ Requirements: HL_SR482
+
+    .weak _coreDisableFlashEcc_
+    .type _coreDisableFlashEcc_, %function
+
+_coreDisableFlashEcc_:
+
+        stmfd sp!, {r0}
+        mrc   p15, #0x00, r0,         c1, c0,  #0x01
+        bic   r0,  r0,    #0x02000000
+        mcr   p15, #0x00, r0,         c1, c0,  #0x01
+        ldmfd sp!, {r0}
+        bx    lr
+
+/*-------------------------------------------------------------------------------*/
+@ Enable Offset via Vic controller
+@ SourceId : CORE_SourceId_012
+@ DesignId : CORE_DesignId_005
+@ Requirements: HL_SR483
+
+    .weak _coreEnableIrqVicOffset_
+    .type _coreEnableIrqVicOffset_, %function
+
+_coreEnableIrqVicOffset_:
+
+        stmfd sp!, {r0}
+        mrc   p15, #0, r0,         c1, c0,  #0
+        orr   r0,  r0,    #0x01000000
+        mcr   p15, #0, r0,         c1, c0,  #0
+        ldmfd sp!, {r0}
+        bx    lr
+
+/*-------------------------------------------------------------------------------*/
+@ Get data fault status register
+@ SourceId : CORE_SourceId_013
+@ DesignId : CORE_DesignId_013
+@ Requirements: HL_SR495
+
+    .weak _coreGetDataFault_
+    .type _coreGetDataFault_, %function
+
+_coreGetDataFault_:
+
+        mrc   p15, #0, r0, c5, c0,  #0
+        bx    lr
+
+/*-------------------------------------------------------------------------------*/
+@ Clear data fault status register
+@ SourceId : CORE_SourceId_014
+@ DesignId : CORE_DesignId_014
+@ Requirements: HL_SR495
+
+    .weak _coreClearDataFault_
+    .type _coreClearDataFault_, %function
+
+_coreClearDataFault_:
+
+        stmfd sp!, {r0}
+        mov   r0,  #0
+        mcr   p15, #0, r0, c5, c0,  #0
+        ldmfd sp!, {r0}
+        bx    lr
+
+/*-------------------------------------------------------------------------------*/
+@ Get instruction fault status register
+@ SourceId : CORE_SourceId_015
+@ DesignId : CORE_DesignId_015
+@ Requirements: HL_SR495
+
+    .weak _coreGetInstructionFault_
+    .type _coreGetInstructionFault_, %function
+
+_coreGetInstructionFault_:
+
+        mrc   p15, #0, r0, c5, c0, #1
+        bx    lr
+
+/*-------------------------------------------------------------------------------*/
+@ Clear instruction fault status register
+@ SourceId : CORE_SourceId_016
+@ DesignId : CORE_DesignId_016
+@ Requirements: HL_SR495
+
+    .weak _coreClearInstructionFault_
+    .type _coreClearInstructionFault_, %function
+
+_coreClearInstructionFault_:
+
+        stmfd sp!, {r0}
+        mov   r0,  #0
+        mcr   p15, #0, r0, c5, c0, #1
+        ldmfd sp!, {r0}
+        bx    lr
+
+/*-------------------------------------------------------------------------------*/
+@ Get data fault address register
+@ SourceId : CORE_SourceId_017
+@ DesignId : CORE_DesignId_017
+@ Requirements: HL_SR495
+
+    .weak _coreGetDataFaultAddress_
+    .type _coreGetDataFaultAddress_, %function
+
+_coreGetDataFaultAddress_:
+
+        mrc   p15, #0, r0, c6, c0,  #0
+        bx    lr
+
+/*-------------------------------------------------------------------------------*/
+@ Clear data fault address register
+@ SourceId : CORE_SourceId_018
+@ DesignId : CORE_DesignId_018
+@ Requirements: HL_SR495
+
+    .weak _coreClearDataFaultAddress_
+    .type _coreClearDataFaultAddress_, %function
+
+_coreClearDataFaultAddress_:
+
+        stmfd sp!, {r0}
+        mov   r0,  #0
+        mcr   p15, #0, r0, c6, c0,  #0
+        ldmfd sp!, {r0}
+        bx    lr
+
+/*-------------------------------------------------------------------------------*/
+@ Get instruction fault address register
+@ SourceId : CORE_SourceId_019
+@ DesignId : CORE_DesignId_019
+@ Requirements: HL_SR495
+
+    .weak _coreGetInstructionFaultAddress_
+    .type _coreGetInstructionFaultAddress_, %function
+
+_coreGetInstructionFaultAddress_:
+
+        mrc   p15, #0, r0, c6, c0, #2
+        bx    lr
+
+/*-------------------------------------------------------------------------------*/
+@ Clear instruction fault address register
+@ SourceId : CORE_SourceId_020
+@ DesignId : CORE_DesignId_020
+@ Requirements: HL_SR495
+
+    .weak _coreClearInstructionFaultAddress_
+    .type _coreClearInstructionFaultAddress_, %function
+
+_coreClearInstructionFaultAddress_:
+
+        stmfd sp!, {r0}
+        mov   r0,  #0
+        mcr   p15, #0, r0, c6, c0, #2
+        ldmfd sp!, {r0}
+        bx    lr
+
+/*-------------------------------------------------------------------------------*/
+@ Get auxiliary data fault status register
+@ SourceId : CORE_SourceId_021
+@ DesignId : CORE_DesignId_021
+@ Requirements: HL_SR496
+
+    .weak _coreGetAuxiliaryDataFault_
+    .type _coreGetAuxiliaryDataFault_, %function
+
+_coreGetAuxiliaryDataFault_:
+
+        mrc   p15, #0, r0, c5, c1, #0
+        bx    lr
+
+/*-------------------------------------------------------------------------------*/
+@ Clear auxiliary data fault status register
+@ SourceId : CORE_SourceId_022
+@ DesignId : CORE_DesignId_022
+@ Requirements: HL_SR496
+
+    .weak _coreClearAuxiliaryDataFault_
+    .type _coreClearAuxiliaryDataFault_, %function
+
+_coreClearAuxiliaryDataFault_:
+
+        stmfd sp!, {r0}
+        mov   r0,  #0
+        mcr   p15, #0, r0, c5, c1, #0
+        ldmfd sp!, {r0}
+        bx    lr
+
+/*-------------------------------------------------------------------------------*/
+@ Get auxiliary instruction fault status register
+@ SourceId : CORE_SourceId_023
+@ DesignId : CORE_DesignId_023
+@ Requirements: HL_SR496
+
+    .weak _coreGetAuxiliaryInstructionFault_
+    .type _coreGetAuxiliaryInstructionFault_, %function
+
+_coreGetAuxiliaryInstructionFault_:
+
+        mrc   p15, #0, r0, c5, c1, #1
+        bx    lr
+
+/*-------------------------------------------------------------------------------*/
+@ Clear auxiliary instruction fault status register
+@ SourceId : CORE_SourceId_024
+@ DesignId : CORE_DesignId_024
+@ Requirements: HL_SR496
+
+    .weak _coreClearAuxiliaryInstructionFault_
+    .type _coreClearAuxiliaryInstructionFault_, %function
+
+_coreClearAuxiliaryInstructionFault_:
+
+        stmfd sp!, {r0}
+        mov   r0,  #0
+        mrc   p15, #0, r0, c5, c1, #1
+        ldmfd sp!, {r0}
+        bx    lr
+
+/*-------------------------------------------------------------------------------*/
+@ Clear ESM CCM errorss
+
+    .weak _esmCcmErrorsClear_
+    .type _esmCcmErrorsClear_, %function
+
+_esmCcmErrorsClear_:
+
+        stmfd sp!, {r0-r2}
+        ldr   r0, ESMSR1_REG      @ load the ESMSR1 status register address
+        ldr   r2, ESMSR1_ERR_CLR
+        str   r2, [r0]            @ clear the ESMSR1 register
+
+        ldr   r0, ESMSR2_REG      @ load the ESMSR2 status register address
+        ldr   r2, ESMSR2_ERR_CLR
+        str   r2, [r0]            @ clear the ESMSR2 register
+
+        ldr   r0, ESMSSR2_REG     @ load the ESMSSR2 status register address
+        ldr   r2, ESMSSR2_ERR_CLR
+        str   r2, [r0]            @ clear the ESMSSR2 register
+
+        ldr   r0, ESMKEY_REG      @ load the ESMKEY register address
+        mov   r2, #0x5            @ load R2 with 0x5
+        str   r2, [r0]            @ clear the ESMKEY register
+
+        ldr   r0, VIM_INTREQ      @ load the INTREQ register address
+        ldr   r2, VIM_INT_CLR
+        str   r2, [r0]            @ clear the INTREQ register
+        ldr   r0, CCMR4_STAT_REG  @ load the CCMR4 status register address
+        ldr   r2, CCMR4_ERR_CLR
+        str   r2, [r0]            @ clear the CCMR4 status register
+        ldmfd sp!, {r0-r2}
+        bx    lr
+
+ESMSR1_REG:      .word 0xFFFFF518
+ESMSR2_REG:      .word 0xFFFFF51C
+ESMSR3_REG:      .word 0xFFFFF520
+ESMKEY_REG:      .word 0xFFFFF538
+ESMSSR2_REG:     .word 0xFFFFF53C
+CCMR4_STAT_REG:  .word 0xFFFFF600
+ERR_CLR_WRD:     .word 0xFFFFFFFF
+CCMR4_ERR_CLR:   .word 0x00010000
+ESMSR1_ERR_CLR:  .word 0x80000000
+ESMSR2_ERR_CLR:  .word 0x00000004
+ESMSSR2_ERR_CLR: .word 0x00000004
+VIM_INT_CLR:     .word 0x00000001
+VIM_INTREQ:      .word 0xFFFFFE20
+
+
+#if 1/*-------------------------------------------------------------------------------*/
+@ Work Around for Errata CORTEX-R4#57:
+@
+@ Errata Description:
+@            Conditional VMRS APSR_Nzcv, FPSCR May Evaluate With Incorrect Flags
+@ Workaround:
+@            Disable out-of-order single-precision floating point
+@            multiply-accumulate instruction completion
+
+    .weak _errata_CORTEXR4_57_
+    .type _errata_CORTEXR4_57_, %function
+
+_errata_CORTEXR4_57_:
+
+        push {r0}
+        mrc p15, #0, r0, c15, c0, #0 @ Read Secondary Auxiliary Control Register
+        orr r0, r0, #0x10000         @ Set BIT 16 (Set DOOFMACS)
+        mcr p15, #0, r0, c15, c0, #0 @ Write Secondary Auxiliary Control Register
+        pop {r0}
+        bx lr
+#endif
+
+/*-------------------------------------------------------------------------------*/
+@ Work Around for Errata CORTEX-R4#66:
+@
+@ Errata Description:
+@            Register Corruption During A Load-Multiple Instruction At
+@            an Exception Vector
+@ Workaround:
+@            Disable out-of-order completion for divide instructions in
+@            Auxiliary Control register
+
+    .weak _errata_CORTEXR4_66_
+    .type _errata_CORTEXR4_66_, %function
+
+_errata_CORTEXR4_66_:
+
+        push {r0}
+        mrc p15, #0, r0, c1, c0, #1 @ Read Auxiliary Control register
+        orr r0, r0, #0x80           @ Set BIT 7 (Disable out-of-order completion
+                                    @ for divide instructions.)
+        mcr p15, #0, r0, c1, c0, #1 @ Write Auxiliary Control register
+        pop {r0}
+        bx lr
+/*-------------------------------------------------------------------------------*/

c/src/lib/libbsp/arm/tms570/hwinit/tms570_tcram_tests.c

@@ -0,0 +1,185 @@
+/**
+ * @file tms570_tcram_tests.c
+ *
+ * @ingroup tms570
+ *
+ * @brief TCRAM selftest function.
+ */
+/*
+ * Copyright (c) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ *
+ * Algorithms are based on Ti manuals and Ti HalCoGen generated
+ * code available under following copyright.
+ */
+/*
+ * Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <stdint.h>
+#include <bsp/tms570.h>
+#include "tms570_selftest.h"
+#include "tms570_hwinit.h"
+
+#define tcramA1bitError (*(volatile uint32_t *)(0x08400000U))
+#define tcramA2bitError (*(volatile uint32_t *)(0x08400010U))
+
+#define tcramB1bitError (*(volatile uint32_t *)(0x08400008U))
+#define tcramB2bitError (*(volatile uint32_t *)(0x08400018U))
+
+#define tcramA1bit      (*(volatile uint64_t *)(0x08000000U))
+#define tcramA2bit      (*(volatile uint64_t *)(0x08000010U))
+
+#define tcramB1bit      (*(volatile uint64_t *)(0x08000008U))
+#define tcramB2bit      (*(volatile uint64_t *)(0x08000018U))
+
+/**
+ * @brief Check TCRAM ECC error detection logic (HCG:checkRAMECC)
+ *
+ * This function checks TCRAM ECC error detection and correction logic.
+ * The function does not return in case of TCRAM error.
+ * It calls bsp_selftest_fail_notification() instead.
+ *
+ */
+/* SourceId : SELFTEST_SourceId_034 */
+/* DesignId : SELFTEST_DesignId_019 */
+/* Requirements : HL_SR408 */
+void  tms570_check_tcram_ecc( void )
+{
+  volatile uint64_t ramread;
+  volatile uint32_t regread;
+  uint32_t tcram1ErrStat, tcram2ErrStat = 0U;
+
+  uint64_t tcramA1_bk = tcramA1bit;
+  uint64_t tcramB1_bk = tcramB1bit;
+  uint64_t tcramA2_bk = tcramA2bit;
+  uint64_t tcramB2_bk = tcramB2bit;
+
+  /* Clear RAMOCUUR before setting RAMTHRESHOLD register */
+  TMS570_TCRAM1.RAMOCCUR = 0U;
+  TMS570_TCRAM2.RAMOCCUR = 0U;
+
+  /* Set Single-bit Error Threshold Count as 1 */
+  TMS570_TCRAM1.RAMTHRESHOLD = 1U;
+  TMS570_TCRAM2.RAMTHRESHOLD = 1U;
+
+  /* Enable single bit error generation */
+  TMS570_TCRAM1.RAMINTCTRL = 1U;
+  TMS570_TCRAM2.RAMINTCTRL = 1U;
+
+  /* Enable writes to ECC RAM, enable ECC error response */
+  TMS570_TCRAM1.RAMCTRL = 0x0005010AU;
+  TMS570_TCRAM2.RAMCTRL = 0x0005010AU;
+
+  /* Force a single bit error in both the banks */
+  _coreDisableRamEcc_();
+  tcramA1bitError ^= 1U;
+  tcramB1bitError ^= 1U;
+  _coreEnableRamEcc_();
+
+  /* Read the corrupted data to generate single bit error */
+  ramread = tcramA1bit;
+  ramread = tcramB1bit;
+  (void)ramread;
+
+  /* Check for error status */
+  tcram1ErrStat = TMS570_TCRAM1.RAMERRSTATUS & 0x1U;
+  tcram2ErrStat = TMS570_TCRAM2.RAMERRSTATUS & 0x1U;
+  /*SAFETYMCUSW 139 S MR:13.7  <APPROVED> "LDRA Tool issue" */
+  /*SAFETYMCUSW 139 S MR:13.7  <APPROVED> "LDRA Tool issue" */
+  if ((tcram1ErrStat == 0U) || (tcram2ErrStat == 0U)) {
+        /* TCRAM module does not reflect 1-bit error reported by CPU */
+    bsp_selftest_fail_notification(CHECKRAMECC_FAIL1);
+  } else {
+    if (!tms570_esm_channel_sr_get(1, 26) || !tms570_esm_channel_sr_get(1, 28)) {
+      /* TCRAM 1-bit error not flagged in ESM */
+      bsp_selftest_fail_notification(CHECKRAMECC_FAIL2);
+    } else {
+      /* Clear single bit error flag in TCRAM module */
+      TMS570_TCRAM1.RAMERRSTATUS = 0x1U;
+      TMS570_TCRAM2.RAMERRSTATUS = 0x1U;
+
+      /* Clear ESM status */
+      tms570_esm_channel_sr_clear(1, 26);
+      tms570_esm_channel_sr_clear(1, 28);
+    }
+  }
+
+#if 0
+  /*
+   * This test sequence requires that data abort exception
+   * handler checks for ECC test write enable in RAMCTR (bit 8)
+   * and if the access abort is intended then it should clear
+   * error status TCRAM status register and checks and clears
+   * ESM group3 uncorrectable TCRAM error channels.
+   *
+   * More modifications in BSP and RTEMS ARM support are
+   * required to make this code work.
+   */
+
+  /* Force a double bit error in both the banks */
+  _coreDisableRamEcc_();
+  tcramA2bitError ^= 3U;
+  tcramB2bitError ^= 3U;
+  _coreEnableRamEcc_();
+
+  /* Read the corrupted data to generate double bit error */
+  ramread = tcramA2bit;
+  ramread = tcramB2bit;
+  /* read from location with 2-bit ECC error this will cause a data abort to be generated */
+  /* See HalCoGen support src/sys/asm/dabort.asm */
+  /* _ARMV4_Exception_data_abort_default has to include solution for this special case for RTEMS */
+#endif
+
+  regread = TMS570_TCRAM1.RAMUERRADDR;
+  regread = TMS570_TCRAM2.RAMUERRADDR;
+  (void)regread;
+
+  /* disable writes to ECC RAM */
+  TMS570_TCRAM1.RAMCTRL = 0x0005000AU;
+  TMS570_TCRAM2.RAMCTRL = 0x0005000AU;
+
+  /* Compute correct ECC */
+  tcramA1bit = tcramA1_bk;
+  tcramB1bit = tcramB1_bk;
+  tcramA2bit = tcramA2_bk;
+  tcramB2bit = tcramB2_bk;
+}

c/src/lib/libbsp/arm/tms570/include/irq.h

@@ -103,6 +103,10 @@
 #define TMS570_IRQ_HET2_LEVEL_1 73
 #define TMS570_IRQ_SCI2_LEVEL_1 74
 #define TMS570_IRQ_HET_TU2_LEVEL_1 75
+#define TMS570_IRQ_EMAC_MISC 76
+#define TMS570_IRQ_EMAC_TX   77
+#define TMS570_IRQ_EMAC_THRESH 78
+#define TMS570_IRQ_EMAC_RX   79
 #define TMS570_IRQ_HWA_INT_REQ_H 80
 #define TMS570_IRQ_HWA_INT_REQ_H 81
 #define TMS570_IRQ_DCC_DONE_INTERRUPT 82

c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_adc.h

@@ -36,8 +36,8 @@
  * of the authors and should not be interpreted as representing official policies,
  * either expressed or implied, of the FreeBSD Project.
 */
-#ifndef LIBBSP_ARM_tms570_ADC
+#ifndef LIBBSP_ARM_TMS570_ADC
-#define LIBBSP_ARM_tms570_ADC
+#define LIBBSP_ARM_TMS570_ADC
 
 #include <bsp/utility.h>
 
@@ -115,71 +115,71 @@ typedef struct{
 } tms570_adc_t;
 
 
-/*-----------------------TMS570_ADCBUF0-----------------------*/
+/*----------------------TMS570_ADC_BUFx----------------------*/
 /* field: G2_EMPTY_10bit_mode - Group2 FIFO Empty. */
-#define TMS570_ADC_BUF0_G2_EMPTY_10bit_mode BSP_FLD32(15)
+#define TMS570_ADC_BUFx_G2_EMPTY_10bit_mode BSP_BIT32(15)
 
 /* field: G2_CHID_10bit_mode - Group2 Channel Id. */
-#define TMS570_ADC_BUF0_G2_CHID_10bit_mode(val) BSP_FLD32(val,10, 14)
+#define TMS570_ADC_BUFx_G2_CHID_10bit_mode(val) BSP_FLD32(val,10, 14)
-#define TMS570_ADC_BUF0_G2_CHID_10bit_mode_GET(reg) BSP_FLD32GET(reg,10, 14)
+#define TMS570_ADC_BUFx_G2_CHID_10bit_mode_GET(reg) BSP_FLD32GET(reg,10, 14)
-#define TMS570_ADC_BUF0_G2_CHID_10bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,10, 14)
+#define TMS570_ADC_BUFx_G2_CHID_10bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,10, 14)
 
 /* field: G2_DR_10bit_mode - Group2 Digital Conversion Result. */
-#define TMS570_ADC_BUF0_G2_DR_10bit_mode(val) BSP_FLD32(val,0, 9)
+#define TMS570_ADC_BUFx_G2_DR_10bit_mode(val) BSP_FLD32(val,0, 9)
-#define TMS570_ADC_BUF0_G2_DR_10bit_mode_GET(reg) BSP_FLD32GET(reg,0, 9)
+#define TMS570_ADC_BUFx_G2_DR_10bit_mode_GET(reg) BSP_FLD32GET(reg,0, 9)
-#define TMS570_ADC_BUF0_G2_DR_10bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
+#define TMS570_ADC_BUFx_G2_DR_10bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
 
 /* field: G2_EMPTY_12bit_mode - Group2 FIFO Empty. */
-#define TMS570_ADC_BUF0_G2_EMPTY_12bit_mode BSP_FLD32(31)
+#define TMS570_ADC_BUFx_G2_EMPTY_12bit_mode BSP_BIT32(31)
 
 /* field: G2_CHID_12bit_mode - Group2 Channel Id. */
-#define TMS570_ADC_BUF0_G2_CHID_12bit_mode(val) BSP_FLD32(val,16, 20)
+#define TMS570_ADC_BUFx_G2_CHID_12bit_mode(val) BSP_FLD32(val,16, 20)
-#define TMS570_ADC_BUF0_G2_CHID_12bit_mode_GET(reg) BSP_FLD32GET(reg,16, 20)
+#define TMS570_ADC_BUFx_G2_CHID_12bit_mode_GET(reg) BSP_FLD32GET(reg,16, 20)
-#define TMS570_ADC_BUF0_G2_CHID_12bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,16, 20)
+#define TMS570_ADC_BUFx_G2_CHID_12bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,16, 20)
 
 /* field: G2_DR_12bit_mode - Group2 Digital Conversion Result. */
-#define TMS570_ADC_BUF0_G2_DR_12bit_mode(val) BSP_FLD32(val,0, 11)
+#define TMS570_ADC_BUFx_G2_DR_12bit_mode(val) BSP_FLD32(val,0, 11)
-#define TMS570_ADC_BUF0_G2_DR_12bit_mode_GET(reg) BSP_FLD32GET(reg,0, 11)
+#define TMS570_ADC_BUFx_G2_DR_12bit_mode_GET(reg) BSP_FLD32GET(reg,0, 11)
-#define TMS570_ADC_BUF0_G2_DR_12bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
+#define TMS570_ADC_BUFx_G2_DR_12bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
 
 
-/*----------------------TMS570_ADCRSTCR----------------------*/
+/*----------------------TMS570_ADC_RSTCR----------------------*/
 /* field: RESET - This bit is used to reset the ADC internal state machines and control/status registers. */
-#define TMS570_ADC_RSTCR_RESET BSP_FLD32(0)
+#define TMS570_ADC_RSTCR_RESET BSP_BIT32(0)
 
 
-/*---------------------TMS570_ADCOPMODECR---------------------*/
+/*--------------------TMS570_ADC_OPMODECR--------------------*/
 /* field: 10_12_BIT - This bit controls the resolution of the ADC core. */
-#define TMS570_ADC_OPMODECR_10_12_BIT BSP_FLD32(31)
+#define TMS570_ADC_OPMODECR_10_12_BIT BSP_BIT32(31)
 
 
-/*---------------------TMS570_ADCCLOCKCR---------------------*/
+/*---------------------TMS570_ADC_CLOCKCR---------------------*/
 /* field: PS - ADC Clock Prescaler. These bits define the prescaler value for the ADC core clock (ADCLK). */
 #define TMS570_ADC_CLOCKCR_PS(val) BSP_FLD32(val,0, 4)
 #define TMS570_ADC_CLOCKCR_PS_GET(reg) BSP_FLD32GET(reg,0, 4)
 #define TMS570_ADC_CLOCKCR_PS_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
 
 
-/*----------------------TMS570_ADCCALCR----------------------*/
+/*----------------------TMS570_ADC_CALCR----------------------*/
 /* field: SELF_TEST - ADC Self Test Enable. */
-#define TMS570_ADC_CALCR_SELF_TEST BSP_FLD32(24)
+#define TMS570_ADC_CALCR_SELF_TEST BSP_BIT32(24)
 
 /* field: CAL_ST - ADC Calibration Conversion Start. */
-#define TMS570_ADC_CALCR_CAL_ST BSP_FLD32(16)
+#define TMS570_ADC_CALCR_CAL_ST BSP_BIT32(16)
 
 /* field: BRIDGE_EN - Bridge Enable. */
-#define TMS570_ADC_CALCR_BRIDGE_EN BSP_FLD32(9)
+#define TMS570_ADC_CALCR_BRIDGE_EN BSP_BIT32(9)
 
 /* field: HILO - ADC Self Test mode and Calibration Mode Reference Source Selection. */
-#define TMS570_ADC_CALCR_HILO BSP_FLD32(8)
+#define TMS570_ADC_CALCR_HILO BSP_BIT32(8)
 
 /* field: CAL_EN - ADC Calibration Enable. */
-#define TMS570_ADC_CALCR_CAL_EN BSP_FLD32(0)
+#define TMS570_ADC_CALCR_CAL_EN BSP_BIT32(0)
 
 
-/*---------------------TMS570_ADCGxMODECR---------------------*/
+/*--------------------TMS570_ADC_GxMODECR--------------------*/
 /* field: No_Reset_on_ChnSel - No Event Group Results Memory Reset on New Channel Select. */
-#define TMS570_ADC_GxMODECR_No_Reset_on_ChnSel BSP_FLD32(16)
+#define TMS570_ADC_GxMODECR_No_Reset_on_ChnSel BSP_BIT32(16)
 
 /* field: EV_DATA_FMT - Event Group Read Data Format. */
 #define TMS570_ADC_GxMODECR_EV_DATA_FMT(val) BSP_FLD32(val,8, 9)
@@ -187,12 +187,12 @@ typedef struct{
 #define TMS570_ADC_GxMODECR_EV_DATA_FMT_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
 
 
-/*----------------------TMS570_ADCEVSRC----------------------*/
+/*----------------------TMS570_ADC_EVSRC----------------------*/
 /* field: EV_EDG_BOTH - rising and falling edge detected on the selected trigger source. */
-#define TMS570_ADC_EVSRC_EV_EDG_BOTH BSP_FLD32(4)
+#define TMS570_ADC_EVSRC_EV_EDG_BOTH BSP_BIT32(4)
 
 /* field: EV_EDG_SEL - Event Group Trigger Edge Polarity Select. */
-#define TMS570_ADC_EVSRC_EV_EDG_SEL BSP_FLD32(3)
+#define TMS570_ADC_EVSRC_EV_EDG_SEL BSP_BIT32(3)
 
 /* field: EV_SRC - Event Group Trigger Source. */
 #define TMS570_ADC_EVSRC_EV_SRC(val) BSP_FLD32(val,0, 2)
@@ -200,12 +200,12 @@ typedef struct{
 #define TMS570_ADC_EVSRC_EV_SRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
 
 
-/*----------------------TMS570_ADCG1SRC----------------------*/
+/*----------------------TMS570_ADC_G1SRC----------------------*/
 /* field: GI_EDG_BOTH - Group1 Trigger Edge Polarity Select. */
-#define TMS570_ADC_G1SRC_GI_EDG_BOTH BSP_FLD32(4)
+#define TMS570_ADC_G1SRC_GI_EDG_BOTH BSP_BIT32(4)
 
 /* field: G1_EDG_SEL - Group1 Trigger Edge Polarity Select. */
-#define TMS570_ADC_G1SRC_G1_EDG_SEL BSP_FLD32(3)
+#define TMS570_ADC_G1SRC_G1_EDG_SEL BSP_BIT32(3)
 
 /* field: G1_SRC - Group1 Trigger Source. */
 #define TMS570_ADC_G1SRC_G1_SRC(val) BSP_FLD32(val,0, 2)
@@ -213,12 +213,12 @@ typedef struct{
 #define TMS570_ADC_G1SRC_G1_SRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
 
 
-/*----------------------TMS570_ADCG2SRC----------------------*/
+/*----------------------TMS570_ADC_G2SRC----------------------*/
 /* field: G2_EDG_BOTH - Group2 Trigger Edge Polarity Select. */
-#define TMS570_ADC_G2SRC_G2_EDG_BOTH BSP_FLD32(4)
+#define TMS570_ADC_G2SRC_G2_EDG_BOTH BSP_BIT32(4)
 
 /* field: G2_EDG_SEL - Group2 Trigger Edge Polarity Select. */
-#define TMS570_ADC_G2SRC_G2_EDG_SEL BSP_FLD32(3)
+#define TMS570_ADC_G2SRC_G2_EDG_SEL BSP_BIT32(3)
 
 /* field: G2_SRC - Group2 Trigger Source. */
 #define TMS570_ADC_G2SRC_G2_SRC(val) BSP_FLD32(val,0, 2)
@@ -226,32 +226,32 @@ typedef struct{
 #define TMS570_ADC_G2SRC_G2_SRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
 
 
-/*---------------------TMS570_ADCGxINTENA---------------------*/
+/*--------------------TMS570_ADC_GxINTENA--------------------*/
 /* field: EV_END_INT_EN - Event Group Conversion End Interrupt Enable. Please refer to Section 19.5. */
-#define TMS570_ADC_GxINTENA_EV_END_INT_EN BSP_FLD32(3)
+#define TMS570_ADC_GxINTENA_EV_END_INT_EN BSP_BIT32(3)
 
 /* field: EV_OVR_INT_EN - write a new conversion result to the Event Group results memory which is already full. */
-#define TMS570_ADC_GxINTENA_EV_OVR_INT_EN BSP_FLD32(1)
+#define TMS570_ADC_GxINTENA_EV_OVR_INT_EN BSP_BIT32(1)
 
 /* field: EV_THR_INT_EN - Event Group Threshold Interrupt Enable. */
-#define TMS570_ADC_GxINTENA_EV_THR_INT_EN BSP_FLD32(0)
+#define TMS570_ADC_GxINTENA_EV_THR_INT_EN BSP_BIT32(0)
 
 
-/*---------------------TMS570_ADCGxINTFLG---------------------*/
+/*--------------------TMS570_ADC_GxINTFLG--------------------*/
 /* field: EV_END - Event Group Conversion End. */
-#define TMS570_ADC_GxINTFLG_EV_END BSP_FLD32(3)
+#define TMS570_ADC_GxINTFLG_EV_END BSP_BIT32(3)
 
 /* field: EV_MEM_EMPTY - Event Group Results Memory Empty. This is a read-only bit; writes have no effect. It is not asource of an interrupt from the ADC module. */
-#define TMS570_ADC_GxINTFLG_EV_MEM_EMPTY BSP_FLD32(2)
+#define TMS570_ADC_GxINTFLG_EV_MEM_EMPTY BSP_BIT32(2)
 
 /* field: EV_MEM_OVERRUN - Event Group Memory Overrun. This is a read-only bit; writes have no effect. */
-#define TMS570_ADC_GxINTFLG_EV_MEM_OVERRUN BSP_FLD32(1)
+#define TMS570_ADC_GxINTFLG_EV_MEM_OVERRUN BSP_BIT32(1)
 
 /* field: EV_THR_INT_FLG - Event Group Threshold Interrupt Flag. */
-#define TMS570_ADC_GxINTFLG_EV_THR_INT_FLG BSP_FLD32(0)
+#define TMS570_ADC_GxINTFLG_EV_THR_INT_FLG BSP_BIT32(0)
 
 
-/*---------------------TMS570_ADCGxINTCR---------------------*/
+/*---------------------TMS570_ADC_GxINTCR---------------------*/
 /* field: Sign_Extension - These bits always read the same as the bit 8 of this register. */
 #define TMS570_ADC_GxINTCR_Sign_Extension(val) BSP_FLD32(val,9, 15)
 #define TMS570_ADC_GxINTCR_Sign_Extension_GET(reg) BSP_FLD32GET(reg,9, 15)
@@ -263,55 +263,55 @@ typedef struct{
 #define TMS570_ADC_GxINTCR_EV_THR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
 
 
-/*---------------------TMS570_ADCEVDMACR---------------------*/
+/*---------------------TMS570_ADC_EVDMACR---------------------*/
 /* field: EV_BLOCKS - Number of Event Group Result buffers to be transferred using DMA if the ADC module is */
 #define TMS570_ADC_EVDMACR_EV_BLOCKS(val) BSP_FLD32(val,16, 24)
 #define TMS570_ADC_EVDMACR_EV_BLOCKS_GET(reg) BSP_FLD32GET(reg,16, 24)
 #define TMS570_ADC_EVDMACR_EV_BLOCKS_SET(reg,val) BSP_FLD32SET(reg, val,16, 24)
 
 /* field: DMA_EV_END - Event Group Conversion End DMA Transfer Enable. */
-#define TMS570_ADC_EVDMACR_DMA_EV_END BSP_FLD32(3)
+#define TMS570_ADC_EVDMACR_DMA_EV_END BSP_BIT32(3)
 
 /* field: EV_BLK_XFER - Event Group Block DMA Transfer Enable. */
-#define TMS570_ADC_EVDMACR_EV_BLK_XFER BSP_FLD32(2)
+#define TMS570_ADC_EVDMACR_EV_BLK_XFER BSP_BIT32(2)
 
 /* field: EV_DMA_EN - Event Group DMA Transfer Enable. */
-#define TMS570_ADC_EVDMACR_EV_DMA_EN BSP_FLD32(0)
+#define TMS570_ADC_EVDMACR_EV_DMA_EN BSP_BIT32(0)
 
 
-/*---------------------TMS570_ADCG1DMACR---------------------*/
+/*---------------------TMS570_ADC_G1DMACR---------------------*/
 /* field: G1_BLOCKS - Number of Group1 Result buffers to be transferred using DMA if the ADC module is configured */
 #define TMS570_ADC_G1DMACR_G1_BLOCKS(val) BSP_FLD32(val,16, 24)
 #define TMS570_ADC_G1DMACR_G1_BLOCKS_GET(reg) BSP_FLD32GET(reg,16, 24)
 #define TMS570_ADC_G1DMACR_G1_BLOCKS_SET(reg,val) BSP_FLD32SET(reg, val,16, 24)
 
 /* field: DMA_G1_END - Group1 Conversion End DMA Transfer Enable. */
-#define TMS570_ADC_G1DMACR_DMA_G1_END BSP_FLD32(3)
+#define TMS570_ADC_G1DMACR_DMA_G1_END BSP_BIT32(3)
 
 /* field: G1_BLK_XFER - Group1 Block DMA Transfer Enable. */
-#define TMS570_ADC_G1DMACR_G1_BLK_XFER BSP_FLD32(2)
+#define TMS570_ADC_G1DMACR_G1_BLK_XFER BSP_BIT32(2)
 
 /* field: G1_DMA_EN - Group1 DMA Transfer Enable. */
-#define TMS570_ADC_G1DMACR_G1_DMA_EN BSP_FLD32(0)
+#define TMS570_ADC_G1DMACR_G1_DMA_EN BSP_BIT32(0)
 
 
-/*---------------------TMS570_ADCG2DMACR---------------------*/
+/*---------------------TMS570_ADC_G2DMACR---------------------*/
 /* field: G2_BLOCKS - Number of Group2 Result buffers to be transferred using DMA if the ADC module is configured */
 #define TMS570_ADC_G2DMACR_G2_BLOCKS(val) BSP_FLD32(val,16, 24)
 #define TMS570_ADC_G2DMACR_G2_BLOCKS_GET(reg) BSP_FLD32GET(reg,16, 24)
 #define TMS570_ADC_G2DMACR_G2_BLOCKS_SET(reg,val) BSP_FLD32SET(reg, val,16, 24)
 
 /* field: DMA_G2_END - Group2 Conversion End DMA Transfer Enable. */
-#define TMS570_ADC_G2DMACR_DMA_G2_END BSP_FLD32(3)
+#define TMS570_ADC_G2DMACR_DMA_G2_END BSP_BIT32(3)
 
 /* field: G2_BLK_XFER - Group2 Block DMA Transfer Enable. */
-#define TMS570_ADC_G2DMACR_G2_BLK_XFER BSP_FLD32(2)
+#define TMS570_ADC_G2DMACR_G2_BLK_XFER BSP_BIT32(2)
 
 /* field: G2_DMA_EN - Group2 DMA Transfer Enable. */
-#define TMS570_ADC_G2DMACR_G2_DMA_EN BSP_FLD32(0)
+#define TMS570_ADC_G2DMACR_G2_DMA_EN BSP_BIT32(0)
 
 
-/*----------------------TMS570_ADCBNDCR----------------------*/
+/*----------------------TMS570_ADC_BNDCR----------------------*/
 /* field: BNDA - Buffer Boundary A. */
 #define TMS570_ADC_BNDCR_BNDA(val) BSP_FLD32(val,16, 24)
 #define TMS570_ADC_BNDCR_BNDA_GET(reg) BSP_FLD32GET(reg,16, 24)
@@ -323,9 +323,9 @@ typedef struct{
 #define TMS570_ADC_BNDCR_BNDB_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
 
 
-/*----------------------TMS570_ADCBNDEND----------------------*/
+/*---------------------TMS570_ADC_BNDEND---------------------*/
 /* field: BUF_INIT_ACTIVE - ADC Results Memory Auto-initialization Status. */
-#define TMS570_ADC_BNDEND_BUF_INIT_ACTIVE BSP_FLD32(16)
+#define TMS570_ADC_BNDEND_BUF_INIT_ACTIVE BSP_BIT32(16)
 
 /* field: BNDEND - Buffer Boundary End. */
 #define TMS570_ADC_BNDEND_BNDEND(val) BSP_FLD32(val,0, 2)
@@ -333,274 +333,274 @@ typedef struct{
 #define TMS570_ADC_BNDEND_BNDEND_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
 
 
-/*----------------------TMS570_ADCEVSAMP----------------------*/
+/*---------------------TMS570_ADC_EVSAMP---------------------*/
 /* field: EV_ACQ - Event Group Acquisition Time. */
 #define TMS570_ADC_EVSAMP_EV_ACQ(val) BSP_FLD32(val,0, 11)
 #define TMS570_ADC_EVSAMP_EV_ACQ_GET(reg) BSP_FLD32GET(reg,0, 11)
 #define TMS570_ADC_EVSAMP_EV_ACQ_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
 
 
-/*----------------------TMS570_ADCG1SAMP----------------------*/
+/*---------------------TMS570_ADC_G1SAMP---------------------*/
 /* field: G1_ACQ - Group1 Acquisition Time. These bits define the sampling window (SW) for the Group1 conversions. */
 #define TMS570_ADC_G1SAMP_G1_ACQ(val) BSP_FLD32(val,0, 11)
 #define TMS570_ADC_G1SAMP_G1_ACQ_GET(reg) BSP_FLD32GET(reg,0, 11)
 #define TMS570_ADC_G1SAMP_G1_ACQ_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
 
 
-/*----------------------TMS570_ADCG2SAMP----------------------*/
+/*---------------------TMS570_ADC_G2SAMP---------------------*/
 /* field: G2_ACQ - Group2 Acquisition Time. These bits define the sampling window (SW) for the Group2 conversions. */
 #define TMS570_ADC_G2SAMP_G2_ACQ(val) BSP_FLD32(val,0, 11)
 #define TMS570_ADC_G2SAMP_G2_ACQ_GET(reg) BSP_FLD32GET(reg,0, 11)
 #define TMS570_ADC_G2SAMP_G2_ACQ_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
 
 
-/*-----------------------TMS570_ADCEVSR-----------------------*/
+/*----------------------TMS570_ADC_EVSR----------------------*/
 /* field: EV_MEM_EMPTY - Event Group Results Memory Empty. */
-#define TMS570_ADC_EVSR_EV_MEM_EMPTY BSP_FLD32(3)
+#define TMS570_ADC_EVSR_EV_MEM_EMPTY BSP_BIT32(3)
 
 /* field: EV_BUSY - Event Group Conversion Busy. */
-#define TMS570_ADC_EVSR_EV_BUSY BSP_FLD32(2)
+#define TMS570_ADC_EVSR_EV_BUSY BSP_BIT32(2)
 
 /* field: EV_STOP - Event Group Conversion Stopped. */
-#define TMS570_ADC_EVSR_EV_STOP BSP_FLD32(1)
+#define TMS570_ADC_EVSR_EV_STOP BSP_BIT32(1)
 
 /* field: EV_END - Event Group Conversions Ended. */
-#define TMS570_ADC_EVSR_EV_END BSP_FLD32(0)
+#define TMS570_ADC_EVSR_EV_END BSP_BIT32(0)
 
 
-/*-----------------------TMS570_ADCG1SR-----------------------*/
+/*----------------------TMS570_ADC_G1SR----------------------*/
 /* field: G1_MEM_EMPTY - Group1 Results Memory Empty. */
-#define TMS570_ADC_G1SR_G1_MEM_EMPTY BSP_FLD32(3)
+#define TMS570_ADC_G1SR_G1_MEM_EMPTY BSP_BIT32(3)
 
 /* field: G1_BUSY - Group1 Conversion Busy. */
-#define TMS570_ADC_G1SR_G1_BUSY BSP_FLD32(2)
+#define TMS570_ADC_G1SR_G1_BUSY BSP_BIT32(2)
 
 /* field: G1_STOP - Group1 Conversion Stopped. */
-#define TMS570_ADC_G1SR_G1_STOP BSP_FLD32(1)
+#define TMS570_ADC_G1SR_G1_STOP BSP_BIT32(1)
 
 /* field: G1_END - Group1 Conversions Ended. */
-#define TMS570_ADC_G1SR_G1_END BSP_FLD32(0)
+#define TMS570_ADC_G1SR_G1_END BSP_BIT32(0)
 
 
-/*-----------------------TMS570_ADCG2SR-----------------------*/
+/*----------------------TMS570_ADC_G2SR----------------------*/
 /* field: G2_MEM_EMPTY - Group2 Results Memory Empty. */
-#define TMS570_ADC_G2SR_G2_MEM_EMPTY BSP_FLD32(3)
+#define TMS570_ADC_G2SR_G2_MEM_EMPTY BSP_BIT32(3)
 
 /* field: G2_BUSY - Group2 Conversion Busy. */
-#define TMS570_ADC_G2SR_G2_BUSY BSP_FLD32(2)
+#define TMS570_ADC_G2SR_G2_BUSY BSP_BIT32(2)
 
 /* field: G2_STOP - Group2 Conversion Stopped. */
-#define TMS570_ADC_G2SR_G2_STOP BSP_FLD32(1)
+#define TMS570_ADC_G2SR_G2_STOP BSP_BIT32(1)
 
 /* field: G2_END - Group2 Conversions Ended. */
-#define TMS570_ADC_G2SR_G2_END BSP_FLD32(0)
+#define TMS570_ADC_G2SR_G2_END BSP_BIT32(0)
 
 
-/*----------------------TMS570_ADCGxSEL----------------------*/
+/*----------------------TMS570_ADC_GxSEL----------------------*/
 /* field: EV_SEL - Event Group channels selected. */
 #define TMS570_ADC_GxSEL_EV_SEL(val) BSP_FLD32(val,0, 15)
 #define TMS570_ADC_GxSEL_EV_SEL_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_ADC_GxSEL_EV_SEL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*-----------------------TMS570_ADCCALR-----------------------*/
+/*----------------------TMS570_ADC_CALR----------------------*/
 /* field: ADCALR - ADC Calibration Result and Offset Error Correction Value. */
 #define TMS570_ADC_CALR_ADCALR(val) BSP_FLD32(val,0, 11)
 #define TMS570_ADC_CALR_ADCALR_GET(reg) BSP_FLD32GET(reg,0, 11)
 #define TMS570_ADC_CALR_ADCALR_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
 
 
-/*---------------------TMS570_ADCSMSTATE---------------------*/
+/*---------------------TMS570_ADC_SMSTATE---------------------*/
 /* field: LAST_CONV - ADC Input Channel's Last Converted Value. */
 #define TMS570_ADC_SMSTATE_LAST_CONV(val) BSP_FLD32(val,0, 23)
 #define TMS570_ADC_SMSTATE_LAST_CONV_GET(reg) BSP_FLD32GET(reg,0, 23)
 #define TMS570_ADC_SMSTATE_LAST_CONV_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
 
 
-/*---------------------TMS570_ADCLASTCONV---------------------*/
+/*--------------------TMS570_ADC_LASTCONV--------------------*/
 /* field: LAST_CONV - ADC Input Channel's Last Converted Value. */
 #define TMS570_ADC_LASTCONV_LAST_CONV(val) BSP_FLD32(val,0, 23)
 #define TMS570_ADC_LASTCONV_LAST_CONV_GET(reg) BSP_FLD32GET(reg,0, 23)
 #define TMS570_ADC_LASTCONV_LAST_CONV_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
 
 
-/*----------------------TMS570_ADCGxBUF----------------------*/
+/*----------------------TMS570_ADC_GxBUF----------------------*/
 /* field: ADEVT_DIR - ADEVT Pin Direction. */
-#define TMS570_ADC_GxBUF_ADEVT_DIR BSP_FLD32(0)
+#define TMS570_ADC_GxBUF_ADEVT_DIR BSP_BIT32(0)
 
 
-/*-------------------TMS570_ADCEVEMUBUFFER-------------------*/
+/*-------------------TMS570_ADC_EVEMUBUFFER-------------------*/
 /* field: ADEVT_DIR - ADEVT Pin Direction. */
-#define TMS570_ADC_EVEMUBUFFER_ADEVT_DIR BSP_FLD32(0)
+#define TMS570_ADC_EVEMUBUFFER_ADEVT_DIR BSP_BIT32(0)
 
 
-/*-------------------TMS570_ADCG1EMUBUFFER-------------------*/
+/*-------------------TMS570_ADC_G1EMUBUFFER-------------------*/
 /* field: ADEVT_DIR - ADEVT Pin Direction. */
-#define TMS570_ADC_G1EMUBUFFER_ADEVT_DIR BSP_FLD32(0)
+#define TMS570_ADC_G1EMUBUFFER_ADEVT_DIR BSP_BIT32(0)
 
 
-/*-------------------TMS570_ADCG2EMUBUFFER-------------------*/
+/*-------------------TMS570_ADC_G2EMUBUFFER-------------------*/
 /* field: ADEVT_DIR - ADEVT Pin Direction. */
-#define TMS570_ADC_G2EMUBUFFER_ADEVT_DIR BSP_FLD32(0)
+#define TMS570_ADC_G2EMUBUFFER_ADEVT_DIR BSP_BIT32(0)
 
 
-/*----------------------TMS570_ADCEVTDIR----------------------*/
+/*---------------------TMS570_ADC_EVTDIR---------------------*/
 /* field: ADEVT_DIR - ADEVT Pin Direction. */
-#define TMS570_ADC_EVTDIR_ADEVT_DIR BSP_FLD32(0)
+#define TMS570_ADC_EVTDIR_ADEVT_DIR BSP_BIT32(0)
 
 
-/*----------------------TMS570_ADCEVTOUT----------------------*/
+/*---------------------TMS570_ADC_EVTOUT---------------------*/
 /* field: ADEVT_OUT - ADEVT Pin Output Value. */
-#define TMS570_ADC_EVTOUT_ADEVT_OUT BSP_FLD32(0)
+#define TMS570_ADC_EVTOUT_ADEVT_OUT BSP_BIT32(0)
 
 
-/*----------------------TMS570_ADCEVTIN----------------------*/
+/*----------------------TMS570_ADC_EVTIN----------------------*/
 /* field: ADEVT_IN - ADEVT Pin Input Value. This is a read-only bit which reflects the logic level on the ADEVT pin. */
-#define TMS570_ADC_EVTIN_ADEVT_IN BSP_FLD32(0)
+#define TMS570_ADC_EVTIN_ADEVT_IN BSP_BIT32(0)
 
 
-/*----------------------TMS570_ADCEVTSET----------------------*/
+/*---------------------TMS570_ADC_EVTSET---------------------*/
 /* field: ADEVT_SET - ADEVT Pin Set. This bit drives the output of the ADEVT pin high. */
-#define TMS570_ADC_EVTSET_ADEVT_SET BSP_FLD32(0)
+#define TMS570_ADC_EVTSET_ADEVT_SET BSP_BIT32(0)
 
 
-/*----------------------TMS570_ADCEVTCLR----------------------*/
+/*---------------------TMS570_ADC_EVTCLR---------------------*/
 /* field: ADEVT_CLR - ADEVT Pin Clear. A read from this bit always returns the current state of the ADEVT pin. */
-#define TMS570_ADC_EVTCLR_ADEVT_CLR BSP_FLD32(0)
+#define TMS570_ADC_EVTCLR_ADEVT_CLR BSP_BIT32(0)
 
 
-/*----------------------TMS570_ADCEVTPDR----------------------*/
+/*---------------------TMS570_ADC_EVTPDR---------------------*/
 /* field: ADEVT_PDR - ADEVT Pin Open Drain Enable. */
-#define TMS570_ADC_EVTPDR_ADEVT_PDR BSP_FLD32(0)
+#define TMS570_ADC_EVTPDR_ADEVT_PDR BSP_BIT32(0)
 
 
-/*---------------------TMS570_ADCEVTPDIS---------------------*/
+/*---------------------TMS570_ADC_EVTPDIS---------------------*/
 /* field: ADEVT_PDIS - ADEVT Pin Pull Control Disable. */
-#define TMS570_ADC_EVTPDIS_ADEVT_PDIS BSP_FLD32(0)
+#define TMS570_ADC_EVTPDIS_ADEVT_PDIS BSP_BIT32(0)
 
 
-/*---------------------TMS570_ADCEVTPSEL---------------------*/
+/*---------------------TMS570_ADC_EVTPSEL---------------------*/
 /* field: ADEVT_PSEL - ADEVT Pin Pull Control Select. */
-#define TMS570_ADC_EVTPSEL_ADEVT_PSEL BSP_FLD32(0)
+#define TMS570_ADC_EVTPSEL_ADEVT_PSEL BSP_BIT32(0)
 
 
-/*-------------------TMS570_ADCEVSAMPDISEN-------------------*/
+/*-------------------TMS570_ADC_EVSAMPDISEN-------------------*/
 /* field: EV_SAMP_DIS_CYC - Event Group sample cap discharge cycles. */
 #define TMS570_ADC_EVSAMPDISEN_EV_SAMP_DIS_CYC(val) BSP_FLD32(val,8, 15)
 #define TMS570_ADC_EVSAMPDISEN_EV_SAMP_DIS_CYC_GET(reg) BSP_FLD32GET(reg,8, 15)
 #define TMS570_ADC_EVSAMPDISEN_EV_SAMP_DIS_CYC_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
 
 /* field: EV_SAMP_DIS_EN - Event Group sample cap discharge enable. */
-#define TMS570_ADC_EVSAMPDISEN_EV_SAMP_DIS_EN BSP_FLD32(0)
+#define TMS570_ADC_EVSAMPDISEN_EV_SAMP_DIS_EN BSP_BIT32(0)
 
 
-/*-------------------TMS570_ADCG1SAMPDISEN-------------------*/
+/*-------------------TMS570_ADC_G1SAMPDISEN-------------------*/
 /* field: G1_SAMP_DIS_CYC - Group1 sample cap discharge cycles. */
 #define TMS570_ADC_G1SAMPDISEN_G1_SAMP_DIS_CYC(val) BSP_FLD32(val,8, 15)
 #define TMS570_ADC_G1SAMPDISEN_G1_SAMP_DIS_CYC_GET(reg) BSP_FLD32GET(reg,8, 15)
 #define TMS570_ADC_G1SAMPDISEN_G1_SAMP_DIS_CYC_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
 
 /* field: G1_SAMP_DIS_EN - Group1 sample cap discharge enable. */
-#define TMS570_ADC_G1SAMPDISEN_G1_SAMP_DIS_EN BSP_FLD32(0)
+#define TMS570_ADC_G1SAMPDISEN_G1_SAMP_DIS_EN BSP_BIT32(0)
 
 
-/*-------------------TMS570_ADCG2SAMPDISEN-------------------*/
+/*-------------------TMS570_ADC_G2SAMPDISEN-------------------*/
 /* field: G2_SAMP_DIS_CYC - for which the ADC internal sampling capacitor is allowed to discharge before sampling the input */
 #define TMS570_ADC_G2SAMPDISEN_G2_SAMP_DIS_CYC(val) BSP_FLD32(val,8, 15)
 #define TMS570_ADC_G2SAMPDISEN_G2_SAMP_DIS_CYC_GET(reg) BSP_FLD32GET(reg,8, 15)
 #define TMS570_ADC_G2SAMPDISEN_G2_SAMP_DIS_CYC_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
 
 /* field: G2_SAMP_DIS_EN - Group2 sample cap discharge enable. */
-#define TMS570_ADC_G2SAMPDISEN_G2_SAMP_DIS_EN BSP_FLD32(0)
+#define TMS570_ADC_G2SAMPDISEN_G2_SAMP_DIS_EN BSP_BIT32(0)
 
 
-/*--------------------TMS570_ADCMAGINTCR1--------------------*/
+/*--------------------TMS570_ADC_MAGINTCRx--------------------*/
 /* field: MAG_CHID2 - These bits specify the channel number from 0 to 31 for which the conversion result needs to be */
-#define TMS570_ADC_MAGINTCR1_MAG_CHID2(val) BSP_FLD32(val,26, 30)
+#define TMS570_ADC_MAGINTCRx_MAG_CHID2(val) BSP_FLD32(val,26, 30)
-#define TMS570_ADC_MAGINTCR1_MAG_CHID2_GET(reg) BSP_FLD32GET(reg,26, 30)
+#define TMS570_ADC_MAGINTCRx_MAG_CHID2_GET(reg) BSP_FLD32GET(reg,26, 30)
-#define TMS570_ADC_MAGINTCR1_MAG_CHID2_SET(reg,val) BSP_FLD32SET(reg, val,26, 30)
+#define TMS570_ADC_MAGINTCRx_MAG_CHID2_SET(reg,val) BSP_FLD32SET(reg, val,26, 30)
 
 /* field: MAG_THR2 - These bits specify the 10-bit compare value which the ADC will use for the comparison with the */
-#define TMS570_ADC_MAGINTCR1_MAG_THR2(val) BSP_FLD32(val,16, 25)
+#define TMS570_ADC_MAGINTCRx_MAG_THR2(val) BSP_FLD32(val,16, 25)
-#define TMS570_ADC_MAGINTCR1_MAG_THR2_GET(reg) BSP_FLD32GET(reg,16, 25)
+#define TMS570_ADC_MAGINTCRx_MAG_THR2_GET(reg) BSP_FLD32GET(reg,16, 25)
-#define TMS570_ADC_MAGINTCR1_MAG_THR2_SET(reg,val) BSP_FLD32SET(reg, val,16, 25)
+#define TMS570_ADC_MAGINTCRx_MAG_THR2_SET(reg,val) BSP_FLD32SET(reg, val,16, 25)
 
 /* field: COMP_CHID2 - These bits specify the channel number from 0 to 31 whose last conversion result is compared */
-#define TMS570_ADC_MAGINTCR1_COMP_CHID2(val) BSP_FLD32(val,8, 12)
+#define TMS570_ADC_MAGINTCRx_COMP_CHID2(val) BSP_FLD32(val,8, 12)
-#define TMS570_ADC_MAGINTCR1_COMP_CHID2_GET(reg) BSP_FLD32GET(reg,8, 12)
+#define TMS570_ADC_MAGINTCRx_COMP_CHID2_GET(reg) BSP_FLD32GET(reg,8, 12)
-#define TMS570_ADC_MAGINTCR1_COMP_CHID2_SET(reg,val) BSP_FLD32SET(reg, val,8, 12)
+#define TMS570_ADC_MAGINTCRx_COMP_CHID2_SET(reg,val) BSP_FLD32SET(reg, val,8, 12)
 
 /* field: CHN_THR_COMP2 - Channel OR Threshold comparison. */
-#define TMS570_ADC_MAGINTCR1_CHN_THR_COMP2 BSP_FLD32(1)
+#define TMS570_ADC_MAGINTCRx_CHN_THR_COMP2 BSP_BIT32(1)
 
 /* field: CMP_GE_LT2 - Greater than or equal to OR Less than comparison operator. */
-#define TMS570_ADC_MAGINTCR1_CMP_GE_LT2 BSP_FLD32(0)
+#define TMS570_ADC_MAGINTCRx_CMP_GE_LT2 BSP_BIT32(0)
 
 
-/*-------------------TMS570_ADCMAGINT1MASK-------------------*/
+/*-------------------TMS570_ADC_MAGINTxMASK-------------------*/
 /* field: MAG_INT0_MASK - These bits specify the mask for the comparison in order to generate the magnitude compare */
-#define TMS570_ADC_MAGINT1MASK_MAG_INT0_MASK(val) BSP_FLD32(val,0, 9)
+#define TMS570_ADC_MAGINTxMASK_MAG_INT0_MASK(val) BSP_FLD32(val,0, 9)
-#define TMS570_ADC_MAGINT1MASK_MAG_INT0_MASK_GET(reg) BSP_FLD32GET(reg,0, 9)
+#define TMS570_ADC_MAGINTxMASK_MAG_INT0_MASK_GET(reg) BSP_FLD32GET(reg,0, 9)
-#define TMS570_ADC_MAGINT1MASK_MAG_INT0_MASK_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
+#define TMS570_ADC_MAGINTxMASK_MAG_INT0_MASK_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
 
 
-/*-----------------TMS570_ADCMAGTHRINTENASET-----------------*/
+/*-----------------TMS570_ADC_MAGTHRINTENASET-----------------*/
 /* field: MAG_INT_ENA_SET - Each of these three bits, when set, enable the corresponding magnitude compare interrupt. */
 #define TMS570_ADC_MAGTHRINTENASET_MAG_INT_ENA_SET(val) BSP_FLD32(val,0, 2)
 #define TMS570_ADC_MAGTHRINTENASET_MAG_INT_ENA_SET_GET(reg) BSP_FLD32GET(reg,0, 2)
 #define TMS570_ADC_MAGTHRINTENASET_MAG_INT_ENA_SET_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
 
 
-/*-----------------TMS570_ADCMAGTHRINTENACLR-----------------*/
+/*-----------------TMS570_ADC_MAGTHRINTENACLR-----------------*/
 /* field: MAG_INT_ENA_CLR - Each of these three bits, when set, enable the corresponding magnitude compare interrupt. */
 #define TMS570_ADC_MAGTHRINTENACLR_MAG_INT_ENA_CLR(val) BSP_FLD32(val,0, 2)
 #define TMS570_ADC_MAGTHRINTENACLR_MAG_INT_ENA_CLR_GET(reg) BSP_FLD32GET(reg,0, 2)
 #define TMS570_ADC_MAGTHRINTENACLR_MAG_INT_ENA_CLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
 
 
-/*-------------------TMS570_ADCMAGTHRINTFLG-------------------*/
+/*------------------TMS570_ADC_MAGTHRINTFLG------------------*/
 /* field: MAG_INT_FLG - Magnitude Compare Interrupt Flags. */
 #define TMS570_ADC_MAGTHRINTFLG_MAG_INT_FLG(val) BSP_FLD32(val,0, 2)
 #define TMS570_ADC_MAGTHRINTFLG_MAG_INT_FLG_GET(reg) BSP_FLD32GET(reg,0, 2)
 #define TMS570_ADC_MAGTHRINTFLG_MAG_INT_FLG_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
 
 
-/*-----------------TMS570_ADCMAGTHRINTOFFSET-----------------*/
+/*-----------------TMS570_ADC_MAGTHRINTOFFSET-----------------*/
 /* field: MAG_INT_OFF - Magnitude Compare Interrupt Offset. */
 #define TMS570_ADC_MAGTHRINTOFFSET_MAG_INT_OFF(val) BSP_FLD32(val,0, 3)
 #define TMS570_ADC_MAGTHRINTOFFSET_MAG_INT_OFF_GET(reg) BSP_FLD32GET(reg,0, 3)
 #define TMS570_ADC_MAGTHRINTOFFSET_MAG_INT_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*------------------TMS570_ADCGxFIFORESETCR------------------*/
+/*------------------TMS570_ADC_GxFIFORESETCR------------------*/
 /* field: EV_FIFO_RESET - allows the ADC module to overwrite the contents of the Event Group results memory starting from */
-#define TMS570_ADC_GxFIFORESETCR_EV_FIFO_RESET BSP_FLD32(0)
+#define TMS570_ADC_GxFIFORESETCR_EV_FIFO_RESET BSP_BIT32(0)
 
 
-/*-------------------TMS570_ADCEVRAMWRADDR-------------------*/
+/*-------------------TMS570_ADC_EVRAMWRADDR-------------------*/
 /* field: G1_RAM_ADDR - Group1 results memory write pointer. */
 #define TMS570_ADC_EVRAMWRADDR_G1_RAM_ADDR(val) BSP_FLD32(val,0, 8)
 #define TMS570_ADC_EVRAMWRADDR_G1_RAM_ADDR_GET(reg) BSP_FLD32GET(reg,0, 8)
 #define TMS570_ADC_EVRAMWRADDR_G1_RAM_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
 
 
-/*-------------------TMS570_ADCG1RAMWRADDR-------------------*/
+/*-------------------TMS570_ADC_G1RAMWRADDR-------------------*/
 /* field: G1_RAM_ADDR - Group1 results memory write pointer. */
 #define TMS570_ADC_G1RAMWRADDR_G1_RAM_ADDR(val) BSP_FLD32(val,0, 8)
 #define TMS570_ADC_G1RAMWRADDR_G1_RAM_ADDR_GET(reg) BSP_FLD32GET(reg,0, 8)
 #define TMS570_ADC_G1RAMWRADDR_G1_RAM_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
 
 
-/*-------------------TMS570_ADCG2RAMWRADDR-------------------*/
+/*-------------------TMS570_ADC_G2RAMWRADDR-------------------*/
 /* field: G2_RAM_ADDR - Group2 results memory write pointer. */
 #define TMS570_ADC_G2RAMWRADDR_G2_RAM_ADDR(val) BSP_FLD32(val,0, 8)
 #define TMS570_ADC_G2RAMWRADDR_G2_RAM_ADDR_GET(reg) BSP_FLD32GET(reg,0, 8)
 #define TMS570_ADC_G2RAMWRADDR_G2_RAM_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
 
 
-/*----------------------TMS570_ADCPARCR----------------------*/
+/*----------------------TMS570_ADC_PARCR----------------------*/
 /* field: TEST - This bit maps the parity bits into the ADC results' RAM frame so that the application can access */
-#define TMS570_ADC_PARCR_TEST BSP_FLD32(8)
+#define TMS570_ADC_PARCR_TEST BSP_BIT32(8)
 
 /* field: PARITY_ENA - PARITY ENA */
 #define TMS570_ADC_PARCR_PARITY_ENA(val) BSP_FLD32(val,0, 3)
@@ -608,14 +608,14 @@ typedef struct{
 #define TMS570_ADC_PARCR_PARITY_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*---------------------TMS570_ADCPARADDR---------------------*/
+/*---------------------TMS570_ADC_PARADDR---------------------*/
 /* field: ERROR_ADDRESS - These bits hold the address of the first parity error generated in the ADC results' RAM. */
 #define TMS570_ADC_PARADDR_ERROR_ADDRESS(val) BSP_FLD32(val,2, 11)
 #define TMS570_ADC_PARADDR_ERROR_ADDRESS_GET(reg) BSP_FLD32GET(reg,2, 11)
 #define TMS570_ADC_PARADDR_ERROR_ADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,2, 11)
 
 
-/*-------------------TMS570_ADCPWRUPDLYCTRL-------------------*/
+/*------------------TMS570_ADC_PWRUPDLYCTRL------------------*/
 /* field: PWRUP_DLY - This register defines the number of VCLK cycles that the ADC state machine has to wait after */
 #define TMS570_ADC_PWRUPDLYCTRL_PWRUP_DLY(val) BSP_FLD32(val,0, 9)
 #define TMS570_ADC_PWRUPDLYCTRL_PWRUP_DLY_GET(reg) BSP_FLD32GET(reg,0, 9)
@@ -623,4 +623,4 @@ typedef struct{
 
 
 
-#endif /* LIBBSP_ARM_tms570_ADC */
+#endif /* LIBBSP_ARM_TMS570_ADC */

c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_ccmsr.h

@@ -36,8 +36,8 @@
  * of the authors and should not be interpreted as representing official policies,
  * either expressed or implied, of the FreeBSD Project.
 */
-#ifndef LIBBSP_ARM_tms570_CCMSR
+#ifndef LIBBSP_ARM_TMS570_CCMSR
-#define LIBBSP_ARM_tms570_CCMSR
+#define LIBBSP_ARM_TMS570_CCMSR
 
 #include <bsp/utility.h>
 
@@ -47,21 +47,21 @@ typedef struct{
 } tms570_ccmsr_t;
 
 
-/*---------------------TMS570_CCMSRCCMSR---------------------*/
+/*---------------------TMS570_CCMSR_CCMSR---------------------*/
 /* field: CMPE - Compare Error */
-#define TMS570_CCMSR_CCMSR_CMPE BSP_FLD32(16)
+#define TMS570_CCMSR_CCMSR_CMPE BSP_BIT32(16)
 
 /* field: STC - Self-test Complete */
-#define TMS570_CCMSR_CCMSR_STC BSP_FLD32(8)
+#define TMS570_CCMSR_CCMSR_STC BSP_BIT32(8)
 
 /* field: STET - Self-test Error Type */
-#define TMS570_CCMSR_CCMSR_STET BSP_FLD32(1)
+#define TMS570_CCMSR_CCMSR_STET BSP_BIT32(1)
 
 /* field: STE - Self-test Error */
-#define TMS570_CCMSR_CCMSR_STE BSP_FLD32(0)
+#define TMS570_CCMSR_CCMSR_STE BSP_BIT32(0)
 
 
-/*--------------------TMS570_CCMSRCCMKEYR--------------------*/
+/*--------------------TMS570_CCMSR_CCMKEYR--------------------*/
 /* field: MKEY - Mode Key */
 #define TMS570_CCMSR_CCMKEYR_MKEY(val) BSP_FLD32(val,0, 3)
 #define TMS570_CCMSR_CCMKEYR_MKEY_GET(reg) BSP_FLD32GET(reg,0, 3)
@@ -69,4 +69,4 @@ typedef struct{
 
 
 
-#endif /* LIBBSP_ARM_tms570_CCMSR */
+#endif /* LIBBSP_ARM_TMS570_CCMSR */

c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_crc.h

@@ -36,8 +36,8 @@
  * of the authors and should not be interpreted as representing official policies,
  * either expressed or implied, of the FreeBSD Project.
 */
-#ifndef LIBBSP_ARM_tms570_CRC
+#ifndef LIBBSP_ARM_TMS570_CRC
-#define LIBBSP_ARM_tms570_CRC
+#define LIBBSP_ARM_TMS570_CRC
 
 #include <bsp/utility.h>
 
@@ -91,27 +91,27 @@ typedef struct{
 } tms570_crc_t;
 
 
-/*----------------------TMS570_CRCCTRL0----------------------*/
+/*----------------------TMS570_CRC_CTRL0----------------------*/
 /* field: CH2_PSA_SWREST - Channel 2 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. */
-#define TMS570_CRC_CTRL0_CH2_PSA_SWREST BSP_FLD32(8)
+#define TMS570_CRC_CTRL0_CH2_PSA_SWREST BSP_BIT32(8)
 
 /* field: CH1_PSA_SWREST - Channel 1 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. */
-#define TMS570_CRC_CTRL0_CH1_PSA_SWREST BSP_FLD32(0)
+#define TMS570_CRC_CTRL0_CH1_PSA_SWREST BSP_BIT32(0)
 
 
-/*----------------------TMS570_CRCCTRL1----------------------*/
+/*----------------------TMS570_CRC_CTRL1----------------------*/
 /* field: PWDN - Power Down. */
-#define TMS570_CRC_CTRL1_PWDN BSP_FLD32(0)
+#define TMS570_CRC_CTRL1_PWDN BSP_BIT32(0)
 
 
-/*----------------------TMS570_CRCCTRL2----------------------*/
+/*----------------------TMS570_CRC_CTRL2----------------------*/
 /* field: CH2_MODE - Channel 2 Mode Selection */
 #define TMS570_CRC_CTRL2_CH2_MODE(val) BSP_FLD32(val,8, 9)
 #define TMS570_CRC_CTRL2_CH2_MODE_GET(reg) BSP_FLD32GET(reg,8, 9)
 #define TMS570_CRC_CTRL2_CH2_MODE_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
 
 /* field: CH1_TRACEEN - Channel 1 Data Trace Enable. When set, the channel is put into data trace mode. */
-#define TMS570_CRC_CTRL2_CH1_TRACEEN BSP_FLD32(4)
+#define TMS570_CRC_CTRL2_CH1_TRACEEN BSP_BIT32(4)
 
 /* field: CH1_MODE - Channel 1 Mode Selection */
 #define TMS570_CRC_CTRL2_CH1_MODE(val) BSP_FLD32(val,0, 1)
@@ -119,309 +119,261 @@ typedef struct{
 #define TMS570_CRC_CTRL2_CH1_MODE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
 
 
-/*-----------------------TMS570_CRCINTS-----------------------*/
+/*----------------------TMS570_CRC_INTS----------------------*/
 /* field: CH2_TIMEOUTENS - Channel 2 Timeout Interrupt Enable Bit. */
-#define TMS570_CRC_INTS_CH2_TIMEOUTENS BSP_FLD32(12)
+#define TMS570_CRC_INTS_CH2_TIMEOUTENS BSP_BIT32(12)
 
 /* field: CH2_UNDERENS - Channel 2 Underrun Interrupt Enable Bit. */
-#define TMS570_CRC_INTS_CH2_UNDERENS BSP_FLD32(11)
+#define TMS570_CRC_INTS_CH2_UNDERENS BSP_BIT32(11)
 
 /* field: CH2_OVERENS - Channel 2 Overrun Interrupt Enable Bit. */
-#define TMS570_CRC_INTS_CH2_OVERENS BSP_FLD32(10)
+#define TMS570_CRC_INTS_CH2_OVERENS BSP_BIT32(10)
 
 /* field: CH2_CRCFAILENS - Channel 2 CRC Fail Interrupt Enable Bit. */
-#define TMS570_CRC_INTS_CH2_CRCFAILENS BSP_FLD32(9)
+#define TMS570_CRC_INTS_CH2_CRCFAILENS BSP_BIT32(9)
 
 /* field: CH2_CCITENS - Channel 2 Compression Complete Interrupt Enable Bit. */
-#define TMS570_CRC_INTS_CH2_CCITENS BSP_FLD32(8)
+#define TMS570_CRC_INTS_CH2_CCITENS BSP_BIT32(8)
 
 /* field: CH1_TIMEOUTENS - Channel 1 Timeout Interrupt Enable Bit. */
-#define TMS570_CRC_INTS_CH1_TIMEOUTENS BSP_FLD32(4)
+#define TMS570_CRC_INTS_CH1_TIMEOUTENS BSP_BIT32(4)
 
 /* field: CH1_UNDERENS - Channel 1 Underrun Interrupt Enable Bit. */
-#define TMS570_CRC_INTS_CH1_UNDERENS BSP_FLD32(3)
+#define TMS570_CRC_INTS_CH1_UNDERENS BSP_BIT32(3)
 
 /* field: CH1_OVERENS - CH1_OVERENS Channel 1 Overrun Interrupt Enable Bit. */
-#define TMS570_CRC_INTS_CH1_OVERENS BSP_FLD32(2)
+#define TMS570_CRC_INTS_CH1_OVERENS BSP_BIT32(2)
 
 /* field: CH1_CRCFAILENS - Channel 1 CRC Fail Interrupt Enable Bit. */
-#define TMS570_CRC_INTS_CH1_CRCFAILENS BSP_FLD32(1)
+#define TMS570_CRC_INTS_CH1_CRCFAILENS BSP_BIT32(1)
 
 /* field: CH1_CCITENS - Channel 1 Compression Complete Interrupt Enable Bit. */
-#define TMS570_CRC_INTS_CH1_CCITENS BSP_FLD32(0)
+#define TMS570_CRC_INTS_CH1_CCITENS BSP_BIT32(0)
 
 
-/*-----------------------TMS570_CRCINTR-----------------------*/
+/*----------------------TMS570_CRC_INTR----------------------*/
 /* field: CH2_TIMEOUTENR - Channel 2 Timeout Interrupt Enable Bit. */
-#define TMS570_CRC_INTR_CH2_TIMEOUTENR BSP_FLD32(12)
+#define TMS570_CRC_INTR_CH2_TIMEOUTENR BSP_BIT32(12)
 
 /* field: CH2_UNDERENR - Channel 2 Underrun Interrupt Enable Bit. */
-#define TMS570_CRC_INTR_CH2_UNDERENR BSP_FLD32(11)
+#define TMS570_CRC_INTR_CH2_UNDERENR BSP_BIT32(11)
 
 /* field: CH2_OVERENR - Channel 2 Overrun Interrupt Enable Bit. */
-#define TMS570_CRC_INTR_CH2_OVERENR BSP_FLD32(10)
+#define TMS570_CRC_INTR_CH2_OVERENR BSP_BIT32(10)
 
 /* field: CH2_CRCFAILENR - Channel 2 CRC Fail Interrupt Enable Bit. */
-#define TMS570_CRC_INTR_CH2_CRCFAILENR BSP_FLD32(9)
+#define TMS570_CRC_INTR_CH2_CRCFAILENR BSP_BIT32(9)
 
 /* field: CH2_CCITENR - Channel 2 Compression Complete Interrupt Enable Bit. */
-#define TMS570_CRC_INTR_CH2_CCITENR BSP_FLD32(8)
+#define TMS570_CRC_INTR_CH2_CCITENR BSP_BIT32(8)
 
 /* field: CH1_TIMEOUTENR - Channel 1 Timeout Interrupt Enable Bit. */
-#define TMS570_CRC_INTR_CH1_TIMEOUTENR BSP_FLD32(4)
+#define TMS570_CRC_INTR_CH1_TIMEOUTENR BSP_BIT32(4)
 
 /* field: CH1_UNDERENR - interrupt. Writing a zero has no effect. */
-#define TMS570_CRC_INTR_CH1_UNDERENR BSP_FLD32(3)
+#define TMS570_CRC_INTR_CH1_UNDERENR BSP_BIT32(3)
 
 /* field: CH1_OVERENR - CH1_OVERENR */
-#define TMS570_CRC_INTR_CH1_OVERENR BSP_FLD32(2)
+#define TMS570_CRC_INTR_CH1_OVERENR BSP_BIT32(2)
 
 /* field: CH1_CRCFAILENR - Channel 1 CRC Fail Interrupt Enable Bit. */
-#define TMS570_CRC_INTR_CH1_CRCFAILENR BSP_FLD32(1)
+#define TMS570_CRC_INTR_CH1_CRCFAILENR BSP_BIT32(1)
 
 /* field: CH1_CCITENR - Channel 1 Compression Complete Interrupt Enable Bit. */
-#define TMS570_CRC_INTR_CH1_CCITENR BSP_FLD32(0)
+#define TMS570_CRC_INTR_CH1_CCITENR BSP_BIT32(0)
 
 
-/*----------------------TMS570_CRCSTATUS----------------------*/
+/*---------------------TMS570_CRC_STATUS---------------------*/
 /* field: CH2_TIMEOUT - Channel 2 CRC Timeout Status Flag. This bit is cleared by writing a '1' to it only. */
-#define TMS570_CRC_STATUS_CH2_TIMEOUT BSP_FLD32(12)
+#define TMS570_CRC_STATUS_CH2_TIMEOUT BSP_BIT32(12)
 
 /* field: CH2_UNDER - Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a '1' to it only. */
-#define TMS570_CRC_STATUS_CH2_UNDER BSP_FLD32(11)
+#define TMS570_CRC_STATUS_CH2_UNDER BSP_BIT32(11)
 
 /* field: CH2_OVER - Channel 2 CRC Overrun Status Flag. This bit is cleared by writing a '1' to it only. */
-#define TMS570_CRC_STATUS_CH2_OVER BSP_FLD32(10)
+#define TMS570_CRC_STATUS_CH2_OVER BSP_BIT32(10)
 
 /* field: CH2_CRCFAIL - Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a '1' to it only. */
-#define TMS570_CRC_STATUS_CH2_CRCFAIL BSP_FLD32(9)
+#define TMS570_CRC_STATUS_CH2_CRCFAIL BSP_BIT32(9)
 
 /* field: CH2_CCIT - Channel 2 CRC Pattern Compression Complete Status Flag. */
-#define TMS570_CRC_STATUS_CH2_CCIT BSP_FLD32(8)
+#define TMS570_CRC_STATUS_CH2_CCIT BSP_BIT32(8)
 
 /* field: CH1_TIMEOUT - Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). */
-#define TMS570_CRC_STATUS_CH1_TIMEOUT BSP_FLD32(4)
+#define TMS570_CRC_STATUS_CH1_TIMEOUT BSP_BIT32(4)
 
 /* field: CH1_UNDER - Channel 1 Underrun Interrupt Enable Bit. */
-#define TMS570_CRC_STATUS_CH1_UNDER BSP_FLD32(3)
+#define TMS570_CRC_STATUS_CH1_UNDER BSP_BIT32(3)
 
 /* field: CH1_OVER - Channel 1 Overrun Interrupt Enable Bit. Writing a one to this bit disable the overrun interrupt. */
-#define TMS570_CRC_STATUS_CH1_OVER BSP_FLD32(2)
+#define TMS570_CRC_STATUS_CH1_OVER BSP_BIT32(2)
 
 /* field: CH1_CRCFAIL - Channel 1 CRC Fail Interrupt Enable Bit. */
-#define TMS570_CRC_STATUS_CH1_CRCFAIL BSP_FLD32(1)
+#define TMS570_CRC_STATUS_CH1_CRCFAIL BSP_BIT32(1)
 
 /* field: CH1_CCIT - Channel 1 CRC Pattern Compression Complete Status Flag. */
-#define TMS570_CRC_STATUS_CH1_CCIT BSP_FLD32(0)
+#define TMS570_CRC_STATUS_CH1_CCIT BSP_BIT32(0)
 
 
-/*-------------------TMS570_CRCINT_OFFS_REG-------------------*/
+/*------------------TMS570_CRC_INT_OFFS_REG------------------*/
 /* field: OFSTREG - CRC Interrupt Offset. This register indicates the highest priority pending interrupt vector address. */
 #define TMS570_CRC_INT_OFFS_REG_OFSTREG(val) BSP_FLD32(val,0, 7)
 #define TMS570_CRC_INT_OFFS_REG_OFSTREG_GET(reg) BSP_FLD32GET(reg,0, 7)
 #define TMS570_CRC_INT_OFFS_REG_OFSTREG_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*-----------------------TMS570_CRCBUSY-----------------------*/
+/*----------------------TMS570_CRC_BUSY----------------------*/
 /* field: CH2_BUSY - CH2_BUSY. */
-#define TMS570_CRC_BUSY_CH2_BUSY BSP_FLD32(8)
+#define TMS570_CRC_BUSY_CH2_BUSY BSP_BIT32(8)
 
 /* field: CH1_BUSY - CH1_BUSY. */
-#define TMS570_CRC_BUSY_CH1_BUSY BSP_FLD32(0)
+#define TMS570_CRC_BUSY_CH1_BUSY BSP_BIT32(0)
 
 
-/*-------------------TMS570_CRCPCOUNT_REG1-------------------*/
+/*-------------------TMS570_CRC_PCOUNT_REG1-------------------*/
 /* field: CRC_PAT_COUNT1 - Channel 1 Pattern Counter Preload Register. */
 #define TMS570_CRC_PCOUNT_REG1_CRC_PAT_COUNT1(val) BSP_FLD32(val,0, 19)
 #define TMS570_CRC_PCOUNT_REG1_CRC_PAT_COUNT1_GET(reg) BSP_FLD32GET(reg,0, 19)
 #define TMS570_CRC_PCOUNT_REG1_CRC_PAT_COUNT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 19)
 
 
-/*-------------------TMS570_CRCSCOUNT_REG1-------------------*/
+/*-------------------TMS570_CRC_SCOUNT_REG1-------------------*/
 /* field: CRC_SEC_COUNT1 - Channel 1 Sector Counter Preload Register. */
 #define TMS570_CRC_SCOUNT_REG1_CRC_SEC_COUNT1(val) BSP_FLD32(val,0, 15)
 #define TMS570_CRC_SCOUNT_REG1_CRC_SEC_COUNT1_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_CRC_SCOUNT_REG1_CRC_SEC_COUNT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*-------------------TMS570_CRCCURSEC_REG1-------------------*/
+/*-------------------TMS570_CRC_CURSEC_REG1-------------------*/
 /* field: CRC_CURSEC1 - Channel 1 Current Sector ID Register. */
 #define TMS570_CRC_CURSEC_REG1_CRC_CURSEC1(val) BSP_FLD32(val,0, 15)
 #define TMS570_CRC_CURSEC_REG1_CRC_CURSEC1_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_CRC_CURSEC_REG1_CRC_CURSEC1_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_CRCWDTOPLD1---------------------*/
+/*--------------------TMS570_CRC_WDTOPLD1--------------------*/
 /* field: CRC_WDTOPLD1 - CRC_WDTOPLD1 */
 #define TMS570_CRC_WDTOPLD1_CRC_WDTOPLD1(val) BSP_FLD32(val,0, 23)
 #define TMS570_CRC_WDTOPLD1_CRC_WDTOPLD1_GET(reg) BSP_FLD32GET(reg,0, 23)
 #define TMS570_CRC_WDTOPLD1_CRC_WDTOPLD1_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
 
 
-/*---------------------TMS570_CRCBCTOPLD1---------------------*/
+/*--------------------TMS570_CRC_BCTOPLD1--------------------*/
 /* field: CRC_BCTOPLD1 - Channel 1 Block Complete Timeout Counter Preload Register. */
 #define TMS570_CRC_BCTOPLD1_CRC_BCTOPLD1(val) BSP_FLD32(val,0, 23)
 #define TMS570_CRC_BCTOPLD1_CRC_BCTOPLD1_GET(reg) BSP_FLD32GET(reg,0, 23)
 #define TMS570_CRC_BCTOPLD1_CRC_BCTOPLD1_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
 
 
-/*-------------------TMS570_CRCPSA_SIGREGL1-------------------*/
+/*------------------TMS570_CRC_PSA_SIGREGL1------------------*/
 /* field: PSASIG1 - Channel 1 PSA Signature Low Register. */
-#define TMS570_CRC_PSA_SIGREGL1_PSASIG1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_CRC_PSA_SIGREGL1_PSASIG1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_CRC_PSA_SIGREGL1_PSASIG1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_CRC_PSA_SIGREGH1------------------*/
-/*-------------------TMS570_CRCPSA_SIGREGH1-------------------*/
 /* field: PSASIG1 - register. */
-#define TMS570_CRC_PSA_SIGREGH1_PSASIG1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_CRC_PSA_SIGREGH1_PSASIG1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_CRC_PSA_SIGREGH1_PSASIG1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*----------------------TMS570_CRC_REGL1----------------------*/
-/*----------------------TMS570_CRCREGL1----------------------*/
 /* field: CRC1 - Channel 1 CRC Value Low Register. */
-#define TMS570_CRC_REGL1_CRC1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_CRC_REGL1_CRC1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_CRC_REGL1_CRC1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*----------------------TMS570_CRC_REGH1----------------------*/
-/*----------------------TMS570_CRCREGH1----------------------*/
 /* field: CRC1 - Channel 1 CRC Value Low Register. */
-#define TMS570_CRC_REGH1_CRC1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_CRC_REGH1_CRC1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_CRC_REGH1_CRC1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-----------------TMS570_CRC_PSA_SECSIGREGL1-----------------*/
-/*-----------------TMS570_CRCPSA_SECSIGREGL1-----------------*/
 /* field: PSASECSIG1 - Channel 1 PSA Sector Signature Low Register. */
-#define TMS570_CRC_PSA_SECSIGREGL1_PSASECSIG1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_CRC_PSA_SECSIGREGL1_PSASECSIG1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_CRC_PSA_SECSIGREGL1_PSASECSIG1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-----------------TMS570_CRC_PSA_SECSIGREGH1-----------------*/
-/*-----------------TMS570_CRCPSA_SECSIGREGH1-----------------*/
 /* field: PSASECSIG1 - Channel 1 PSA Sector Signature High Register. */
-#define TMS570_CRC_PSA_SECSIGREGH1_PSASECSIG1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_CRC_PSA_SECSIGREGH1_PSASECSIG1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_CRC_PSA_SECSIGREGH1_PSASECSIG1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_CRC_RAW_DATAREGL1------------------*/
-/*------------------TMS570_CRCRAW_DATAREGL1------------------*/
 /* field: RAW_DATA1 - hannel 1 Raw Data Low Register.This register contains bits 31:0 of the uncompressed raw data. */
-#define TMS570_CRC_RAW_DATAREGL1_RAW_DATA1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_CRC_RAW_DATAREGL1_RAW_DATA1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_CRC_RAW_DATAREGL1_RAW_DATA1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_CRC_RAW_DATAREGH1------------------*/
-/*------------------TMS570_CRCRAW_DATAREGH1------------------*/
 /* field: RAW_DATA1 - Channel 1 Raw Data High Register. This register contains bits 63:32 of the uncompressed raw data. */
-#define TMS570_CRC_RAW_DATAREGH1_RAW_DATA1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_CRC_RAW_DATAREGH1_RAW_DATA1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_CRC_RAW_DATAREGH1_RAW_DATA1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_CRC_PCOUNT_REG2-------------------*/
-/*-------------------TMS570_CRCPCOUNT_REG2-------------------*/
 /* field: CRC_PAT_COUNT2 - Channel 2 Pattern Counter Preload Register. */
 #define TMS570_CRC_PCOUNT_REG2_CRC_PAT_COUNT2(val) BSP_FLD32(val,0, 19)
 #define TMS570_CRC_PCOUNT_REG2_CRC_PAT_COUNT2_GET(reg) BSP_FLD32GET(reg,0, 19)
 #define TMS570_CRC_PCOUNT_REG2_CRC_PAT_COUNT2_SET(reg,val) BSP_FLD32SET(reg, val,0, 19)
 
 
-/*-------------------TMS570_CRCSCOUNT_REG2-------------------*/
+/*-------------------TMS570_CRC_SCOUNT_REG2-------------------*/
 /* field: CRC_SEC_COUNT2 - Channel 2 Sector Counter Preload Register. */
 #define TMS570_CRC_SCOUNT_REG2_CRC_SEC_COUNT2(val) BSP_FLD32(val,0, 15)
 #define TMS570_CRC_SCOUNT_REG2_CRC_SEC_COUNT2_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_CRC_SCOUNT_REG2_CRC_SEC_COUNT2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*-------------------TMS570_CRCCURSEC_REG2-------------------*/
+/*-------------------TMS570_CRC_CURSEC_REG2-------------------*/
 /* field: CRC_CURSEC2 - Channel 2 Current Sector ID Register. */
 #define TMS570_CRC_CURSEC_REG2_CRC_CURSEC2(val) BSP_FLD32(val,0, 15)
 #define TMS570_CRC_CURSEC_REG2_CRC_CURSEC2_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_CRC_CURSEC_REG2_CRC_CURSEC2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_CRCWDTOPLD2---------------------*/
+/*--------------------TMS570_CRC_WDTOPLD2--------------------*/
 /* field: CRC_WDTOPLD2 - Channel 2 Watchdog Timeout Counter Preload Register. */
 #define TMS570_CRC_WDTOPLD2_CRC_WDTOPLD2(val) BSP_FLD32(val,0, 23)
 #define TMS570_CRC_WDTOPLD2_CRC_WDTOPLD2_GET(reg) BSP_FLD32GET(reg,0, 23)
 #define TMS570_CRC_WDTOPLD2_CRC_WDTOPLD2_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
 
 
-/*---------------------TMS570_CRCBCTOPLD2---------------------*/
+/*--------------------TMS570_CRC_BCTOPLD2--------------------*/
 /* field: CRC_BCTOPLD2 - Channel 2 Block Complete Timeout Counter Preload Register. */
 #define TMS570_CRC_BCTOPLD2_CRC_BCTOPLD2(val) BSP_FLD32(val,0, 23)
 #define TMS570_CRC_BCTOPLD2_CRC_BCTOPLD2_GET(reg) BSP_FLD32GET(reg,0, 23)
 #define TMS570_CRC_BCTOPLD2_CRC_BCTOPLD2_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
 
 
-/*-------------------TMS570_CRCPSA_SIGREGL2-------------------*/
+/*------------------TMS570_CRC_PSA_SIGREGL2------------------*/
 /* field: PSASIG2 - Channel 2 PSA Signature Low Register. */
-#define TMS570_CRC_PSA_SIGREGL2_PSASIG2(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_CRC_PSA_SIGREGL2_PSASIG2_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_CRC_PSA_SIGREGL2_PSASIG2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_CRC_PSA_SIGREGH2------------------*/
-/*-------------------TMS570_CRCPSA_SIGREGH2-------------------*/
 /* field: PSASIG2 - Channel 2 PSA Signature High Register. */
-#define TMS570_CRC_PSA_SIGREGH2_PSASIG2(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_CRC_PSA_SIGREGH2_PSASIG2_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_CRC_PSA_SIGREGH2_PSASIG2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*----------------------TMS570_CRC_REGL2----------------------*/
-/*----------------------TMS570_CRCREGL2----------------------*/
 /* field: CRC2 - stored at CRC2[31:0] register. */
-#define TMS570_CRC_REGL2_CRC2(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_CRC_REGL2_CRC2_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_CRC_REGL2_CRC2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*----------------------TMS570_CRC_REGH2----------------------*/
-/*----------------------TMS570_CRCREGH2----------------------*/
 /* field: CRC2 - Channel 2 CRC Value High Register. */
-#define TMS570_CRC_REGH2_CRC2(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_CRC_REGH2_CRC2_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_CRC_REGH2_CRC2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-----------------TMS570_CRC_PSA_SECSIGREGL2-----------------*/
-/*-----------------TMS570_CRCPSA_SECSIGREGL2-----------------*/
 /* field: PSASECSIG2 - Channel 2 PSA Sector Signature Low Register. */
-#define TMS570_CRC_PSA_SECSIGREGL2_PSASECSIG2(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_CRC_PSA_SECSIGREGL2_PSASECSIG2_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_CRC_PSA_SECSIGREGL2_PSASECSIG2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-----------------TMS570_CRC_PSA_SECSIGREGH2-----------------*/
-/*-----------------TMS570_CRCPSA_SECSIGREGH2-----------------*/
 /* field: PSASECSIG2 - Channel 2 PSA Sector Signature High Register. */
-#define TMS570_CRC_PSA_SECSIGREGH2_PSASECSIG2(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_CRC_PSA_SECSIGREGH2_PSASECSIG2_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_CRC_PSA_SECSIGREGH2_PSASECSIG2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_CRC_RAW_DATAREGL2------------------*/
-/*------------------TMS570_CRCRAW_DATAREGL2------------------*/
 /* field: RAW_DATA2 - Channel 2 Raw Data Low Register. This register contains bits 31:0 of the uncompressed raw data.. */
-#define TMS570_CRC_RAW_DATAREGL2_RAW_DATA2(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_CRC_RAW_DATAREGL2_RAW_DATA2_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_CRC_RAW_DATAREGL2_RAW_DATA2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_CRC_RAW_DATAREGH2------------------*/
-/*------------------TMS570_CRCRAW_DATAREGH2------------------*/
 /* field: RAW_DATA2 - Channel 2 Raw Data High Register. This register contains bits 63:32 of the uncompressed raw data.. */
-#define TMS570_CRC_RAW_DATAREGH2_RAW_DATA2(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_CRC_RAW_DATAREGH2_RAW_DATA2_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_CRC_RAW_DATAREGH2_RAW_DATA2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*---------------------TMS570_CRC_BUS_SEL---------------------*/
-/*---------------------TMS570_CRCBUS_SEL---------------------*/
 /* field: MEn - Enable/disables the tracing of Peripheral Bus Master */
-#define TMS570_CRC_BUS_SEL_MEn BSP_FLD32(2)
+#define TMS570_CRC_BUS_SEL_MEn BSP_BIT32(2)
 
 /* field: DTCMEn - Enable/disables the tracing of data TCM */
-#define TMS570_CRC_BUS_SEL_DTCMEn BSP_FLD32(1)
+#define TMS570_CRC_BUS_SEL_DTCMEn BSP_BIT32(1)
 
 /* field: ITCMEn - Enable/disables the tracing of instruction TCM */
-#define TMS570_CRC_BUS_SEL_ITCMEn BSP_FLD32(0)
+#define TMS570_CRC_BUS_SEL_ITCMEn BSP_BIT32(0)
 
 
 
-#endif /* LIBBSP_ARM_tms570_CRC */
+#endif /* LIBBSP_ARM_TMS570_CRC */

c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dcan.h

@@ -36,8 +36,8 @@
  * of the authors and should not be interpreted as representing official policies,
  * either expressed or implied, of the FreeBSD Project.
 */
-#ifndef LIBBSP_ARM_tms570_DCAN
+#ifndef LIBBSP_ARM_TMS570_DCAN
-#define LIBBSP_ARM_tms570_DCAN
+#define LIBBSP_ARM_TMS570_DCAN
 
 #include <bsp/utility.h>
 
@@ -91,30 +91,30 @@ typedef struct{
 } tms570_dcan_t;
 
 
-/*-----------------------TMS570_DCANCTL-----------------------*/
+/*----------------------TMS570_DCAN_CTL----------------------*/
 /* field: WUBA - Automatic wake up on bus activity when in local power down mode */
-#define TMS570_DCAN_CTL_WUBA BSP_FLD32(25)
+#define TMS570_DCAN_CTL_WUBA BSP_BIT32(25)
 
 /* field: PDR - Request for local low power down mode */
-#define TMS570_DCAN_CTL_PDR BSP_FLD32(24)
+#define TMS570_DCAN_CTL_PDR BSP_BIT32(24)
 
 /* field: DE3 - Enable DMA request line for IF3 */
-#define TMS570_DCAN_CTL_DE3 BSP_FLD32(20)
+#define TMS570_DCAN_CTL_DE3 BSP_BIT32(20)
 
 /* field: DE2 - Enable DMA request line for IF2 */
-#define TMS570_DCAN_CTL_DE2 BSP_FLD32(19)
+#define TMS570_DCAN_CTL_DE2 BSP_BIT32(19)
 
 /* field: DE1 - Enable DMA request line for IF1 */
-#define TMS570_DCAN_CTL_DE1 BSP_FLD32(18)
+#define TMS570_DCAN_CTL_DE1 BSP_BIT32(18)
 
 /* field: IE1 - Interrupt line 1 Enable */
-#define TMS570_DCAN_CTL_IE1 BSP_FLD32(17)
+#define TMS570_DCAN_CTL_IE1 BSP_BIT32(17)
 
 /* field: InitDbg - Internal Init state while debug access */
-#define TMS570_DCAN_CTL_InitDbg BSP_FLD32(16)
+#define TMS570_DCAN_CTL_InitDbg BSP_BIT32(16)
 
 /* field: SWR - SW Reset Enable */
-#define TMS570_DCAN_CTL_SWR BSP_FLD32(15)
+#define TMS570_DCAN_CTL_SWR BSP_BIT32(15)
 
 /* field: PMD - Parity on/off */
 #define TMS570_DCAN_CTL_PMD(val) BSP_FLD32(val,10, 13)
@@ -122,57 +122,57 @@ typedef struct{
 #define TMS570_DCAN_CTL_PMD_SET(reg,val) BSP_FLD32SET(reg, val,10, 13)
 
 /* field: ABO - Auto-Bus-On Enable */
-#define TMS570_DCAN_CTL_ABO BSP_FLD32(9)
+#define TMS570_DCAN_CTL_ABO BSP_BIT32(9)
 
 /* field: IDS - Interruption Debug Support Enable */
-#define TMS570_DCAN_CTL_IDS BSP_FLD32(8)
+#define TMS570_DCAN_CTL_IDS BSP_BIT32(8)
 
 /* field: Test - Test Mode Enable */
-#define TMS570_DCAN_CTL_Test BSP_FLD32(7)
+#define TMS570_DCAN_CTL_Test BSP_BIT32(7)
 
 /* field: CCE - Configuration Change Enable */
-#define TMS570_DCAN_CTL_CCE BSP_FLD32(6)
+#define TMS570_DCAN_CTL_CCE BSP_BIT32(6)
 
 /* field: DAR - Disable Automatic Retransmission */
-#define TMS570_DCAN_CTL_DAR BSP_FLD32(5)
+#define TMS570_DCAN_CTL_DAR BSP_BIT32(5)
 
 /* field: EIE - Error Interrupt Enable */
-#define TMS570_DCAN_CTL_EIE BSP_FLD32(3)
+#define TMS570_DCAN_CTL_EIE BSP_BIT32(3)
 
 /* field: SIE - Status Change Interrupt Enable */
-#define TMS570_DCAN_CTL_SIE BSP_FLD32(2)
+#define TMS570_DCAN_CTL_SIE BSP_BIT32(2)
 
 /* field: IE0 - Interrupt line 0 Enable */
-#define TMS570_DCAN_CTL_IE0 BSP_FLD32(1)
+#define TMS570_DCAN_CTL_IE0 BSP_BIT32(1)
 
 /* field: Init - Initialization */
-#define TMS570_DCAN_CTL_Init BSP_FLD32(0)
+#define TMS570_DCAN_CTL_Init BSP_BIT32(0)
 
 
-/*-----------------------TMS570_DCANES-----------------------*/
+/*-----------------------TMS570_DCAN_ES-----------------------*/
 /* field: PDA - Local power down mode acknowledge */
-#define TMS570_DCAN_ES_PDA BSP_FLD32(10)
+#define TMS570_DCAN_ES_PDA BSP_BIT32(10)
 
 /* field: WakeUp_Pnd - Wake Up Pending */
-#define TMS570_DCAN_ES_WakeUp_Pnd BSP_FLD32(9)
+#define TMS570_DCAN_ES_WakeUp_Pnd BSP_BIT32(9)
 
 /* field: PER - Parity Error Detected */
-#define TMS570_DCAN_ES_PER BSP_FLD32(8)
+#define TMS570_DCAN_ES_PER BSP_BIT32(8)
 
 /* field: BOff - Bus-Off State */
-#define TMS570_DCAN_ES_BOff BSP_FLD32(7)
+#define TMS570_DCAN_ES_BOff BSP_BIT32(7)
 
 /* field: EWarn - Warning State */
-#define TMS570_DCAN_ES_EWarn BSP_FLD32(6)
+#define TMS570_DCAN_ES_EWarn BSP_BIT32(6)
 
 /* field: EPass - Error Passive State */
-#define TMS570_DCAN_ES_EPass BSP_FLD32(5)
+#define TMS570_DCAN_ES_EPass BSP_BIT32(5)
 
 /* field: RxOK - Received a message successfully */
-#define TMS570_DCAN_ES_RxOK BSP_FLD32(4)
+#define TMS570_DCAN_ES_RxOK BSP_BIT32(4)
 
 /* field: TxOK - Transmitted a message successfully */
-#define TMS570_DCAN_ES_TxOK BSP_FLD32(3)
+#define TMS570_DCAN_ES_TxOK BSP_BIT32(3)
 
 /* field: LEC - Last Error Code */
 #define TMS570_DCAN_ES_LEC(val) BSP_FLD32(val,0, 2)
@@ -180,9 +180,9 @@ typedef struct{
 #define TMS570_DCAN_ES_LEC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
 
 
-/*----------------------TMS570_DCANERRC----------------------*/
+/*----------------------TMS570_DCAN_ERRC----------------------*/
 /* field: RP - Receive Error Passive */
-#define TMS570_DCAN_ERRC_RP BSP_FLD32(15)
+#define TMS570_DCAN_ERRC_RP BSP_BIT32(15)
 
 /* field: REC - Receive Error Counter. Actual state of the Receive Error Counter. (values from 0 to 255). */
 #define TMS570_DCAN_ERRC_REC(val) BSP_FLD32(val,8, 14)
@@ -195,7 +195,7 @@ typedef struct{
 #define TMS570_DCAN_ERRC_TEC_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*-----------------------TMS570_DCANBTR-----------------------*/
+/*----------------------TMS570_DCAN_BTR----------------------*/
 /* field: BRPE - Baud Rate Prescaler Extension. */
 #define TMS570_DCAN_BTR_BRPE(val) BSP_FLD32(val,16, 19)
 #define TMS570_DCAN_BTR_BRPE_GET(reg) BSP_FLD32GET(reg,16, 19)
@@ -222,7 +222,7 @@ typedef struct{
 #define TMS570_DCAN_BTR_BRP_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
 
 
-/*-----------------------TMS570_DCANINT-----------------------*/
+/*----------------------TMS570_DCAN_INT----------------------*/
 /* field: Int1ID - Interrupt 1 Identifier (indicates the message object with the highest pending interrupt) */
 #define TMS570_DCAN_INT_Int1ID(val) BSP_FLD32(val,16, 23)
 #define TMS570_DCAN_INT_Int1ID_GET(reg) BSP_FLD32GET(reg,16, 23)
@@ -234,15 +234,15 @@ typedef struct{
 #define TMS570_DCAN_INT_Int0ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*----------------------TMS570_DCANTEST----------------------*/
+/*----------------------TMS570_DCAN_TEST----------------------*/
 /* field: RDA - RAM Direct Access Enable */
-#define TMS570_DCAN_TEST_RDA BSP_FLD32(9)
+#define TMS570_DCAN_TEST_RDA BSP_BIT32(9)
 
 /* field: EXL - External Loop Back Mode */
-#define TMS570_DCAN_TEST_EXL BSP_FLD32(8)
+#define TMS570_DCAN_TEST_EXL BSP_BIT32(8)
 
 /* field: Rx - Receive Pin. Monitors the actual value of the CAN_RX pin. */
-#define TMS570_DCAN_TEST_Rx BSP_FLD32(7)
+#define TMS570_DCAN_TEST_Rx BSP_BIT32(7)
 
 /* field: Tx - Control of CAN_TX pin */
 #define TMS570_DCAN_TEST_Tx(val) BSP_FLD32(val,5, 6)
@@ -250,13 +250,13 @@ typedef struct{
 #define TMS570_DCAN_TEST_Tx_SET(reg,val) BSP_FLD32SET(reg, val,5, 6)
 
 /* field: LBack - Loop Back Mode */
-#define TMS570_DCAN_TEST_LBack BSP_FLD32(4)
+#define TMS570_DCAN_TEST_LBack BSP_BIT32(4)
 
 /* field: Silent - Silent Mode */
-#define TMS570_DCAN_TEST_Silent BSP_FLD32(3)
+#define TMS570_DCAN_TEST_Silent BSP_BIT32(3)
 
 
-/*----------------------TMS570_DCANPERR----------------------*/
+/*----------------------TMS570_DCAN_PERR----------------------*/
 /* field: Word_Number - Word number where parity error has been detected */
 #define TMS570_DCAN_PERR_Word_Number(val) BSP_FLD32(val,8, 10)
 #define TMS570_DCAN_PERR_Word_Number_GET(reg) BSP_FLD32GET(reg,8, 10)
@@ -268,14 +268,11 @@ typedef struct{
 #define TMS570_DCAN_PERR_Message_Number_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*----------------------TMS570_DCANABOTR----------------------*/
+/*---------------------TMS570_DCAN_ABOTR---------------------*/
 /* field: ABO_Time - Number of VBUS clock cycles before a Bus-Off recovery sequence is */
-#define TMS570_DCAN_ABOTR_ABO_Time(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_DCAN_ABOTR_ABO_Time_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_DCAN_ABOTR_ABO_Time_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*---------------------TMS570_DCAN_TXRQX---------------------*/
-/*----------------------TMS570_DCANTXRQX----------------------*/
 /* field: TxRqstReg8 - TxRqstReg8 */
 #define TMS570_DCAN_TXRQX_TxRqstReg8(val) BSP_FLD32(val,14, 15)
 #define TMS570_DCAN_TXRQX_TxRqstReg8_GET(reg) BSP_FLD32GET(reg,14, 15)
@@ -317,14 +314,11 @@ typedef struct{
 #define TMS570_DCAN_TXRQX_TxRqstReg1_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
 
 
-/*----------------------TMS570_DCANTXRQx----------------------*/
+/*---------------------TMS570_DCAN_TXRQx---------------------*/
 /* field: TxRqsX - Transmission Request Bits (for all message objects) */
-#define TMS570_DCAN_TXRQx_TxRqsX(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_DCAN_TXRQx_TxRqsX_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_DCAN_TXRQx_TxRqsX_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*---------------------TMS570_DCAN_NWDATX---------------------*/
-/*---------------------TMS570_DCANNWDATX---------------------*/
 /* field: NewDatReg8 - TxRqstReg8 */
 #define TMS570_DCAN_NWDATX_NewDatReg8(val) BSP_FLD32(val,14, 15)
 #define TMS570_DCAN_NWDATX_NewDatReg8_GET(reg) BSP_FLD32GET(reg,14, 15)
@@ -366,14 +360,11 @@ typedef struct{
 #define TMS570_DCAN_NWDATX_NewDatReg1_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
 
 
-/*---------------------TMS570_DCANNWDATx---------------------*/
+/*---------------------TMS570_DCAN_NWDATx---------------------*/
 /* field: NewDatX - New Data Bits (for all message objects) */
-#define TMS570_DCAN_NWDATx_NewDatX(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_DCAN_NWDATx_NewDatX_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_DCAN_NWDATx_NewDatX_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*--------------------TMS570_DCAN_INTPNDX--------------------*/
-/*---------------------TMS570_DCANINTPNDX---------------------*/
 /* field: IntPndReg8 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Interrupt Pending X Register will be set. */
 #define TMS570_DCAN_INTPNDX_IntPndReg8(val) BSP_FLD32(val,14, 15)
 #define TMS570_DCAN_INTPNDX_IntPndReg8_GET(reg) BSP_FLD32GET(reg,14, 15)
@@ -415,14 +406,11 @@ typedef struct{
 #define TMS570_DCAN_INTPNDX_IntPndReg1_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
 
 
-/*---------------------TMS570_DCANINTPNDx---------------------*/
+/*--------------------TMS570_DCAN_INTPNDx--------------------*/
 /* field: IntPndX - Interrupt Pending Bits (for all message objects) */
-#define TMS570_DCAN_INTPNDx_IntPndX(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_DCAN_INTPNDx_IntPndX_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_DCAN_INTPNDx_IntPndX_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*--------------------TMS570_DCAN_MSGVALX--------------------*/
-/*---------------------TMS570_DCANMSGVALX---------------------*/
 /* field: MsgValReg8 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Message Valid X Register will be set. */
 #define TMS570_DCAN_MSGVALX_MsgValReg8(val) BSP_FLD32(val,14, 15)
 #define TMS570_DCAN_MSGVALX_MsgValReg8_GET(reg) BSP_FLD32GET(reg,14, 15)
@@ -464,50 +452,44 @@ typedef struct{
 #define TMS570_DCAN_MSGVALX_MsgValReg1_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
 
 
-/*---------------------TMS570_DCANMSGVALx---------------------*/
+/*--------------------TMS570_DCAN_MSGVALx--------------------*/
 /* field: MsgVal1To32 - Message Valid Bits (for all message objects) */
-#define TMS570_DCAN_MSGVALx_MsgVal1To32(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_DCAN_MSGVALx_MsgVal1To32_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_DCAN_MSGVALx_MsgVal1To32_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*--------------------TMS570_DCAN_INTMUXx--------------------*/
-/*---------------------TMS570_DCANINTMUXx---------------------*/
 /* field: IntMux1To32 - Multiplexes IntPnd value to either DCAN0INT or DCAN1INT interrupt lines. */
-#define TMS570_DCAN_INTMUXx_IntMux1To32(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_DCAN_INTMUXx_IntMux1To32_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_DCAN_INTMUXx_IntMux1To32_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*---------------------TMS570_DCAN_IF1CMD---------------------*/
-/*---------------------TMS570_DCANIF1CMD---------------------*/
 /* field: WR_RD - Write/Read */
-#define TMS570_DCAN_IF1CMD_WR_RD BSP_FLD32(23)
+#define TMS570_DCAN_IF1CMD_WR_RD BSP_BIT32(23)
 
 /* field: Mask - Access Mask bits */
-#define TMS570_DCAN_IF1CMD_Mask BSP_FLD32(22)
+#define TMS570_DCAN_IF1CMD_Mask BSP_BIT32(22)
 
 /* field: Arb - Access Arbitration bits */
-#define TMS570_DCAN_IF1CMD_Arb BSP_FLD32(21)
+#define TMS570_DCAN_IF1CMD_Arb BSP_BIT32(21)
 
 /* field: Control - Access Control bits */
-#define TMS570_DCAN_IF1CMD_Control BSP_FLD32(20)
+#define TMS570_DCAN_IF1CMD_Control BSP_BIT32(20)
 
 /* field: ClrIntPnd - Clear Interrupt Pending bit */
-#define TMS570_DCAN_IF1CMD_ClrIntPnd BSP_FLD32(19)
+#define TMS570_DCAN_IF1CMD_ClrIntPnd BSP_BIT32(19)
 
 /* field: TxRqst_NewDat - Access Transmission Request bit */
-#define TMS570_DCAN_IF1CMD_TxRqst_NewDat BSP_FLD32(18)
+#define TMS570_DCAN_IF1CMD_TxRqst_NewDat BSP_BIT32(18)
 
 /* field: Data_A - Access Data Bytes 0-3 */
-#define TMS570_DCAN_IF1CMD_Data_A BSP_FLD32(17)
+#define TMS570_DCAN_IF1CMD_Data_A BSP_BIT32(17)
 
 /* field: Data_B - Access Data Bytes 4-7 */
-#define TMS570_DCAN_IF1CMD_Data_B BSP_FLD32(16)
+#define TMS570_DCAN_IF1CMD_Data_B BSP_BIT32(16)
 
 /* field: Busy - Busy flag */
-#define TMS570_DCAN_IF1CMD_Busy BSP_FLD32(15)
+#define TMS570_DCAN_IF1CMD_Busy BSP_BIT32(15)
 
 /* field: DMA_Active - Activation of DMA feature for subsequent internal IF1/IF2 update */
-#define TMS570_DCAN_IF1CMD_DMA_Active BSP_FLD32(14)
+#define TMS570_DCAN_IF1CMD_DMA_Active BSP_BIT32(14)
 
 /* field: Message_Number - Number of message object in Message RAM that is used for data transfer */
 #define TMS570_DCAN_IF1CMD_Message_Number(val) BSP_FLD32(val,0, 7)
@@ -515,12 +497,12 @@ typedef struct{
 #define TMS570_DCAN_IF1CMD_Message_Number_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*---------------------TMS570_DCANIF1MSK---------------------*/
+/*---------------------TMS570_DCAN_IF1MSK---------------------*/
 /* field: MXtd - Mask Extended Identifier */
-#define TMS570_DCAN_IF1MSK_MXtd BSP_FLD32(31)
+#define TMS570_DCAN_IF1MSK_MXtd BSP_BIT32(31)
 
 /* field: MDir - Mask Message Direction */
-#define TMS570_DCAN_IF1MSK_MDir BSP_FLD32(30)
+#define TMS570_DCAN_IF1MSK_MDir BSP_BIT32(30)
 
 /* field: Msk - Identifier Mask */
 #define TMS570_DCAN_IF1MSK_Msk(val) BSP_FLD32(val,0, 28)
@@ -528,15 +510,15 @@ typedef struct{
 #define TMS570_DCAN_IF1MSK_Msk_SET(reg,val) BSP_FLD32SET(reg, val,0, 28)
 
 
-/*---------------------TMS570_DCANIF1ARB---------------------*/
+/*---------------------TMS570_DCAN_IF1ARB---------------------*/
 /* field: MsgVal - Message Valid */
-#define TMS570_DCAN_IF1ARB_MsgVal BSP_FLD32(31)
+#define TMS570_DCAN_IF1ARB_MsgVal BSP_BIT32(31)
 
 /* field: Xtd - Extended Identifier */
-#define TMS570_DCAN_IF1ARB_Xtd BSP_FLD32(30)
+#define TMS570_DCAN_IF1ARB_Xtd BSP_BIT32(30)
 
 /* field: Dir - Message direction */
-#define TMS570_DCAN_IF1ARB_Dir BSP_FLD32(29)
+#define TMS570_DCAN_IF1ARB_Dir BSP_BIT32(29)
 
 /* field: ID - Message Identifier */
 #define TMS570_DCAN_IF1ARB_ID(val) BSP_FLD32(val,0, 28)
@@ -544,33 +526,33 @@ typedef struct{
 #define TMS570_DCAN_IF1ARB_ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 28)
 
 
-/*---------------------TMS570_DCANIF1MCTL---------------------*/
+/*--------------------TMS570_DCAN_IF1MCTL--------------------*/
 /* field: NewDat - New Data */
-#define TMS570_DCAN_IF1MCTL_NewDat BSP_FLD32(15)
+#define TMS570_DCAN_IF1MCTL_NewDat BSP_BIT32(15)
 
 /* field: MsgLst - Message Lost (only valid for message objects with direction = receive) */
-#define TMS570_DCAN_IF1MCTL_MsgLst BSP_FLD32(14)
+#define TMS570_DCAN_IF1MCTL_MsgLst BSP_BIT32(14)
 
 /* field: IntPnd - Interrupt Pending */
-#define TMS570_DCAN_IF1MCTL_IntPnd BSP_FLD32(13)
+#define TMS570_DCAN_IF1MCTL_IntPnd BSP_BIT32(13)
 
 /* field: UMask - Use Acceptance Mask */
-#define TMS570_DCAN_IF1MCTL_UMask BSP_FLD32(12)
+#define TMS570_DCAN_IF1MCTL_UMask BSP_BIT32(12)
 
 /* field: TxIE - Transmit Interrupt Enable */
-#define TMS570_DCAN_IF1MCTL_TxIE BSP_FLD32(11)
+#define TMS570_DCAN_IF1MCTL_TxIE BSP_BIT32(11)
 
 /* field: RxIE - Receive Interrupt Enable */
-#define TMS570_DCAN_IF1MCTL_RxIE BSP_FLD32(10)
+#define TMS570_DCAN_IF1MCTL_RxIE BSP_BIT32(10)
 
 /* field: RmtEn - Remote Enable */
-#define TMS570_DCAN_IF1MCTL_RmtEn BSP_FLD32(9)
+#define TMS570_DCAN_IF1MCTL_RmtEn BSP_BIT32(9)
 
 /* field: TxRqst - Transmit Request */
-#define TMS570_DCAN_IF1MCTL_TxRqst BSP_FLD32(8)
+#define TMS570_DCAN_IF1MCTL_TxRqst BSP_BIT32(8)
 
 /* field: EoB - Data Frame has 0-8 data bits */
-#define TMS570_DCAN_IF1MCTL_EoB BSP_FLD32(7)
+#define TMS570_DCAN_IF1MCTL_EoB BSP_BIT32(7)
 
 /* field: DLC - Data Length Code */
 #define TMS570_DCAN_IF1MCTL_DLC(val) BSP_FLD32(val,0, 3)
@@ -578,7 +560,7 @@ typedef struct{
 #define TMS570_DCAN_IF1MCTL_DLC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*---------------------TMS570_DCANIF1DATA---------------------*/
+/*--------------------TMS570_DCAN_IF1DATA--------------------*/
 /* field: Data0 - Data 0 */
 #define TMS570_DCAN_IF1DATA_Data0(val) BSP_FLD32(val,0, 7)
 #define TMS570_DCAN_IF1DATA_Data0_GET(reg) BSP_FLD32GET(reg,0, 7)
@@ -600,7 +582,7 @@ typedef struct{
 #define TMS570_DCAN_IF1DATA_Data3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
 
 
-/*---------------------TMS570_DCANIF1DATB---------------------*/
+/*--------------------TMS570_DCAN_IF1DATB--------------------*/
 /* field: Data4 - Data 4 */
 #define TMS570_DCAN_IF1DATB_Data4(val) BSP_FLD32(val,0, 7)
 #define TMS570_DCAN_IF1DATB_Data4_GET(reg) BSP_FLD32GET(reg,0, 7)
@@ -622,36 +604,36 @@ typedef struct{
 #define TMS570_DCAN_IF1DATB_Data7_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
 
 
-/*---------------------TMS570_DCANIF2CMD---------------------*/
+/*---------------------TMS570_DCAN_IF2CMD---------------------*/
 /* field: WR_RD - Write/Read */
-#define TMS570_DCAN_IF2CMD_WR_RD BSP_FLD32(23)
+#define TMS570_DCAN_IF2CMD_WR_RD BSP_BIT32(23)
 
 /* field: Mask - Access Mask bits */
-#define TMS570_DCAN_IF2CMD_Mask BSP_FLD32(22)
+#define TMS570_DCAN_IF2CMD_Mask BSP_BIT32(22)
 
 /* field: Arb - Access Arbitration bits */
-#define TMS570_DCAN_IF2CMD_Arb BSP_FLD32(21)
+#define TMS570_DCAN_IF2CMD_Arb BSP_BIT32(21)
 
 /* field: Control - Access Control bits */
-#define TMS570_DCAN_IF2CMD_Control BSP_FLD32(20)
+#define TMS570_DCAN_IF2CMD_Control BSP_BIT32(20)
 
 /* field: ClrIntPnd - Clear Interrupt Pending bit */
-#define TMS570_DCAN_IF2CMD_ClrIntPnd BSP_FLD32(19)
+#define TMS570_DCAN_IF2CMD_ClrIntPnd BSP_BIT32(19)
 
 /* field: TxRqst_NewDat - Access Transmission Request bit */
-#define TMS570_DCAN_IF2CMD_TxRqst_NewDat BSP_FLD32(18)
+#define TMS570_DCAN_IF2CMD_TxRqst_NewDat BSP_BIT32(18)
 
 /* field: Data_A - Access Data Bytes 0-3 */
-#define TMS570_DCAN_IF2CMD_Data_A BSP_FLD32(17)
+#define TMS570_DCAN_IF2CMD_Data_A BSP_BIT32(17)
 
 /* field: Data_B - Access Data Bytes 4-7 */
-#define TMS570_DCAN_IF2CMD_Data_B BSP_FLD32(16)
+#define TMS570_DCAN_IF2CMD_Data_B BSP_BIT32(16)
 
 /* field: Busy - Busy flag */
-#define TMS570_DCAN_IF2CMD_Busy BSP_FLD32(15)
+#define TMS570_DCAN_IF2CMD_Busy BSP_BIT32(15)
 
 /* field: DMA_Active - Activation of DMA feature for subsequent internal IF1/IF2 update */
-#define TMS570_DCAN_IF2CMD_DMA_Active BSP_FLD32(14)
+#define TMS570_DCAN_IF2CMD_DMA_Active BSP_BIT32(14)
 
 /* field: Message_Number - Number of message object in Message RAM that is used for data transfer */
 #define TMS570_DCAN_IF2CMD_Message_Number(val) BSP_FLD32(val,0, 7)
@@ -659,12 +641,12 @@ typedef struct{
 #define TMS570_DCAN_IF2CMD_Message_Number_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*---------------------TMS570_DCANIF2MSK---------------------*/
+/*---------------------TMS570_DCAN_IF2MSK---------------------*/
 /* field: MXtd - Mask Extended Identifier */
-#define TMS570_DCAN_IF2MSK_MXtd BSP_FLD32(31)
+#define TMS570_DCAN_IF2MSK_MXtd BSP_BIT32(31)
 
 /* field: MDir - Mask Message Direction */
-#define TMS570_DCAN_IF2MSK_MDir BSP_FLD32(30)
+#define TMS570_DCAN_IF2MSK_MDir BSP_BIT32(30)
 
 /* field: Msk - Identifier Mask */
 #define TMS570_DCAN_IF2MSK_Msk(val) BSP_FLD32(val,0, 28)
@@ -672,15 +654,15 @@ typedef struct{
 #define TMS570_DCAN_IF2MSK_Msk_SET(reg,val) BSP_FLD32SET(reg, val,0, 28)
 
 
-/*---------------------TMS570_DCANIF2ARB---------------------*/
+/*---------------------TMS570_DCAN_IF2ARB---------------------*/
 /* field: MsgVal - Message Valid */
-#define TMS570_DCAN_IF2ARB_MsgVal BSP_FLD32(31)
+#define TMS570_DCAN_IF2ARB_MsgVal BSP_BIT32(31)
 
 /* field: Xtd - Extended Identifier */
-#define TMS570_DCAN_IF2ARB_Xtd BSP_FLD32(30)
+#define TMS570_DCAN_IF2ARB_Xtd BSP_BIT32(30)
 
 /* field: Dir - Message direction */
-#define TMS570_DCAN_IF2ARB_Dir BSP_FLD32(29)
+#define TMS570_DCAN_IF2ARB_Dir BSP_BIT32(29)
 
 /* field: ID - Message Identifier */
 #define TMS570_DCAN_IF2ARB_ID(val) BSP_FLD32(val,0, 28)
@@ -688,33 +670,33 @@ typedef struct{
 #define TMS570_DCAN_IF2ARB_ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 28)
 
 
-/*---------------------TMS570_DCANIF2MCTL---------------------*/
+/*--------------------TMS570_DCAN_IF2MCTL--------------------*/
 /* field: NewDat - New Data */
-#define TMS570_DCAN_IF2MCTL_NewDat BSP_FLD32(15)
+#define TMS570_DCAN_IF2MCTL_NewDat BSP_BIT32(15)
 
 /* field: MsgLst - Message Lost (only valid for message objects with direction = receive) */
-#define TMS570_DCAN_IF2MCTL_MsgLst BSP_FLD32(14)
+#define TMS570_DCAN_IF2MCTL_MsgLst BSP_BIT32(14)
 
 /* field: IntPnd - Interrupt Pending */
-#define TMS570_DCAN_IF2MCTL_IntPnd BSP_FLD32(13)
+#define TMS570_DCAN_IF2MCTL_IntPnd BSP_BIT32(13)
 
 /* field: UMask - Use Acceptance Mask */
-#define TMS570_DCAN_IF2MCTL_UMask BSP_FLD32(12)
+#define TMS570_DCAN_IF2MCTL_UMask BSP_BIT32(12)
 
 /* field: TxIE - Transmit Interrupt Enable */
-#define TMS570_DCAN_IF2MCTL_TxIE BSP_FLD32(11)
+#define TMS570_DCAN_IF2MCTL_TxIE BSP_BIT32(11)
 
 /* field: RxIE - Receive Interrupt Enable */
-#define TMS570_DCAN_IF2MCTL_RxIE BSP_FLD32(10)
+#define TMS570_DCAN_IF2MCTL_RxIE BSP_BIT32(10)
 
 /* field: RmtEn - Remote Enable */
-#define TMS570_DCAN_IF2MCTL_RmtEn BSP_FLD32(9)
+#define TMS570_DCAN_IF2MCTL_RmtEn BSP_BIT32(9)
 
 /* field: TxRqst - Transmit Request */
-#define TMS570_DCAN_IF2MCTL_TxRqst BSP_FLD32(8)
+#define TMS570_DCAN_IF2MCTL_TxRqst BSP_BIT32(8)
 
 /* field: EoB - Data Frame has 0-8 data bits */
-#define TMS570_DCAN_IF2MCTL_EoB BSP_FLD32(7)
+#define TMS570_DCAN_IF2MCTL_EoB BSP_BIT32(7)
 
 /* field: DLC - Data Length Code */
 #define TMS570_DCAN_IF2MCTL_DLC(val) BSP_FLD32(val,0, 3)
@@ -722,7 +704,7 @@ typedef struct{
 #define TMS570_DCAN_IF2MCTL_DLC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*---------------------TMS570_DCANIF2DATA---------------------*/
+/*--------------------TMS570_DCAN_IF2DATA--------------------*/
 /* field: Data0 - Data 0 */
 #define TMS570_DCAN_IF2DATA_Data0(val) BSP_FLD32(val,0, 7)
 #define TMS570_DCAN_IF2DATA_Data0_GET(reg) BSP_FLD32GET(reg,0, 7)
@@ -744,7 +726,7 @@ typedef struct{
 #define TMS570_DCAN_IF2DATA_Data3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
 
 
-/*---------------------TMS570_DCANIF2DATB---------------------*/
+/*--------------------TMS570_DCAN_IF2DATB--------------------*/
 /* field: Data4 - Data 4 */
 #define TMS570_DCAN_IF2DATB_Data4(val) BSP_FLD32(val,0, 7)
 #define TMS570_DCAN_IF2DATB_Data4_GET(reg) BSP_FLD32GET(reg,0, 7)
@@ -766,47 +748,47 @@ typedef struct{
 #define TMS570_DCAN_IF2DATB_Data7_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
 
 
-/*---------------------TMS570_DCANIF3OBS---------------------*/
+/*---------------------TMS570_DCAN_IF3OBS---------------------*/
 /* field: IF3_Upd - IF3 Update Data */
-#define TMS570_DCAN_IF3OBS_IF3_Upd BSP_FLD32(15)
+#define TMS570_DCAN_IF3OBS_IF3_Upd BSP_BIT32(15)
 
 /* field: IF3_SDB - IF3 Status of Data B read access */
-#define TMS570_DCAN_IF3OBS_IF3_SDB BSP_FLD32(12)
+#define TMS570_DCAN_IF3OBS_IF3_SDB BSP_BIT32(12)
 
 /* field: IF3_SDA - IF3 Status of Data A read access */
-#define TMS570_DCAN_IF3OBS_IF3_SDA BSP_FLD32(11)
+#define TMS570_DCAN_IF3OBS_IF3_SDA BSP_BIT32(11)
 
 /* field: IF3_SC - IF3 Status of Control bits read access */
-#define TMS570_DCAN_IF3OBS_IF3_SC BSP_FLD32(10)
+#define TMS570_DCAN_IF3OBS_IF3_SC BSP_BIT32(10)
 
 /* field: IF3_SA - IF3 Status of Arbitration data read access */
-#define TMS570_DCAN_IF3OBS_IF3_SA BSP_FLD32(9)
+#define TMS570_DCAN_IF3OBS_IF3_SA BSP_BIT32(9)
 
 /* field: IF3_SM - IF3 Status of Mask data read access */
-#define TMS570_DCAN_IF3OBS_IF3_SM BSP_FLD32(8)
+#define TMS570_DCAN_IF3OBS_IF3_SM BSP_BIT32(8)
 
 /* field: Data_B - Data B read observation */
-#define TMS570_DCAN_IF3OBS_Data_B BSP_FLD32(4)
+#define TMS570_DCAN_IF3OBS_Data_B BSP_BIT32(4)
 
 /* field: Data_A - Data A read observation */
-#define TMS570_DCAN_IF3OBS_Data_A BSP_FLD32(3)
+#define TMS570_DCAN_IF3OBS_Data_A BSP_BIT32(3)
 
 /* field: Ctrl - Ctrl read observation */
-#define TMS570_DCAN_IF3OBS_Ctrl BSP_FLD32(2)
+#define TMS570_DCAN_IF3OBS_Ctrl BSP_BIT32(2)
 
 /* field: Arb - Arbitration data read observation */
-#define TMS570_DCAN_IF3OBS_Arb BSP_FLD32(1)
+#define TMS570_DCAN_IF3OBS_Arb BSP_BIT32(1)
 
 /* field: Mask - Mask data read observation */
-#define TMS570_DCAN_IF3OBS_Mask BSP_FLD32(0)
+#define TMS570_DCAN_IF3OBS_Mask BSP_BIT32(0)
 
 
-/*---------------------TMS570_DCANIF3MSK---------------------*/
+/*---------------------TMS570_DCAN_IF3MSK---------------------*/
 /* field: MXtd - Mask Extended Identifier */
-#define TMS570_DCAN_IF3MSK_MXtd BSP_FLD32(31)
+#define TMS570_DCAN_IF3MSK_MXtd BSP_BIT32(31)
 
 /* field: MDir - Mask Message Direction */
-#define TMS570_DCAN_IF3MSK_MDir BSP_FLD32(30)
+#define TMS570_DCAN_IF3MSK_MDir BSP_BIT32(30)
 
 /* field: Msk - Identifier Mask */
 #define TMS570_DCAN_IF3MSK_Msk(val) BSP_FLD32(val,0, 28)
@@ -814,15 +796,15 @@ typedef struct{
 #define TMS570_DCAN_IF3MSK_Msk_SET(reg,val) BSP_FLD32SET(reg, val,0, 28)
 
 
-/*---------------------TMS570_DCANIF3ARB---------------------*/
+/*---------------------TMS570_DCAN_IF3ARB---------------------*/
 /* field: MsgVal - Message Valid */
-#define TMS570_DCAN_IF3ARB_MsgVal BSP_FLD32(31)
+#define TMS570_DCAN_IF3ARB_MsgVal BSP_BIT32(31)
 
 /* field: Xtd - Extended Identifier */
-#define TMS570_DCAN_IF3ARB_Xtd BSP_FLD32(30)
+#define TMS570_DCAN_IF3ARB_Xtd BSP_BIT32(30)
 
 /* field: Dir - Message direction */
-#define TMS570_DCAN_IF3ARB_Dir BSP_FLD32(29)
+#define TMS570_DCAN_IF3ARB_Dir BSP_BIT32(29)
 
 /* field: ID - Message Identifier */
 #define TMS570_DCAN_IF3ARB_ID(val) BSP_FLD32(val,0, 28)
@@ -830,33 +812,33 @@ typedef struct{
 #define TMS570_DCAN_IF3ARB_ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 28)
 
 
-/*---------------------TMS570_DCANIF3MCTL---------------------*/
+/*--------------------TMS570_DCAN_IF3MCTL--------------------*/
 /* field: NewDat - New Data */
-#define TMS570_DCAN_IF3MCTL_NewDat BSP_FLD32(15)
+#define TMS570_DCAN_IF3MCTL_NewDat BSP_BIT32(15)
 
 /* field: MsgLst - Message Lost (only valid for message objects with direction = receive) */
-#define TMS570_DCAN_IF3MCTL_MsgLst BSP_FLD32(14)
+#define TMS570_DCAN_IF3MCTL_MsgLst BSP_BIT32(14)
 
 /* field: IntPnd - Interrupt Pending */
-#define TMS570_DCAN_IF3MCTL_IntPnd BSP_FLD32(13)
+#define TMS570_DCAN_IF3MCTL_IntPnd BSP_BIT32(13)
 
 /* field: UMask - Use Acceptance Mask */
-#define TMS570_DCAN_IF3MCTL_UMask BSP_FLD32(12)
+#define TMS570_DCAN_IF3MCTL_UMask BSP_BIT32(12)
 
 /* field: TxIE - Transmit Interrupt Enable */
-#define TMS570_DCAN_IF3MCTL_TxIE BSP_FLD32(11)
+#define TMS570_DCAN_IF3MCTL_TxIE BSP_BIT32(11)
 
 /* field: RxIE - Receive Interrupt Enable */
-#define TMS570_DCAN_IF3MCTL_RxIE BSP_FLD32(10)
+#define TMS570_DCAN_IF3MCTL_RxIE BSP_BIT32(10)
 
 /* field: RmtEn - Remote Enable */
-#define TMS570_DCAN_IF3MCTL_RmtEn BSP_FLD32(9)
+#define TMS570_DCAN_IF3MCTL_RmtEn BSP_BIT32(9)
 
 /* field: TxRqst - TxRqst */
-#define TMS570_DCAN_IF3MCTL_TxRqst BSP_FLD32(8)
+#define TMS570_DCAN_IF3MCTL_TxRqst BSP_BIT32(8)
 
 /* field: EoB - End of Block */
-#define TMS570_DCAN_IF3MCTL_EoB BSP_FLD32(7)
+#define TMS570_DCAN_IF3MCTL_EoB BSP_BIT32(7)
 
 /* field: DLC - Data Length Code */
 #define TMS570_DCAN_IF3MCTL_DLC(val) BSP_FLD32(val,0, 3)
@@ -864,7 +846,7 @@ typedef struct{
 #define TMS570_DCAN_IF3MCTL_DLC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*---------------------TMS570_DCANIF3DATA---------------------*/
+/*--------------------TMS570_DCAN_IF3DATA--------------------*/
 /* field: Data0 - Data 0 */
 #define TMS570_DCAN_IF3DATA_Data0(val) BSP_FLD32(val,0, 7)
 #define TMS570_DCAN_IF3DATA_Data0_GET(reg) BSP_FLD32GET(reg,0, 7)
@@ -886,7 +868,7 @@ typedef struct{
 #define TMS570_DCAN_IF3DATA_Data3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
 
 
-/*---------------------TMS570_DCANIF3DATB---------------------*/
+/*--------------------TMS570_DCAN_IF3DATB--------------------*/
 /* field: Data4 - Data 4 */
 #define TMS570_DCAN_IF3DATB_Data4(val) BSP_FLD32(val,0, 7)
 #define TMS570_DCAN_IF3DATB_Data4_GET(reg) BSP_FLD32GET(reg,0, 7)
@@ -908,55 +890,52 @@ typedef struct{
 #define TMS570_DCAN_IF3DATB_Data7_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
 
 
-/*---------------------TMS570_DCANIF3UEy---------------------*/
+/*---------------------TMS570_DCAN_IF3UEy---------------------*/
 /* field: IF3UpdEn - IF3 Update Enabled (for all message objects) */
-#define TMS570_DCAN_IF3UEy_IF3UpdEn(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_DCAN_IF3UEy_IF3UpdEn_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_DCAN_IF3UEy_IF3UpdEn_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*----------------------TMS570_DCAN_TIOC----------------------*/
-/*----------------------TMS570_DCANTIOC----------------------*/
 /* field: PU - CAN_TX Pullup/Pulldown select. This bit is only active when CAN_TX is configured to be an input. */
-#define TMS570_DCAN_TIOC_PU BSP_FLD32(18)
+#define TMS570_DCAN_TIOC_PU BSP_BIT32(18)
 
 /* field: PD - CAN_TX pull disable. This bit is only active when CAN_TX is configured to be an input. */
-#define TMS570_DCAN_TIOC_PD BSP_FLD32(17)
+#define TMS570_DCAN_TIOC_PD BSP_BIT32(17)
 
 /* field: OD - CAN_TX open drain enable. */
-#define TMS570_DCAN_TIOC_OD BSP_FLD32(16)
+#define TMS570_DCAN_TIOC_OD BSP_BIT32(16)
 
 /* field: Func - CAN_TX function. This bit changes the function of the CAN_TX pin. */
-#define TMS570_DCAN_TIOC_Func BSP_FLD32(3)
+#define TMS570_DCAN_TIOC_Func BSP_BIT32(3)
 
 /* field: Dir - CAN_TX data direction. */
-#define TMS570_DCAN_TIOC_Dir BSP_FLD32(2)
+#define TMS570_DCAN_TIOC_Dir BSP_BIT32(2)
 
 /* field: Out - CAN_TX data out write. */
-#define TMS570_DCAN_TIOC_Out BSP_FLD32(1)
+#define TMS570_DCAN_TIOC_Out BSP_BIT32(1)
 
 
-/*----------------------TMS570_DCANRIOC----------------------*/
+/*----------------------TMS570_DCAN_RIOC----------------------*/
 /* field: PU - CAN_RX Pullup/Pulldown select. This bit is only active when CAN_RX is configured to be an input. */
-#define TMS570_DCAN_RIOC_PU BSP_FLD32(18)
+#define TMS570_DCAN_RIOC_PU BSP_BIT32(18)
 
 /* field: PD - CAN_RX pull disable. This bit is only active when CAN_RX is configured to be an input. */
-#define TMS570_DCAN_RIOC_PD BSP_FLD32(17)
+#define TMS570_DCAN_RIOC_PD BSP_BIT32(17)
 
 /* field: OD - CAN_RX open drain enable. */
-#define TMS570_DCAN_RIOC_OD BSP_FLD32(16)
+#define TMS570_DCAN_RIOC_OD BSP_BIT32(16)
 
 /* field: Func - CAN_RX function. This bit changes the function of the CAN_RX pin. */
-#define TMS570_DCAN_RIOC_Func BSP_FLD32(3)
+#define TMS570_DCAN_RIOC_Func BSP_BIT32(3)
 
 /* field: Dir - CAN_RX data direction. */
-#define TMS570_DCAN_RIOC_Dir BSP_FLD32(2)
+#define TMS570_DCAN_RIOC_Dir BSP_BIT32(2)
 
 /* field: Out - CAN_RX data out write. */
-#define TMS570_DCAN_RIOC_Out BSP_FLD32(1)
+#define TMS570_DCAN_RIOC_Out BSP_BIT32(1)
 
 /* field: In - CAN_RX data in. */
-#define TMS570_DCAN_RIOC_In BSP_FLD32(0)
+#define TMS570_DCAN_RIOC_In BSP_BIT32(0)
 
 
 
-#endif /* LIBBSP_ARM_tms570_DCAN */
+#endif /* LIBBSP_ARM_TMS570_DCAN */

c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dcc.h

@@ -36,8 +36,8 @@
  * of the authors and should not be interpreted as representing official policies,
  * either expressed or implied, of the FreeBSD Project.
 */
-#ifndef LIBBSP_ARM_tms570_DCC
+#ifndef LIBBSP_ARM_TMS570_DCC
-#define LIBBSP_ARM_tms570_DCC
+#define LIBBSP_ARM_TMS570_DCC
 
 #include <bsp/utility.h>
 
@@ -56,7 +56,7 @@ typedef struct{
 } tms570_dcc_t;
 
 
-/*----------------------TMS570_DCCGCTRL----------------------*/
+/*----------------------TMS570_DCC_GCTRL----------------------*/
 /* field: DONE_INT_ENA - Done Interrupt Enable. */
 #define TMS570_DCC_GCTRL_DONE_INT_ENA(val) BSP_FLD32(val,12, 15)
 #define TMS570_DCC_GCTRL_DONE_INT_ENA_GET(reg) BSP_FLD32GET(reg,12, 15)
@@ -78,7 +78,7 @@ typedef struct{
 #define TMS570_DCC_GCTRL_DCC_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*-----------------------TMS570_DCCREV-----------------------*/
+/*-----------------------TMS570_DCC_REV-----------------------*/
 /* field: SCHEME - Reads return 01, writes have no effect. */
 #define TMS570_DCC_REV_SCHEME(val) BSP_FLD32(val,30, 31)
 #define TMS570_DCC_REV_SCHEME_GET(reg) BSP_FLD32GET(reg,30, 31)
@@ -110,57 +110,57 @@ typedef struct{
 #define TMS570_DCC_REV_MINOR_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
 
 
-/*---------------------TMS570_DCCCNT0SEED---------------------*/
+/*--------------------TMS570_DCC_CNT0SEED--------------------*/
 /* field: COUNT0_SEED - Seed value for DCC Counter0. */
 #define TMS570_DCC_CNT0SEED_COUNT0_SEED(val) BSP_FLD32(val,0, 19)
 #define TMS570_DCC_CNT0SEED_COUNT0_SEED_GET(reg) BSP_FLD32GET(reg,0, 19)
 #define TMS570_DCC_CNT0SEED_COUNT0_SEED_SET(reg,val) BSP_FLD32SET(reg, val,0, 19)
 
 
-/*--------------------TMS570_DCCVALID0SEED--------------------*/
+/*-------------------TMS570_DCC_VALID0SEED-------------------*/
 /* field: VALID0_SEED - XXX */
 #define TMS570_DCC_VALID0SEED_VALID0_SEED(val) BSP_FLD32(val,0, 15)
 #define TMS570_DCC_VALID0SEED_VALID0_SEED_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_DCC_VALID0SEED_VALID0_SEED_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_DCCCNT1SEED---------------------*/
+/*--------------------TMS570_DCC_CNT1SEED--------------------*/
 /* field: COUNT1_SEED - Seed value for DCC Counter1. */
 #define TMS570_DCC_CNT1SEED_COUNT1_SEED(val) BSP_FLD32(val,0, 19)
 #define TMS570_DCC_CNT1SEED_COUNT1_SEED_GET(reg) BSP_FLD32GET(reg,0, 19)
 #define TMS570_DCC_CNT1SEED_COUNT1_SEED_SET(reg,val) BSP_FLD32SET(reg, val,0, 19)
 
 
-/*-----------------------TMS570_DCCSTAT-----------------------*/
+/*----------------------TMS570_DCC_STAT----------------------*/
 /* field: DONE_FLG - Single-Shot Sequence Done flag. */
-#define TMS570_DCC_STAT_DONE_FLG BSP_FLD32(1)
+#define TMS570_DCC_STAT_DONE_FLG BSP_BIT32(1)
 
 /* field: ERR_FLG - Error flag. Indicates that a DCC error has occurred. */
-#define TMS570_DCC_STAT_ERR_FLG BSP_FLD32(0)
+#define TMS570_DCC_STAT_ERR_FLG BSP_BIT32(0)
 
 
-/*-----------------------TMS570_DCCCNT0-----------------------*/
+/*----------------------TMS570_DCC_CNT0----------------------*/
 /* field: COUNT0 - Current value of DCC Counter0. */
 #define TMS570_DCC_CNT0_COUNT0(val) BSP_FLD32(val,0, 19)
 #define TMS570_DCC_CNT0_COUNT0_GET(reg) BSP_FLD32GET(reg,0, 19)
 #define TMS570_DCC_CNT0_COUNT0_SET(reg,val) BSP_FLD32SET(reg, val,0, 19)
 
 
-/*----------------------TMS570_DCCVALID0----------------------*/
+/*---------------------TMS570_DCC_VALID0---------------------*/
 /* field: VALID0 - Current value for DCC Valid0. */
 #define TMS570_DCC_VALID0_VALID0(val) BSP_FLD32(val,0, 15)
 #define TMS570_DCC_VALID0_VALID0_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_DCC_VALID0_VALID0_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*-----------------------TMS570_DCCCNT1-----------------------*/
+/*----------------------TMS570_DCC_CNT1----------------------*/
 /* field: COUNT1 - Current value for DCC Counter1. */
 #define TMS570_DCC_CNT1_COUNT1(val) BSP_FLD32(val,0, 19)
 #define TMS570_DCC_CNT1_COUNT1_GET(reg) BSP_FLD32GET(reg,0, 19)
 #define TMS570_DCC_CNT1_COUNT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 19)
 
 
-/*--------------------TMS570_DCCCNT1CLKSRC--------------------*/
+/*-------------------TMS570_DCC_CNT1CLKSRC-------------------*/
 /* field: KEY - Key to enable clock source selection for Counter1. */
 #define TMS570_DCC_CNT1CLKSRC_KEY(val) BSP_FLD32(val,12, 15)
 #define TMS570_DCC_CNT1CLKSRC_KEY_GET(reg) BSP_FLD32GET(reg,12, 15)
@@ -172,7 +172,7 @@ typedef struct{
 #define TMS570_DCC_CNT1CLKSRC_CNT1_CLKSRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*--------------------TMS570_DCCCNT0CLKSRC--------------------*/
+/*-------------------TMS570_DCC_CNT0CLKSRC-------------------*/
 /* field: CNT0_CLKSRC - Clock Source for Counter0 */
 #define TMS570_DCC_CNT0CLKSRC_CNT0_CLKSRC(val) BSP_FLD32(val,0, 3)
 #define TMS570_DCC_CNT0CLKSRC_CNT0_CLKSRC_GET(reg) BSP_FLD32GET(reg,0, 3)
@@ -180,4 +180,4 @@ typedef struct{
 
 
 
-#endif /* LIBBSP_ARM_tms570_DCC */
+#endif /* LIBBSP_ARM_TMS570_DCC */

c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dma.h

@@ -36,8 +36,8 @@
  * of the authors and should not be interpreted as representing official policies,
  * either expressed or implied, of the FreeBSD Project.
 */
-#ifndef LIBBSP_ARM_tms570_DMA
+#ifndef LIBBSP_ARM_TMS570_DMA
-#define LIBBSP_ARM_tms570_DMA
+#define LIBBSP_ARM_TMS570_DMA
 
 #include <bsp/utility.h>
 
@@ -140,26 +140,20 @@ typedef struct{
 } tms570_dma_t;
 
 
-/*---------------------TMS570_DMASTARTADD---------------------*/
+/*--------------------TMS570_DMA_STARTADD--------------------*/
 /* field: STARTADDRESS - Start Address defines the address at which the region begins. */
-#define TMS570_DMA_STARTADD_STARTADDRESS(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_DMA_STARTADD_STARTADDRESS_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_DMA_STARTADD_STARTADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*---------------------TMS570_DMA_ENDADD---------------------*/
-/*----------------------TMS570_DMAENDADD----------------------*/
 /* field: ENDADDRESS - End Address defines the address at which the region ends. */
-#define TMS570_DMA_ENDADD_ENDADDRESS(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_DMA_ENDADD_ENDADDRESS_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_DMA_ENDADD_ENDADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*----------------------TMS570_DMA_GCTRL----------------------*/
-/*----------------------TMS570_DMAGCTRL----------------------*/
 /* field: DMA_EN - DMA enable bit. */
-#define TMS570_DMA_GCTRL_DMA_EN BSP_FLD32(16)
+#define TMS570_DMA_GCTRL_DMA_EN BSP_BIT32(16)
 
 /* field: BUS_BUSY - This bit indicates status of DMA external AHB bus status. */
-#define TMS570_DMA_GCTRL_BUS_BUSY BSP_FLD32(14)
+#define TMS570_DMA_GCTRL_BUS_BUSY BSP_BIT32(14)
 
 /* field: DEBUG_MODE - Debug Mode. */
 #define TMS570_DMA_GCTRL_DEBUG_MODE(val) BSP_FLD32(val,8, 9)
@@ -167,80 +161,80 @@ typedef struct{
 #define TMS570_DMA_GCTRL_DEBUG_MODE_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
 
 /* field: DMA_RES - DMA software reset */
-#define TMS570_DMA_GCTRL_DMA_RES BSP_FLD32(0)
+#define TMS570_DMA_GCTRL_DMA_RES BSP_BIT32(0)
 
 
-/*-----------------------TMS570_DMAPEND-----------------------*/
+/*----------------------TMS570_DMA_PEND----------------------*/
 /* field: PEND - Channel pending register. */
 #define TMS570_DMA_PEND_PEND(val) BSP_FLD32(val,0, 15)
 #define TMS570_DMA_PEND_PEND_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_DMA_PEND_PEND_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_DMADMASTAT---------------------*/
+/*---------------------TMS570_DMA_DMASTAT---------------------*/
 /* field: STCH - Status of DMA channels. */
 #define TMS570_DMA_DMASTAT_STCH(val) BSP_FLD32(val,0, 15)
 #define TMS570_DMA_DMASTAT_STCH_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_DMA_DMASTAT_STCH_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_DMAHWCHENAS---------------------*/
+/*--------------------TMS570_DMA_HWCHENAS--------------------*/
 /* field: HWCHENA - Hardware channel enable bit. */
 #define TMS570_DMA_HWCHENAS_HWCHENA(val) BSP_FLD32(val,0, 15)
 #define TMS570_DMA_HWCHENAS_HWCHENA_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_DMA_HWCHENAS_HWCHENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_DMAHWCHENAR---------------------*/
+/*--------------------TMS570_DMA_HWCHENAR--------------------*/
 /* field: HWCHDIS - HW channel disable bit. */
 #define TMS570_DMA_HWCHENAR_HWCHDIS(val) BSP_FLD32(val,0, 15)
 #define TMS570_DMA_HWCHENAR_HWCHDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_DMA_HWCHENAR_HWCHDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_DMASWCHENAS---------------------*/
+/*--------------------TMS570_DMA_SWCHENAS--------------------*/
 /* field: SWCHENA - SW channel enable bit. */
 #define TMS570_DMA_SWCHENAS_SWCHENA(val) BSP_FLD32(val,0, 15)
 #define TMS570_DMA_SWCHENAS_SWCHENA_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_DMA_SWCHENAS_SWCHENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_DMASWCHENAR---------------------*/
+/*--------------------TMS570_DMA_SWCHENAR--------------------*/
 /* field: SWCHDIS - SW channel disable bit. */
 #define TMS570_DMA_SWCHENAR_SWCHDIS(val) BSP_FLD32(val,0, 15)
 #define TMS570_DMA_SWCHENAR_SWCHDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_DMA_SWCHENAR_SWCHDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_DMACHPRIOS---------------------*/
+/*---------------------TMS570_DMA_CHPRIOS---------------------*/
 /* field: CPS - Channel priority set bit. */
 #define TMS570_DMA_CHPRIOS_CPS(val) BSP_FLD32(val,0, 15)
 #define TMS570_DMA_CHPRIOS_CPS_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_DMA_CHPRIOS_CPS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_DMACHPRIOR---------------------*/
+/*---------------------TMS570_DMA_CHPRIOR---------------------*/
 /* field: CPR - Channel priority reset bit. */
 #define TMS570_DMA_CHPRIOR_CPR(val) BSP_FLD32(val,0, 15)
 #define TMS570_DMA_CHPRIOR_CPR_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_DMA_CHPRIOR_CPR_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_DMAGCHIENAS---------------------*/
+/*--------------------TMS570_DMA_GCHIENAS--------------------*/
 /* field: GCHIE - Global channel interrupt enable bit. */
 #define TMS570_DMA_GCHIENAS_GCHIE(val) BSP_FLD32(val,0, 15)
 #define TMS570_DMA_GCHIENAS_GCHIE_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_DMA_GCHIENAS_GCHIE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_DMAGCHIENAR---------------------*/
+/*--------------------TMS570_DMA_GCHIENAR--------------------*/
 /* field: GCHID - Global channel interrupt disable bit. */
 #define TMS570_DMA_GCHIENAR_GCHID(val) BSP_FLD32(val,0, 15)
 #define TMS570_DMA_GCHIENAR_GCHID_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_DMA_GCHIENAR_GCHID_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_DMADREQASI---------------------*/
+/*---------------------TMS570_DMA_DREQASI---------------------*/
 /* field: CH0ASI - Channel 0 assignment. This bit field chooses the DMA request assignment for channel 0. */
 #define TMS570_DMA_DREQASI_CH0ASI(val) BSP_FLD32(val,24, 29)
 #define TMS570_DMA_DREQASI_CH0ASI_GET(reg) BSP_FLD32GET(reg,24, 29)
@@ -262,7 +256,7 @@ typedef struct{
 #define TMS570_DMA_DREQASI_CH3ASI_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
 
 
-/*-----------------------TMS570_DMAPAR0-----------------------*/
+/*----------------------TMS570_DMA_PAR0----------------------*/
 /* field: CH0PA - These bit fields determine to which port channel 0 is assigned. */
 #define TMS570_DMA_PAR0_CH0PA(val) BSP_FLD32(val,28, 30)
 #define TMS570_DMA_PAR0_CH0PA_GET(reg) BSP_FLD32GET(reg,28, 30)
@@ -304,7 +298,7 @@ typedef struct{
 #define TMS570_DMA_PAR0_CH7PA_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
 
 
-/*-----------------------TMS570_DMAPAR1-----------------------*/
+/*----------------------TMS570_DMA_PAR1----------------------*/
 /* field: CH8PA - These bit fields determine to which port channel 8 is assigned. */
 #define TMS570_DMA_PAR1_CH8PA(val) BSP_FLD32(val,28, 30)
 #define TMS570_DMA_PAR1_CH8PA_GET(reg) BSP_FLD32GET(reg,28, 30)
@@ -346,140 +340,140 @@ typedef struct{
 #define TMS570_DMA_PAR1_CH15PA_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
 
 
-/*----------------------TMS570_DMAFTCMAP----------------------*/
+/*---------------------TMS570_DMA_FTCMAP---------------------*/
 /* field: FTCAB - Frame transfer complete (FTC) interrupt to Group A or Group B. */
 #define TMS570_DMA_FTCMAP_FTCAB(val) BSP_FLD32(val,0, 15)
 #define TMS570_DMA_FTCMAP_FTCAB_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_DMA_FTCMAP_FTCAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*----------------------TMS570_DMALFSMAP----------------------*/
+/*---------------------TMS570_DMA_LFSMAP---------------------*/
 /* field: LFSAB - Last frame started (LFS) interrupt to Group A or Group B. */
 #define TMS570_DMA_LFSMAP_LFSAB(val) BSP_FLD32(val,0, 15)
 #define TMS570_DMA_LFSMAP_LFSAB_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_DMA_LFSMAP_LFSAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*----------------------TMS570_DMAHBCMAP----------------------*/
+/*---------------------TMS570_DMA_HBCMAP---------------------*/
 /* field: HBCAB - Half block complete (HBC) interrupt to Group A or Group B. */
 #define TMS570_DMA_HBCMAP_HBCAB(val) BSP_FLD32(val,0, 15)
 #define TMS570_DMA_HBCMAP_HBCAB_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_DMA_HBCMAP_HBCAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*----------------------TMS570_DMABTCMAP----------------------*/
+/*---------------------TMS570_DMA_BTCMAP---------------------*/
 /* field: BTCAB - Block transfer complete (BTC) interrupt to Group A or Group B */
 #define TMS570_DMA_BTCMAP_BTCAB(val) BSP_FLD32(val,0, 15)
 #define TMS570_DMA_BTCMAP_BTCAB_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_DMA_BTCMAP_BTCAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*----------------------TMS570_DMABERMAP----------------------*/
+/*---------------------TMS570_DMA_BERMAP---------------------*/
 /* field: BERAB - Bus error (BER) interrupt to Group A or Group B. */
 #define TMS570_DMA_BERMAP_BERAB(val) BSP_FLD32(val,0, 15)
 #define TMS570_DMA_BERMAP_BERAB_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_DMA_BERMAP_BERAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*--------------------TMS570_DMAFTCINTENAS--------------------*/
+/*-------------------TMS570_DMA_FTCINTENAS-------------------*/
 /* field: FTCINTENA - Frame transfer complete (FTC) interrupt enable. */
 #define TMS570_DMA_FTCINTENAS_FTCINTENA(val) BSP_FLD32(val,0, 15)
 #define TMS570_DMA_FTCINTENAS_FTCINTENA_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_DMA_FTCINTENAS_FTCINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*--------------------TMS570_DMAFTCINTENAR--------------------*/
+/*-------------------TMS570_DMA_FTCINTENAR-------------------*/
 /* field: FTCINTDIS - Frame transfer complete (FTC) interrupt disable. */
 #define TMS570_DMA_FTCINTENAR_FTCINTDIS(val) BSP_FLD32(val,0, 15)
 #define TMS570_DMA_FTCINTENAR_FTCINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_DMA_FTCINTENAR_FTCINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*--------------------TMS570_DMALFSINTENAS--------------------*/
+/*-------------------TMS570_DMA_LFSINTENAS-------------------*/
 /* field: LFSINTENA - Last frame started (LFS) interrupt enable. */
 #define TMS570_DMA_LFSINTENAS_LFSINTENA(val) BSP_FLD32(val,0, 15)
 #define TMS570_DMA_LFSINTENAS_LFSINTENA_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_DMA_LFSINTENAS_LFSINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*--------------------TMS570_DMALFSINTENAR--------------------*/
+/*-------------------TMS570_DMA_LFSINTENAR-------------------*/
 /* field: LFSINTDIS - Last frame started (LFS) interrupt disable. */
 #define TMS570_DMA_LFSINTENAR_LFSINTDIS(val) BSP_FLD32(val,0, 15)
 #define TMS570_DMA_LFSINTENAR_LFSINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_DMA_LFSINTENAR_LFSINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*--------------------TMS570_DMAHBCINTENAS--------------------*/
+/*-------------------TMS570_DMA_HBCINTENAS-------------------*/
 /* field: HBCINTENA - Half block complete (HBC) interrupt enable. */
 #define TMS570_DMA_HBCINTENAS_HBCINTENA(val) BSP_FLD32(val,0, 15)
 #define TMS570_DMA_HBCINTENAS_HBCINTENA_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_DMA_HBCINTENAS_HBCINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*--------------------TMS570_DMAHBCINTENAR--------------------*/
+/*-------------------TMS570_DMA_HBCINTENAR-------------------*/
 /* field: HBCINTDIS - Half block complete (HBC) interrupt disable. */
 #define TMS570_DMA_HBCINTENAR_HBCINTDIS(val) BSP_FLD32(val,0, 15)
 #define TMS570_DMA_HBCINTENAR_HBCINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_DMA_HBCINTENAR_HBCINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*--------------------TMS570_DMABTCINTENAS--------------------*/
+/*-------------------TMS570_DMA_BTCINTENAS-------------------*/
 /* field: BTCINTENA - Block transfer complete (BTC) interrupt enable. */
 #define TMS570_DMA_BTCINTENAS_BTCINTENA(val) BSP_FLD32(val,0, 15)
 #define TMS570_DMA_BTCINTENAS_BTCINTENA_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_DMA_BTCINTENAS_BTCINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*--------------------TMS570_DMABTCINTENAR--------------------*/
+/*-------------------TMS570_DMA_BTCINTENAR-------------------*/
 /* field: BTCINTDIS - Block transfer complete (BTC) interurpt disable. */
 #define TMS570_DMA_BTCINTENAR_BTCINTDIS(val) BSP_FLD32(val,0, 15)
 #define TMS570_DMA_BTCINTENAR_BTCINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_DMA_BTCINTENAR_BTCINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_DMAGINTFLAG---------------------*/
+/*--------------------TMS570_DMA_GINTFLAG--------------------*/
 /* field: GINT - Global interrupt flags. */
 #define TMS570_DMA_GINTFLAG_GINT(val) BSP_FLD32(val,0, 15)
 #define TMS570_DMA_GINTFLAG_GINT_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_DMA_GINTFLAG_GINT_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_DMAFTCFLAG---------------------*/
+/*---------------------TMS570_DMA_FTCFLAG---------------------*/
 /* field: FTCI - Frame transfer complete (FTC) flags. */
 #define TMS570_DMA_FTCFLAG_FTCI(val) BSP_FLD32(val,0, 15)
 #define TMS570_DMA_FTCFLAG_FTCI_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_DMA_FTCFLAG_FTCI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_DMALFSFLAG---------------------*/
+/*---------------------TMS570_DMA_LFSFLAG---------------------*/
 /* field: LFSI - Last frame started (LFS) flags. */
 #define TMS570_DMA_LFSFLAG_LFSI(val) BSP_FLD32(val,0, 15)
 #define TMS570_DMA_LFSFLAG_LFSI_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_DMA_LFSFLAG_LFSI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_DMAHBCFLAG---------------------*/
+/*---------------------TMS570_DMA_HBCFLAG---------------------*/
 /* field: HBCI - Half block transfer (HBC) complete flags. */
 #define TMS570_DMA_HBCFLAG_HBCI(val) BSP_FLD32(val,0, 15)
 #define TMS570_DMA_HBCFLAG_HBCI_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_DMA_HBCFLAG_HBCI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_DMABTCFLAG---------------------*/
+/*---------------------TMS570_DMA_BTCFLAG---------------------*/
 /* field: BTCI - Block transfer complete (BTC) flags. */
 #define TMS570_DMA_BTCFLAG_BTCI(val) BSP_FLD32(val,0, 15)
 #define TMS570_DMA_BTCFLAG_BTCI_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_DMA_BTCFLAG_BTCI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_DMABERFLAG---------------------*/
+/*---------------------TMS570_DMA_BERFLAG---------------------*/
 /* field: BERI - Bus error (BER) flags. */
 #define TMS570_DMA_BERFLAG_BERI(val) BSP_FLD32(val,0, 15)
 #define TMS570_DMA_BERFLAG_BERI_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_DMA_BERFLAG_BERI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*--------------------TMS570_DMAFTCAOFFSET--------------------*/
+/*-------------------TMS570_DMA_FTCAOFFSET-------------------*/
 /* field: sbz - These bits should always be programmed as zero. */
 #define TMS570_DMA_FTCAOFFSET_sbz(val) BSP_FLD32(val,6, 7)
 #define TMS570_DMA_FTCAOFFSET_sbz_GET(reg) BSP_FLD32GET(reg,6, 7)
@@ -491,130 +485,118 @@ typedef struct{
 #define TMS570_DMA_FTCAOFFSET_FTCA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
 
 
-/*--------------------TMS570_DMALFSAOFFSET--------------------*/
+/*-------------------TMS570_DMA_LFSAOFFSET-------------------*/
 /* field: LFSA - Channel causing LFS interrupt Group A. */
 #define TMS570_DMA_LFSAOFFSET_LFSA(val) BSP_FLD32(val,0, 5)
 #define TMS570_DMA_LFSAOFFSET_LFSA_GET(reg) BSP_FLD32GET(reg,0, 5)
 #define TMS570_DMA_LFSAOFFSET_LFSA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
 
 
-/*--------------------TMS570_DMAHBCAOFFSET--------------------*/
+/*-------------------TMS570_DMA_HBCAOFFSET-------------------*/
 /* field: HBCA - Channel causing HBC interrupt Group A. */
 #define TMS570_DMA_HBCAOFFSET_HBCA(val) BSP_FLD32(val,0, 5)
 #define TMS570_DMA_HBCAOFFSET_HBCA_GET(reg) BSP_FLD32GET(reg,0, 5)
 #define TMS570_DMA_HBCAOFFSET_HBCA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
 
 
-/*--------------------TMS570_DMABTCAOFFSET--------------------*/
+/*-------------------TMS570_DMA_BTCAOFFSET-------------------*/
 /* field: BTCA - Channel causing BTC interrupt Group A. */
 #define TMS570_DMA_BTCAOFFSET_BTCA(val) BSP_FLD32(val,0, 5)
 #define TMS570_DMA_BTCAOFFSET_BTCA_GET(reg) BSP_FLD32GET(reg,0, 5)
 #define TMS570_DMA_BTCAOFFSET_BTCA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
 
 
-/*--------------------TMS570_DMABERAOFFSET--------------------*/
+/*-------------------TMS570_DMA_BERAOFFSET-------------------*/
 /* field: BERA - Channel causing BER interrupt Group A. */
 #define TMS570_DMA_BERAOFFSET_BERA(val) BSP_FLD32(val,0, 5)
 #define TMS570_DMA_BERAOFFSET_BERA_GET(reg) BSP_FLD32GET(reg,0, 5)
 #define TMS570_DMA_BERAOFFSET_BERA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
 
 
-/*--------------------TMS570_DMAFTCBOFFSET--------------------*/
+/*-------------------TMS570_DMA_FTCBOFFSET-------------------*/
 /* field: FTCB - Channel causing FTC interrupt Group B. */
 #define TMS570_DMA_FTCBOFFSET_FTCB(val) BSP_FLD32(val,0, 5)
 #define TMS570_DMA_FTCBOFFSET_FTCB_GET(reg) BSP_FLD32GET(reg,0, 5)
 #define TMS570_DMA_FTCBOFFSET_FTCB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
 
 
-/*--------------------TMS570_DMALFSBOFFSET--------------------*/
+/*-------------------TMS570_DMA_LFSBOFFSET-------------------*/
 /* field: LFSB - Channel causing LFS interrupt Group B. */
 #define TMS570_DMA_LFSBOFFSET_LFSB(val) BSP_FLD32(val,0, 5)
 #define TMS570_DMA_LFSBOFFSET_LFSB_GET(reg) BSP_FLD32GET(reg,0, 5)
 #define TMS570_DMA_LFSBOFFSET_LFSB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
 
 
-/*--------------------TMS570_DMAHBCBOFFSET--------------------*/
+/*-------------------TMS570_DMA_HBCBOFFSET-------------------*/
 /* field: HBCB - Channel causing HBC interrupt Group B. */
 #define TMS570_DMA_HBCBOFFSET_HBCB(val) BSP_FLD32(val,0, 5)
 #define TMS570_DMA_HBCBOFFSET_HBCB_GET(reg) BSP_FLD32GET(reg,0, 5)
 #define TMS570_DMA_HBCBOFFSET_HBCB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
 
 
-/*--------------------TMS570_DMABTCBOFFSET--------------------*/
+/*-------------------TMS570_DMA_BTCBOFFSET-------------------*/
 /* field: BTCB - interrupt for Group B if the corresponding interrupt enable is set. */
 #define TMS570_DMA_BTCBOFFSET_BTCB(val) BSP_FLD32(val,0, 5)
 #define TMS570_DMA_BTCBOFFSET_BTCB_GET(reg) BSP_FLD32GET(reg,0, 5)
 #define TMS570_DMA_BTCBOFFSET_BTCB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
 
 
-/*--------------------TMS570_DMABERBOFFSET--------------------*/
+/*-------------------TMS570_DMA_BERBOFFSET-------------------*/
 /* field: BERB - Channel causing BER interrupt Group B. */
 #define TMS570_DMA_BERBOFFSET_BERB(val) BSP_FLD32(val,0, 5)
 #define TMS570_DMA_BERBOFFSET_BERB_GET(reg) BSP_FLD32GET(reg,0, 5)
 #define TMS570_DMA_BERBOFFSET_BERB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
 
 
-/*----------------------TMS570_DMAPTCRL----------------------*/
+/*----------------------TMS570_DMA_PTCRL----------------------*/
 /* field: PENDB - Transfers pending for Port B. This flag determines if transfers are ongoing on port B. */
-#define TMS570_DMA_PTCRL_PENDB BSP_FLD32(24)
+#define TMS570_DMA_PTCRL_PENDB BSP_BIT32(24)
 
 /* field: BYB - Bypass FIFO B. */
-#define TMS570_DMA_PTCRL_BYB BSP_FLD32(18)
+#define TMS570_DMA_PTCRL_BYB BSP_BIT32(18)
 
 /* field: PSFRHQPB - Priority scheme fix or rotate for high priority queue of Port B. */
-#define TMS570_DMA_PTCRL_PSFRHQPB BSP_FLD32(17)
+#define TMS570_DMA_PTCRL_PSFRHQPB BSP_BIT32(17)
 
 /* field: PSFRLQPB - Priority scheme fix or rotate for low priority queue of Port B. */
-#define TMS570_DMA_PTCRL_PSFRLQPB BSP_FLD32(16)
+#define TMS570_DMA_PTCRL_PSFRLQPB BSP_BIT32(16)
 
 
-/*----------------------TMS570_DMARTCTRL----------------------*/
+/*---------------------TMS570_DMA_RTCTRL---------------------*/
 /* field: RTC - RAM Test Control. */
-#define TMS570_DMA_RTCTRL_RTC BSP_FLD32(0)
+#define TMS570_DMA_RTCTRL_RTC BSP_BIT32(0)
 
 
-/*----------------------TMS570_DMADCTRL----------------------*/
+/*----------------------TMS570_DMA_DCTRL----------------------*/
 /* field: CHNUM - Channel Number. */
 #define TMS570_DMA_DCTRL_CHNUM(val) BSP_FLD32(val,24, 28)
 #define TMS570_DMA_DCTRL_CHNUM_GET(reg) BSP_FLD32GET(reg,24, 28)
 #define TMS570_DMA_DCTRL_CHNUM_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
 
 /* field: DMADBGS - DMA debug status. */
-#define TMS570_DMA_DCTRL_DMADBGS BSP_FLD32(16)
+#define TMS570_DMA_DCTRL_DMADBGS BSP_BIT32(16)
 
 /* field: DBGEN - Debug Enable. */
-#define TMS570_DMA_DCTRL_DBGEN BSP_FLD32(0)
+#define TMS570_DMA_DCTRL_DBGEN BSP_BIT32(0)
 
 
-/*-----------------------TMS570_DMAWPR-----------------------*/
+/*-----------------------TMS570_DMA_WPR-----------------------*/
 /* field: WP - Watch point. */
-#define TMS570_DMA_WPR_WP(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_DMA_WPR_WP_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_DMA_WPR_WP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-----------------------TMS570_DMA_WMR-----------------------*/
-/*-----------------------TMS570_DMAWMR-----------------------*/
 /* field: WM - Watch mask. */
-#define TMS570_DMA_WMR_WM(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_DMA_WMR_WM_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_DMA_WMR_WM_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*--------------------TMS570_DMA_PBACSADDR--------------------*/
-/*--------------------TMS570_DMAPBACSADDR--------------------*/
 /* field: PBACSA - Port B Active Channel Source Address. */
-#define TMS570_DMA_PBACSADDR_PBACSA(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_DMA_PBACSADDR_PBACSA_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_DMA_PBACSADDR_PBACSA_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*--------------------TMS570_DMA_PBACDADDR--------------------*/
-/*--------------------TMS570_DMAPBACDADDR--------------------*/
 /* field: PBACDA - address of the active channel as broadcasted in Section 16.3.1.3 for Port B. */
-#define TMS570_DMA_PBACDADDR_PBACDA(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_DMA_PBACDADDR_PBACDA_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_DMA_PBACDADDR_PBACDA_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*---------------------TMS570_DMA_PBACTC---------------------*/
-/*----------------------TMS570_DMAPBACTC----------------------*/
 /* field: PBFTCOUNT - Port B active channel frame count. */
 #define TMS570_DMA_PBACTC_PBFTCOUNT(val) BSP_FLD32(val,16, 28)
 #define TMS570_DMA_PBACTC_PBFTCOUNT_GET(reg) BSP_FLD32GET(reg,16, 28)
@@ -626,12 +608,12 @@ typedef struct{
 #define TMS570_DMA_PBACTC_PBETCOUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 12)
 
 
-/*----------------------TMS570_DMADMAPCR----------------------*/
+/*---------------------TMS570_DMA_DMAPCR---------------------*/
 /* field: ERRA - Error action. */
-#define TMS570_DMA_DMAPCR_ERRA BSP_FLD32(16)
+#define TMS570_DMA_DMAPCR_ERRA BSP_BIT32(16)
 
 /* field: TEST - When this bit is set, the parity bits are memory mapped to make them accessible by the CPU. */
-#define TMS570_DMA_DMAPCR_TEST BSP_FLD32(8)
+#define TMS570_DMA_DMAPCR_TEST BSP_BIT32(8)
 
 /* field: PARITY_ENA - Parity error detection enable. */
 #define TMS570_DMA_DMAPCR_PARITY_ENA(val) BSP_FLD32(val,0, 3)
@@ -639,9 +621,9 @@ typedef struct{
 #define TMS570_DMA_DMAPCR_PARITY_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*----------------------TMS570_DMADMAPAR----------------------*/
+/*---------------------TMS570_DMA_DMAPAR---------------------*/
 /* field: EDFLAG - Parity Error Detection Flag. */
-#define TMS570_DMA_DMAPAR_EDFLAG BSP_FLD32(24)
+#define TMS570_DMA_DMAPAR_EDFLAG BSP_BIT32(24)
 
 /* field: ERRORADDRESS - Error address. These bits hold the address of the first parity error generated in the RAM. */
 #define TMS570_DMA_DMAPAR_ERRORADDRESS(val) BSP_FLD32(val,0, 11)
@@ -649,12 +631,12 @@ typedef struct{
 #define TMS570_DMA_DMAPAR_ERRORADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
 
 
-/*--------------------TMS570_DMADMAMPCTRL--------------------*/
+/*--------------------TMS570_DMA_DMAMPCTRL--------------------*/
 /* field: INT3AB - Interrupt assignment of region 3 to Group A or Group B. */
-#define TMS570_DMA_DMAMPCTRL_INT3AB BSP_FLD32(28)
+#define TMS570_DMA_DMAMPCTRL_INT3AB BSP_BIT32(28)
 
 /* field: INT3ENA - Interrupt enable of region 3. */
-#define TMS570_DMA_DMAMPCTRL_INT3ENA BSP_FLD32(27)
+#define TMS570_DMA_DMAMPCTRL_INT3ENA BSP_BIT32(27)
 
 /* field: REG3AP - Region 3 access permission. */
 #define TMS570_DMA_DMAMPCTRL_REG3AP(val) BSP_FLD32(val,25, 26)
@@ -662,13 +644,13 @@ typedef struct{
 #define TMS570_DMA_DMAMPCTRL_REG3AP_SET(reg,val) BSP_FLD32SET(reg, val,25, 26)
 
 /* field: REG3ENA - Region 3 enable. */
-#define TMS570_DMA_DMAMPCTRL_REG3ENA BSP_FLD32(24)
+#define TMS570_DMA_DMAMPCTRL_REG3ENA BSP_BIT32(24)
 
 /* field: INT2AB - Interrupt assignment of region 2 to Group A or Group B. */
-#define TMS570_DMA_DMAMPCTRL_INT2AB BSP_FLD32(20)
+#define TMS570_DMA_DMAMPCTRL_INT2AB BSP_BIT32(20)
 
 /* field: INT2ENA - Interrupt enable of region 2. */
-#define TMS570_DMA_DMAMPCTRL_INT2ENA BSP_FLD32(19)
+#define TMS570_DMA_DMAMPCTRL_INT2ENA BSP_BIT32(19)
 
 /* field: REG2AP - Region 2 access permission. These bits determine the access permission for region 2. */
 #define TMS570_DMA_DMAMPCTRL_REG2AP(val) BSP_FLD32(val,17, 18)
@@ -676,13 +658,13 @@ typedef struct{
 #define TMS570_DMA_DMAMPCTRL_REG2AP_SET(reg,val) BSP_FLD32SET(reg, val,17, 18)
 
 /* field: REG2ENA - Region 2 enable. */
-#define TMS570_DMA_DMAMPCTRL_REG2ENA BSP_FLD32(16)
+#define TMS570_DMA_DMAMPCTRL_REG2ENA BSP_BIT32(16)
 
 /* field: INT1AB - Interrupt assignment of region 1 to Group A or Group B. */
-#define TMS570_DMA_DMAMPCTRL_INT1AB BSP_FLD32(12)
+#define TMS570_DMA_DMAMPCTRL_INT1AB BSP_BIT32(12)
 
 /* field: INT1ENA - Interrupt enable of region 1. */
-#define TMS570_DMA_DMAMPCTRL_INT1ENA BSP_FLD32(11)
+#define TMS570_DMA_DMAMPCTRL_INT1ENA BSP_BIT32(11)
 
 /* field: REG1AP - Region 1 access permission. */
 #define TMS570_DMA_DMAMPCTRL_REG1AP(val) BSP_FLD32(val,9, 10)
@@ -690,13 +672,13 @@ typedef struct{
 #define TMS570_DMA_DMAMPCTRL_REG1AP_SET(reg,val) BSP_FLD32SET(reg, val,9, 10)
 
 /* field: REG1ENA - Region 1 enable. */
-#define TMS570_DMA_DMAMPCTRL_REG1ENA BSP_FLD32(8)
+#define TMS570_DMA_DMAMPCTRL_REG1ENA BSP_BIT32(8)
 
 /* field: INT0AB - Interrupt assignment of region 0 to Group A or Group B. */
-#define TMS570_DMA_DMAMPCTRL_INT0AB BSP_FLD32(4)
+#define TMS570_DMA_DMAMPCTRL_INT0AB BSP_BIT32(4)
 
 /* field: INT0ENA - Interrupt enable of region 0. */
-#define TMS570_DMA_DMAMPCTRL_INT0ENA BSP_FLD32(3)
+#define TMS570_DMA_DMAMPCTRL_INT0ENA BSP_BIT32(3)
 
 /* field: REG0AP - Region 0 access permission. These bits determine the access permission for region 0. */
 #define TMS570_DMA_DMAMPCTRL_REG0AP(val) BSP_FLD32(val,1, 2)
@@ -704,29 +686,26 @@ typedef struct{
 #define TMS570_DMA_DMAMPCTRL_REG0AP_SET(reg,val) BSP_FLD32SET(reg, val,1, 2)
 
 /* field: REG0ENA - Region 0 enable. */
-#define TMS570_DMA_DMAMPCTRL_REG0ENA BSP_FLD32(0)
+#define TMS570_DMA_DMAMPCTRL_REG0ENA BSP_BIT32(0)
 
 
-/*---------------------TMS570_DMADMAMPST---------------------*/
+/*---------------------TMS570_DMA_DMAMPST---------------------*/
 /* field: REG3FT - Region 3 fault. */
-#define TMS570_DMA_DMAMPST_REG3FT BSP_FLD32(24)
+#define TMS570_DMA_DMAMPST_REG3FT BSP_BIT32(24)
 
 /* field: REG2FT - Region 2 fault. */
-#define TMS570_DMA_DMAMPST_REG2FT BSP_FLD32(16)
+#define TMS570_DMA_DMAMPST_REG2FT BSP_BIT32(16)
 
 /* field: REG1FT - Region 1 fault. */
-#define TMS570_DMA_DMAMPST_REG1FT BSP_FLD32(8)
+#define TMS570_DMA_DMAMPST_REG1FT BSP_BIT32(8)
 
 /* field: REG0FT - Region 0 fault. */
-#define TMS570_DMA_DMAMPST_REG0FT BSP_FLD32(0)
+#define TMS570_DMA_DMAMPST_REG0FT BSP_BIT32(0)
 
 
-/*---------------------TMS570_DMADMAMPROS---------------------*/
+/*--------------------TMS570_DMA_DMAMPROS--------------------*/
 /* field: STARTADDRESS - Start Address defines the address at which the region begins. */
-#define TMS570_DMA_DMAMPROS_STARTADDRESS(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_DMA_DMAMPROS_STARTADDRESS_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_DMA_DMAMPROS_STARTADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
 
-
+#endif /* LIBBSP_ARM_TMS570_DMA */
-#endif /* LIBBSP_ARM_tms570_DMA */

c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dmm.h

@@ -36,8 +36,8 @@
  * of the authors and should not be interpreted as representing official policies,
  * either expressed or implied, of the FreeBSD Project.
 */
-#ifndef LIBBSP_ARM_tms570_DMM
+#ifndef LIBBSP_ARM_TMS570_DMM
-#define LIBBSP_ARM_tms570_DMM
+#define LIBBSP_ARM_TMS570_DMM
 
 #include <bsp/utility.h>
 
@@ -81,18 +81,18 @@ typedef struct{
 } tms570_dmm_t;
 
 
-/*---------------------TMS570_DMMGLBCTRL---------------------*/
+/*---------------------TMS570_DMM_GLBCTRL---------------------*/
 /* field: BUSY - Busy indicator. */
-#define TMS570_DMM_GLBCTRL_BUSY BSP_FLD32(24)
+#define TMS570_DMM_GLBCTRL_BUSY BSP_BIT32(24)
 
 /* field: CONTCLK - Continuous DMMCLK input. */
-#define TMS570_DMM_GLBCTRL_CONTCLK BSP_FLD32(18)
+#define TMS570_DMM_GLBCTRL_CONTCLK BSP_BIT32(18)
 
 /* field: COS - Continue on suspend. Influences behavior of module while in debug mode. */
-#define TMS570_DMM_GLBCTRL_COS BSP_FLD32(17)
+#define TMS570_DMM_GLBCTRL_COS BSP_BIT32(17)
 
 /* field: RESET - Reset. */
-#define TMS570_DMM_GLBCTRL_RESET BSP_FLD32(16)
+#define TMS570_DMM_GLBCTRL_RESET BSP_BIT32(16)
 
 /* field: DDM_WIDTH - Packet Width in direct data mode. */
 #define TMS570_DMM_GLBCTRL_DDM_WIDTH(val) BSP_FLD32(val,9, 10)
@@ -100,7 +100,7 @@ typedef struct{
 #define TMS570_DMM_GLBCTRL_DDM_WIDTH_SET(reg,val) BSP_FLD32SET(reg, val,9, 10)
 
 /* field: TM_DMM - Packet Format. */
-#define TMS570_DMM_GLBCTRL_TM_DMM BSP_FLD32(8)
+#define TMS570_DMM_GLBCTRL_TM_DMM BSP_BIT32(8)
 
 /* field: ON_OFF - Switch module on or off */
 #define TMS570_DMM_GLBCTRL_ON_OFF(val) BSP_FLD32(val,0, 3)
@@ -108,313 +108,310 @@ typedef struct{
 #define TMS570_DMM_GLBCTRL_ON_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*----------------------TMS570_DMMINTSET----------------------*/
+/*---------------------TMS570_DMM_INTSET---------------------*/
 /* field: PROG_BUFF - Programmable Buffer Interrupt Set. */
-#define TMS570_DMM_INTSET_PROG_BUFF BSP_FLD32(17)
+#define TMS570_DMM_INTSET_PROG_BUFF BSP_BIT32(17)
 
 /* field: EO_BUFF - EO_BUFF */
-#define TMS570_DMM_INTSET_EO_BUFF BSP_FLD32(16)
+#define TMS570_DMM_INTSET_EO_BUFF BSP_BIT32(16)
 
 /* field: DEST3REG2 - Destination 3 Region 2 Interrupt Set. */
-#define TMS570_DMM_INTSET_DEST3REG2 BSP_FLD32(15)
+#define TMS570_DMM_INTSET_DEST3REG2 BSP_BIT32(15)
 
 /* field: DEST3REG1 - Destination 3 Region 1 Interrupt Set. */
-#define TMS570_DMM_INTSET_DEST3REG1 BSP_FLD32(14)
+#define TMS570_DMM_INTSET_DEST3REG1 BSP_BIT32(14)
 
 /* field: DEST2REG2 - Destination 2 Region 2 Interrupt Set. */
-#define TMS570_DMM_INTSET_DEST2REG2 BSP_FLD32(13)
+#define TMS570_DMM_INTSET_DEST2REG2 BSP_BIT32(13)
 
 /* field: DEST2REG1 - Destination 2 Region 1 Interrupt Set. */
-#define TMS570_DMM_INTSET_DEST2REG1 BSP_FLD32(12)
+#define TMS570_DMM_INTSET_DEST2REG1 BSP_BIT32(12)
 
 /* field: DEST1REG2 - Destination 1 Region 2 Interrupt Set. */
-#define TMS570_DMM_INTSET_DEST1REG2 BSP_FLD32(11)
+#define TMS570_DMM_INTSET_DEST1REG2 BSP_BIT32(11)
 
 /* field: DEST1REG1 - DEST1REG1 */
-#define TMS570_DMM_INTSET_DEST1REG1 BSP_FLD32(10)
+#define TMS570_DMM_INTSET_DEST1REG1 BSP_BIT32(10)
 
 /* field: DEST0REG2 - Destination 0 Region 2 Interrupt Set. */
-#define TMS570_DMM_INTSET_DEST0REG2 BSP_FLD32(9)
+#define TMS570_DMM_INTSET_DEST0REG2 BSP_BIT32(9)
 
 /* field: DEST0REG1 - Destination 0 Region 1 Interrupt Set. */
-#define TMS570_DMM_INTSET_DEST0REG1 BSP_FLD32(8)
+#define TMS570_DMM_INTSET_DEST0REG1 BSP_BIT32(8)
 
 /* field: BUSERROR - Bus Error Response for errors generated when doing internal bus transfers. */
-#define TMS570_DMM_INTSET_BUSERROR BSP_FLD32(7)
+#define TMS570_DMM_INTSET_BUSERROR BSP_BIT32(7)
 
 /* field: BUFF_OVF - Buffer Overflow. */
-#define TMS570_DMM_INTSET_BUFF_OVF BSP_FLD32(6)
+#define TMS570_DMM_INTSET_BUFF_OVF BSP_BIT32(6)
 
 /* field: SRC_OVF - Source Overflow. */
-#define TMS570_DMM_INTSET_SRC_OVF BSP_FLD32(5)
+#define TMS570_DMM_INTSET_SRC_OVF BSP_BIT32(5)
 
 /* field: DEST3_ERR - Destination 3 Error. */
-#define TMS570_DMM_INTSET_DEST3_ERR BSP_FLD32(4)
+#define TMS570_DMM_INTSET_DEST3_ERR BSP_BIT32(4)
 
 /* field: DEST2_ERR - Destination 2 Error Interrupt Set. */
-#define TMS570_DMM_INTSET_DEST2_ERR BSP_FLD32(3)
+#define TMS570_DMM_INTSET_DEST2_ERR BSP_BIT32(3)
 
 /* field: DEST1_ERR - Destination 1 Error Interrupt Set. */
-#define TMS570_DMM_INTSET_DEST1_ERR BSP_FLD32(2)
+#define TMS570_DMM_INTSET_DEST1_ERR BSP_BIT32(2)
 
 /* field: DEST0_ERR - Destination 0 Error Interrupt Set. */
-#define TMS570_DMM_INTSET_DEST0_ERR BSP_FLD32(1)
+#define TMS570_DMM_INTSET_DEST0_ERR BSP_BIT32(1)
 
 /* field: PACKET_ERR_INT - Packet Error. */
-#define TMS570_DMM_INTSET_PACKET_ERR_INT BSP_FLD32(0)
+#define TMS570_DMM_INTSET_PACKET_ERR_INT BSP_BIT32(0)
 
 
-/*----------------------TMS570_DMMINTCLR----------------------*/
+/*---------------------TMS570_DMM_INTCLR---------------------*/
 /* field: PROG_BUFF - Programmable Buffer Interrupt Set. */
-#define TMS570_DMM_INTCLR_PROG_BUFF BSP_FLD32(17)
+#define TMS570_DMM_INTCLR_PROG_BUFF BSP_BIT32(17)
 
 /* field: EO_BUFF - End of Buffer Interrupt Set. */
-#define TMS570_DMM_INTCLR_EO_BUFF BSP_FLD32(16)
+#define TMS570_DMM_INTCLR_EO_BUFF BSP_BIT32(16)
 
 /* field: DEST3REG2 - was accessed at the startaddress of Destination 3 Region 2. */
-#define TMS570_DMM_INTCLR_DEST3REG2 BSP_FLD32(15)
+#define TMS570_DMM_INTCLR_DEST3REG2 BSP_BIT32(15)
 
 /* field: DEST3REG1 - Destination 3 Region 1 Interrupt Set. */
-#define TMS570_DMM_INTCLR_DEST3REG1 BSP_FLD32(14)
+#define TMS570_DMM_INTCLR_DEST3REG1 BSP_BIT32(14)
 
 /* field: DEST2REG2 - Destination 2 Region 2 Interrupt Set. */
-#define TMS570_DMM_INTCLR_DEST2REG2 BSP_FLD32(13)
+#define TMS570_DMM_INTCLR_DEST2REG2 BSP_BIT32(13)
 
 /* field: DEST2REG1 - Destination 2 Region 1 Interrupt Set. */
-#define TMS570_DMM_INTCLR_DEST2REG1 BSP_FLD32(12)
+#define TMS570_DMM_INTCLR_DEST2REG1 BSP_BIT32(12)
 
 /* field: DEST1REG2 - Destination 1 Region 2 Interrupt Set. */
-#define TMS570_DMM_INTCLR_DEST1REG2 BSP_FLD32(11)
+#define TMS570_DMM_INTCLR_DEST1REG2 BSP_BIT32(11)
 
 /* field: DEST1REG1 - Destination 1 Region 1 Interrupt Set. */
-#define TMS570_DMM_INTCLR_DEST1REG1 BSP_FLD32(10)
+#define TMS570_DMM_INTCLR_DEST1REG1 BSP_BIT32(10)
 
 /* field: DEST0REG2 - Destination 0 Region 2 Interrupt Set. */
-#define TMS570_DMM_INTCLR_DEST0REG2 BSP_FLD32(9)
+#define TMS570_DMM_INTCLR_DEST0REG2 BSP_BIT32(9)
 
 /* field: DEST0REG1 - Destination 0 Region 1 Interrupt Set. */
-#define TMS570_DMM_INTCLR_DEST0REG1 BSP_FLD32(8)
+#define TMS570_DMM_INTCLR_DEST0REG1 BSP_BIT32(8)
 
 /* field: BUSERROR - Bus Error Response for errors generated when doing internal bus transfers. */
-#define TMS570_DMM_INTCLR_BUSERROR BSP_FLD32(7)
+#define TMS570_DMM_INTCLR_BUSERROR BSP_BIT32(7)
 
 /* field: BUFF_OVF - Buffer Overflow. */
-#define TMS570_DMM_INTCLR_BUFF_OVF BSP_FLD32(6)
+#define TMS570_DMM_INTCLR_BUFF_OVF BSP_BIT32(6)
 
 /* field: SRC_OVF - Source Overflow. */
-#define TMS570_DMM_INTCLR_SRC_OVF BSP_FLD32(5)
+#define TMS570_DMM_INTCLR_SRC_OVF BSP_BIT32(5)
 
 /* field: DEST3_ERR - Destination 3 Error. */
-#define TMS570_DMM_INTCLR_DEST3_ERR BSP_FLD32(4)
+#define TMS570_DMM_INTCLR_DEST3_ERR BSP_BIT32(4)
 
 /* field: DEST2_ERR - Destination 2 Error Interrupt Set. */
-#define TMS570_DMM_INTCLR_DEST2_ERR BSP_FLD32(3)
+#define TMS570_DMM_INTCLR_DEST2_ERR BSP_BIT32(3)
 
 /* field: DEST1_ERR - Destination 1 Error Interrupt Set. */
-#define TMS570_DMM_INTCLR_DEST1_ERR BSP_FLD32(2)
+#define TMS570_DMM_INTCLR_DEST1_ERR BSP_BIT32(2)
 
 /* field: DEST0_ERR - Destination 0 Error Interrupt Set. */
-#define TMS570_DMM_INTCLR_DEST0_ERR BSP_FLD32(1)
+#define TMS570_DMM_INTCLR_DEST0_ERR BSP_BIT32(1)
 
 /* field: PACKET_ERR_INT - Packet Error. */
-#define TMS570_DMM_INTCLR_PACKET_ERR_INT BSP_FLD32(0)
+#define TMS570_DMM_INTCLR_PACKET_ERR_INT BSP_BIT32(0)
 
 
-/*----------------------TMS570_DMMINTLVL----------------------*/
+/*---------------------TMS570_DMM_INTLVL---------------------*/
 /* field: PROG_BUFF - Programmable Buffer Interrupt Level */
-#define TMS570_DMM_INTLVL_PROG_BUFF BSP_FLD32(17)
+#define TMS570_DMM_INTLVL_PROG_BUFF BSP_BIT32(17)
 
 /* field: EO_BUFF - End of Buffer Interrupt Level */
-#define TMS570_DMM_INTLVL_EO_BUFF BSP_FLD32(16)
+#define TMS570_DMM_INTLVL_EO_BUFF BSP_BIT32(16)
 
 /* field: DEST3REG2 - Destination 3 Region 2 Interrupt Level */
-#define TMS570_DMM_INTLVL_DEST3REG2 BSP_FLD32(15)
+#define TMS570_DMM_INTLVL_DEST3REG2 BSP_BIT32(15)
 
 /* field: DEST3REG1 - Destination 3 Region 1 Interrupt Level */
-#define TMS570_DMM_INTLVL_DEST3REG1 BSP_FLD32(14)
+#define TMS570_DMM_INTLVL_DEST3REG1 BSP_BIT32(14)
 
 /* field: DEST2REG2 - Destination 2 Region 2 Interrupt Level */
-#define TMS570_DMM_INTLVL_DEST2REG2 BSP_FLD32(13)
+#define TMS570_DMM_INTLVL_DEST2REG2 BSP_BIT32(13)
 
 /* field: DEST2REG1 - Destination 2 Region 1 Interrupt Level */
-#define TMS570_DMM_INTLVL_DEST2REG1 BSP_FLD32(12)
+#define TMS570_DMM_INTLVL_DEST2REG1 BSP_BIT32(12)
 
 /* field: DEST1REG2 - Destination 1 Region 2 Interrupt Level */
-#define TMS570_DMM_INTLVL_DEST1REG2 BSP_FLD32(11)
+#define TMS570_DMM_INTLVL_DEST1REG2 BSP_BIT32(11)
 
 /* field: DEST1REG1 - Destination 1 Region 1 Interrupt Level */
-#define TMS570_DMM_INTLVL_DEST1REG1 BSP_FLD32(10)
+#define TMS570_DMM_INTLVL_DEST1REG1 BSP_BIT32(10)
 
 /* field: DEST0REG2 - Destination 0 Region 2 Interrupt Level */
-#define TMS570_DMM_INTLVL_DEST0REG2 BSP_FLD32(9)
+#define TMS570_DMM_INTLVL_DEST0REG2 BSP_BIT32(9)
 
 /* field: DEST0REG1 - Destination 0 Region 1 Interrupt Level */
-#define TMS570_DMM_INTLVL_DEST0REG1 BSP_FLD32(8)
+#define TMS570_DMM_INTLVL_DEST0REG1 BSP_BIT32(8)
 
 /* field: BUSERROR - BMM Bus Error Response */
-#define TMS570_DMM_INTLVL_BUSERROR BSP_FLD32(7)
+#define TMS570_DMM_INTLVL_BUSERROR BSP_BIT32(7)
 
 /* field: BUFF_OVF - Write Buffer Overflow Interrupt Level */
-#define TMS570_DMM_INTLVL_BUFF_OVF BSP_FLD32(6)
+#define TMS570_DMM_INTLVL_BUFF_OVF BSP_BIT32(6)
 
 /* field: SRC_OVF - Source Overflow Interrupt Level */
-#define TMS570_DMM_INTLVL_SRC_OVF BSP_FLD32(5)
+#define TMS570_DMM_INTLVL_SRC_OVF BSP_BIT32(5)
 
 /* field: DEST3_ERR - Destination 3 Error Interrupt Level */
-#define TMS570_DMM_INTLVL_DEST3_ERR BSP_FLD32(4)
+#define TMS570_DMM_INTLVL_DEST3_ERR BSP_BIT32(4)
 
 /* field: DEST2_ERR - Destination 2 Error Interrupt Level */
-#define TMS570_DMM_INTLVL_DEST2_ERR BSP_FLD32(3)
+#define TMS570_DMM_INTLVL_DEST2_ERR BSP_BIT32(3)
 
 /* field: DEST1_ERR - Destination 1 Error Interrupt Level */
-#define TMS570_DMM_INTLVL_DEST1_ERR BSP_FLD32(2)
+#define TMS570_DMM_INTLVL_DEST1_ERR BSP_BIT32(2)
 
 /* field: DEST0_ERR - Destination 0 Error Interrupt Level */
-#define TMS570_DMM_INTLVL_DEST0_ERR BSP_FLD32(1)
+#define TMS570_DMM_INTLVL_DEST0_ERR BSP_BIT32(1)
 
 /* field: PACKET_ERR_INT - Packet Error Interrupt Level */
-#define TMS570_DMM_INTLVL_PACKET_ERR_INT BSP_FLD32(0)
+#define TMS570_DMM_INTLVL_PACKET_ERR_INT BSP_BIT32(0)
 
 
-/*----------------------TMS570_DMMINTFLG----------------------*/
+/*---------------------TMS570_DMM_INTFLG---------------------*/
 /* field: PROG_BUFF - Programmable Buffer Interrupt Flag */
-#define TMS570_DMM_INTFLG_PROG_BUFF BSP_FLD32(17)
+#define TMS570_DMM_INTFLG_PROG_BUFF BSP_BIT32(17)
 
 /* field: EO_BUFF - End of Buffer Interrupt Flag */
-#define TMS570_DMM_INTFLG_EO_BUFF BSP_FLD32(16)
+#define TMS570_DMM_INTFLG_EO_BUFF BSP_BIT32(16)
 
 /* field: DEST3REG2 - Destination 3 Region 2 Interrupt Flag */
-#define TMS570_DMM_INTFLG_DEST3REG2 BSP_FLD32(15)
+#define TMS570_DMM_INTFLG_DEST3REG2 BSP_BIT32(15)
 
 /* field: DEST3REG1 - Destination 3 Region 1 Interrupt Flag */
-#define TMS570_DMM_INTFLG_DEST3REG1 BSP_FLD32(14)
+#define TMS570_DMM_INTFLG_DEST3REG1 BSP_BIT32(14)
 
 /* field: DEST2REG2 - Destination 2 Region 2 Interrupt Flag */
-#define TMS570_DMM_INTFLG_DEST2REG2 BSP_FLD32(13)
+#define TMS570_DMM_INTFLG_DEST2REG2 BSP_BIT32(13)
 
 /* field: DEST2REG1 - Destination 2 Region 1 Interrupt Flag */
-#define TMS570_DMM_INTFLG_DEST2REG1 BSP_FLD32(12)
+#define TMS570_DMM_INTFLG_DEST2REG1 BSP_BIT32(12)
 
 /* field: DEST1REG2 - Destination 1 Region 2 Interrupt Flag */
-#define TMS570_DMM_INTFLG_DEST1REG2 BSP_FLD32(11)
+#define TMS570_DMM_INTFLG_DEST1REG2 BSP_BIT32(11)
 
 /* field: DEST1REG1 - Destination 1 Region 1 Interrupt Flag */
-#define TMS570_DMM_INTFLG_DEST1REG1 BSP_FLD32(10)
+#define TMS570_DMM_INTFLG_DEST1REG1 BSP_BIT32(10)
 
 /* field: DEST0REG2 - Destination 0 Region 2 Interrupt Flag */
-#define TMS570_DMM_INTFLG_DEST0REG2 BSP_FLD32(9)
+#define TMS570_DMM_INTFLG_DEST0REG2 BSP_BIT32(9)
 
 /* field: DEST0REG1 - Destination 0 Region 1 Interrupt Flag */
-#define TMS570_DMM_INTFLG_DEST0REG1 BSP_FLD32(8)
+#define TMS570_DMM_INTFLG_DEST0REG1 BSP_BIT32(8)
 
 /* field: BUSERROR - BMM Bus Error Response. */
-#define TMS570_DMM_INTFLG_BUSERROR BSP_FLD32(7)
+#define TMS570_DMM_INTFLG_BUSERROR BSP_BIT32(7)
 
 /* field: BUFF_OVF - Write Buffer Overflow Interrupt Flag */
-#define TMS570_DMM_INTFLG_BUFF_OVF BSP_FLD32(6)
+#define TMS570_DMM_INTFLG_BUFF_OVF BSP_BIT32(6)
 
 /* field: SRC_OVF - Source Overflow Interrupt Flag */
-#define TMS570_DMM_INTFLG_SRC_OVF BSP_FLD32(5)
+#define TMS570_DMM_INTFLG_SRC_OVF BSP_BIT32(5)
 
 /* field: DEST3_ERR - Destination 3 Error Interrupt Flag */
-#define TMS570_DMM_INTFLG_DEST3_ERR BSP_FLD32(4)
+#define TMS570_DMM_INTFLG_DEST3_ERR BSP_BIT32(4)
 
 /* field: DEST2_ERR - Destination 2 Error Interrupt Flag */
-#define TMS570_DMM_INTFLG_DEST2_ERR BSP_FLD32(3)
+#define TMS570_DMM_INTFLG_DEST2_ERR BSP_BIT32(3)
 
 /* field: DEST1_ERR - Destination 1 Error Interrupt Flag */
-#define TMS570_DMM_INTFLG_DEST1_ERR BSP_FLD32(2)
+#define TMS570_DMM_INTFLG_DEST1_ERR BSP_BIT32(2)
 
 /* field: DEST0_ERR - Destination 0 Error Interrupt Flag */
-#define TMS570_DMM_INTFLG_DEST0_ERR BSP_FLD32(1)
+#define TMS570_DMM_INTFLG_DEST0_ERR BSP_BIT32(1)
 
 /* field: PACKET_ERR_INT - Packet Error Interrupt Flag */
-#define TMS570_DMM_INTFLG_PACKET_ERR_INT BSP_FLD32(0)
+#define TMS570_DMM_INTFLG_PACKET_ERR_INT BSP_BIT32(0)
 
 
-/*-----------------------TMS570_DMMOFF1-----------------------*/
+/*----------------------TMS570_DMM_OFF1----------------------*/
 /* field: OFFSET - User and privilege mode (read): */
 #define TMS570_DMM_OFF1_OFFSET(val) BSP_FLD32(val,0, 4)
 #define TMS570_DMM_OFF1_OFFSET_GET(reg) BSP_FLD32GET(reg,0, 4)
 #define TMS570_DMM_OFF1_OFFSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
 
 
-/*-----------------------TMS570_DMMOFF2-----------------------*/
+/*----------------------TMS570_DMM_OFF2----------------------*/
 /* field: OFFSET - User and privilege mode (read): */
 #define TMS570_DMM_OFF2_OFFSET(val) BSP_FLD32(val,0, 4)
 #define TMS570_DMM_OFF2_OFFSET_GET(reg) BSP_FLD32GET(reg,0, 4)
 #define TMS570_DMM_OFF2_OFFSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
 
 
-/*---------------------TMS570_DMMDDMDEST---------------------*/
+/*---------------------TMS570_DMM_DDMDEST---------------------*/
 /* field: STARTADDR - These bits define the starting address of the buffer. */
-#define TMS570_DMM_DDMDEST_STARTADDR(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_DMM_DDMDEST_STARTADDR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_DMM_DDMDEST_STARTADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*----------------------TMS570_DMM_DDMBL----------------------*/
-/*----------------------TMS570_DMMDDMBL----------------------*/
 /* field: BLOCKSIZE - These bits define the size of the buffer region */
 #define TMS570_DMM_DDMBL_BLOCKSIZE(val) BSP_FLD32(val,0, 3)
 #define TMS570_DMM_DDMBL_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,0, 3)
 #define TMS570_DMM_DDMBL_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*----------------------TMS570_DMMDDMPT----------------------*/
+/*----------------------TMS570_DMM_DDMPT----------------------*/
 /* field: POINTER - These bits hold the pointer to the next entry to be written in the buffer. */
 #define TMS570_DMM_DDMPT_POINTER(val) BSP_FLD32(val,0, 14)
 #define TMS570_DMM_DDMPT_POINTER_GET(reg) BSP_FLD32GET(reg,0, 14)
 #define TMS570_DMM_DDMPT_POINTER_SET(reg,val) BSP_FLD32SET(reg, val,0, 14)
 
 
-/*----------------------TMS570_DMMINTPT----------------------*/
+/*----------------------TMS570_DMM_INTPT----------------------*/
 /* field: INTPT - Interrupt Pointer. When the buffer pointer (Section 30.3. */
 #define TMS570_DMM_INTPT_INTPT(val) BSP_FLD32(val,0, 14)
 #define TMS570_DMM_INTPT_INTPT_GET(reg) BSP_FLD32GET(reg,0, 14)
 #define TMS570_DMM_INTPT_INTPT_SET(reg,val) BSP_FLD32SET(reg, val,0, 14)
 
 
-/*--------------------TMS570_DMMDEST0REG1--------------------*/
+/*--------------------TMS570_DMM_DESTxREG1--------------------*/
 /* field: BASEADDR - These bits define the base address of the 256kB region where the buffer is located. */
-#define TMS570_DMM_DEST0REG1_BASEADDR(val) BSP_FLD32(val,18, 31)
+#define TMS570_DMM_DESTxREG1_BASEADDR(val) BSP_FLD32(val,18, 31)
-#define TMS570_DMM_DEST0REG1_BASEADDR_GET(reg) BSP_FLD32GET(reg,18, 31)
+#define TMS570_DMM_DESTxREG1_BASEADDR_GET(reg) BSP_FLD32GET(reg,18, 31)
-#define TMS570_DMM_DEST0REG1_BASEADDR_SET(reg,val) BSP_FLD32SET(reg, val,18, 31)
+#define TMS570_DMM_DESTxREG1_BASEADDR_SET(reg,val) BSP_FLD32SET(reg, val,18, 31)
 
 /* field: BLOCKADDR - These bits define the starting address of the buffer in the 256kB page. */
-#define TMS570_DMM_DEST0REG1_BLOCKADDR(val) BSP_FLD32(val,0, 17)
+#define TMS570_DMM_DESTxREG1_BLOCKADDR(val) BSP_FLD32(val,0, 17)
-#define TMS570_DMM_DEST0REG1_BLOCKADDR_GET(reg) BSP_FLD32GET(reg,0, 17)
+#define TMS570_DMM_DESTxREG1_BLOCKADDR_GET(reg) BSP_FLD32GET(reg,0, 17)
-#define TMS570_DMM_DEST0REG1_BLOCKADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 17)
+#define TMS570_DMM_DESTxREG1_BLOCKADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 17)
 
 
-/*---------------------TMS570_DMMDEST0BL1---------------------*/
+/*--------------------TMS570_DMM_DESTxBL1--------------------*/
 /* field: BLOCKSIZE - These bits define the length of the buffer region. */
-#define TMS570_DMM_DEST0BL1_BLOCKSIZE(val) BSP_FLD32(val,0, 3)
+#define TMS570_DMM_DESTxBL1_BLOCKSIZE(val) BSP_FLD32(val,0, 3)
-#define TMS570_DMM_DEST0BL1_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_DMM_DESTxBL1_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,0, 3)
-#define TMS570_DMM_DEST0BL1_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+#define TMS570_DMM_DESTxBL1_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*--------------------TMS570_DMMDEST0REG2--------------------*/
+/*--------------------TMS570_DMM_DESTxREG2--------------------*/
 /* field: BASEADDR - These bits define the base address of the 256kB region where the buffer is located. */
-#define TMS570_DMM_DEST0REG2_BASEADDR(val) BSP_FLD32(val,18, 31)
+#define TMS570_DMM_DESTxREG2_BASEADDR(val) BSP_FLD32(val,18, 31)
-#define TMS570_DMM_DEST0REG2_BASEADDR_GET(reg) BSP_FLD32GET(reg,18, 31)
+#define TMS570_DMM_DESTxREG2_BASEADDR_GET(reg) BSP_FLD32GET(reg,18, 31)
-#define TMS570_DMM_DEST0REG2_BASEADDR_SET(reg,val) BSP_FLD32SET(reg, val,18, 31)
+#define TMS570_DMM_DESTxREG2_BASEADDR_SET(reg,val) BSP_FLD32SET(reg, val,18, 31)
 
 /* field: BLOCKADDR - These bits define the starting address of the buffer in the 256kB page. */
-#define TMS570_DMM_DEST0REG2_BLOCKADDR(val) BSP_FLD32(val,0, 17)
+#define TMS570_DMM_DESTxREG2_BLOCKADDR(val) BSP_FLD32(val,0, 17)
-#define TMS570_DMM_DEST0REG2_BLOCKADDR_GET(reg) BSP_FLD32GET(reg,0, 17)
+#define TMS570_DMM_DESTxREG2_BLOCKADDR_GET(reg) BSP_FLD32GET(reg,0, 17)
-#define TMS570_DMM_DEST0REG2_BLOCKADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 17)
+#define TMS570_DMM_DESTxREG2_BLOCKADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 17)
 
 
-/*---------------------TMS570_DMMDEST0BL2---------------------*/
+/*--------------------TMS570_DMM_DESTxBL2--------------------*/
 /* field: BLOCKSIZE - These bits define the length of the buffer region. */
-#define TMS570_DMM_DEST0BL2_BLOCKSIZE(val) BSP_FLD32(val,0, 3)
+#define TMS570_DMM_DESTxBL2_BLOCKSIZE(val) BSP_FLD32(val,0, 3)
-#define TMS570_DMM_DEST0BL2_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_DMM_DESTxBL2_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,0, 3)
-#define TMS570_DMM_DEST0BL2_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+#define TMS570_DMM_DESTxBL2_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*-----------------------TMS570_DMMPC0-----------------------*/
+/*-----------------------TMS570_DMM_PC0-----------------------*/
 /* field: ENAFUNC - Functional mode of DMMENA pin. */
-#define TMS570_DMM_PC0_ENAFUNC BSP_FLD32(18)
+#define TMS570_DMM_PC0_ENAFUNC BSP_BIT32(18)
 
 /* field: DATAxFUNC - Functional mode of DMMDATA[x] pin. */
 #define TMS570_DMM_PC0_DATAxFUNC(val) BSP_FLD32(val,2, 17)
@@ -422,15 +419,15 @@ typedef struct{
 #define TMS570_DMM_PC0_DATAxFUNC_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
 
 /* field: CLKFUNC - Functional mode of DMMCLK pin. */
-#define TMS570_DMM_PC0_CLKFUNC BSP_FLD32(1)
+#define TMS570_DMM_PC0_CLKFUNC BSP_BIT32(1)
 
 /* field: SYNCFUNC - Functional mode of DMMSYNC pin. */
-#define TMS570_DMM_PC0_SYNCFUNC BSP_FLD32(0)
+#define TMS570_DMM_PC0_SYNCFUNC BSP_BIT32(0)
 
 
-/*-----------------------TMS570_DMMPC1-----------------------*/
+/*-----------------------TMS570_DMM_PC1-----------------------*/
 /* field: ENADIR - Direction of DMMENA pin. */
-#define TMS570_DMM_PC1_ENADIR BSP_FLD32(18)
+#define TMS570_DMM_PC1_ENADIR BSP_BIT32(18)
 
 /* field: DATAxDIR - Direction of DMMDATA[x] pin. */
 #define TMS570_DMM_PC1_DATAxDIR(val) BSP_FLD32(val,2, 17)
@@ -438,15 +435,15 @@ typedef struct{
 #define TMS570_DMM_PC1_DATAxDIR_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
 
 /* field: CLKDIR - Direction of DMMCLK pin. */
-#define TMS570_DMM_PC1_CLKDIR BSP_FLD32(1)
+#define TMS570_DMM_PC1_CLKDIR BSP_BIT32(1)
 
 /* field: SYNCDIR - Direction of DMMSYNC pin. */
-#define TMS570_DMM_PC1_SYNCDIR BSP_FLD32(0)
+#define TMS570_DMM_PC1_SYNCDIR BSP_BIT32(0)
 
 
-/*-----------------------TMS570_DMMPC2-----------------------*/
+/*-----------------------TMS570_DMM_PC2-----------------------*/
 /* field: ENAIN - DMMENA input. This bit reflects the state of the pin in all modes. */
-#define TMS570_DMM_PC2_ENAIN BSP_FLD32(18)
+#define TMS570_DMM_PC2_ENAIN BSP_BIT32(18)
 
 /* field: DATAxIN - DMMDATA[x] input. This bit reflects the state of the pin in all modes. */
 #define TMS570_DMM_PC2_DATAxIN(val) BSP_FLD32(val,2, 17)
@@ -454,15 +451,15 @@ typedef struct{
 #define TMS570_DMM_PC2_DATAxIN_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
 
 /* field: CLKIN - DMMCLK input. This bit reflects the state of the pin in all modes. */
-#define TMS570_DMM_PC2_CLKIN BSP_FLD32(1)
+#define TMS570_DMM_PC2_CLKIN BSP_BIT32(1)
 
 /* field: SYNCIN - DMMSYNC input. */
-#define TMS570_DMM_PC2_SYNCIN BSP_FLD32(0)
+#define TMS570_DMM_PC2_SYNCIN BSP_BIT32(0)
 
 
-/*-----------------------TMS570_DMMPC3-----------------------*/
+/*-----------------------TMS570_DMM_PC3-----------------------*/
 /* field: ENAOUT - Output state of DMMENA pin. */
-#define TMS570_DMM_PC3_ENAOUT BSP_FLD32(18)
+#define TMS570_DMM_PC3_ENAOUT BSP_BIT32(18)
 
 /* field: DATAxOUT - Output state of DMMDATA[x] pin. This bit sets the pin to logic low or high level. */
 #define TMS570_DMM_PC3_DATAxOUT(val) BSP_FLD32(val,2, 17)
@@ -470,15 +467,15 @@ typedef struct{
 #define TMS570_DMM_PC3_DATAxOUT_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
 
 /* field: CLKOUT - Output state of DMMCLK pin. */
-#define TMS570_DMM_PC3_CLKOUT BSP_FLD32(1)
+#define TMS570_DMM_PC3_CLKOUT BSP_BIT32(1)
 
 /* field: SYNCOUT - Output state of DMMSYNC pin. This bit sets the pin to logic low or high level. */
-#define TMS570_DMM_PC3_SYNCOUT BSP_FLD32(0)
+#define TMS570_DMM_PC3_SYNCOUT BSP_BIT32(0)
 
 
-/*-----------------------TMS570_DMMPC4-----------------------*/
+/*-----------------------TMS570_DMM_PC4-----------------------*/
 /* field: ENASET - control register bit to 1 regardless of the current value in the ENAOUT bit. */
-#define TMS570_DMM_PC4_ENASET BSP_FLD32(18)
+#define TMS570_DMM_PC4_ENASET BSP_BIT32(18)
 
 /* field: DATAxSET - Sets output state of DMMDATA[x] pin to logic high. */
 #define TMS570_DMM_PC4_DATAxSET(val) BSP_FLD32(val,2, 17)
@@ -486,15 +483,15 @@ typedef struct{
 #define TMS570_DMM_PC4_DATAxSET_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
 
 /* field: CLKSET - Sets output state of DMMCLK pin to logic high. */
-#define TMS570_DMM_PC4_CLKSET BSP_FLD32(1)
+#define TMS570_DMM_PC4_CLKSET BSP_BIT32(1)
 
 /* field: SYNCSET - Sets output state of DMMSYNC pin logic high. */
-#define TMS570_DMM_PC4_SYNCSET BSP_FLD32(0)
+#define TMS570_DMM_PC4_SYNCSET BSP_BIT32(0)
 
 
-/*-----------------------TMS570_DMMPC5-----------------------*/
+/*-----------------------TMS570_DMM_PC5-----------------------*/
 /* field: ENACLR - Sets output state of DMMENA pin to logic low. */
-#define TMS570_DMM_PC5_ENACLR BSP_FLD32(18)
+#define TMS570_DMM_PC5_ENACLR BSP_BIT32(18)
 
 /* field: DATAxCLR - Sets output state of DMMDATA[x] pin to logic low. */
 #define TMS570_DMM_PC5_DATAxCLR(val) BSP_FLD32(val,2, 17)
@@ -502,15 +499,15 @@ typedef struct{
 #define TMS570_DMM_PC5_DATAxCLR_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
 
 /* field: CLKCLR - Sets output state of DMMCLK pin to logic low. */
-#define TMS570_DMM_PC5_CLKCLR BSP_FLD32(1)
+#define TMS570_DMM_PC5_CLKCLR BSP_BIT32(1)
 
 /* field: SYNCCLR - Sets output state of DMMSYNC pin to logic low. */
-#define TMS570_DMM_PC5_SYNCCLR BSP_FLD32(0)
+#define TMS570_DMM_PC5_SYNCCLR BSP_BIT32(0)
 
 
-/*-----------------------TMS570_DMMPC6-----------------------*/
+/*-----------------------TMS570_DMM_PC6-----------------------*/
 /* field: ENAPDR - Open Drain enable. */
-#define TMS570_DMM_PC6_ENAPDR BSP_FLD32(18)
+#define TMS570_DMM_PC6_ENAPDR BSP_BIT32(18)
 
 /* field: DATAxPDR - Open Drain enable. */
 #define TMS570_DMM_PC6_DATAxPDR(val) BSP_FLD32(val,2, 17)
@@ -518,15 +515,15 @@ typedef struct{
 #define TMS570_DMM_PC6_DATAxPDR_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
 
 /* field: CLKPDR - Open Drain enable. */
-#define TMS570_DMM_PC6_CLKPDR BSP_FLD32(1)
+#define TMS570_DMM_PC6_CLKPDR BSP_BIT32(1)
 
 /* field: SYNCPDR - Open Drain enable. */
-#define TMS570_DMM_PC6_SYNCPDR BSP_FLD32(0)
+#define TMS570_DMM_PC6_SYNCPDR BSP_BIT32(0)
 
 
-/*-----------------------TMS570_DMMPC7-----------------------*/
+/*-----------------------TMS570_DMM_PC7-----------------------*/
 /* field: ENAPDIS - Pull disable. */
-#define TMS570_DMM_PC7_ENAPDIS BSP_FLD32(18)
+#define TMS570_DMM_PC7_ENAPDIS BSP_BIT32(18)
 
 /* field: DATAxPDIS - Pull disable. */
 #define TMS570_DMM_PC7_DATAxPDIS(val) BSP_FLD32(val,2, 17)
@@ -534,15 +531,15 @@ typedef struct{
 #define TMS570_DMM_PC7_DATAxPDIS_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
 
 /* field: CLKPDIS - Pull disable. */
-#define TMS570_DMM_PC7_CLKPDIS BSP_FLD32(1)
+#define TMS570_DMM_PC7_CLKPDIS BSP_BIT32(1)
 
 /* field: SYNCPDIS - Pull disable. */
-#define TMS570_DMM_PC7_SYNCPDIS BSP_FLD32(0)
+#define TMS570_DMM_PC7_SYNCPDIS BSP_BIT32(0)
 
 
-/*-----------------------TMS570_DMMPC8-----------------------*/
+/*-----------------------TMS570_DMM_PC8-----------------------*/
 /* field: ENAPSEL - Pull disable. */
-#define TMS570_DMM_PC8_ENAPSEL BSP_FLD32(18)
+#define TMS570_DMM_PC8_ENAPSEL BSP_BIT32(18)
 
 /* field: DATAxPSEL - Pull disable. */
 #define TMS570_DMM_PC8_DATAxPSEL(val) BSP_FLD32(val,2, 17)
@@ -550,11 +547,11 @@ typedef struct{
 #define TMS570_DMM_PC8_DATAxPSEL_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
 
 /* field: CLKPSEL - Pull disable. */
-#define TMS570_DMM_PC8_CLKPSEL BSP_FLD32(1)
+#define TMS570_DMM_PC8_CLKPSEL BSP_BIT32(1)
 
 /* field: SYNCPSEL - Pull disable. */
-#define TMS570_DMM_PC8_SYNCPSEL BSP_FLD32(0)
+#define TMS570_DMM_PC8_SYNCPSEL BSP_BIT32(0)
 
 
 
-#endif /* LIBBSP_ARM_tms570_DMM */
+#endif /* LIBBSP_ARM_TMS570_DMM */

c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_efuse.h

@@ -36,8 +36,8 @@
  * of the authors and should not be interpreted as representing official policies,
  * either expressed or implied, of the FreeBSD Project.
 */
-#ifndef LIBBSP_ARM_tms570_EFUSE
+#ifndef LIBBSP_ARM_TMS570_EFUSE
-#define LIBBSP_ARM_tms570_EFUSE
+#define LIBBSP_ARM_TMS570_EFUSE
 
 #include <bsp/utility.h>
 
@@ -53,33 +53,33 @@ typedef struct{
 } tms570_efuse_t;
 
 
-/*--------------------TMS570_EFUSEEFCBOUND--------------------*/
+/*-------------------TMS570_EFUSE_EFCBOUND-------------------*/
 /* field: EFC_Self_Test_Error - This bit drives the self test error signal when bit 17 (Self Test Error OE) is high. */
-#define TMS570_EFUSE_EFCBOUND_EFC_Self_Test_Error BSP_FLD32(21)
+#define TMS570_EFUSE_EFCBOUND_EFC_Self_Test_Error BSP_BIT32(21)
 
 /* field: EFC_Single_Bit_Error - This bit drives the single bit error signal when bit 16 (Single bit Error OE) is high. */
-#define TMS570_EFUSE_EFCBOUND_EFC_Single_Bit_Error BSP_FLD32(20)
+#define TMS570_EFUSE_EFCBOUND_EFC_Single_Bit_Error BSP_BIT32(20)
 
 /* field: EFC_Instruction_Error - This bit drives the instruction error signal when bit 15 (Instruction Error OE) is high. */
-#define TMS570_EFUSE_EFCBOUND_EFC_Instruction_Error BSP_FLD32(19)
+#define TMS570_EFUSE_EFCBOUND_EFC_Instruction_Error BSP_BIT32(19)
 
 /* field: EFC_Autoload_Error - This bit drives the Autoload Error signal when bit 14 (Autoload Error OE) is high. */
-#define TMS570_EFUSE_EFCBOUND_EFC_Autoload_Error BSP_FLD32(18)
+#define TMS570_EFUSE_EFCBOUND_EFC_Autoload_Error BSP_BIT32(18)
 
 /* field: Self_Test_Error_OE - The Self Test Error Output Enable bit determines if the EFC Self Test signal comes from the */
-#define TMS570_EFUSE_EFCBOUND_Self_Test_Error_OE BSP_FLD32(17)
+#define TMS570_EFUSE_EFCBOUND_Self_Test_Error_OE BSP_BIT32(17)
 
 /* field: Single_Bit_Error_OE - The single bit error output enable signal determines if the EFC Single Bit Error signal comes */
-#define TMS570_EFUSE_EFCBOUND_Single_Bit_Error_OE BSP_FLD32(16)
+#define TMS570_EFUSE_EFCBOUND_Single_Bit_Error_OE BSP_BIT32(16)
 
 /* field: Instruction_Error_OE - comes from the eFuse controller or from bit 19 of the boundary register. */
-#define TMS570_EFUSE_EFCBOUND_Instruction_Error_OE BSP_FLD32(15)
+#define TMS570_EFUSE_EFCBOUND_Instruction_Error_OE BSP_BIT32(15)
 
 /* field: Autoload_Error_OE - The autoload error output enable signal determines if the EFC Autoload Error signal comes */
-#define TMS570_EFUSE_EFCBOUND_Autoload_Error_OE BSP_FLD32(14)
+#define TMS570_EFUSE_EFCBOUND_Autoload_Error_OE BSP_BIT32(14)
 
 /* field: EFC_ECC_Selftest - The eFuse Controller ECC Selftest Enable bit starts the selftest of the ECC logic if the four */
-#define TMS570_EFUSE_EFCBOUND_EFC_ECC_Selftest BSP_FLD32(13)
+#define TMS570_EFUSE_EFCBOUND_EFC_ECC_Selftest BSP_BIT32(13)
 
 /* field: Input_Enable - The eFuse Controller ECC Selftest Enable bit starts the selftest of the ECC logic if the four */
 #define TMS570_EFUSE_EFCBOUND_Input_Enable(val) BSP_FLD32(val,0, 3)
@@ -87,26 +87,26 @@ typedef struct{
 #define TMS570_EFUSE_EFCBOUND_Input_Enable_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*--------------------TMS570_EFUSEEFCPINS--------------------*/
+/*--------------------TMS570_EFUSE_EFCPINS--------------------*/
 /* field: EFC_Selftest_Done - This bit can be polled to determine when the EFC ECC selftest is complete */
-#define TMS570_EFUSE_EFCPINS_EFC_Selftest_Done BSP_FLD32(15)
+#define TMS570_EFUSE_EFCPINS_EFC_Selftest_Done BSP_BIT32(15)
 
 /* field: EFC_Selftest_Error - This bit indicates the pass/fail status of the EFC ECC Selftest once the EFC Selftest Done */
-#define TMS570_EFUSE_EFCPINS_EFC_Selftest_Error BSP_FLD32(14)
+#define TMS570_EFUSE_EFCPINS_EFC_Selftest_Error BSP_BIT32(14)
 
 /* field: EFC_Single_Bit_Error - This bit indicates if a single bit error was corrected by the ECC logic during the autoload */
-#define TMS570_EFUSE_EFCPINS_EFC_Single_Bit_Error BSP_FLD32(12)
+#define TMS570_EFUSE_EFCPINS_EFC_Single_Bit_Error BSP_BIT32(12)
 
 /* field: EFC_Instruction_Error - This bit indicates an error occured during a factory test or program operation. */
-#define TMS570_EFUSE_EFCPINS_EFC_Instruction_Error BSP_FLD32(11)
+#define TMS570_EFUSE_EFCPINS_EFC_Instruction_Error BSP_BIT32(11)
 
 /* field: EFC_Autoload_Error - This bit indicates that some non-correctable error occurred during the autoload sequence */
-#define TMS570_EFUSE_EFCPINS_EFC_Autoload_Error BSP_FLD32(10)
+#define TMS570_EFUSE_EFCPINS_EFC_Autoload_Error BSP_BIT32(10)
 
 
-/*------------------TMS570_EFUSEEFC_ERR_STAT------------------*/
+/*-----------------TMS570_EFUSE_EFC_ERR_STAT-----------------*/
 /* field: Instruc_Done - Instruction done. */
-#define TMS570_EFUSE_EFC_ERR_STAT_Instruc_Done BSP_FLD32(5)
+#define TMS570_EFUSE_EFC_ERR_STAT_Instruc_Done BSP_BIT32(5)
 
 /* field: Error_Code - The error status of the last instruction executed by the eFuse Controller */
 #define TMS570_EFUSE_EFC_ERR_STAT_Error_Code(val) BSP_FLD32(val,0, 4)
@@ -114,19 +114,13 @@ typedef struct{
 #define TMS570_EFUSE_EFC_ERR_STAT_Error_Code_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
 
 
-/*-------------------TMS570_EFUSEEFC_ST_CY-------------------*/
+/*-------------------TMS570_EFUSE_EFC_ST_CY-------------------*/
 /* field: Cycles - This register is used to determine the number of cycles to run the eFuse controller ECC logic self test. */
-#define TMS570_EFUSE_EFC_ST_CY_Cycles(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_EFUSE_EFC_ST_CY_Cycles_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_EFUSE_EFC_ST_CY_Cycles_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_EFUSE_EFC_ST_SIG------------------*/
-/*-------------------TMS570_EFUSEEFC_ST_SIG-------------------*/
 /* field: Signature - This register is used to hold the expected signature for the eFuse ECC logic self test. */
-#define TMS570_EFUSE_EFC_ST_SIG_Signature(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_EFUSE_EFC_ST_SIG_Signature_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_EFUSE_EFC_ST_SIG_Signature_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
 
-
+#endif /* LIBBSP_ARM_TMS570_EFUSE */
-#endif /* LIBBSP_ARM_tms570_EFUSE */

c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emac.h

@@ -1,239 +0,0 @@
-/* The header file is generated by make_header.py from EMAC.json */
-/* Current script's version can be found at: */
-/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
-
-/*
- * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
- *
- * Czech Technical University in Prague
- * Zikova 1903/4
- * 166 36 Praha 6
- * Czech Republic
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this
- *    list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * The views and conclusions contained in the software and documentation are those
- * of the authors and should not be interpreted as representing official policies,
- * either expressed or implied, of the FreeBSD Project.
-*/
-#ifndef LIBBSP_ARM_tms570_EMAC
-#define LIBBSP_ARM_tms570_EMAC
-
-#include <bsp/utility.h>
-
-typedef struct{
-  uint32_t REVID;             /*MDIO Revision ID Register*/
-  uint32_t CONTROL;           /*MDIO Control Register*/
-  uint32_t ALIVE;             /*PHY Alive Status register*/
-  uint32_t LINK;              /*PHY Link Status Register*/
-  uint32_t LINKINTRAW;        /*MDIO Link Status Change Interrupt (Unmasked) Register*/
-  uint32_t LINKINTMASKED;     /*MDIO Link Status Change Interrupt (Masked) Register*/
-  uint8_t reserved1 [8];
-  uint32_t USERINTRAW;        /*MDIO User Command Complete Interrupt (Unmasked) Register*/
-  uint32_t USERINTMASKED;     /*MDIO User Command Complete Interrupt (Masked) Register*/
-  uint32_t USERINTMASKSET;    /*MDIO User Command Complete Interrupt Mask Set Register*/
-  uint32_t USERINTMASKCLEAR;  /*MDIO User Command Complete Interrupt Mask Clear Register*/
-  uint8_t reserved2 [80];
-  uint32_t USERACCESS0;       /*MDIO User Access Register 0*/
-  uint32_t USERPHYSEL0;       /*MDIO User PHY Select Register 0*/
-  uint32_t USERACCESS1;       /*MDIO User Access Register 1*/
-  uint32_t USERPHYSEL1;       /*MDIO User PHY Select Register 1*/
-} tms570_emac_t;
-
-
-/*----------------------TMS570_EMACREVID----------------------*/
-/* field: REV - Identifies the MDIO Module revision. */
-#define TMS570_EMAC_REVID_REV(val) BSP_FLD32(val,0, 31)
-#define TMS570_EMAC_REVID_REV_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_EMAC_REVID_REV_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
-
-/*---------------------TMS570_EMACCONTROL---------------------*/
-/* field: IDLE - State machine IDLE status bit. */
-#define TMS570_EMAC_CONTROL_IDLE BSP_FLD32(31)
-
-/* field: ENABLE - State machine enable control bit. */
-#define TMS570_EMAC_CONTROL_ENABLE BSP_FLD32(30)
-
-/* field: HIGHEST_USER_CHANNEL - Highest user channel that is available in the module. It is currently set to 1. */
-#define TMS570_EMAC_CONTROL_HIGHEST_USER_CHANNEL(val) BSP_FLD32(val,24, 28)
-#define TMS570_EMAC_CONTROL_HIGHEST_USER_CHANNEL_GET(reg) BSP_FLD32GET(reg,24, 28)
-#define TMS570_EMAC_CONTROL_HIGHEST_USER_CHANNEL_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
-
-/* field: PREAMBLE - Preamble disable */
-#define TMS570_EMAC_CONTROL_PREAMBLE BSP_FLD32(20)
-
-/* field: FAULT - Fault indicator. */
-#define TMS570_EMAC_CONTROL_FAULT BSP_FLD32(19)
-
-/* field: FAULTENB - Fault detect enable. */
-#define TMS570_EMAC_CONTROL_FAULTENB BSP_FLD32(18)
-
-/* field: CLKDIV - Clock Divider bits. */
-#define TMS570_EMAC_CONTROL_CLKDIV(val) BSP_FLD32(val,0, 15)
-#define TMS570_EMAC_CONTROL_CLKDIV_GET(reg) BSP_FLD32GET(reg,0, 15)
-#define TMS570_EMAC_CONTROL_CLKDIV_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-
-
-/*----------------------TMS570_EMACALIVE----------------------*/
-/* field: ALIVE - MDIO Alive bits. */
-#define TMS570_EMAC_ALIVE_ALIVE(val) BSP_FLD32(val,0, 31)
-#define TMS570_EMAC_ALIVE_ALIVE_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_EMAC_ALIVE_ALIVE_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
-
-/*----------------------TMS570_EMACLINK----------------------*/
-/* field: LINK - MDIO Link state bits. This register is updated after a read of the generic status register of a PHY. */
-#define TMS570_EMAC_LINK_LINK(val) BSP_FLD32(val,0, 31)
-#define TMS570_EMAC_LINK_LINK_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_EMAC_LINK_LINK_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
-
-/*-------------------TMS570_EMACLINKINTRAW-------------------*/
-/* field: USERPHY1 - MDIO Link change event, raw value. */
-#define TMS570_EMAC_LINKINTRAW_USERPHY1 BSP_FLD32(1)
-
-/* field: USERPHY0 - MDIO Link change event, raw value. */
-#define TMS570_EMAC_LINKINTRAW_USERPHY0 BSP_FLD32(0)
-
-
-/*------------------TMS570_EMACLINKINTMASKED------------------*/
-/* field: USERPHY1 - MDIO Link change interrupt, masked value. */
-#define TMS570_EMAC_LINKINTMASKED_USERPHY1 BSP_FLD32(1)
-
-/* field: USERPHY0 - MDIO Link change interrupt, masked value. */
-#define TMS570_EMAC_LINKINTMASKED_USERPHY0 BSP_FLD32(0)
-
-
-/*-------------------TMS570_EMACUSERINTRAW-------------------*/
-/* field: USERACCESS1 - MDIO User command complete event bit. */
-#define TMS570_EMAC_USERINTRAW_USERACCESS1 BSP_FLD32(1)
-
-/* field: USERACCESS0 - MDIO User command complete event bit. */
-#define TMS570_EMAC_USERINTRAW_USERACCESS0 BSP_FLD32(0)
-
-
-/*------------------TMS570_EMACUSERINTMASKED------------------*/
-/* field: USERACCESS1 - Masked value of MDIO User command complete interrupt. */
-#define TMS570_EMAC_USERINTMASKED_USERACCESS1 BSP_FLD32(1)
-
-/* field: USERACCESS0 - Masked value of MDIO User command complete interrupt. */
-#define TMS570_EMAC_USERINTMASKED_USERACCESS0 BSP_FLD32(0)
-
-
-/*-----------------TMS570_EMACUSERINTMASKSET-----------------*/
-/* field: USERACCESS1 - MDIO user interrupt mask set for USERINTMASKED[1]. */
-#define TMS570_EMAC_USERINTMASKSET_USERACCESS1 BSP_FLD32(1)
-
-/* field: USERACCESS0 - MDIO user interrupt mask set for USERINTMASKED[0]. */
-#define TMS570_EMAC_USERINTMASKSET_USERACCESS0 BSP_FLD32(0)
-
-
-/*----------------TMS570_EMACUSERINTMASKCLEAR----------------*/
-/* field: USERACCESS1 - MDIO user command complete interrupt mask clear for USERINTMASKED[1]. */
-#define TMS570_EMAC_USERINTMASKCLEAR_USERACCESS1 BSP_FLD32(1)
-
-/* field: USERACCESS0 - MDIO user command complete interrupt mask clear for USERINTMASKED[0]. */
-#define TMS570_EMAC_USERINTMASKCLEAR_USERACCESS0 BSP_FLD32(0)
-
-
-/*-------------------TMS570_EMACUSERACCESS0-------------------*/
-/* field: GO - Go bit. */
-#define TMS570_EMAC_USERACCESS0_GO BSP_FLD32(31)
-
-/* field: WRITE - Write enable bit. */
-#define TMS570_EMAC_USERACCESS0_WRITE BSP_FLD32(30)
-
-/* field: ACK - Acknowledge bit. This bit is set if the PHY acknowledged the read transaction. */
-#define TMS570_EMAC_USERACCESS0_ACK BSP_FLD32(29)
-
-/* field: REGADR - Register address bits. */
-#define TMS570_EMAC_USERACCESS0_REGADR(val) BSP_FLD32(val,21, 25)
-#define TMS570_EMAC_USERACCESS0_REGADR_GET(reg) BSP_FLD32GET(reg,21, 25)
-#define TMS570_EMAC_USERACCESS0_REGADR_SET(reg,val) BSP_FLD32SET(reg, val,21, 25)
-
-/* field: PHYADR - PHY address bits. This field specifies the PHY to be accessed for this transaction. */
-#define TMS570_EMAC_USERACCESS0_PHYADR(val) BSP_FLD32(val,16, 20)
-#define TMS570_EMAC_USERACCESS0_PHYADR_GET(reg) BSP_FLD32GET(reg,16, 20)
-#define TMS570_EMAC_USERACCESS0_PHYADR_SET(reg,val) BSP_FLD32SET(reg, val,16, 20)
-
-/* field: DATA - User data bits. */
-#define TMS570_EMAC_USERACCESS0_DATA(val) BSP_FLD32(val,0, 15)
-#define TMS570_EMAC_USERACCESS0_DATA_GET(reg) BSP_FLD32GET(reg,0, 15)
-#define TMS570_EMAC_USERACCESS0_DATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-
-
-/*-------------------TMS570_EMACUSERPHYSEL0-------------------*/
-/* field: LINKSEL - Link status determination select bit. */
-#define TMS570_EMAC_USERPHYSEL0_LINKSEL BSP_FLD32(7)
-
-/* field: LINKINTENB - Link change interrupt enable. */
-#define TMS570_EMAC_USERPHYSEL0_LINKINTENB BSP_FLD32(6)
-
-/* field: PHYADRMON - PHY address whose link status is to be monitored. */
-#define TMS570_EMAC_USERPHYSEL0_PHYADRMON(val) BSP_FLD32(val,0, 4)
-#define TMS570_EMAC_USERPHYSEL0_PHYADRMON_GET(reg) BSP_FLD32GET(reg,0, 4)
-#define TMS570_EMAC_USERPHYSEL0_PHYADRMON_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
-
-
-/*-------------------TMS570_EMACUSERACCESS1-------------------*/
-/* field: GO - Go bit. */
-#define TMS570_EMAC_USERACCESS1_GO BSP_FLD32(31)
-
-/* field: WRITE - Write enable bit. */
-#define TMS570_EMAC_USERACCESS1_WRITE BSP_FLD32(30)
-
-/* field: ACK - Acknowledge bit. This bit is set if the PHY acknowledged the read transaction. */
-#define TMS570_EMAC_USERACCESS1_ACK BSP_FLD32(29)
-
-/* field: REGADR - Register address bits. */
-#define TMS570_EMAC_USERACCESS1_REGADR(val) BSP_FLD32(val,21, 25)
-#define TMS570_EMAC_USERACCESS1_REGADR_GET(reg) BSP_FLD32GET(reg,21, 25)
-#define TMS570_EMAC_USERACCESS1_REGADR_SET(reg,val) BSP_FLD32SET(reg, val,21, 25)
-
-/* field: PHYADR - PHY address bits. This field specifies the PHY to be accessed for this transaction. */
-#define TMS570_EMAC_USERACCESS1_PHYADR(val) BSP_FLD32(val,16, 20)
-#define TMS570_EMAC_USERACCESS1_PHYADR_GET(reg) BSP_FLD32GET(reg,16, 20)
-#define TMS570_EMAC_USERACCESS1_PHYADR_SET(reg,val) BSP_FLD32SET(reg, val,16, 20)
-
-/* field: DATA - User data bits. */
-#define TMS570_EMAC_USERACCESS1_DATA(val) BSP_FLD32(val,0, 15)
-#define TMS570_EMAC_USERACCESS1_DATA_GET(reg) BSP_FLD32GET(reg,0, 15)
-#define TMS570_EMAC_USERACCESS1_DATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-
-
-/*-------------------TMS570_EMACUSERPHYSEL1-------------------*/
-/* field: LINKSEL - Link status determination select bit. */
-#define TMS570_EMAC_USERPHYSEL1_LINKSEL BSP_FLD32(7)
-
-/* field: LINKINTENB - Link change interrupt enable. */
-#define TMS570_EMAC_USERPHYSEL1_LINKINTENB BSP_FLD32(6)
-
-/* field: PHYADRMON - PHY address whose link status is to be monitored. */
-#define TMS570_EMAC_USERPHYSEL1_PHYADRMON(val) BSP_FLD32(val,0, 4)
-#define TMS570_EMAC_USERPHYSEL1_PHYADRMON_GET(reg) BSP_FLD32GET(reg,0, 4)
-#define TMS570_EMAC_USERPHYSEL1_PHYADRMON_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
-
-
-
-#endif /* LIBBSP_ARM_tms570_EMAC */

c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emacc.h

@@ -0,0 +1,285 @@
+/* The header file is generated by make_header.py from EMACC.json */
+/* Current script's version can be found at: */
+/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
+
+/*
+ * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are those
+ * of the authors and should not be interpreted as representing official policies,
+ * either expressed or implied, of the FreeBSD Project.
+*/
+#ifndef LIBBSP_ARM_TMS570_EMACC
+#define LIBBSP_ARM_TMS570_EMACC
+
+#include <bsp/utility.h>
+
+typedef struct{
+  uint32_t REVID;             /*EMAC Control Module Revision ID Register*/
+  uint32_t SOFTRESET;         /*EMAC Control Module Software Reset Register*/
+  uint8_t reserved1 [4];
+  uint32_t INTCONTROL;        /*EMAC Control Module Interrupt Control Register*/
+  uint32_t C0RXTHRESHEN;      /*EMAC Control Module Receive Threshold Interrupt Enable Register*/
+  uint32_t C0RXEN;            /*EMAC Control Module Receive Interrupt Enable Register*/
+  uint32_t C0TXEN;            /*EMAC Control Module Transmit Interrupt Enable Register*/
+  uint32_t C0MISCEN;          /*EMAC Control Module Miscellaneous Interrupt Enable Register*/
+  uint8_t reserved2 [32];
+  uint32_t C0RXTHRESHSTAT;    /*EMAC Control Module Receive Threshold Interrupt Status Register*/
+  uint32_t C0RXSTAT;          /*EMAC Control Module Receive Interrupt Status Register*/
+  uint32_t C0TXSTAT;          /*EMAC Control Module Transmit Interrupt Status Register*/
+  uint32_t C0MISCSTAT;        /*EMAC Control Module Miscellaneous Interrupt Status Register*/
+  uint8_t reserved3 [32];
+  uint32_t C0RXIMAX;          /*EMAC Control Module Receive Interrupts Per Millisecond Register*/
+  uint32_t C0TXIMAX;          /*EMAC Control Module Transmit Interrupts Per Millisecond Register*/
+} tms570_emacc_t;
+
+
+/*---------------------TMS570_EMACC_REVID---------------------*/
+/* field: REV - Identifies the EMAC Control Module revision. */
+/* Whole 32 bits */
+
+/*-------------------TMS570_EMACC_SOFTRESET-------------------*/
+/* field: RESET - Software reset bit for the EMAC Control Module. */
+#define TMS570_EMACC_SOFTRESET_RESET BSP_BIT32(0)
+
+
+/*------------------TMS570_EMACC_INTCONTROL------------------*/
+/* field: C0TXPACEEN - Enable pacing for TX interrupt pulse generation */
+#define TMS570_EMACC_INTCONTROL_C0TXPACEEN BSP_BIT32(17)
+
+/* field: C0RXPACEEN - Enable pacing for RX interrupt pulse generation */
+#define TMS570_EMACC_INTCONTROL_C0RXPACEEN BSP_BIT32(16)
+
+/* field: INTPRESCALE - Number of internal EMAC module reference clock periods within a 4 us time window (see */
+#define TMS570_EMACC_INTCONTROL_INTPRESCALE(val) BSP_FLD32(val,0, 11)
+#define TMS570_EMACC_INTCONTROL_INTPRESCALE_GET(reg) BSP_FLD32GET(reg,0, 11)
+#define TMS570_EMACC_INTCONTROL_INTPRESCALE_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
+
+
+/*-----------------TMS570_EMACC_C0RXTHRESHEN-----------------*/
+/* field: RXCH7THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 7 */
+#define TMS570_EMACC_C0RXTHRESHEN_RXCH7THRESHEN BSP_BIT32(7)
+
+/* field: RXCH6THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 6 */
+#define TMS570_EMACC_C0RXTHRESHEN_RXCH6THRESHEN BSP_BIT32(6)
+
+/* field: RXCH5THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 5 */
+#define TMS570_EMACC_C0RXTHRESHEN_RXCH5THRESHEN BSP_BIT32(5)
+
+/* field: RXCH4THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 4 */
+#define TMS570_EMACC_C0RXTHRESHEN_RXCH4THRESHEN BSP_BIT32(4)
+
+/* field: RXCH3THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 3 */
+#define TMS570_EMACC_C0RXTHRESHEN_RXCH3THRESHEN BSP_BIT32(3)
+
+/* field: RXCH2THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 2 */
+#define TMS570_EMACC_C0RXTHRESHEN_RXCH2THRESHEN BSP_BIT32(2)
+
+/* field: RXCH1THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 1 */
+#define TMS570_EMACC_C0RXTHRESHEN_RXCH1THRESHEN BSP_BIT32(1)
+
+/* field: RXCH0THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 0 */
+#define TMS570_EMACC_C0RXTHRESHEN_RXCH0THRESHEN BSP_BIT32(0)
+
+
+/*--------------------TMS570_EMACC_C0RXEN--------------------*/
+/* field: RXCH7EN - Enable C0RXPULSE interrupt generation for RX Channel 7 */
+#define TMS570_EMACC_C0RXEN_RXCH7EN BSP_BIT32(7)
+
+/* field: RXCH6EN - Enable C0RXPULSE interrupt generation for RX Channel 6 */
+#define TMS570_EMACC_C0RXEN_RXCH6EN BSP_BIT32(6)
+
+/* field: RXCH5EN - Enable C0RXPULSE interrupt generation for RX Channel 5 */
+#define TMS570_EMACC_C0RXEN_RXCH5EN BSP_BIT32(5)
+
+/* field: RXCH4EN - Enable C0RXPULSE interrupt generation for RX Channel 4 */
+#define TMS570_EMACC_C0RXEN_RXCH4EN BSP_BIT32(4)
+
+/* field: RXCH3EN - Enable C0RXPULSE interrupt generation for RX Channel 3 */
+#define TMS570_EMACC_C0RXEN_RXCH3EN BSP_BIT32(3)
+
+/* field: RXCH2EN - Enable C0RXPULSE interrupt generation for RX Channel 2 */
+#define TMS570_EMACC_C0RXEN_RXCH2EN BSP_BIT32(2)
+
+/* field: RXCH1EN - Enable C0RXPULSE interrupt generation for RX Channel 1 */
+#define TMS570_EMACC_C0RXEN_RXCH1EN BSP_BIT32(1)
+
+/* field: RXCH0EN - Enable C0RXPULSE interrupt generation for RX Channel 0 */
+#define TMS570_EMACC_C0RXEN_RXCH0EN BSP_BIT32(0)
+
+
+/*--------------------TMS570_EMACC_C0TXEN--------------------*/
+/* field: TXCH7EN - Enable C0TXPULSE interrupt generation for TX Channel 7 */
+#define TMS570_EMACC_C0TXEN_TXCH7EN BSP_BIT32(7)
+
+/* field: TXCH6EN - TXCH6EN */
+#define TMS570_EMACC_C0TXEN_TXCH6EN BSP_BIT32(6)
+
+/* field: TXCH5EN - Enable C0TXPULSE interrupt generation for TX Channel 5 */
+#define TMS570_EMACC_C0TXEN_TXCH5EN BSP_BIT32(5)
+
+/* field: TXCH4EN - Enable C0TXPULSE interrupt generation for TX Channel 4 */
+#define TMS570_EMACC_C0TXEN_TXCH4EN BSP_BIT32(4)
+
+/* field: TXCH3EN - Enable C0TXPULSE interrupt generation for TX Channel 3 */
+#define TMS570_EMACC_C0TXEN_TXCH3EN BSP_BIT32(3)
+
+/* field: TXCH2EN - Enable C0TXPULSE interrupt generation for TX Channel 2 */
+#define TMS570_EMACC_C0TXEN_TXCH2EN BSP_BIT32(2)
+
+/* field: TXCH1EN - Enable C0TXPULSE interrupt generation for TX Channel 1 */
+#define TMS570_EMACC_C0TXEN_TXCH1EN BSP_BIT32(1)
+
+/* field: TXCH0EN - Enable C0TXPULSE interrupt generation for TX Channel 0 */
+#define TMS570_EMACC_C0TXEN_TXCH0EN BSP_BIT32(0)
+
+
+/*-------------------TMS570_EMACC_C0MISCEN-------------------*/
+/* field: STATPENDEN - Enable C0MISCPULSE interrupt generation when EMAC statistics interrupts are generated */
+#define TMS570_EMACC_C0MISCEN_STATPENDEN BSP_BIT32(3)
+
+/* field: HOSTPENDEN - HOSTPENDEN */
+#define TMS570_EMACC_C0MISCEN_HOSTPENDEN BSP_BIT32(2)
+
+/* field: LINKINT0EN - Enable C0MISCPULSE interrupt generation when MDIO LINKINT0 interrupts (corresponding to */
+#define TMS570_EMACC_C0MISCEN_LINKINT0EN BSP_BIT32(1)
+
+/* field: USERINT0EN - Enable C0MISCPULSE interrupt generation when MDIO USERINT0 interrupts (corresponding */
+#define TMS570_EMACC_C0MISCEN_USERINT0EN BSP_BIT32(0)
+
+
+/*----------------TMS570_EMACC_C0RXTHRESHSTAT----------------*/
+/* field: RXCH7THRESHSTAT - Interrupt status for RX Channel 7 masked by the C0RXTHRESHEN register */
+#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH7THRESHSTAT BSP_BIT32(7)
+
+/* field: RXCH6THRESHSTAT - Interrupt status for RX Channel 6 masked by the C0RXTHRESHEN register */
+#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH6THRESHSTAT BSP_BIT32(6)
+
+/* field: RXCH5THRESHSTAT - Interrupt status for RX Channel 5 masked by the C0RXTHRESHEN register */
+#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH5THRESHSTAT BSP_BIT32(5)
+
+/* field: RXCH4THRESHSTAT - Interrupt status for RX Channel 4 masked by the C0RXTHRESHEN register */
+#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH4THRESHSTAT BSP_BIT32(4)
+
+/* field: RXCH3THRESHSTAT - Interrupt status for RX Channel 3 masked by the C0RXTHRESHEN register */
+#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH3THRESHSTAT BSP_BIT32(3)
+
+/* field: RXCH2THRESHSTAT - Interrupt status for RX Channel 2 masked by the C0RXTHRESHEN register */
+#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH2THRESHSTAT BSP_BIT32(2)
+
+/* field: RXCH1THRESHSTAT - Interrupt status for RX Channel 1 masked by the C0RXTHRESHEN register */
+#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH1THRESHSTAT BSP_BIT32(1)
+
+/* field: RXCH0THRESHSTAT - Interrupt status for RX Channel 0 masked by the C0RXTHRESHEN register */
+#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH0THRESHSTAT BSP_BIT32(0)
+
+
+/*-------------------TMS570_EMACC_C0RXSTAT-------------------*/
+/* field: RXCH7STAT - RXCH7STAT */
+#define TMS570_EMACC_C0RXSTAT_RXCH7STAT BSP_BIT32(7)
+
+/* field: RXCH6STAT - Interrupt status for RX Channel 6 masked by the C0RXEN register */
+#define TMS570_EMACC_C0RXSTAT_RXCH6STAT BSP_BIT32(6)
+
+/* field: RXCH5STAT - Interrupt status for RX Channel 5 masked by the C0RXEN register */
+#define TMS570_EMACC_C0RXSTAT_RXCH5STAT BSP_BIT32(5)
+
+/* field: RXCH4STAT - Interrupt status for RX Channel 4 masked by the C0RXEN register */
+#define TMS570_EMACC_C0RXSTAT_RXCH4STAT BSP_BIT32(4)
+
+/* field: RXCH3STAT - Interrupt status for RX Channel 3 masked by the C0RXEN register */
+#define TMS570_EMACC_C0RXSTAT_RXCH3STAT BSP_BIT32(3)
+
+/* field: RXCH2STAT - H2STAT Interrupt status for RX Channel 2 masked by the C0RXEN register */
+#define TMS570_EMACC_C0RXSTAT_RXCH2STAT BSP_BIT32(2)
+
+/* field: RXCH1STAT - Interrupt status for RX Channel 1 masked by the C0RXEN register */
+#define TMS570_EMACC_C0RXSTAT_RXCH1STAT BSP_BIT32(1)
+
+/* field: RXCH0STAT - Interrupt status for RX Channel 0 masked by the C0RXEN register */
+#define TMS570_EMACC_C0RXSTAT_RXCH0STAT BSP_BIT32(0)
+
+
+/*-------------------TMS570_EMACC_C0TXSTAT-------------------*/
+/* field: TXCH7STAT - Interrupt status for TX Channel 7 masked by the C0TXEN register */
+#define TMS570_EMACC_C0TXSTAT_TXCH7STAT BSP_BIT32(7)
+
+/* field: TXCH6STAT - TXCH6STAT */
+#define TMS570_EMACC_C0TXSTAT_TXCH6STAT BSP_BIT32(6)
+
+/* field: TXCH5STAT - Interrupt status for TX Channel 5 masked by the C0TXEN register */
+#define TMS570_EMACC_C0TXSTAT_TXCH5STAT BSP_BIT32(5)
+
+/* field: TXCH4STAT - Interrupt status for TX Channel 4 masked by the C0TXEN register */
+#define TMS570_EMACC_C0TXSTAT_TXCH4STAT BSP_BIT32(4)
+
+/* field: TXCH3STAT - Interrupt status for TX Channel 3 masked by the C0TXEN register */
+#define TMS570_EMACC_C0TXSTAT_TXCH3STAT BSP_BIT32(3)
+
+/* field: TXCH2STAT - Interrupt status for TX Channel 2 masked by the C0TXEN register */
+#define TMS570_EMACC_C0TXSTAT_TXCH2STAT BSP_BIT32(2)
+
+/* field: TXCH1STAT - Interrupt status for TX Channel 1 masked by the C0TXEN register */
+#define TMS570_EMACC_C0TXSTAT_TXCH1STAT BSP_BIT32(1)
+
+/* field: TXCH0STAT - Interrupt status for TX Channel 0 masked by the C0TXEN register */
+#define TMS570_EMACC_C0TXSTAT_TXCH0STAT BSP_BIT32(0)
+
+
+/*------------------TMS570_EMACC_C0MISCSTAT------------------*/
+/* field: STATPENDSTAT - Interrupt status for EMAC STATPEND masked by the C0MISCEN register */
+#define TMS570_EMACC_C0MISCSTAT_STATPENDSTAT BSP_BIT32(3)
+
+/* field: HOSTPENDSTAT - Interrupt status for EMAC HOSTPEND masked by the C0MISCEN register */
+#define TMS570_EMACC_C0MISCSTAT_HOSTPENDSTAT BSP_BIT32(2)
+
+/* field: LINKINT0STAT - Interrupt status for MDIO LINKINT0 masked by the C0MISCEN register */
+#define TMS570_EMACC_C0MISCSTAT_LINKINT0STAT BSP_BIT32(1)
+
+/* field: USERINT0STAT - Interrupt status for MDIO USERINT0 masked by the C0MISCEN register */
+#define TMS570_EMACC_C0MISCSTAT_USERINT0STAT BSP_BIT32(0)
+
+
+/*-------------------TMS570_EMACC_C0RXIMAX-------------------*/
+/* field: RXIMAX - RXIMAX is the desired number of C0RXPULSE interrupts generated per millisecond when */
+#define TMS570_EMACC_C0RXIMAX_RXIMAX(val) BSP_FLD32(val,0, 5)
+#define TMS570_EMACC_C0RXIMAX_RXIMAX_GET(reg) BSP_FLD32GET(reg,0, 5)
+#define TMS570_EMACC_C0RXIMAX_RXIMAX_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
+
+
+/*-------------------TMS570_EMACC_C0TXIMAX-------------------*/
+/* field: TXIMAX - TXIMAX is the desired number of C0TXPULSE interrupts generated per millisecond when */
+#define TMS570_EMACC_C0TXIMAX_TXIMAX(val) BSP_FLD32(val,0, 5)
+#define TMS570_EMACC_C0TXIMAX_TXIMAX_GET(reg) BSP_FLD32GET(reg,0, 5)
+#define TMS570_EMACC_C0TXIMAX_TXIMAX_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
+
+
+
+#endif /* LIBBSP_ARM_TMS570_EMACC */

c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emacm.h

@@ -36,8 +36,8 @@
  * of the authors and should not be interpreted as representing official policies,
  * either expressed or implied, of the FreeBSD Project.
 */
-#ifndef LIBBSP_ARM_tms570_EMACM
+#ifndef LIBBSP_ARM_TMS570_EMACM
-#define LIBBSP_ARM_tms570_EMACM
+#define LIBBSP_ARM_TMS570_EMACM
 
 #include <bsp/utility.h>
 
@@ -102,160 +102,154 @@ typedef struct{
 } tms570_emacm_t;
 
 
-/*--------------------TMS570_EMACMTXREVID--------------------*/
+/*--------------------TMS570_EMACM_TXREVID--------------------*/
 /* field: TXREV - Transmit module revision */
-#define TMS570_EMACM_TXREVID_TXREV(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_EMACM_TXREVID_TXREV_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_EMACM_TXREVID_TXREV_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_EMACM_TXCONTROL-------------------*/
-/*-------------------TMS570_EMACMTXCONTROL-------------------*/
 /* field: TXEN - Transmit enable */
-#define TMS570_EMACM_TXCONTROL_TXEN BSP_FLD32(0)
+#define TMS570_EMACM_TXCONTROL_TXEN BSP_BIT32(0)
 
 
-/*-------------------TMS570_EMACMTXTEARDOWN-------------------*/
+/*------------------TMS570_EMACM_TXTEARDOWN------------------*/
 /* field: TXTDNCH - Transmit teardown channel. */
 #define TMS570_EMACM_TXTEARDOWN_TXTDNCH(val) BSP_FLD32(val,0, 2)
 #define TMS570_EMACM_TXTEARDOWN_TXTDNCH_GET(reg) BSP_FLD32GET(reg,0, 2)
 #define TMS570_EMACM_TXTEARDOWN_TXTDNCH_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
 
 
-/*--------------------TMS570_EMACMRXREVID--------------------*/
+/*--------------------TMS570_EMACM_RXREVID--------------------*/
 /* field: RXREV - Receive module revision */
-#define TMS570_EMACM_RXREVID_RXREV(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_EMACM_RXREVID_RXREV_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_EMACM_RXREVID_RXREV_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_EMACM_RXCONTROL-------------------*/
-/*-------------------TMS570_EMACMRXCONTROL-------------------*/
 /* field: RXEN - Receive enable */
-#define TMS570_EMACM_RXCONTROL_RXEN BSP_FLD32(0)
+#define TMS570_EMACM_RXCONTROL_RXEN BSP_BIT32(0)
 
 
-/*-------------------TMS570_EMACMRXTEARDOWN-------------------*/
+/*------------------TMS570_EMACM_RXTEARDOWN------------------*/
 /* field: RXTDNCH - Receive teardown channel. */
 #define TMS570_EMACM_RXTEARDOWN_RXTDNCH(val) BSP_FLD32(val,0, 2)
 #define TMS570_EMACM_RXTEARDOWN_RXTDNCH_GET(reg) BSP_FLD32GET(reg,0, 2)
 #define TMS570_EMACM_RXTEARDOWN_RXTDNCH_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
 
 
-/*------------------TMS570_EMACMTXINTSTATRAW------------------*/
+/*-----------------TMS570_EMACM_TXINTSTATRAW-----------------*/
 /* field: TX7PEND - TX7PEND raw interrupt read (before mask) */
-#define TMS570_EMACM_TXINTSTATRAW_TX7PEND BSP_FLD32(7)
+#define TMS570_EMACM_TXINTSTATRAW_TX7PEND BSP_BIT32(7)
 
 /* field: TX6PEND - TX6PEND raw interrupt read (before mask) */
-#define TMS570_EMACM_TXINTSTATRAW_TX6PEND BSP_FLD32(6)
+#define TMS570_EMACM_TXINTSTATRAW_TX6PEND BSP_BIT32(6)
 
 /* field: TX5PEND - TX5PEND raw interrupt read (before mask) */
-#define TMS570_EMACM_TXINTSTATRAW_TX5PEND BSP_FLD32(5)
+#define TMS570_EMACM_TXINTSTATRAW_TX5PEND BSP_BIT32(5)
 
 /* field: TX4PEND - X4PEND raw interrupt read (before mask) */
-#define TMS570_EMACM_TXINTSTATRAW_TX4PEND BSP_FLD32(4)
+#define TMS570_EMACM_TXINTSTATRAW_TX4PEND BSP_BIT32(4)
 
 /* field: TX3PEND - TX3PEND raw interrupt read (before mask) */
-#define TMS570_EMACM_TXINTSTATRAW_TX3PEND BSP_FLD32(3)
+#define TMS570_EMACM_TXINTSTATRAW_TX3PEND BSP_BIT32(3)
 
 /* field: TX2PEND - TX2PEND raw interrupt read (before mask) */
-#define TMS570_EMACM_TXINTSTATRAW_TX2PEND BSP_FLD32(2)
+#define TMS570_EMACM_TXINTSTATRAW_TX2PEND BSP_BIT32(2)
 
 /* field: TX1PEND - TX1PEND raw interrupt read (before mask) */
-#define TMS570_EMACM_TXINTSTATRAW_TX1PEND BSP_FLD32(1)
+#define TMS570_EMACM_TXINTSTATRAW_TX1PEND BSP_BIT32(1)
 
 /* field: TX0PEND - TX0PEND raw interrupt read (before mask) */
-#define TMS570_EMACM_TXINTSTATRAW_TX0PEND BSP_FLD32(0)
+#define TMS570_EMACM_TXINTSTATRAW_TX0PEND BSP_BIT32(0)
 
 
-/*----------------TMS570_EMACMTXINTSTATMASKED----------------*/
+/*----------------TMS570_EMACM_TXINTSTATMASKED----------------*/
 /* field: TX7PEND - TX7PEND masked interrupt read */
-#define TMS570_EMACM_TXINTSTATMASKED_TX7PEND BSP_FLD32(7)
+#define TMS570_EMACM_TXINTSTATMASKED_TX7PEND BSP_BIT32(7)
 
 /* field: TX6PEND - TX6PEND masked interrupt read */
-#define TMS570_EMACM_TXINTSTATMASKED_TX6PEND BSP_FLD32(6)
+#define TMS570_EMACM_TXINTSTATMASKED_TX6PEND BSP_BIT32(6)
 
 /* field: TX5PEND - TX5PEND masked interrupt read */
-#define TMS570_EMACM_TXINTSTATMASKED_TX5PEND BSP_FLD32(5)
+#define TMS570_EMACM_TXINTSTATMASKED_TX5PEND BSP_BIT32(5)
 
 /* field: TX4PEND - TX4PEND masked interrupt read */
-#define TMS570_EMACM_TXINTSTATMASKED_TX4PEND BSP_FLD32(4)
+#define TMS570_EMACM_TXINTSTATMASKED_TX4PEND BSP_BIT32(4)
 
 /* field: TX3PEND - TX3PEND masked interrupt read */
-#define TMS570_EMACM_TXINTSTATMASKED_TX3PEND BSP_FLD32(3)
+#define TMS570_EMACM_TXINTSTATMASKED_TX3PEND BSP_BIT32(3)
 
 /* field: TX2PEND - TX2PEND masked interrupt read */
-#define TMS570_EMACM_TXINTSTATMASKED_TX2PEND BSP_FLD32(2)
+#define TMS570_EMACM_TXINTSTATMASKED_TX2PEND BSP_BIT32(2)
 
 /* field: TX1PEND - TX1PEND masked interrupt read */
-#define TMS570_EMACM_TXINTSTATMASKED_TX1PEND BSP_FLD32(1)
+#define TMS570_EMACM_TXINTSTATMASKED_TX1PEND BSP_BIT32(1)
 
 /* field: TX0PEND - TX0PEND masked interrupt read */
-#define TMS570_EMACM_TXINTSTATMASKED_TX0PEND BSP_FLD32(0)
+#define TMS570_EMACM_TXINTSTATMASKED_TX0PEND BSP_BIT32(0)
 
 
-/*------------------TMS570_EMACMTXINTMASKSET------------------*/
+/*-----------------TMS570_EMACM_TXINTMASKSET-----------------*/
 /* field: TX7MASK - Transmit channel 7 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_TXINTMASKSET_TX7MASK BSP_FLD32(7)
+#define TMS570_EMACM_TXINTMASKSET_TX7MASK BSP_BIT32(7)
 
 /* field: TX6MASK - Transmit channel 6 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_TXINTMASKSET_TX6MASK BSP_FLD32(6)
+#define TMS570_EMACM_TXINTMASKSET_TX6MASK BSP_BIT32(6)
 
 /* field: TX5MASK - Transmit channel 5 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_TXINTMASKSET_TX5MASK BSP_FLD32(5)
+#define TMS570_EMACM_TXINTMASKSET_TX5MASK BSP_BIT32(5)
 
 /* field: TX4MASK - Transmit channel 4 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_TXINTMASKSET_TX4MASK BSP_FLD32(4)
+#define TMS570_EMACM_TXINTMASKSET_TX4MASK BSP_BIT32(4)
 
 /* field: TX3MASK - Transmit channel 3 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_TXINTMASKSET_TX3MASK BSP_FLD32(3)
+#define TMS570_EMACM_TXINTMASKSET_TX3MASK BSP_BIT32(3)
 
 /* field: TX2MASK - Transmit channel 2 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_TXINTMASKSET_TX2MASK BSP_FLD32(2)
+#define TMS570_EMACM_TXINTMASKSET_TX2MASK BSP_BIT32(2)
 
 /* field: TX1MASK - Transmit channel 1 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_TXINTMASKSET_TX1MASK BSP_FLD32(1)
+#define TMS570_EMACM_TXINTMASKSET_TX1MASK BSP_BIT32(1)
 
 /* field: TX0MASK - Transmit channel 0 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_TXINTMASKSET_TX0MASK BSP_FLD32(0)
+#define TMS570_EMACM_TXINTMASKSET_TX0MASK BSP_BIT32(0)
 
 
-/*-----------------TMS570_EMACMTXINTMASKCLEAR-----------------*/
+/*----------------TMS570_EMACM_TXINTMASKCLEAR----------------*/
 /* field: TX7MASK - Transmit channel 7 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_TXINTMASKCLEAR_TX7MASK BSP_FLD32(7)
+#define TMS570_EMACM_TXINTMASKCLEAR_TX7MASK BSP_BIT32(7)
 
 /* field: TX6MASK - Transmit channel 6 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_TXINTMASKCLEAR_TX6MASK BSP_FLD32(6)
+#define TMS570_EMACM_TXINTMASKCLEAR_TX6MASK BSP_BIT32(6)
 
 /* field: TX5MASK - Transmit channel 5 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_TXINTMASKCLEAR_TX5MASK BSP_FLD32(5)
+#define TMS570_EMACM_TXINTMASKCLEAR_TX5MASK BSP_BIT32(5)
 
 /* field: TX4MASK - Transmit channel 4 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_TXINTMASKCLEAR_TX4MASK BSP_FLD32(4)
+#define TMS570_EMACM_TXINTMASKCLEAR_TX4MASK BSP_BIT32(4)
 
 /* field: TX3MASK - Transmit channel 3 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_TXINTMASKCLEAR_TX3MASK BSP_FLD32(3)
+#define TMS570_EMACM_TXINTMASKCLEAR_TX3MASK BSP_BIT32(3)
 
 /* field: TX2MASK - Transmit channel 2 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_TXINTMASKCLEAR_TX2MASK BSP_FLD32(2)
+#define TMS570_EMACM_TXINTMASKCLEAR_TX2MASK BSP_BIT32(2)
 
 /* field: TX1MASK - Transmit channel 1 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_TXINTMASKCLEAR_TX1MASK BSP_FLD32(1)
+#define TMS570_EMACM_TXINTMASKCLEAR_TX1MASK BSP_BIT32(1)
 
 /* field: TX0MASK - Transmit channel 0 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_TXINTMASKCLEAR_TX0MASK BSP_FLD32(0)
+#define TMS570_EMACM_TXINTMASKCLEAR_TX0MASK BSP_BIT32(0)
 
 
-/*------------------TMS570_EMACMMACINVECTOR------------------*/
+/*------------------TMS570_EMACM_MACINVECTOR------------------*/
 /* field: STATPEND - EMAC module statistics interrupt (STATPEND) pending status bit */
-#define TMS570_EMACM_MACINVECTOR_STATPEND BSP_FLD32(27)
+#define TMS570_EMACM_MACINVECTOR_STATPEND BSP_BIT32(27)
 
 /* field: HOSTPEND - EMAC module host error interrupt (HOSTPEND) pending status bit */
-#define TMS570_EMACM_MACINVECTOR_HOSTPEND BSP_FLD32(26)
+#define TMS570_EMACM_MACINVECTOR_HOSTPEND BSP_BIT32(26)
 
 /* field: LINKINT0 - MDIO module USERPHYSEL0 (LINKINT0) status bit */
-#define TMS570_EMACM_MACINVECTOR_LINKINT0 BSP_FLD32(25)
+#define TMS570_EMACM_MACINVECTOR_LINKINT0 BSP_BIT32(25)
 
 /* field: USERINT0 - MDIO module USERACCESS0 (USERINT0) status bit */
-#define TMS570_EMACM_MACINVECTOR_USERINT0 BSP_FLD32(24)
+#define TMS570_EMACM_MACINVECTOR_USERINT0 BSP_BIT32(24)
 
 /* field: TXPEND - Transmit channels 0-7 interrupt (TXnPEND) pending status. Bit 16 is TX0PEND. */
 #define TMS570_EMACM_MACINVECTOR_TXPEND(val) BSP_FLD32(val,16, 23)
@@ -273,266 +267,266 @@ typedef struct{
 #define TMS570_EMACM_MACINVECTOR_RXPEND_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*------------------TMS570_EMACMMACEOIVECTOR------------------*/
+/*-----------------TMS570_EMACM_MACEOIVECTOR-----------------*/
 /* field: INTVECT - Acknowledge EMAC Control Module Interrupts */
 #define TMS570_EMACM_MACEOIVECTOR_INTVECT(val) BSP_FLD32(val,0, 4)
 #define TMS570_EMACM_MACEOIVECTOR_INTVECT_GET(reg) BSP_FLD32GET(reg,0, 4)
 #define TMS570_EMACM_MACEOIVECTOR_INTVECT_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
 
 
-/*------------------TMS570_EMACMRXINTSTATRAW------------------*/
+/*-----------------TMS570_EMACM_RXINTSTATRAW-----------------*/
 /* field: RX7THRESHPEND - RX7THRESHPEND raw interrupt read (before mask) */
-#define TMS570_EMACM_RXINTSTATRAW_RX7THRESHPEND BSP_FLD32(15)
+#define TMS570_EMACM_RXINTSTATRAW_RX7THRESHPEND BSP_BIT32(15)
 
 /* field: RX6THRESHPEND - RX6THRESHPEND raw interrupt read (before mask) */
-#define TMS570_EMACM_RXINTSTATRAW_RX6THRESHPEND BSP_FLD32(14)
+#define TMS570_EMACM_RXINTSTATRAW_RX6THRESHPEND BSP_BIT32(14)
 
 /* field: RX5THRESHPEND - RX5THRESHPEND raw interrupt read (before mask) */
-#define TMS570_EMACM_RXINTSTATRAW_RX5THRESHPEND BSP_FLD32(13)
+#define TMS570_EMACM_RXINTSTATRAW_RX5THRESHPEND BSP_BIT32(13)
 
 /* field: RX4THRESHPEND - RX4THRESHPEND raw interrupt read (before mask) */
-#define TMS570_EMACM_RXINTSTATRAW_RX4THRESHPEND BSP_FLD32(12)
+#define TMS570_EMACM_RXINTSTATRAW_RX4THRESHPEND BSP_BIT32(12)
 
 /* field: RX3THRESHPEND - RX3THRESHPEND raw interrupt read (before mask) */
-#define TMS570_EMACM_RXINTSTATRAW_RX3THRESHPEND BSP_FLD32(11)
+#define TMS570_EMACM_RXINTSTATRAW_RX3THRESHPEND BSP_BIT32(11)
 
 /* field: RX2THRESHPEND - RX2THRESHPEND raw interrupt read (before mask) */
-#define TMS570_EMACM_RXINTSTATRAW_RX2THRESHPEND BSP_FLD32(10)
+#define TMS570_EMACM_RXINTSTATRAW_RX2THRESHPEND BSP_BIT32(10)
 
 /* field: RX1THRESHPEND - RX1THRESHPEND raw interrupt read (before mask) */
-#define TMS570_EMACM_RXINTSTATRAW_RX1THRESHPEND BSP_FLD32(9)
+#define TMS570_EMACM_RXINTSTATRAW_RX1THRESHPEND BSP_BIT32(9)
 
 /* field: RX0THRESHPEND - RX0THRESHPEND raw interrupt read (before mask) */
-#define TMS570_EMACM_RXINTSTATRAW_RX0THRESHPEND BSP_FLD32(8)
+#define TMS570_EMACM_RXINTSTATRAW_RX0THRESHPEND BSP_BIT32(8)
 
 /* field: RX7PEND - RX7PEND raw interrupt read (before mask) */
-#define TMS570_EMACM_RXINTSTATRAW_RX7PEND BSP_FLD32(7)
+#define TMS570_EMACM_RXINTSTATRAW_RX7PEND BSP_BIT32(7)
 
 /* field: RX6PEND - RX6PEND raw interrupt read (before mask) */
-#define TMS570_EMACM_RXINTSTATRAW_RX6PEND BSP_FLD32(6)
+#define TMS570_EMACM_RXINTSTATRAW_RX6PEND BSP_BIT32(6)
 
 /* field: RX5PEND - RX5PEND raw interrupt read (before mask) */
-#define TMS570_EMACM_RXINTSTATRAW_RX5PEND BSP_FLD32(5)
+#define TMS570_EMACM_RXINTSTATRAW_RX5PEND BSP_BIT32(5)
 
 /* field: RX4PEND - RX4PEND raw interrupt read (before mask) */
-#define TMS570_EMACM_RXINTSTATRAW_RX4PEND BSP_FLD32(4)
+#define TMS570_EMACM_RXINTSTATRAW_RX4PEND BSP_BIT32(4)
 
 /* field: RX3PEND - RX3PEND raw interrupt read (before mask) */
-#define TMS570_EMACM_RXINTSTATRAW_RX3PEND BSP_FLD32(3)
+#define TMS570_EMACM_RXINTSTATRAW_RX3PEND BSP_BIT32(3)
 
 /* field: RX2PEND - RX2PEND raw interrupt read (before mask) */
-#define TMS570_EMACM_RXINTSTATRAW_RX2PEND BSP_FLD32(2)
+#define TMS570_EMACM_RXINTSTATRAW_RX2PEND BSP_BIT32(2)
 
 /* field: RX1PEND - RX1PEND raw interrupt read (before mask) */
-#define TMS570_EMACM_RXINTSTATRAW_RX1PEND BSP_FLD32(1)
+#define TMS570_EMACM_RXINTSTATRAW_RX1PEND BSP_BIT32(1)
 
 /* field: RX0PEND - RX0PEND raw interrupt read (before mask) */
-#define TMS570_EMACM_RXINTSTATRAW_RX0PEND BSP_FLD32(0)
+#define TMS570_EMACM_RXINTSTATRAW_RX0PEND BSP_BIT32(0)
 
 
-/*----------------TMS570_EMACMRXINTSTATMASKED----------------*/
+/*----------------TMS570_EMACM_RXINTSTATMASKED----------------*/
 /* field: RX7THRESHPEND - RX7THRESHPEND masked interrupt read */
-#define TMS570_EMACM_RXINTSTATMASKED_RX7THRESHPEND BSP_FLD32(15)
+#define TMS570_EMACM_RXINTSTATMASKED_RX7THRESHPEND BSP_BIT32(15)
 
 /* field: RX6THRESHPEND - RX6THRESHPEND masked interrupt read */
-#define TMS570_EMACM_RXINTSTATMASKED_RX6THRESHPEND BSP_FLD32(14)
+#define TMS570_EMACM_RXINTSTATMASKED_RX6THRESHPEND BSP_BIT32(14)
 
 /* field: RX5THRESHPEND - RX5THRESHPEND masked interrupt read */
-#define TMS570_EMACM_RXINTSTATMASKED_RX5THRESHPEND BSP_FLD32(13)
+#define TMS570_EMACM_RXINTSTATMASKED_RX5THRESHPEND BSP_BIT32(13)
 
 /* field: RX4THRESHPEND - RX4THRESHPEND masked interrupt read */
-#define TMS570_EMACM_RXINTSTATMASKED_RX4THRESHPEND BSP_FLD32(12)
+#define TMS570_EMACM_RXINTSTATMASKED_RX4THRESHPEND BSP_BIT32(12)
 
 /* field: RX3THRESHPEND - RX3THRESHPEND masked interrupt read */
-#define TMS570_EMACM_RXINTSTATMASKED_RX3THRESHPEND BSP_FLD32(11)
+#define TMS570_EMACM_RXINTSTATMASKED_RX3THRESHPEND BSP_BIT32(11)
 
 /* field: RX2THRESHPEND - RX2THRESHPEND masked interrupt read */
-#define TMS570_EMACM_RXINTSTATMASKED_RX2THRESHPEND BSP_FLD32(10)
+#define TMS570_EMACM_RXINTSTATMASKED_RX2THRESHPEND BSP_BIT32(10)
 
 /* field: RX1THRESHPEND - RX1THRESHPEND masked interrupt read */
-#define TMS570_EMACM_RXINTSTATMASKED_RX1THRESHPEND BSP_FLD32(9)
+#define TMS570_EMACM_RXINTSTATMASKED_RX1THRESHPEND BSP_BIT32(9)
 
 /* field: RX0THRESHPEND - RX0THRESHPEND masked interrupt read */
-#define TMS570_EMACM_RXINTSTATMASKED_RX0THRESHPEND BSP_FLD32(8)
+#define TMS570_EMACM_RXINTSTATMASKED_RX0THRESHPEND BSP_BIT32(8)
 
 /* field: RX7PEND - RX7PEND masked interrupt read */
-#define TMS570_EMACM_RXINTSTATMASKED_RX7PEND BSP_FLD32(7)
+#define TMS570_EMACM_RXINTSTATMASKED_RX7PEND BSP_BIT32(7)
 
 /* field: RX6PEND - RX6PEND masked interrupt read */
-#define TMS570_EMACM_RXINTSTATMASKED_RX6PEND BSP_FLD32(6)
+#define TMS570_EMACM_RXINTSTATMASKED_RX6PEND BSP_BIT32(6)
 
 /* field: RX5PEND - RX5PEND masked interrupt read */
-#define TMS570_EMACM_RXINTSTATMASKED_RX5PEND BSP_FLD32(5)
+#define TMS570_EMACM_RXINTSTATMASKED_RX5PEND BSP_BIT32(5)
 
 /* field: RX4PEND - RX4PEND masked interrupt read */
-#define TMS570_EMACM_RXINTSTATMASKED_RX4PEND BSP_FLD32(4)
+#define TMS570_EMACM_RXINTSTATMASKED_RX4PEND BSP_BIT32(4)
 
 /* field: RX3PEND - RX3PEND masked interrupt read */
-#define TMS570_EMACM_RXINTSTATMASKED_RX3PEND BSP_FLD32(3)
+#define TMS570_EMACM_RXINTSTATMASKED_RX3PEND BSP_BIT32(3)
 
 /* field: RX2PEND - RX2PEND masked interrupt read */
-#define TMS570_EMACM_RXINTSTATMASKED_RX2PEND BSP_FLD32(2)
+#define TMS570_EMACM_RXINTSTATMASKED_RX2PEND BSP_BIT32(2)
 
 /* field: RX1PEND - RX1PEND masked interrupt read */
-#define TMS570_EMACM_RXINTSTATMASKED_RX1PEND BSP_FLD32(1)
+#define TMS570_EMACM_RXINTSTATMASKED_RX1PEND BSP_BIT32(1)
 
 /* field: RX0PEND - RX0PEND masked interrupt read */
-#define TMS570_EMACM_RXINTSTATMASKED_RX0PEND BSP_FLD32(0)
+#define TMS570_EMACM_RXINTSTATMASKED_RX0PEND BSP_BIT32(0)
 
 
-/*------------------TMS570_EMACMRXINTMASKSET------------------*/
+/*-----------------TMS570_EMACM_RXINTMASKSET-----------------*/
 /* field: RX7THRESHMASK - Receive channel 7 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKSET_RX7THRESHMASK BSP_FLD32(15)
+#define TMS570_EMACM_RXINTMASKSET_RX7THRESHMASK BSP_BIT32(15)
 
 /* field: RX6THRESHMASK - Receive channel 6 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKSET_RX6THRESHMASK BSP_FLD32(14)
+#define TMS570_EMACM_RXINTMASKSET_RX6THRESHMASK BSP_BIT32(14)
 
 /* field: RX5THRESHMASK - Receive channel 5 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKSET_RX5THRESHMASK BSP_FLD32(13)
+#define TMS570_EMACM_RXINTMASKSET_RX5THRESHMASK BSP_BIT32(13)
 
 /* field: RX4THRESHMASK - Receive channel 4 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKSET_RX4THRESHMASK BSP_FLD32(12)
+#define TMS570_EMACM_RXINTMASKSET_RX4THRESHMASK BSP_BIT32(12)
 
 /* field: RX3THRESHMASK - Receive channel 3 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKSET_RX3THRESHMASK BSP_FLD32(11)
+#define TMS570_EMACM_RXINTMASKSET_RX3THRESHMASK BSP_BIT32(11)
 
 /* field: RX2THRESHMASK - Receive channel 2 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKSET_RX2THRESHMASK BSP_FLD32(10)
+#define TMS570_EMACM_RXINTMASKSET_RX2THRESHMASK BSP_BIT32(10)
 
 /* field: RX1THRESHMASK - Receive channel 1 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKSET_RX1THRESHMASK BSP_FLD32(9)
+#define TMS570_EMACM_RXINTMASKSET_RX1THRESHMASK BSP_BIT32(9)
 
 /* field: RX0THRESHMASK - Receive channel 0 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKSET_RX0THRESHMASK BSP_FLD32(8)
+#define TMS570_EMACM_RXINTMASKSET_RX0THRESHMASK BSP_BIT32(8)
 
 /* field: RX7MASK - Receive channel 7 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKSET_RX7MASK BSP_FLD32(7)
+#define TMS570_EMACM_RXINTMASKSET_RX7MASK BSP_BIT32(7)
 
 /* field: RX6MASK - Receive channel 6 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKSET_RX6MASK BSP_FLD32(6)
+#define TMS570_EMACM_RXINTMASKSET_RX6MASK BSP_BIT32(6)
 
 /* field: RX5MASK - Receive channel 5 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKSET_RX5MASK BSP_FLD32(5)
+#define TMS570_EMACM_RXINTMASKSET_RX5MASK BSP_BIT32(5)
 
 /* field: RX4MASK - Receive channel 4 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKSET_RX4MASK BSP_FLD32(4)
+#define TMS570_EMACM_RXINTMASKSET_RX4MASK BSP_BIT32(4)
 
 /* field: RX3MASK - Receive channel 3 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKSET_RX3MASK BSP_FLD32(3)
+#define TMS570_EMACM_RXINTMASKSET_RX3MASK BSP_BIT32(3)
 
 /* field: RX2MASK - Receive channel 2 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKSET_RX2MASK BSP_FLD32(2)
+#define TMS570_EMACM_RXINTMASKSET_RX2MASK BSP_BIT32(2)
 
 /* field: RX1MASK - Receive channel 1 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKSET_RX1MASK BSP_FLD32(1)
+#define TMS570_EMACM_RXINTMASKSET_RX1MASK BSP_BIT32(1)
 
 /* field: RX0MASK - Receive channel 0 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKSET_RX0MASK BSP_FLD32(0)
+#define TMS570_EMACM_RXINTMASKSET_RX0MASK BSP_BIT32(0)
 
 
-/*-----------------TMS570_EMACMRXINTMASKCLEAR-----------------*/
+/*----------------TMS570_EMACM_RXINTMASKCLEAR----------------*/
 /* field: RX7THRESHMASK - Receive channel 7 threshold mask clear bit. */
-#define TMS570_EMACM_RXINTMASKCLEAR_RX7THRESHMASK BSP_FLD32(15)
+#define TMS570_EMACM_RXINTMASKCLEAR_RX7THRESHMASK BSP_BIT32(15)
 
 /* field: RX6THRESHMASK - Receive channel 6 threshold mask clear bit. */
-#define TMS570_EMACM_RXINTMASKCLEAR_RX6THRESHMASK BSP_FLD32(14)
+#define TMS570_EMACM_RXINTMASKCLEAR_RX6THRESHMASK BSP_BIT32(14)
 
 /* field: RX5THRESHMASK - Receive channel 5 threshold mask clear bit. */
-#define TMS570_EMACM_RXINTMASKCLEAR_RX5THRESHMASK BSP_FLD32(13)
+#define TMS570_EMACM_RXINTMASKCLEAR_RX5THRESHMASK BSP_BIT32(13)
 
 /* field: RX4THRESHMASK - Receive channel 4 threshold mask clear bit. */
-#define TMS570_EMACM_RXINTMASKCLEAR_RX4THRESHMASK BSP_FLD32(12)
+#define TMS570_EMACM_RXINTMASKCLEAR_RX4THRESHMASK BSP_BIT32(12)
 
 /* field: RX3THRESHMASK - Receive channel 3 threshold mask clear bit. */
-#define TMS570_EMACM_RXINTMASKCLEAR_RX3THRESHMASK BSP_FLD32(11)
+#define TMS570_EMACM_RXINTMASKCLEAR_RX3THRESHMASK BSP_BIT32(11)
 
 /* field: RX2THRESHMASK - Receive channel 2 threshold mask clear bit. */
-#define TMS570_EMACM_RXINTMASKCLEAR_RX2THRESHMASK BSP_FLD32(10)
+#define TMS570_EMACM_RXINTMASKCLEAR_RX2THRESHMASK BSP_BIT32(10)
 
 /* field: RX1THRESHMASK - Receive channel 1 threshold mask clear bit. */
-#define TMS570_EMACM_RXINTMASKCLEAR_RX1THRESHMASK BSP_FLD32(9)
+#define TMS570_EMACM_RXINTMASKCLEAR_RX1THRESHMASK BSP_BIT32(9)
 
 /* field: RX0THRESHMASK - Receive channel 0 threshold mask clear bit. */
-#define TMS570_EMACM_RXINTMASKCLEAR_RX0THRESHMASK BSP_FLD32(8)
+#define TMS570_EMACM_RXINTMASKCLEAR_RX0THRESHMASK BSP_BIT32(8)
 
 /* field: RX7MASK - Receive channel 7 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKCLEAR_RX7MASK BSP_FLD32(7)
+#define TMS570_EMACM_RXINTMASKCLEAR_RX7MASK BSP_BIT32(7)
 
 /* field: RX6MASK - Receive channel 6 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKCLEAR_RX6MASK BSP_FLD32(6)
+#define TMS570_EMACM_RXINTMASKCLEAR_RX6MASK BSP_BIT32(6)
 
 /* field: RX5MASK - Receive channel 5 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKCLEAR_RX5MASK BSP_FLD32(5)
+#define TMS570_EMACM_RXINTMASKCLEAR_RX5MASK BSP_BIT32(5)
 
 /* field: RX4MASK - Receive channel 4 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKCLEAR_RX4MASK BSP_FLD32(4)
+#define TMS570_EMACM_RXINTMASKCLEAR_RX4MASK BSP_BIT32(4)
 
 /* field: RX3MASK - Receive channel 3 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKCLEAR_RX3MASK BSP_FLD32(3)
+#define TMS570_EMACM_RXINTMASKCLEAR_RX3MASK BSP_BIT32(3)
 
 /* field: RX2MASK - Receive channel 2 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKCLEAR_RX2MASK BSP_FLD32(2)
+#define TMS570_EMACM_RXINTMASKCLEAR_RX2MASK BSP_BIT32(2)
 
 /* field: RX1MASK - Receive channel 1 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKCLEAR_RX1MASK BSP_FLD32(1)
+#define TMS570_EMACM_RXINTMASKCLEAR_RX1MASK BSP_BIT32(1)
 
 /* field: RX0MASK - Receive channel 0 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKCLEAR_RX0MASK BSP_FLD32(0)
+#define TMS570_EMACM_RXINTMASKCLEAR_RX0MASK BSP_BIT32(0)
 
 
-/*-----------------TMS570_EMACMMACINTSTATRAW-----------------*/
+/*-----------------TMS570_EMACM_MACINTSTATRAW-----------------*/
 /* field: HOSTPEND - Host pending interrupt (HOSTPEND); raw interrupt read (before mask). */
-#define TMS570_EMACM_MACINTSTATRAW_HOSTPEND BSP_FLD32(1)
+#define TMS570_EMACM_MACINTSTATRAW_HOSTPEND BSP_BIT32(1)
 
 /* field: STATPEND - Statistics pending interrupt (STATPEND); raw interrupt read (before mask). */
-#define TMS570_EMACM_MACINTSTATRAW_STATPEND BSP_FLD32(0)
+#define TMS570_EMACM_MACINTSTATRAW_STATPEND BSP_BIT32(0)
 
 
-/*----------------TMS570_EMACMMACINTSTATMASKED----------------*/
+/*---------------TMS570_EMACM_MACINTSTATMASKED---------------*/
 /* field: HOSTPEND - Host pending interrupt (HOSTPEND); masked interrupt read. */
-#define TMS570_EMACM_MACINTSTATMASKED_HOSTPEND BSP_FLD32(1)
+#define TMS570_EMACM_MACINTSTATMASKED_HOSTPEND BSP_BIT32(1)
 
 /* field: STATPEND - Statistics pending interrupt (STATPEND); masked interrupt read. */
-#define TMS570_EMACM_MACINTSTATMASKED_STATPEND BSP_FLD32(0)
+#define TMS570_EMACM_MACINTSTATMASKED_STATPEND BSP_BIT32(0)
 
 
-/*-----------------TMS570_EMACMMACINTMASKSET-----------------*/
+/*-----------------TMS570_EMACM_MACINTMASKSET-----------------*/
 /* field: HOSTMASK - Host error interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_MACINTMASKSET_HOSTMASK BSP_FLD32(1)
+#define TMS570_EMACM_MACINTMASKSET_HOSTMASK BSP_BIT32(1)
 
 /* field: STATMASK - Statistics interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_MACINTMASKSET_STATMASK BSP_FLD32(0)
+#define TMS570_EMACM_MACINTMASKSET_STATMASK BSP_BIT32(0)
 
 
-/*----------------TMS570_EMACMMACINTMASKCLEAR----------------*/
+/*----------------TMS570_EMACM_MACINTMASKCLEAR----------------*/
 /* field: HOSTMASK - Host error interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_MACINTMASKCLEAR_HOSTMASK BSP_FLD32(1)
+#define TMS570_EMACM_MACINTMASKCLEAR_HOSTMASK BSP_BIT32(1)
 
 /* field: STATMASK - Statistics interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_MACINTMASKCLEAR_STATMASK BSP_FLD32(0)
+#define TMS570_EMACM_MACINTMASKCLEAR_STATMASK BSP_BIT32(0)
 
 
-/*------------------TMS570_EMACMRXMBPENABLE------------------*/
+/*------------------TMS570_EMACM_RXMBPENABLE------------------*/
 /* field: RXPASSCRC - Pass receive CRC enable bit */
-#define TMS570_EMACM_RXMBPENABLE_RXPASSCRC BSP_FLD32(30)
+#define TMS570_EMACM_RXMBPENABLE_RXPASSCRC BSP_BIT32(30)
 
 /* field: RXQOSEN - Receive quality of service enable bit */
-#define TMS570_EMACM_RXMBPENABLE_RXQOSEN BSP_FLD32(29)
+#define TMS570_EMACM_RXMBPENABLE_RXQOSEN BSP_BIT32(29)
 
 /* field: RXNOCHAIN - Receive no buffer chaining bit */
-#define TMS570_EMACM_RXMBPENABLE_RXNOCHAIN BSP_FLD32(28)
+#define TMS570_EMACM_RXMBPENABLE_RXNOCHAIN BSP_BIT32(28)
 
 /* field: RXCMFEN - Receive copy MAC control frames enable bit. */
-#define TMS570_EMACM_RXMBPENABLE_RXCMFEN BSP_FLD32(24)
+#define TMS570_EMACM_RXMBPENABLE_RXCMFEN BSP_BIT32(24)
 
 /* field: RXCSFEN - Receive copy short frames enable bit. */
-#define TMS570_EMACM_RXMBPENABLE_RXCSFEN BSP_FLD32(23)
+#define TMS570_EMACM_RXMBPENABLE_RXCSFEN BSP_BIT32(23)
 
 /* field: RXCEFEN - Receive copy error frames enable bit. */
-#define TMS570_EMACM_RXMBPENABLE_RXCEFEN BSP_FLD32(22)
+#define TMS570_EMACM_RXMBPENABLE_RXCEFEN BSP_BIT32(22)
 
 /* field: RXCAFEN - Receive copy all frames enable bit. */
-#define TMS570_EMACM_RXMBPENABLE_RXCAFEN BSP_FLD32(21)
+#define TMS570_EMACM_RXMBPENABLE_RXCAFEN BSP_BIT32(21)
 
 /* field: RXPROMCH - Receive promiscuous channel select */
 #define TMS570_EMACM_RXMBPENABLE_RXPROMCH(val) BSP_FLD32(val,16, 18)
@@ -540,7 +534,7 @@ typedef struct{
 #define TMS570_EMACM_RXMBPENABLE_RXPROMCH_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
 
 /* field: RXBROADEN - Receive broadcast enable. */
-#define TMS570_EMACM_RXMBPENABLE_RXBROADEN BSP_FLD32(13)
+#define TMS570_EMACM_RXMBPENABLE_RXBROADEN BSP_BIT32(13)
 
 /* field: RXBROADCH - Receive broadcast channel select */
 #define TMS570_EMACM_RXMBPENABLE_RXBROADCH(val) BSP_FLD32(val,8, 10)
@@ -548,137 +542,137 @@ typedef struct{
 #define TMS570_EMACM_RXMBPENABLE_RXBROADCH_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
 
 /* field: RXMULTEN - RX multicast enable. */
-#define TMS570_EMACM_RXMBPENABLE_RXMULTEN BSP_FLD32(5)
+#define TMS570_EMACM_RXMBPENABLE_RXMULTEN BSP_BIT32(5)
 
 
-/*------------------TMS570_EMACMRXUNICASTSET------------------*/
+/*-----------------TMS570_EMACM_RXUNICASTSET-----------------*/
 /* field: RXCH7EN - Receive channel 7 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
-#define TMS570_EMACM_RXUNICASTSET_RXCH7EN BSP_FLD32(7)
+#define TMS570_EMACM_RXUNICASTSET_RXCH7EN BSP_BIT32(7)
 
 /* field: RXCH6EN - Receive channel 6 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
-#define TMS570_EMACM_RXUNICASTSET_RXCH6EN BSP_FLD32(6)
+#define TMS570_EMACM_RXUNICASTSET_RXCH6EN BSP_BIT32(6)
 
 /* field: RXCH5EN - Receive channel 5 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
-#define TMS570_EMACM_RXUNICASTSET_RXCH5EN BSP_FLD32(5)
+#define TMS570_EMACM_RXUNICASTSET_RXCH5EN BSP_BIT32(5)
 
 /* field: RXCH4EN - Receive channel 4 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
-#define TMS570_EMACM_RXUNICASTSET_RXCH4EN BSP_FLD32(4)
+#define TMS570_EMACM_RXUNICASTSET_RXCH4EN BSP_BIT32(4)
 
 /* field: RXCH3EN - Receive channel 3 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
-#define TMS570_EMACM_RXUNICASTSET_RXCH3EN BSP_FLD32(3)
+#define TMS570_EMACM_RXUNICASTSET_RXCH3EN BSP_BIT32(3)
 
 /* field: RXCH2EN - Receive channel 2 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
-#define TMS570_EMACM_RXUNICASTSET_RXCH2EN BSP_FLD32(2)
+#define TMS570_EMACM_RXUNICASTSET_RXCH2EN BSP_BIT32(2)
 
 /* field: RXCH1EN - Receive channel 1 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
-#define TMS570_EMACM_RXUNICASTSET_RXCH1EN BSP_FLD32(1)
+#define TMS570_EMACM_RXUNICASTSET_RXCH1EN BSP_BIT32(1)
 
 /* field: RXCH0EN - Receive channel 0 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
-#define TMS570_EMACM_RXUNICASTSET_RXCH0EN BSP_FLD32(0)
+#define TMS570_EMACM_RXUNICASTSET_RXCH0EN BSP_BIT32(0)
 
 
-/*-----------------TMS570_EMACMRXUNICASTCLEAR-----------------*/
+/*----------------TMS570_EMACM_RXUNICASTCLEAR----------------*/
 /* field: RXCH7EN - Receive channel 7 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
-#define TMS570_EMACM_RXUNICASTCLEAR_RXCH7EN BSP_FLD32(7)
+#define TMS570_EMACM_RXUNICASTCLEAR_RXCH7EN BSP_BIT32(7)
 
 /* field: RXCH6EN - Receive channel 6 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
-#define TMS570_EMACM_RXUNICASTCLEAR_RXCH6EN BSP_FLD32(6)
+#define TMS570_EMACM_RXUNICASTCLEAR_RXCH6EN BSP_BIT32(6)
 
 /* field: RXCH5EN - Receive channel 5 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
-#define TMS570_EMACM_RXUNICASTCLEAR_RXCH5EN BSP_FLD32(5)
+#define TMS570_EMACM_RXUNICASTCLEAR_RXCH5EN BSP_BIT32(5)
 
 /* field: RXCH4EN - Receive channel 4 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
-#define TMS570_EMACM_RXUNICASTCLEAR_RXCH4EN BSP_FLD32(4)
+#define TMS570_EMACM_RXUNICASTCLEAR_RXCH4EN BSP_BIT32(4)
 
 /* field: RXCH3EN - Receive channel 3 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
-#define TMS570_EMACM_RXUNICASTCLEAR_RXCH3EN BSP_FLD32(3)
+#define TMS570_EMACM_RXUNICASTCLEAR_RXCH3EN BSP_BIT32(3)
 
 /* field: RXCH2EN - Receive channel 2 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
-#define TMS570_EMACM_RXUNICASTCLEAR_RXCH2EN BSP_FLD32(2)
+#define TMS570_EMACM_RXUNICASTCLEAR_RXCH2EN BSP_BIT32(2)
 
 /* field: RXCH1EN - Receive channel 1 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
-#define TMS570_EMACM_RXUNICASTCLEAR_RXCH1EN BSP_FLD32(1)
+#define TMS570_EMACM_RXUNICASTCLEAR_RXCH1EN BSP_BIT32(1)
 
 /* field: RXCH0EN - Receive channel 0 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
-#define TMS570_EMACM_RXUNICASTCLEAR_RXCH0EN BSP_FLD32(0)
+#define TMS570_EMACM_RXUNICASTCLEAR_RXCH0EN BSP_BIT32(0)
 
 
-/*--------------------TMS570_EMACMRXMAXLEN--------------------*/
+/*-------------------TMS570_EMACM_RXMAXLEN-------------------*/
 /* field: RXMAXLEN - Receive maximum frame length. These bits determine the maximum length of a received frame. */
 #define TMS570_EMACM_RXMAXLEN_RXMAXLEN(val) BSP_FLD32(val,0, 15)
 #define TMS570_EMACM_RXMAXLEN_RXMAXLEN_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_EMACM_RXMAXLEN_RXMAXLEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*-----------------TMS570_EMACMRXBUFFEROFFSET-----------------*/
+/*----------------TMS570_EMACM_RXBUFFEROFFSET----------------*/
 /* field: RXBUFFEROFFSET - Receive buffer offset value. */
 #define TMS570_EMACM_RXBUFFEROFFSET_RXBUFFEROFFSET(val) BSP_FLD32(val,0, 15)
 #define TMS570_EMACM_RXBUFFEROFFSET_RXBUFFEROFFSET_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_EMACM_RXBUFFEROFFSET_RXBUFFEROFFSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------TMS570_EMACMRXFILTERLOWTHRESH---------------*/
+/*---------------TMS570_EMACM_RXFILTERLOWTHRESH---------------*/
 /* field: RXFILTERTHRESH - Receive filter low threshold. */
 #define TMS570_EMACM_RXFILTERLOWTHRESH_RXFILTERTHRESH(val) BSP_FLD32(val,0, 7)
 #define TMS570_EMACM_RXFILTERLOWTHRESH_RXFILTERTHRESH_GET(reg) BSP_FLD32GET(reg,0, 7)
 #define TMS570_EMACM_RXFILTERLOWTHRESH_RXFILTERTHRESH_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*------------------TMS570_EMACMRXFLOWTHRESH------------------*/
+/*-----------------TMS570_EMACM_RXFLOWTHRESH-----------------*/
 /* field: RXnFLOWTHRESH - Receive flow threshold. */
 #define TMS570_EMACM_RXFLOWTHRESH_RXnFLOWTHRESH(val) BSP_FLD32(val,0, 7)
 #define TMS570_EMACM_RXFLOWTHRESH_RXnFLOWTHRESH_GET(reg) BSP_FLD32GET(reg,0, 7)
 #define TMS570_EMACM_RXFLOWTHRESH_RXnFLOWTHRESH_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*------------------TMS570_EMACMRXFREEBUFFER------------------*/
+/*-----------------TMS570_EMACM_RXFREEBUFFER-----------------*/
 /* field: RXnFREEBUF - Receive free buffer count. These bits contain the count of free buffers available. */
 #define TMS570_EMACM_RXFREEBUFFER_RXnFREEBUF(val) BSP_FLD32(val,0, 15)
 #define TMS570_EMACM_RXFREEBUFFER_RXnFREEBUF_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_EMACM_RXFREEBUFFER_RXnFREEBUF_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*-------------------TMS570_EMACMMACCONTROL-------------------*/
+/*------------------TMS570_EMACM_MACCONTROL------------------*/
 /* field: RMIISPEED - RMII interface transmit and receive speed select. */
-#define TMS570_EMACM_MACCONTROL_RMIISPEED BSP_FLD32(15)
+#define TMS570_EMACM_MACCONTROL_RMIISPEED BSP_BIT32(15)
 
 /* field: RXOFFLENBLOCK - Receive offset / length word write block. */
-#define TMS570_EMACM_MACCONTROL_RXOFFLENBLOCK BSP_FLD32(14)
+#define TMS570_EMACM_MACCONTROL_RXOFFLENBLOCK BSP_BIT32(14)
 
 /* field: RXOWNERSHIP - Receive ownership write bit value. */
-#define TMS570_EMACM_MACCONTROL_RXOWNERSHIP BSP_FLD32(13)
+#define TMS570_EMACM_MACCONTROL_RXOWNERSHIP BSP_BIT32(13)
 
 /* field: CMDIDLE - Command Idle bit */
-#define TMS570_EMACM_MACCONTROL_CMDIDLE BSP_FLD32(11)
+#define TMS570_EMACM_MACCONTROL_CMDIDLE BSP_BIT32(11)
 
 /* field: TXSHORTGAPEN - Transmit Short Gap Enable */
-#define TMS570_EMACM_MACCONTROL_TXSHORTGAPEN BSP_FLD32(10)
+#define TMS570_EMACM_MACCONTROL_TXSHORTGAPEN BSP_BIT32(10)
 
 /* field: TXPTYPE - Transmit queue priority type */
-#define TMS570_EMACM_MACCONTROL_TXPTYPE BSP_FLD32(9)
+#define TMS570_EMACM_MACCONTROL_TXPTYPE BSP_BIT32(9)
 
 /* field: TXPACE - Transmit pacing enable bit */
-#define TMS570_EMACM_MACCONTROL_TXPACE BSP_FLD32(6)
+#define TMS570_EMACM_MACCONTROL_TXPACE BSP_BIT32(6)
 
 /* field: GMIIEN - GMII enable bit */
-#define TMS570_EMACM_MACCONTROL_GMIIEN BSP_FLD32(5)
+#define TMS570_EMACM_MACCONTROL_GMIIEN BSP_BIT32(5)
 
 /* field: TXFLOWEN - Transmit flow control enable bit. */
-#define TMS570_EMACM_MACCONTROL_TXFLOWEN BSP_FLD32(4)
+#define TMS570_EMACM_MACCONTROL_TXFLOWEN BSP_BIT32(4)
 
 /* field: RXBUFFERFLOWEN - Receive buffer flow control enable bit */
-#define TMS570_EMACM_MACCONTROL_RXBUFFERFLOWEN BSP_FLD32(3)
+#define TMS570_EMACM_MACCONTROL_RXBUFFERFLOWEN BSP_BIT32(3)
 
 /* field: LOOPBACK - Loopback mode. The loopback mode forces internal full-duplex mode regardless of the FULLDUPLEX bit. */
-#define TMS570_EMACM_MACCONTROL_LOOPBACK BSP_FLD32(1)
+#define TMS570_EMACM_MACCONTROL_LOOPBACK BSP_BIT32(1)
 
 /* field: FULLDUPLEX - Full duplex mode. */
-#define TMS570_EMACM_MACCONTROL_FULLDUPLEX BSP_FLD32(0)
+#define TMS570_EMACM_MACCONTROL_FULLDUPLEX BSP_BIT32(0)
 
 
-/*-------------------TMS570_EMACMMACSTATUS-------------------*/
+/*-------------------TMS570_EMACM_MACSTATUS-------------------*/
 /* field: IDLE - EMAC idle bit. This bit is cleared to 0 at reset; one clock after reset, it goes to 1. */
-#define TMS570_EMACM_MACSTATUS_IDLE BSP_FLD32(31)
+#define TMS570_EMACM_MACSTATUS_IDLE BSP_BIT32(31)
 
 /* field: TXERRCODE - Transmit host error code. These bits indicate that EMAC detected transmit DMA related host errors. */
 #define TMS570_EMACM_MACSTATUS_TXERRCODE(val) BSP_FLD32(val,20, 23)
@@ -701,31 +695,31 @@ typedef struct{
 #define TMS570_EMACM_MACSTATUS_RXERRCH_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
 
 /* field: RXQOSACT - Receive Quality of Service (QOS) active bit. */
-#define TMS570_EMACM_MACSTATUS_RXQOSACT BSP_FLD32(2)
+#define TMS570_EMACM_MACSTATUS_RXQOSACT BSP_BIT32(2)
 
 /* field: RXFLOWACT - Receive flow control active bit. */
-#define TMS570_EMACM_MACSTATUS_RXFLOWACT BSP_FLD32(1)
+#define TMS570_EMACM_MACSTATUS_RXFLOWACT BSP_BIT32(1)
 
 /* field: TXFLOWACT - Transmit flow control active bit. */
-#define TMS570_EMACM_MACSTATUS_TXFLOWACT BSP_FLD32(0)
+#define TMS570_EMACM_MACSTATUS_TXFLOWACT BSP_BIT32(0)
 
 
-/*-------------------TMS570_EMACMEMCONTROL-------------------*/
+/*-------------------TMS570_EMACM_EMCONTROL-------------------*/
 /* field: SOFT - Emulation soft bit. */
-#define TMS570_EMACM_EMCONTROL_SOFT BSP_FLD32(1)
+#define TMS570_EMACM_EMCONTROL_SOFT BSP_BIT32(1)
 
 /* field: FREE - Emulation free bit. */
-#define TMS570_EMACM_EMCONTROL_FREE BSP_FLD32(0)
+#define TMS570_EMACM_EMCONTROL_FREE BSP_BIT32(0)
 
 
-/*------------------TMS570_EMACMFIFOCONTROL------------------*/
+/*------------------TMS570_EMACM_FIFOCONTROL------------------*/
 /* field: TXCELLTHRESH - Transmit FIFO cell threshold. */
 #define TMS570_EMACM_FIFOCONTROL_TXCELLTHRESH(val) BSP_FLD32(val,0, 1)
 #define TMS570_EMACM_FIFOCONTROL_TXCELLTHRESH_GET(reg) BSP_FLD32GET(reg,0, 1)
 #define TMS570_EMACM_FIFOCONTROL_TXCELLTHRESH_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
 
 
-/*-------------------TMS570_EMACMMACCONFIG-------------------*/
+/*-------------------TMS570_EMACM_MACCONFIG-------------------*/
 /* field: TXCELLDEPTH - Transmit cell depth. These bits indicate the number of cells in the transmit FIFO. */
 #define TMS570_EMACM_MACCONFIG_TXCELLDEPTH(val) BSP_FLD32(val,24, 31)
 #define TMS570_EMACM_MACCONFIG_TXCELLDEPTH_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -747,12 +741,12 @@ typedef struct{
 #define TMS570_EMACM_MACCONFIG_MACCFIG_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*-------------------TMS570_EMACMSOFTRESET-------------------*/
+/*-------------------TMS570_EMACM_SOFTRESET-------------------*/
 /* field: SOFTRESET - Software reset. Writing a 1 to this bit causes the EMAC logic to be reset. */
-#define TMS570_EMACM_SOFTRESET_SOFTRESET BSP_FLD32(0)
+#define TMS570_EMACM_SOFTRESET_SOFTRESET BSP_BIT32(0)
 
 
-/*------------------TMS570_EMACMMACSRCADDRLO------------------*/
+/*-----------------TMS570_EMACM_MACSRCADDRLO-----------------*/
 /* field: MACSRCADDR0 - MAC source address lower 8-0 bits (byte 0) */
 #define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR0(val) BSP_FLD32(val,8, 15)
 #define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR0_GET(reg) BSP_FLD32GET(reg,8, 15)
@@ -764,7 +758,7 @@ typedef struct{
 #define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR1_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*------------------TMS570_EMACMMACSRCADDRHI------------------*/
+/*-----------------TMS570_EMACM_MACSRCADDRHI-----------------*/
 /* field: MACSRCADDR2 - MAC source address bits 23-16 (byte 2) */
 #define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR2(val) BSP_FLD32(val,24, 31)
 #define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR2_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -786,21 +780,15 @@ typedef struct{
 #define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR5_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*--------------------TMS570_EMACMMACHASH1--------------------*/
+/*-------------------TMS570_EMACM_MACHASH1-------------------*/
 /* field: MACHASH1 - Least-significant 32 bits of the hash table corresponding to hash values 0 to 31. */
-#define TMS570_EMACM_MACHASH1_MACHASH1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_EMACM_MACHASH1_MACHASH1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_EMACM_MACHASH1_MACHASH1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_EMACM_MACHASH2-------------------*/
-/*--------------------TMS570_EMACMMACHASH2--------------------*/
 /* field: MACHASH2 - Most-significant 32 bits of the hash table corresponding to hash values 32 to 63. */
-#define TMS570_EMACM_MACHASH2_MACHASH2(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_EMACM_MACHASH2_MACHASH2_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_EMACM_MACHASH2_MACHASH2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_EMACM_BOFFTEST-------------------*/
-/*--------------------TMS570_EMACMBOFFTEST--------------------*/
 /* field: RNDNUM - Backoff random number generator. */
 #define TMS570_EMACM_BOFFTEST_RNDNUM(val) BSP_FLD32(val,16, 25)
 #define TMS570_EMACM_BOFFTEST_RNDNUM_GET(reg) BSP_FLD32GET(reg,16, 25)
@@ -817,33 +805,33 @@ typedef struct{
 #define TMS570_EMACM_BOFFTEST_TXBACKOFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
 
 
-/*-------------------TMS570_EMACMTPACETEST-------------------*/
+/*-------------------TMS570_EMACM_TPACETEST-------------------*/
 /* field: PACEVAL - Pacing register current value. A nonzero value in this field indicates that transmit pacing is active. */
 #define TMS570_EMACM_TPACETEST_PACEVAL(val) BSP_FLD32(val,0, 4)
 #define TMS570_EMACM_TPACETEST_PACEVAL_GET(reg) BSP_FLD32GET(reg,0, 4)
 #define TMS570_EMACM_TPACETEST_PACEVAL_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
 
 
-/*--------------------TMS570_EMACMRXPAUSE--------------------*/
+/*--------------------TMS570_EMACM_RXPAUSE--------------------*/
 /* field: PAUSETIMER - Receive pause timer value. */
 #define TMS570_EMACM_RXPAUSE_PAUSETIMER(val) BSP_FLD32(val,0, 15)
 #define TMS570_EMACM_RXPAUSE_PAUSETIMER_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_EMACM_RXPAUSE_PAUSETIMER_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*--------------------TMS570_EMACMTXPAUSE--------------------*/
+/*--------------------TMS570_EMACM_TXPAUSE--------------------*/
 /* field: PAUSETIMER - Transmit pause timer value. */
 #define TMS570_EMACM_TXPAUSE_PAUSETIMER(val) BSP_FLD32(val,0, 15)
 #define TMS570_EMACM_TXPAUSE_PAUSETIMER_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_EMACM_TXPAUSE_PAUSETIMER_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*-------------------TMS570_EMACMMACADDRLO-------------------*/
+/*-------------------TMS570_EMACM_MACADDRLO-------------------*/
 /* field: VALID - Address valid bit. */
-#define TMS570_EMACM_MACADDRLO_VALID BSP_FLD32(20)
+#define TMS570_EMACM_MACADDRLO_VALID BSP_BIT32(20)
 
 /* field: MATCHFILT - Match or filter bit */
-#define TMS570_EMACM_MACADDRLO_MATCHFILT BSP_FLD32(19)
+#define TMS570_EMACM_MACADDRLO_MATCHFILT BSP_BIT32(19)
 
 /* field: CHANNEL - Channel select. Determines which receive channel a valid address match will be transferred to. */
 #define TMS570_EMACM_MACADDRLO_CHANNEL(val) BSP_FLD32(val,16, 18)
@@ -861,7 +849,7 @@ typedef struct{
 #define TMS570_EMACM_MACADDRLO_MACADDR1_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*-------------------TMS570_EMACMMACADDRHI-------------------*/
+/*-------------------TMS570_EMACM_MACADDRHI-------------------*/
 /* field: MACADDR2 - MAC source address bits 23-16 (byte 2) */
 #define TMS570_EMACM_MACADDRHI_MACADDR2(val) BSP_FLD32(val,24, 31)
 #define TMS570_EMACM_MACADDRHI_MACADDR2_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -883,40 +871,28 @@ typedef struct{
 #define TMS570_EMACM_MACADDRHI_MACADDR5_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*--------------------TMS570_EMACMMACINDEX--------------------*/
+/*-------------------TMS570_EMACM_MACINDEX-------------------*/
 /* field: MACINDEX - MAC address index. All eight addresses share the upper 40 bits. */
 #define TMS570_EMACM_MACINDEX_MACINDEX(val) BSP_FLD32(val,0, 2)
 #define TMS570_EMACM_MACINDEX_MACINDEX_GET(reg) BSP_FLD32GET(reg,0, 2)
 #define TMS570_EMACM_MACINDEX_MACINDEX_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
 
 
-/*---------------------TMS570_EMACMTXHDP---------------------*/
+/*---------------------TMS570_EMACM_TXHDP---------------------*/
 /* field: TXnHDP - Transmit channel n DMA Head Descriptor pointer. */
-#define TMS570_EMACM_TXHDP_TXnHDP(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_EMACM_TXHDP_TXnHDP_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_EMACM_TXHDP_TXnHDP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*---------------------TMS570_EMACM_RXHDP---------------------*/
-/*---------------------TMS570_EMACMRXHDP---------------------*/
 /* field: RXnHDP - Receive channel n DMA Head Descriptor pointer. */
-#define TMS570_EMACM_RXHDP_RXnHDP(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_EMACM_RXHDP_RXnHDP_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_EMACM_RXHDP_RXnHDP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*---------------------TMS570_EMACM_TXCP---------------------*/
-/*----------------------TMS570_EMACMTXCP----------------------*/
 /* field: TXnCP - Transmit channel n completion pointer register is written by the host with the buffer descriptor */
-#define TMS570_EMACM_TXCP_TXnCP(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_EMACM_TXCP_TXnCP_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_EMACM_TXCP_TXnCP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*---------------------TMS570_EMACM_RXCP---------------------*/
-/*----------------------TMS570_EMACMRXCP----------------------*/
 /* field: RXnCP - Receive channel n completion pointer register is written by the host with the buffer descriptor */
-#define TMS570_EMACM_RXCP_RXnCP(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_EMACM_RXCP_RXnCP_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_EMACM_RXCP_RXnCP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
 
-
+#endif /* LIBBSP_ARM_TMS570_EMACM */
-#endif /* LIBBSP_ARM_tms570_EMACM */

c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emif.h

@@ -36,8 +36,8 @@
  * of the authors and should not be interpreted as representing official policies,
  * either expressed or implied, of the FreeBSD Project.
 */
-#ifndef LIBBSP_ARM_tms570_EMIF
+#ifndef LIBBSP_ARM_TMS570_EMIF
-#define LIBBSP_ARM_tms570_EMIF
+#define LIBBSP_ARM_TMS570_EMIF
 
 #include <bsp/utility.h>
 
@@ -62,19 +62,16 @@ typedef struct{
 } tms570_emif_t;
 
 
-/*----------------------TMS570_EMIFMIDR----------------------*/
+/*----------------------TMS570_EMIF_MIDR----------------------*/
 /* field: REV - Module ID of EMIF. See the device-specific data manual. */
-#define TMS570_EMIF_MIDR_REV(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_EMIF_MIDR_REV_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_EMIF_MIDR_REV_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*----------------------TMS570_EMIF_AWCC----------------------*/
-/*----------------------TMS570_EMIFAWCC----------------------*/
 /* field: WP1 - EMIF_nWAIT[1] polarity bit. This bit defines the polarity of the EMIF_nWAIT[1] pin. */
-#define TMS570_EMIF_AWCC_WP1 BSP_FLD32(29)
+#define TMS570_EMIF_AWCC_WP1 BSP_BIT32(29)
 
 /* field: WP0 - EMIF_nWAIT[0] polarity bit. This bit defines the polarity of the EMIF_nWAIT[0] pin. */
-#define TMS570_EMIF_AWCC_WP0 BSP_FLD32(28)
+#define TMS570_EMIF_AWCC_WP0 BSP_BIT32(28)
 
 /* field: CS5_WAIT - Chip Select 5 WAIT signal selection. */
 #define TMS570_EMIF_AWCC_CS5_WAIT(val) BSP_FLD32(val,22, 23)
@@ -102,18 +99,18 @@ typedef struct{
 #define TMS570_EMIF_AWCC_MAX_EXT_WAIT_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*----------------------TMS570_EMIFSDCR----------------------*/
+/*----------------------TMS570_EMIF_SDCR----------------------*/
 /* field: SR - Self-Refresh mode bit. */
-#define TMS570_EMIF_SDCR_SR BSP_FLD32(31)
+#define TMS570_EMIF_SDCR_SR BSP_BIT32(31)
 
 /* field: PD - Power Down bit. This bit controls entering and exiting of the power-down mode. */
-#define TMS570_EMIF_SDCR_PD BSP_FLD32(30)
+#define TMS570_EMIF_SDCR_PD BSP_BIT32(30)
 
 /* field: PDWR - Perform refreshes during power down. */
-#define TMS570_EMIF_SDCR_PDWR BSP_FLD32(29)
+#define TMS570_EMIF_SDCR_PDWR BSP_BIT32(29)
 
 /* field: NM - Narrow mode bit. This bit defines whether a 16- or 32-bit-wide SDRAM is connected to the EMIF. */
-#define TMS570_EMIF_SDCR_NM BSP_FLD32(14)
+#define TMS570_EMIF_SDCR_NM BSP_BIT32(14)
 
 /* field: CL - CAS Latency. */
 #define TMS570_EMIF_SDCR_CL(val) BSP_FLD32(val,9, 11)
@@ -121,7 +118,7 @@ typedef struct{
 #define TMS570_EMIF_SDCR_CL_SET(reg,val) BSP_FLD32SET(reg, val,9, 11)
 
 /* field: BIT11_9LOCK - Bits 11 to 9 lock. CL can only be written if BIT11_9LOCK is simultaneously written with a 1. */
-#define TMS570_EMIF_SDCR_BIT11_9LOCK BSP_FLD32(8)
+#define TMS570_EMIF_SDCR_BIT11_9LOCK BSP_BIT32(8)
 
 /* field: IBANK - Internal SDRAM Bank size. */
 #define TMS570_EMIF_SDCR_IBANK(val) BSP_FLD32(val,4, 6)
@@ -134,19 +131,19 @@ typedef struct{
 #define TMS570_EMIF_SDCR_PAGESIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
 
 
-/*----------------------TMS570_EMIFSDRCR----------------------*/
+/*---------------------TMS570_EMIF_SDRCR---------------------*/
 /* field: RR - Refresh Rate. This field is used to define the SDRAM refresh period in terms of EMIF_CLK cycles. */
 #define TMS570_EMIF_SDRCR_RR(val) BSP_FLD32(val,0, 12)
 #define TMS570_EMIF_SDRCR_RR_GET(reg) BSP_FLD32GET(reg,0, 12)
 #define TMS570_EMIF_SDRCR_RR_SET(reg,val) BSP_FLD32SET(reg, val,0, 12)
 
 
-/*---------------------TMS570_EMIFCE2CFG---------------------*/
+/*---------------------TMS570_EMIF_CE2CFG---------------------*/
 /* field: SS - Select Strobe bit. */
-#define TMS570_EMIF_CE2CFG_SS BSP_FLD32(31)
+#define TMS570_EMIF_CE2CFG_SS BSP_BIT32(31)
 
 /* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */
-#define TMS570_EMIF_CE2CFG_EW BSP_FLD32(30)
+#define TMS570_EMIF_CE2CFG_EW BSP_BIT32(30)
 
 /* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
 #define TMS570_EMIF_CE2CFG_W_SETUP(val) BSP_FLD32(val,26, 29)
@@ -189,12 +186,12 @@ typedef struct{
 #define TMS570_EMIF_CE2CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
 
 
-/*---------------------TMS570_EMIFCE3CFG---------------------*/
+/*---------------------TMS570_EMIF_CE3CFG---------------------*/
 /* field: SS - Select Strobe bit. */
-#define TMS570_EMIF_CE3CFG_SS BSP_FLD32(31)
+#define TMS570_EMIF_CE3CFG_SS BSP_BIT32(31)
 
 /* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */
-#define TMS570_EMIF_CE3CFG_EW BSP_FLD32(30)
+#define TMS570_EMIF_CE3CFG_EW BSP_BIT32(30)
 
 /* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
 #define TMS570_EMIF_CE3CFG_W_SETUP(val) BSP_FLD32(val,26, 29)
@@ -237,12 +234,12 @@ typedef struct{
 #define TMS570_EMIF_CE3CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
 
 
-/*---------------------TMS570_EMIFCE4CFG---------------------*/
+/*---------------------TMS570_EMIF_CE4CFG---------------------*/
 /* field: SS - Select Strobe bit. */
-#define TMS570_EMIF_CE4CFG_SS BSP_FLD32(31)
+#define TMS570_EMIF_CE4CFG_SS BSP_BIT32(31)
 
 /* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */
-#define TMS570_EMIF_CE4CFG_EW BSP_FLD32(30)
+#define TMS570_EMIF_CE4CFG_EW BSP_BIT32(30)
 
 /* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
 #define TMS570_EMIF_CE4CFG_W_SETUP(val) BSP_FLD32(val,26, 29)
@@ -285,12 +282,12 @@ typedef struct{
 #define TMS570_EMIF_CE4CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
 
 
-/*---------------------TMS570_EMIFCE5CFG---------------------*/
+/*---------------------TMS570_EMIF_CE5CFG---------------------*/
 /* field: SS - Select Strobe bit. */
-#define TMS570_EMIF_CE5CFG_SS BSP_FLD32(31)
+#define TMS570_EMIF_CE5CFG_SS BSP_BIT32(31)
 
 /* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */
-#define TMS570_EMIF_CE5CFG_EW BSP_FLD32(30)
+#define TMS570_EMIF_CE5CFG_EW BSP_BIT32(30)
 
 /* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
 #define TMS570_EMIF_CE5CFG_W_SETUP(val) BSP_FLD32(val,26, 29)
@@ -333,7 +330,7 @@ typedef struct{
 #define TMS570_EMIF_CE5CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
 
 
-/*---------------------TMS570_EMIFSDTIMR---------------------*/
+/*---------------------TMS570_EMIF_SDTIMR---------------------*/
 /* field: T_RFC - Specifies the Trfc value of the SDRAM. */
 #define TMS570_EMIF_SDTIMR_T_RFC(val) BSP_FLD32(val,27, 31)
 #define TMS570_EMIF_SDTIMR_T_RFC_GET(reg) BSP_FLD32GET(reg,27, 31)
@@ -370,68 +367,68 @@ typedef struct{
 #define TMS570_EMIF_SDTIMR_T_RRD_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
 
 
-/*---------------------TMS570_EMIFSDSRETR---------------------*/
+/*--------------------TMS570_EMIF_SDSRETR--------------------*/
 /* field: T_XS - This field specifies the minimum number of ECLKOUT cycles from Self-Refresh exit to any command, */
 #define TMS570_EMIF_SDSRETR_T_XS(val) BSP_FLD32(val,0, 4)
 #define TMS570_EMIF_SDSRETR_T_XS_GET(reg) BSP_FLD32GET(reg,0, 4)
 #define TMS570_EMIF_SDSRETR_T_XS_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
 
 
-/*---------------------TMS570_EMIFINTRAW---------------------*/
+/*---------------------TMS570_EMIF_INTRAW---------------------*/
 /* field: WR - Wait Rise. */
-#define TMS570_EMIF_INTRAW_WR BSP_FLD32(2)
+#define TMS570_EMIF_INTRAW_WR BSP_BIT32(2)
 
 /* field: LT - Line Trap. Set to 1 by hardware to indicate illegal memory access type or invalid cache line size. */
-#define TMS570_EMIF_INTRAW_LT BSP_FLD32(1)
+#define TMS570_EMIF_INTRAW_LT BSP_BIT32(1)
 
 /* field: AT - Asynchronous Timeout. */
-#define TMS570_EMIF_INTRAW_AT BSP_FLD32(0)
+#define TMS570_EMIF_INTRAW_AT BSP_BIT32(0)
 
 
-/*---------------------TMS570_EMIFINTMSK---------------------*/
+/*---------------------TMS570_EMIF_INTMSK---------------------*/
 /* field: WR_MASKED - Wait Rise Masked. */
-#define TMS570_EMIF_INTMSK_WR_MASKED BSP_FLD32(2)
+#define TMS570_EMIF_INTMSK_WR_MASKED BSP_BIT32(2)
 
 /* field: LT_MASKED - Masked Line Trap. */
-#define TMS570_EMIF_INTMSK_LT_MASKED BSP_FLD32(1)
+#define TMS570_EMIF_INTMSK_LT_MASKED BSP_BIT32(1)
 
 /* field: AT_MASKED - Asynchronous Timeout Masked. */
-#define TMS570_EMIF_INTMSK_AT_MASKED BSP_FLD32(0)
+#define TMS570_EMIF_INTMSK_AT_MASKED BSP_BIT32(0)
 
 
-/*--------------------TMS570_EMIFINTMSKSET--------------------*/
+/*-------------------TMS570_EMIF_INTMSKSET-------------------*/
 /* field: WR_MASK_SET - Wait Rise Mask Set. This bit determines whether or not the wait rise Interrupt is enabled. */
-#define TMS570_EMIF_INTMSKSET_WR_MASK_SET BSP_FLD32(2)
+#define TMS570_EMIF_INTMSKSET_WR_MASK_SET BSP_BIT32(2)
 
 /* field: LT_MASK_SET - LT_MASK_SET Mask set for LT_MASKED bit in the EMIF interrupt mask register (INTMSK). */
-#define TMS570_EMIF_INTMSKSET_LT_MASK_SET BSP_FLD32(1)
+#define TMS570_EMIF_INTMSKSET_LT_MASK_SET BSP_BIT32(1)
 
 /* field: AT_MASK_SET - Asynchronous Timeout Mask Set. */
-#define TMS570_EMIF_INTMSKSET_AT_MASK_SET BSP_FLD32(0)
+#define TMS570_EMIF_INTMSKSET_AT_MASK_SET BSP_BIT32(0)
 
 
-/*--------------------TMS570_EMIFINTMSKCLR--------------------*/
+/*-------------------TMS570_EMIF_INTMSKCLR-------------------*/
 /* field: WR_MASK_CLR - Wait Rise Mask Clear. This bit determines whether or not the wait rise interrupt is enabled. */
-#define TMS570_EMIF_INTMSKCLR_WR_MASK_CLR BSP_FLD32(2)
+#define TMS570_EMIF_INTMSKCLR_WR_MASK_CLR BSP_BIT32(2)
 
 /* field: LT_MASK_CLR - 1 to this bit clears this bit, clears the LT_MASK_SET bit in the EMIF interrupt mask set register */
-#define TMS570_EMIF_INTMSKCLR_LT_MASK_CLR BSP_FLD32(1)
+#define TMS570_EMIF_INTMSKCLR_LT_MASK_CLR BSP_BIT32(1)
 
 /* field: AT_MASK_CLR - Asynchronous Timeout Mask Clear. */
-#define TMS570_EMIF_INTMSKCLR_AT_MASK_CLR BSP_FLD32(0)
+#define TMS570_EMIF_INTMSKCLR_AT_MASK_CLR BSP_BIT32(0)
 
 
-/*----------------------TMS570_EMIFPMCR----------------------*/
+/*----------------------TMS570_EMIF_PMCR----------------------*/
 /* field: CS5_PG_DEL - Page access delay for NOR Flash connected on CS5. CS5 is not available on this device. */
 #define TMS570_EMIF_PMCR_CS5_PG_DEL(val) BSP_FLD32(val,26, 31)
 #define TMS570_EMIF_PMCR_CS5_PG_DEL_GET(reg) BSP_FLD32GET(reg,26, 31)
 #define TMS570_EMIF_PMCR_CS5_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,26, 31)
 
 /* field: CS5_PG_SIZE - Page Size for NOR Flash connected on CS5. CS5 is not available on this device. */
-#define TMS570_EMIF_PMCR_CS5_PG_SIZE BSP_FLD32(25)
+#define TMS570_EMIF_PMCR_CS5_PG_SIZE BSP_BIT32(25)
 
 /* field: CS5_PG_MD_EN - Page Mode enable for NOR Flash connected on CS5. CS5 is not available on this device. */
-#define TMS570_EMIF_PMCR_CS5_PG_MD_EN BSP_FLD32(24)
+#define TMS570_EMIF_PMCR_CS5_PG_MD_EN BSP_BIT32(24)
 
 /* field: CS4_PG_DEL - Page access delay for NOR Flash connected on CS4. */
 #define TMS570_EMIF_PMCR_CS4_PG_DEL(val) BSP_FLD32(val,18, 23)
@@ -439,10 +436,10 @@ typedef struct{
 #define TMS570_EMIF_PMCR_CS4_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,18, 23)
 
 /* field: CS4_PG_SIZE - Page Size for NOR Flash connected on CS4. */
-#define TMS570_EMIF_PMCR_CS4_PG_SIZE BSP_FLD32(17)
+#define TMS570_EMIF_PMCR_CS4_PG_SIZE BSP_BIT32(17)
 
 /* field: CS4_PG_MD_EN - Page Mode enable for NOR Flash connected on CS4. */
-#define TMS570_EMIF_PMCR_CS4_PG_MD_EN BSP_FLD32(16)
+#define TMS570_EMIF_PMCR_CS4_PG_MD_EN BSP_BIT32(16)
 
 /* field: CS3_PG_DEL - the page read data to be valid, minus one cycle. This value must not be cleared to 0. */
 #define TMS570_EMIF_PMCR_CS3_PG_DEL(val) BSP_FLD32(val,10, 15)
@@ -450,10 +447,10 @@ typedef struct{
 #define TMS570_EMIF_PMCR_CS3_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,10, 15)
 
 /* field: CS3_PG_SIZE - Page Size for NOR Flash connected on CS3. */
-#define TMS570_EMIF_PMCR_CS3_PG_SIZE BSP_FLD32(9)
+#define TMS570_EMIF_PMCR_CS3_PG_SIZE BSP_BIT32(9)
 
 /* field: CS3_PG_MD_EN - Page Mode enable for NOR Flash connected on CS3. */
-#define TMS570_EMIF_PMCR_CS3_PG_MD_EN BSP_FLD32(8)
+#define TMS570_EMIF_PMCR_CS3_PG_MD_EN BSP_BIT32(8)
 
 /* field: CS2_PG_DEL - Page access delay for NOR Flash connected on CS2. */
 #define TMS570_EMIF_PMCR_CS2_PG_DEL(val) BSP_FLD32(val,2, 7)
@@ -461,11 +458,11 @@ typedef struct{
 #define TMS570_EMIF_PMCR_CS2_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,2, 7)
 
 /* field: CS2_PG_SIZE - Page Size for NOR Flash connected on CS2. */
-#define TMS570_EMIF_PMCR_CS2_PG_SIZE BSP_FLD32(1)
+#define TMS570_EMIF_PMCR_CS2_PG_SIZE BSP_BIT32(1)
 
 /* field: CS2_PG_MD_EN - Page Mode enable for NOR Flash connected on CS2. */
-#define TMS570_EMIF_PMCR_CS2_PG_MD_EN BSP_FLD32(0)
+#define TMS570_EMIF_PMCR_CS2_PG_MD_EN BSP_BIT32(0)
 
 
 
-#endif /* LIBBSP_ARM_tms570_EMIF */
+#endif /* LIBBSP_ARM_TMS570_EMIF */

c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_esm.h

@@ -36,8 +36,8 @@
  * of the authors and should not be interpreted as representing official policies,
  * either expressed or implied, of the FreeBSD Project.
 */
-#ifndef LIBBSP_ARM_tms570_ESM
+#ifndef LIBBSP_ARM_TMS570_ESM
-#define LIBBSP_ARM_tms570_ESM
+#define LIBBSP_ARM_TMS570_ESM
 
 #include <bsp/utility.h>
 
@@ -66,150 +66,105 @@ typedef struct{
 } tms570_esm_t;
 
 
-/*---------------------TMS570_ESMEEPAPR1---------------------*/
+/*---------------------TMS570_ESM_EEPAPR1---------------------*/
 /* field: IEPSET - Enable ERROR Pin Action/Response on Group 1. */
-#define TMS570_ESM_EEPAPR1_IEPSET(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_ESM_EEPAPR1_IEPSET_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_ESM_EEPAPR1_IEPSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*---------------------TMS570_ESM_DEPAPR1---------------------*/
-/*---------------------TMS570_ESMDEPAPR1---------------------*/
 /* field: IEPCLR - Disable ERROR Pin Action/Response on Group 1. */
-#define TMS570_ESM_DEPAPR1_IEPCLR(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_ESM_DEPAPR1_IEPCLR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_ESM_DEPAPR1_IEPCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*----------------------TMS570_ESM_IESR1----------------------*/
-/*----------------------TMS570_ESMIESR1----------------------*/
 /* field: INTENSET - Set interrupt Enable */
-#define TMS570_ESM_IESR1_INTENSET(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_ESM_IESR1_INTENSET_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_ESM_IESR1_INTENSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*----------------------TMS570_ESM_IECR1----------------------*/
-/*----------------------TMS570_ESMIECR1----------------------*/
 /* field: INTENCLR - Clear Interrupt Enable */
-#define TMS570_ESM_IECR1_INTENCLR(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_ESM_IECR1_INTENCLR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_ESM_IECR1_INTENCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*----------------------TMS570_ESM_ILSR1----------------------*/
-/*----------------------TMS570_ESMILSR1----------------------*/
 /* field: INTLVLSET - Set Interrupt Priority */
-#define TMS570_ESM_ILSR1_INTLVLSET(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_ESM_ILSR1_INTLVLSET_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_ESM_ILSR1_INTLVLSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*----------------------TMS570_ESM_ILCR1----------------------*/
-/*----------------------TMS570_ESMILCR1----------------------*/
 /* field: INTLVLCLR - Clear Interrupt Priority. */
-#define TMS570_ESM_ILCR1_INTLVLCLR(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_ESM_ILCR1_INTLVLCLR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_ESM_ILCR1_INTLVLCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-----------------------TMS570_ESM_SR-----------------------*/
-/*------------------------TMS570_ESMSR------------------------*/
 /* field: ESF - Error Status Flag. Provides status information on a pending error. */
-#define TMS570_ESM_SR_ESF(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_ESM_SR_ESF_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_ESM_SR_ESF_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*----------------------TMS570_ESM_EPSR----------------------*/
-/*-----------------------TMS570_ESMEPSR-----------------------*/
 /* field: EPSF - ERROR Pin Status Flag. Provides status information for the ERROR Pin. */
-#define TMS570_ESM_EPSR_EPSF BSP_FLD32(0)
+#define TMS570_ESM_EPSR_EPSF BSP_BIT32(0)
 
 
-/*----------------------TMS570_ESMIOFFHR----------------------*/
+/*---------------------TMS570_ESM_IOFFHR---------------------*/
 /* field: INTOFFH - Offset High Level Interrupt. */
 #define TMS570_ESM_IOFFHR_INTOFFH(val) BSP_FLD32(val,0, 6)
 #define TMS570_ESM_IOFFHR_INTOFFH_GET(reg) BSP_FLD32GET(reg,0, 6)
 #define TMS570_ESM_IOFFHR_INTOFFH_SET(reg,val) BSP_FLD32SET(reg, val,0, 6)
 
 
-/*----------------------TMS570_ESMIOFFLR----------------------*/
+/*---------------------TMS570_ESM_IOFFLR---------------------*/
 /* field: INTOFFL - Offset Low Level Interrupt. */
 #define TMS570_ESM_IOFFLR_INTOFFL(val) BSP_FLD32(val,0, 6)
 #define TMS570_ESM_IOFFLR_INTOFFL_GET(reg) BSP_FLD32GET(reg,0, 6)
 #define TMS570_ESM_IOFFLR_INTOFFL_SET(reg,val) BSP_FLD32SET(reg, val,0, 6)
 
 
-/*-----------------------TMS570_ESMLTCR-----------------------*/
+/*----------------------TMS570_ESM_LTCR----------------------*/
 /* field: LTC - ERROR Pin Low-Time Counter */
 #define TMS570_ESM_LTCR_LTC(val) BSP_FLD32(val,0, 15)
 #define TMS570_ESM_LTCR_LTC_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_ESM_LTCR_LTC_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*----------------------TMS570_ESMLTCPR----------------------*/
+/*----------------------TMS570_ESM_LTCPR----------------------*/
 /* field: LTCP - ERROR Pin Low-Time Counter Pre-load Value */
 #define TMS570_ESM_LTCPR_LTCP(val) BSP_FLD32(val,0, 15)
 #define TMS570_ESM_LTCPR_LTCP_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_ESM_LTCPR_LTCP_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*-----------------------TMS570_ESMEKR-----------------------*/
+/*-----------------------TMS570_ESM_EKR-----------------------*/
 /* field: EKEY - Error Key. The key to reset the ERROR pin or to force an error on the ERROR pin. */
 #define TMS570_ESM_EKR_EKEY(val) BSP_FLD32(val,0, 3)
 #define TMS570_ESM_EKR_EKEY_GET(reg) BSP_FLD32GET(reg,0, 3)
 #define TMS570_ESM_EKR_EKEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*-----------------------TMS570_ESMSSR2-----------------------*/
+/*----------------------TMS570_ESM_SSR2----------------------*/
 /* field: ESF - Error Status Flag. Shadow register for status information on pending error. */
-#define TMS570_ESM_SSR2_ESF(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_ESM_SSR2_ESF_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_ESM_SSR2_ESF_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*---------------------TMS570_ESM_IEPSR4---------------------*/
-/*----------------------TMS570_ESMIEPSR4----------------------*/
 /* field: IEPSET - Set Influence on ERROR Pin */
-#define TMS570_ESM_IEPSR4_IEPSET(val) BSP_FLD32(val,32, 63)
+/* Whole 32 bits */
-#define TMS570_ESM_IEPSR4_IEPSET_GET(reg) BSP_FLD32GET(reg,32, 63)
-#define TMS570_ESM_IEPSR4_IEPSET_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
 
-
+/*---------------------TMS570_ESM_IEPCR4---------------------*/
-/*----------------------TMS570_ESMIEPCR4----------------------*/
 /* field: IEPCLR - Clear Influence on ERROR Pin */
-#define TMS570_ESM_IEPCR4_IEPCLR(val) BSP_FLD32(val,32, 63)
+/* Whole 32 bits */
-#define TMS570_ESM_IEPCR4_IEPCLR_GET(reg) BSP_FLD32GET(reg,32, 63)
-#define TMS570_ESM_IEPCR4_IEPCLR_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
 
-
+/*----------------------TMS570_ESM_IESR4----------------------*/
-/*----------------------TMS570_ESMIESR4----------------------*/
 /* field: INTENSET - Set Interrupt Enable */
-#define TMS570_ESM_IESR4_INTENSET(val) BSP_FLD32(val,32, 63)
+/* Whole 32 bits */
-#define TMS570_ESM_IESR4_INTENSET_GET(reg) BSP_FLD32GET(reg,32, 63)
-#define TMS570_ESM_IESR4_INTENSET_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
 
-
+/*----------------------TMS570_ESM_IECR4----------------------*/
-/*----------------------TMS570_ESMIECR4----------------------*/
 /* field: INTENCLR - Clear Interrupt Enable */
-#define TMS570_ESM_IECR4_INTENCLR(val) BSP_FLD32(val,32, 63)
+/* Whole 32 bits */
-#define TMS570_ESM_IECR4_INTENCLR_GET(reg) BSP_FLD32GET(reg,32, 63)
-#define TMS570_ESM_IECR4_INTENCLR_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
 
-
+/*----------------------TMS570_ESM_ILSR4----------------------*/
-/*----------------------TMS570_ESMILSR4----------------------*/
 /* field: INTLVLSET - Set Interrupt Level */
-#define TMS570_ESM_ILSR4_INTLVLSET(val) BSP_FLD32(val,32, 63)
+/* Whole 32 bits */
-#define TMS570_ESM_ILSR4_INTLVLSET_GET(reg) BSP_FLD32GET(reg,32, 63)
-#define TMS570_ESM_ILSR4_INTLVLSET_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
 
-
+/*----------------------TMS570_ESM_ILCR4----------------------*/
-/*----------------------TMS570_ESMILCR4----------------------*/
 /* field: INTLVLCLR - Clear Interrupt Level */
-#define TMS570_ESM_ILCR4_INTLVLCLR(val) BSP_FLD32(val,32, 63)
+/* Whole 32 bits */
-#define TMS570_ESM_ILCR4_INTLVLCLR_GET(reg) BSP_FLD32GET(reg,32, 63)
-#define TMS570_ESM_ILCR4_INTLVLCLR_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
 
-
+/*-----------------------TMS570_ESM_SR4-----------------------*/
-/*-----------------------TMS570_ESMSR4-----------------------*/
 /* field: ESF - Error Status Flag. Provides status information on a pending error. */
-#define TMS570_ESM_SR4_ESF(val) BSP_FLD32(val,32, 63)
+/* Whole 32 bits */
-#define TMS570_ESM_SR4_ESF_GET(reg) BSP_FLD32GET(reg,32, 63)
-#define TMS570_ESM_SR4_ESF_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
 
 
-
+#endif /* LIBBSP_ARM_TMS570_ESM */
-#endif /* LIBBSP_ARM_tms570_ESM */

c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_flash.h

@@ -36,8 +36,8 @@
  * of the authors and should not be interpreted as representing official policies,
  * either expressed or implied, of the FreeBSD Project.
 */
-#ifndef LIBBSP_ARM_tms570_FLASH
+#ifndef LIBBSP_ARM_TMS570_FLASH
-#define LIBBSP_ARM_tms570_FLASH
+#define LIBBSP_ARM_TMS570_FLASH
 
 #include <bsp/utility.h>
 
@@ -95,22 +95,22 @@ typedef struct{
 } tms570_flash_t;
 
 
-/*--------------------TMS570_FLASHFRDCNTL--------------------*/
+/*--------------------TMS570_FLASH_FRDCNTL--------------------*/
 /* field: RWAIT - Random/data Read Wait State */
 #define TMS570_FLASH_FRDCNTL_RWAIT(val) BSP_FLD32(val,8, 11)
 #define TMS570_FLASH_FRDCNTL_RWAIT_GET(reg) BSP_FLD32GET(reg,8, 11)
 #define TMS570_FLASH_FRDCNTL_RWAIT_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
 
 /* field: ASWSTEN - Address Setup Wait State Enable */
-#define TMS570_FLASH_FRDCNTL_ASWSTEN BSP_FLD32(4)
+#define TMS570_FLASH_FRDCNTL_ASWSTEN BSP_BIT32(4)
 
 /* field: ENPIPE - Enable Pipeline Mode */
-#define TMS570_FLASH_FRDCNTL_ENPIPE BSP_FLD32(0)
+#define TMS570_FLASH_FRDCNTL_ENPIPE BSP_BIT32(0)
 
 
-/*-------------------TMS570_FLASHFEDACTRL1-------------------*/
+/*-------------------TMS570_FLASH_FEDACTRL1-------------------*/
 /* field: SUSP_IGNR - Suspend Ignore. */
-#define TMS570_FLASH_FEDACTRL1_SUSP_IGNR BSP_FLD32(24)
+#define TMS570_FLASH_FEDACTRL1_SUSP_IGNR BSP_BIT32(24)
 
 /* field: EDACMODE - Error Correction Mode. */
 #define TMS570_FLASH_FEDACTRL1_EDACMODE(val) BSP_FLD32(val,16, 19)
@@ -118,13 +118,13 @@ typedef struct{
 #define TMS570_FLASH_FEDACTRL1_EDACMODE_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
 
 /* field: EOFEN - Event on Ones Fail Enable */
-#define TMS570_FLASH_FEDACTRL1_EOFEN BSP_FLD32(10)
+#define TMS570_FLASH_FEDACTRL1_EOFEN BSP_BIT32(10)
 
 /* field: EZFEN - Event on Zeros Fail Enable */
-#define TMS570_FLASH_FEDACTRL1_EZFEN BSP_FLD32(9)
+#define TMS570_FLASH_FEDACTRL1_EZFEN BSP_BIT32(9)
 
 /* field: EPEN - Error Profiling Enable. */
-#define TMS570_FLASH_FEDACTRL1_EPEN BSP_FLD32(8)
+#define TMS570_FLASH_FEDACTRL1_EPEN BSP_BIT32(8)
 
 /* field: EDACEN - Error Detection and Correction Enable */
 #define TMS570_FLASH_FEDACTRL1_EDACEN(val) BSP_FLD32(val,0, 3)
@@ -132,21 +132,21 @@ typedef struct{
 #define TMS570_FLASH_FEDACTRL1_EDACEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*-------------------TMS570_FLASHFEDACTRL2-------------------*/
+/*-------------------TMS570_FLASH_FEDACTRL2-------------------*/
 /* field: SEC_THRESHOLD - Single Error Correction Threshold */
 #define TMS570_FLASH_FEDACTRL2_SEC_THRESHOLD(val) BSP_FLD32(val,0, 15)
 #define TMS570_FLASH_FEDACTRL2_SEC_THRESHOLD_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_FLASH_FEDACTRL2_SEC_THRESHOLD_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*-------------------TMS570_FLASHFCORERRCNT-------------------*/
+/*------------------TMS570_FLASH_FCORERRCNT------------------*/
 /* field: FERRCNT - Single Error Correction Count */
 #define TMS570_FLASH_FCORERRCNT_FERRCNT(val) BSP_FLD32(val,0, 15)
 #define TMS570_FLASH_FCORERRCNT_FERRCNT_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_FLASH_FCORERRCNT_FERRCNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*-------------------TMS570_FLASHFCORERRADD-------------------*/
+/*------------------TMS570_FLASH_FCORERRADD------------------*/
 /* field: COR_ERR_ADD - Correctable Error Address */
 #define TMS570_FLASH_FCORERRADD_COR_ERR_ADD(val) BSP_FLD32(val,3, 31)
 #define TMS570_FLASH_FCORERRADD_COR_ERR_ADD_GET(reg) BSP_FLD32GET(reg,3, 31)
@@ -158,12 +158,12 @@ typedef struct{
 #define TMS570_FLASH_FCORERRADD_B_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
 
 
-/*-------------------TMS570_FLASHFCORERRPOS-------------------*/
+/*------------------TMS570_FLASH_FCORERRPOS------------------*/
 /* field: BUS2 - Bus 2 Error */
-#define TMS570_FLASH_FCORERRPOS_BUS2 BSP_FLD32(9)
+#define TMS570_FLASH_FCORERRPOS_BUS2 BSP_BIT32(9)
 
 /* field: TYPE - ErrorType */
-#define TMS570_FLASH_FCORERRPOS_TYPE BSP_FLD32(8)
+#define TMS570_FLASH_FCORERRPOS_TYPE BSP_BIT32(8)
 
 /* field: ERR_POS - The bit address of the single bit error */
 #define TMS570_FLASH_FCORERRPOS_ERR_POS(val) BSP_FLD32(val,0, 7)
@@ -171,53 +171,53 @@ typedef struct{
 #define TMS570_FLASH_FCORERRPOS_ERR_POS_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*------------------TMS570_FLASHFEDACSTATUS------------------*/
+/*------------------TMS570_FLASH_FEDACSTATUS------------------*/
 /* field: Reserved - Read returns 0. Writes have no effect. */
 #define TMS570_FLASH_FEDACSTATUS_Reserved(val) BSP_FLD32(val,26, 31)
 #define TMS570_FLASH_FEDACSTATUS_Reserved_GET(reg) BSP_FLD32GET(reg,26, 31)
 #define TMS570_FLASH_FEDACSTATUS_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,26, 31)
 
 /* field: FSM_DONE - Flash State Machine Done */
-#define TMS570_FLASH_FEDACSTATUS_FSM_DONE BSP_FLD32(24)
+#define TMS570_FLASH_FEDACSTATUS_FSM_DONE BSP_BIT32(24)
 
 /* field: COMB2_MAL_G - Bus 2 Compare Malfunction Flag. */
-#define TMS570_FLASH_FEDACSTATUS_COMB2_MAL_G BSP_FLD32(19)
+#define TMS570_FLASH_FEDACSTATUS_COMB2_MAL_G BSP_BIT32(19)
 
 /* field: ECC_B2_MAL_ - Bus 2 ECC Malfunction Error Flag */
-#define TMS570_FLASH_FEDACSTATUS_ECC_B2_MAL_ BSP_FLD32(18)
+#define TMS570_FLASH_FEDACSTATUS_ECC_B2_MAL_ BSP_BIT32(18)
 
 /* field: B2_UNC_ERR - Bus 2 uncorrectable error */
-#define TMS570_FLASH_FEDACSTATUS_B2_UNC_ERR BSP_FLD32(17)
+#define TMS570_FLASH_FEDACSTATUS_B2_UNC_ERR BSP_BIT32(17)
 
 /* field: B2_COR_ERR - Bus 2 Correctable Error */
-#define TMS570_FLASH_FEDACSTATUS_B2_COR_ERR BSP_FLD32(16)
+#define TMS570_FLASH_FEDACSTATUS_B2_COR_ERR BSP_BIT32(16)
 
 /* field: D_UNC_ERR - Diagnostic Uncorrectable Error */
-#define TMS570_FLASH_FEDACSTATUS_D_UNC_ERR BSP_FLD32(12)
+#define TMS570_FLASH_FEDACSTATUS_D_UNC_ERR BSP_BIT32(12)
 
 /* field: ADD_TAG_ERR - Address Tag Register Error Flag */
-#define TMS570_FLASH_FEDACSTATUS_ADD_TAG_ERR BSP_FLD32(11)
+#define TMS570_FLASH_FEDACSTATUS_ADD_TAG_ERR BSP_BIT32(11)
 
 /* field: ADD_PAR_ERR - Address Parity Error Flag */
-#define TMS570_FLASH_FEDACSTATUS_ADD_PAR_ERR BSP_FLD32(10)
+#define TMS570_FLASH_FEDACSTATUS_ADD_PAR_ERR BSP_BIT32(10)
 
 /* field: B1_UNC_ERR - Bus 1 Uncorrectable Error Flag */
-#define TMS570_FLASH_FEDACSTATUS_B1_UNC_ERR BSP_FLD32(8)
+#define TMS570_FLASH_FEDACSTATUS_B1_UNC_ERR BSP_BIT32(8)
 
 /* field: D_CORR_ERR - Diagnostic Correctable Error Status Flag */
-#define TMS570_FLASH_FEDACSTATUS_D_CORR_ERR BSP_FLD32(3)
+#define TMS570_FLASH_FEDACSTATUS_D_CORR_ERR BSP_BIT32(3)
 
 /* field: ERR_ONE_FLG - Error on One Fail Status Flag */
-#define TMS570_FLASH_FEDACSTATUS_ERR_ONE_FLG BSP_FLD32(2)
+#define TMS570_FLASH_FEDACSTATUS_ERR_ONE_FLG BSP_BIT32(2)
 
 /* field: ERR_ZERO__FLG - Error on Zero Fail Status Flag */
-#define TMS570_FLASH_FEDACSTATUS_ERR_ZERO__FLG BSP_FLD32(1)
+#define TMS570_FLASH_FEDACSTATUS_ERR_ZERO__FLG BSP_BIT32(1)
 
 /* field: ERR_PRF_FLG - Error Profiling Status Flag */
-#define TMS570_FLASH_FEDACSTATUS_ERR_PRF_FLG BSP_FLD32(0)
+#define TMS570_FLASH_FEDACSTATUS_ERR_PRF_FLG BSP_BIT32(0)
 
 
-/*-------------------TMS570_FLASHFUNCERRADD-------------------*/
+/*------------------TMS570_FLASH_FUNCERRADD------------------*/
 /* field: UNC_ERR_ADD - Un-correctable Error Address */
 #define TMS570_FLASH_FUNCERRADD_UNC_ERR_ADD(val) BSP_FLD32(val,3, 31)
 #define TMS570_FLASH_FUNCERRADD_UNC_ERR_ADD_GET(reg) BSP_FLD32GET(reg,3, 31)
@@ -229,7 +229,7 @@ typedef struct{
 #define TMS570_FLASH_FUNCERRADD_B_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
 
 
-/*-------------------TMS570_FLASHFEDACSDIS-------------------*/
+/*-------------------TMS570_FLASH_FEDACSDIS-------------------*/
 /* field: BankID1_Inverse - The bank ID inverse bits are used with the bank ID bits to select the bank for which a sector */
 #define TMS570_FLASH_FEDACSDIS_BankID1_Inverse(val) BSP_FLD32(val,29, 31)
 #define TMS570_FLASH_FEDACSDIS_BankID1_Inverse_GET(reg) BSP_FLD32GET(reg,29, 31)
@@ -271,7 +271,7 @@ typedef struct{
 #define TMS570_FLASH_FEDACSDIS_SectorID0_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*------------------TMS570_FLASHFPRIMADDTAG------------------*/
+/*------------------TMS570_FLASH_FPRIMADDTAG------------------*/
 /* field: PRIM_ADD_TAG - Primary Address Tag Register */
 #define TMS570_FLASH_FPRIMADDTAG_PRIM_ADD_TAG(val) BSP_FLD32(val,4, 31)
 #define TMS570_FLASH_FPRIMADDTAG_PRIM_ADD_TAG_GET(reg) BSP_FLD32GET(reg,4, 31)
@@ -283,33 +283,33 @@ typedef struct{
 #define TMS570_FLASH_FPRIMADDTAG_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*-------------------TMS570_FLASHFDUPADDTAG-------------------*/
+/*------------------TMS570_FLASH_FDUPADDTAG------------------*/
 /* field: DUP_ADD_TAG - Primary Address Tag Register */
 #define TMS570_FLASH_FDUPADDTAG_DUP_ADD_TAG(val) BSP_FLD32(val,4, 31)
 #define TMS570_FLASH_FDUPADDTAG_DUP_ADD_TAG_GET(reg) BSP_FLD32GET(reg,4, 31)
 #define TMS570_FLASH_FDUPADDTAG_DUP_ADD_TAG_SET(reg,val) BSP_FLD32SET(reg, val,4, 31)
 
 
-/*---------------------TMS570_FLASHFBPROT---------------------*/
+/*--------------------TMS570_FLASH_FBPROT--------------------*/
 /* field: PROTL1DIS - PROTL1DIS: Level 1 Protection Disabled */
-#define TMS570_FLASH_FBPROT_PROTL1DIS BSP_FLD32(0)
+#define TMS570_FLASH_FBPROT_PROTL1DIS BSP_BIT32(0)
 
 
-/*----------------------TMS570_FLASHFBSE----------------------*/
+/*---------------------TMS570_FLASH_FBSE---------------------*/
 /* field: BSE - Bank Sector Enable */
 #define TMS570_FLASH_FBSE_BSE(val) BSP_FLD32(val,0, 15)
 #define TMS570_FLASH_FBSE_BSE_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_FLASH_FBSE_BSE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_FLASHFBBUSY---------------------*/
+/*--------------------TMS570_FLASH_FBBUSY--------------------*/
 /* field: BUSY - Bank Busy */
 #define TMS570_FLASH_FBBUSY_BUSY(val) BSP_FLD32(val,0, 7)
 #define TMS570_FLASH_FBBUSY_BUSY_GET(reg) BSP_FLD32GET(reg,0, 7)
 #define TMS570_FLASH_FBBUSY_BUSY_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*----------------------TMS570_FLASHFBAC----------------------*/
+/*---------------------TMS570_FLASH_FBAC---------------------*/
 /* field: OTPPROTDIS - OTP Sector Protection Disable. */
 #define TMS570_FLASH_FBAC_OTPPROTDIS(val) BSP_FLD32(val,16, 23)
 #define TMS570_FLASH_FBAC_OTPPROTDIS_GET(reg) BSP_FLD32GET(reg,16, 23)
@@ -326,7 +326,7 @@ typedef struct{
 #define TMS570_FLASH_FBAC_VREADST_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*-------------------TMS570_FLASHFBFALLBACK-------------------*/
+/*------------------TMS570_FLASH_FBFALLBACK------------------*/
 /* field: BANKPWR7 - Bank 7 Fallback Power Mode */
 #define TMS570_FLASH_FBFALLBACK_BANKPWR7(val) BSP_FLD32(val,14, 15)
 #define TMS570_FLASH_FBFALLBACK_BANKPWR7_GET(reg) BSP_FLD32GET(reg,14, 15)
@@ -343,14 +343,14 @@ typedef struct{
 #define TMS570_FLASH_FBFALLBACK_BANKPWR0_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
 
 
-/*---------------------TMS570_FLASHFBPRDY---------------------*/
+/*--------------------TMS570_FLASH_FBPRDY--------------------*/
 /* field: BANKBUSY - Bank busy bits (one bit for each bank) */
 #define TMS570_FLASH_FBPRDY_BANKBUSY(val) BSP_FLD32(val,16, 23)
 #define TMS570_FLASH_FBPRDY_BANKBUSY_GET(reg) BSP_FLD32GET(reg,16, 23)
 #define TMS570_FLASH_FBPRDY_BANKBUSY_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
 
 /* field: PUMPRDY - Flash pump ready flag */
-#define TMS570_FLASH_FBPRDY_PUMPRDY BSP_FLD32(15)
+#define TMS570_FLASH_FBPRDY_PUMPRDY BSP_BIT32(15)
 
 /* field: BANKRDY - Bank ready bits (one bit for each bank) */
 #define TMS570_FLASH_FBPRDY_BANKRDY(val) BSP_FLD32(val,0, 7)
@@ -358,99 +358,93 @@ typedef struct{
 #define TMS570_FLASH_FBPRDY_BANKRDY_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*---------------------TMS570_FLASHFPAC1---------------------*/
+/*---------------------TMS570_FLASH_FPAC1---------------------*/
 /* field: PSLEEP - Pump Sleep. */
 #define TMS570_FLASH_FPAC1_PSLEEP(val) BSP_FLD32(val,16, 26)
 #define TMS570_FLASH_FPAC1_PSLEEP_GET(reg) BSP_FLD32GET(reg,16, 26)
 #define TMS570_FLASH_FPAC1_PSLEEP_SET(reg,val) BSP_FLD32SET(reg, val,16, 26)
 
 /* field: PUMPPWR - Flash Charge Pump Fallback Power Mode */
-#define TMS570_FLASH_FPAC1_PUMPPWR BSP_FLD32(0)
+#define TMS570_FLASH_FPAC1_PUMPPWR BSP_BIT32(0)
 
 
-/*---------------------TMS570_FLASHFPAC2---------------------*/
+/*---------------------TMS570_FLASH_FPAC2---------------------*/
 /* field: PAGP - Pump Active Grace Period */
 #define TMS570_FLASH_FPAC2_PAGP(val) BSP_FLD32(val,0, 15)
 #define TMS570_FLASH_FPAC2_PAGP_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_FLASH_FPAC2_PAGP_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*----------------------TMS570_FLASHFMAC----------------------*/
+/*---------------------TMS570_FLASH_FMAC---------------------*/
 /* field: BANK - Bank Enable. */
 #define TMS570_FLASH_FMAC_BANK(val) BSP_FLD32(val,0, 2)
 #define TMS570_FLASH_FMAC_BANK_GET(reg) BSP_FLD32GET(reg,0, 2)
 #define TMS570_FLASH_FMAC_BANK_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
 
 
-/*---------------------TMS570_FLASHFMSTAT---------------------*/
+/*--------------------TMS570_FLASH_FMSTAT--------------------*/
 /* field: ILA - Illegal Address */
-#define TMS570_FLASH_FMSTAT_ILA BSP_FLD32(14)
+#define TMS570_FLASH_FMSTAT_ILA BSP_BIT32(14)
 
 /* field: PGV - Program Verify */
-#define TMS570_FLASH_FMSTAT_PGV BSP_FLD32(12)
+#define TMS570_FLASH_FMSTAT_PGV BSP_BIT32(12)
 
 /* field: EV - Erase Verify */
-#define TMS570_FLASH_FMSTAT_EV BSP_FLD32(10)
+#define TMS570_FLASH_FMSTAT_EV BSP_BIT32(10)
 
 /* field: BUSY - Busy */
-#define TMS570_FLASH_FMSTAT_BUSY BSP_FLD32(8)
+#define TMS570_FLASH_FMSTAT_BUSY BSP_BIT32(8)
 
 /* field: ERS - Erase Active */
-#define TMS570_FLASH_FMSTAT_ERS BSP_FLD32(7)
+#define TMS570_FLASH_FMSTAT_ERS BSP_BIT32(7)
 
 /* field: PGM - Program Active */
-#define TMS570_FLASH_FMSTAT_PGM BSP_FLD32(6)
+#define TMS570_FLASH_FMSTAT_PGM BSP_BIT32(6)
 
 /* field: INVDAT - Invalid Data */
-#define TMS570_FLASH_FMSTAT_INVDAT BSP_FLD32(5)
+#define TMS570_FLASH_FMSTAT_INVDAT BSP_BIT32(5)
 
 /* field: CSTAT - Command Status */
-#define TMS570_FLASH_FMSTAT_CSTAT BSP_FLD32(4)
+#define TMS570_FLASH_FMSTAT_CSTAT BSP_BIT32(4)
 
 /* field: VOLTSTAT - Core Voltage Status */
-#define TMS570_FLASH_FMSTAT_VOLTSTAT BSP_FLD32(3)
+#define TMS570_FLASH_FMSTAT_VOLTSTAT BSP_BIT32(3)
 
 /* field: ESUSP - Erase Suspended */
-#define TMS570_FLASH_FMSTAT_ESUSP BSP_FLD32(2)
+#define TMS570_FLASH_FMSTAT_ESUSP BSP_BIT32(2)
 
 /* field: PSUSP - Program Suspended */
-#define TMS570_FLASH_FMSTAT_PSUSP BSP_FLD32(1)
+#define TMS570_FLASH_FMSTAT_PSUSP BSP_BIT32(1)
 
 /* field: SLOCK - Sector Lock Status */
-#define TMS570_FLASH_FMSTAT_SLOCK BSP_FLD32(0)
+#define TMS570_FLASH_FMSTAT_SLOCK BSP_BIT32(0)
 
 
-/*--------------------TMS570_FLASHFEMUDMSW--------------------*/
+/*-------------------TMS570_FLASH_FEMUDMSW-------------------*/
 /* field: EMU_DMSW - EEPROM Emulation Most Significant Data Word */
-#define TMS570_FLASH_FEMUDMSW_EMU_DMSW(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLASH_FEMUDMSW_EMU_DMSW_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLASH_FEMUDMSW_EMU_DMSW_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_FLASH_FEMUDLSW-------------------*/
-/*--------------------TMS570_FLASHFEMUDLSW--------------------*/
 /* field: EMU_DLSW - EEPROM Emulation Least Significant Data Word */
-#define TMS570_FLASH_FEMUDLSW_EMU_DLSW(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLASH_FEMUDLSW_EMU_DLSW_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLASH_FEMUDLSW_EMU_DLSW_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*--------------------TMS570_FLASH_FEMUECC--------------------*/
-/*--------------------TMS570_FLASHFEMUECC--------------------*/
 /* field: EMU_ECC - This register can be written by the CPU in any mode. */
 #define TMS570_FLASH_FEMUECC_EMU_ECC(val) BSP_FLD32(val,0, 7)
 #define TMS570_FLASH_FEMUECC_EMU_ECC_GET(reg) BSP_FLD32GET(reg,0, 7)
 #define TMS570_FLASH_FEMUECC_EMU_ECC_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*--------------------TMS570_FLASHFEMUADDR--------------------*/
+/*-------------------TMS570_FLASH_FEMUADDR-------------------*/
 /* field: EMU_ADDR - EEPROM Emulation Address */
 #define TMS570_FLASH_FEMUADDR_EMU_ADDR(val) BSP_FLD32(val,3, 21)
 #define TMS570_FLASH_FEMUADDR_EMU_ADDR_GET(reg) BSP_FLD32GET(reg,3, 21)
 #define TMS570_FLASH_FEMUADDR_EMU_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,3, 21)
 
 
-/*-------------------TMS570_FLASHFDIAGCTRL-------------------*/
+/*-------------------TMS570_FLASH_FDIAGCTRL-------------------*/
 /* field: DIAG_TRIG - Diagnostic Trigger */
-#define TMS570_FLASH_FDIAGCTRL_DIAG_TRIG BSP_FLD32(24)
+#define TMS570_FLASH_FDIAGCTRL_DIAG_TRIG BSP_BIT32(24)
 
 /* field: DIAG_EN_KEY - Diagnostic Enable Key */
 #define TMS570_FLASH_FDIAGCTRL_DIAG_EN_KEY(val) BSP_FLD32(val,16, 19)
@@ -463,23 +457,17 @@ typedef struct{
 #define TMS570_FLASH_FDIAGCTRL_DIAG_ECC_SEL_SET(reg,val) BSP_FLD32SET(reg, val,12, 14)
 
 
-/*-------------------TMS570_FLASHFRAWDATAH-------------------*/
+/*-------------------TMS570_FLASH_FRAWDATAH-------------------*/
 /* field: RAW_DATA_ - Uncorrected Raw Data */
-#define TMS570_FLASH_FRAWDATAH_RAW_DATA_(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLASH_FRAWDATAH_RAW_DATA__GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLASH_FRAWDATAH_RAW_DATA__SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_FLASH_FRAWDATAL-------------------*/
-/*-------------------TMS570_FLASHFRAWDATAL-------------------*/
 /* field: RAW_DATA_ - Uncorrected Raw Data. Same as FRAW_DATAH but stores lower 32 bits. */
-#define TMS570_FLASH_FRAWDATAL_RAW_DATA_(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLASH_FRAWDATAL_RAW_DATA__GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLASH_FRAWDATAL_RAW_DATA__SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*--------------------TMS570_FLASH_FRAWECC--------------------*/
-/*--------------------TMS570_FLASHFRAWECC--------------------*/
 /* field: PIPE_BUF - Error came from pipeline buffer hit */
-#define TMS570_FLASH_FRAWECC_PIPE_BUF BSP_FLD32(8)
+#define TMS570_FLASH_FRAWECC_PIPE_BUF BSP_BIT32(8)
 
 /* field: RAW_ECC - Uncorrected Raw ECC */
 #define TMS570_FLASH_FRAWECC_RAW_ECC(val) BSP_FLD32(val,0, 7)
@@ -487,9 +475,9 @@ typedef struct{
 #define TMS570_FLASH_FRAWECC_RAW_ECC_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*--------------------TMS570_FLASHFPAROVR--------------------*/
+/*--------------------TMS570_FLASH_FPAROVR--------------------*/
 /* field: BNK_INV_PAR - Buffer Invert Parity */
-#define TMS570_FLASH_FPAROVR_BNK_INV_PAR BSP_FLD32(16)
+#define TMS570_FLASH_FPAROVR_BNK_INV_PAR BSP_BIT32(16)
 
 /* field: BUS_PAR_DIS - Disable Bus Parity */
 #define TMS570_FLASH_FPAROVR_BUS_PAR_DIS(val) BSP_FLD32(val,12, 15)
@@ -502,7 +490,7 @@ typedef struct{
 #define TMS570_FLASH_FPAROVR_PAR_OVR_KEY_SET(reg,val) BSP_FLD32SET(reg, val,9, 11)
 
 /* field: ADD_INV_PAR - Address Odd Parity */
-#define TMS570_FLASH_FPAROVR_ADD_INV_PAR BSP_FLD32(8)
+#define TMS570_FLASH_FPAROVR_ADD_INV_PAR BSP_BIT32(8)
 
 /* field: DAT_INV_PAR - Data Odd Parity */
 #define TMS570_FLASH_FPAROVR_DAT_INV_PAR(val) BSP_FLD32(val,0, 7)
@@ -510,7 +498,7 @@ typedef struct{
 #define TMS570_FLASH_FPAROVR_DAT_INV_PAR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*-------------------TMS570_FLASHFEDACSDIS2-------------------*/
+/*------------------TMS570_FLASH_FEDACSDIS2------------------*/
 /* field: BankID3_Inverse - The bank ID inverse bits are used with the bank ID bits to select the bank for which a sector */
 #define TMS570_FLASH_FEDACSDIS2_BankID3_Inverse(val) BSP_FLD32(val,29, 31)
 #define TMS570_FLASH_FEDACSDIS2_BankID3_Inverse_GET(reg) BSP_FLD32GET(reg,29, 31)
@@ -552,28 +540,28 @@ typedef struct{
 #define TMS570_FLASH_FEDACSDIS2_SectorID2_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*--------------------TMS570_FLASHFSMWRENA--------------------*/
+/*-------------------TMS570_FLASH_FSMWRENA-------------------*/
 /* field: WR_ENA - Flash State Machine Write Enable */
 #define TMS570_FLASH_FSMWRENA_WR_ENA(val) BSP_FLD32(val,0, 2)
 #define TMS570_FLASH_FSMWRENA_WR_ENA_GET(reg) BSP_FLD32GET(reg,0, 2)
 #define TMS570_FLASH_FSMWRENA_WR_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
 
 
-/*-------------------TMS570_FLASHFSMSECTOR-------------------*/
+/*-------------------TMS570_FLASH_FSMSECTOR-------------------*/
 /* field: SECT_ERASED - Sectors Erased */
 #define TMS570_FLASH_FSMSECTOR_SECT_ERASED(val) BSP_FLD32(val,16, 31)
 #define TMS570_FLASH_FSMSECTOR_SECT_ERASED_GET(reg) BSP_FLD32GET(reg,16, 31)
 #define TMS570_FLASH_FSMSECTOR_SECT_ERASED_SET(reg,val) BSP_FLD32SET(reg, val,16, 31)
 
 
-/*------------------TMS570_FLASHEEPROMCONFIG------------------*/
+/*-----------------TMS570_FLASH_EEPROMCONFIG-----------------*/
 /* field: EWAIT - EEPROM Wait state Counter */
 #define TMS570_FLASH_EEPROMCONFIG_EWAIT(val) BSP_FLD32(val,16, 19)
 #define TMS570_FLASH_EEPROMCONFIG_EWAIT_GET(reg) BSP_FLD32GET(reg,16, 19)
 #define TMS570_FLASH_EEPROMCONFIG_EWAIT_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
 
 /* field: AUTOSUSP_EN - Auto Suspend Enable */
-#define TMS570_FLASH_EEPROMCONFIG_AUTOSUSP_EN BSP_FLD32(8)
+#define TMS570_FLASH_EEPROMCONFIG_AUTOSUSP_EN BSP_BIT32(8)
 
 /* field: AUTOSTART_GRACE - Auto-suspend Startup Grace Period */
 #define TMS570_FLASH_EEPROMCONFIG_AUTOSTART_GRACE(val) BSP_FLD32(val,0, 7)
@@ -581,37 +569,37 @@ typedef struct{
 #define TMS570_FLASH_EEPROMCONFIG_AUTOSTART_GRACE_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*--------------------TMS570_FLASHEECTRL1--------------------*/
+/*--------------------TMS570_FLASH_EECTRL1--------------------*/
 /* field: EDACMODE - Error Correction Mode. */
 #define TMS570_FLASH_EECTRL1_EDACMODE(val) BSP_FLD32(val,16, 19)
 #define TMS570_FLASH_EECTRL1_EDACMODE_GET(reg) BSP_FLD32GET(reg,16, 19)
 #define TMS570_FLASH_EECTRL1_EDACMODE_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
 
 /* field: EE_EOFEN - EEPROM Emulation Event on a correctable One's Fail Enable bit */
-#define TMS570_FLASH_EECTRL1_EE_EOFEN BSP_FLD32(10)
+#define TMS570_FLASH_EECTRL1_EE_EOFEN BSP_BIT32(10)
 
 /* field: EE_EZFEN - EEPROM Emulation Event on a correctable Zero's Fail Enable bit */
-#define TMS570_FLASH_EECTRL1_EE_EZFEN BSP_FLD32(9)
+#define TMS570_FLASH_EECTRL1_EE_EZFEN BSP_BIT32(9)
 
 /* field: EE_EPEN - EEPROM Emulation Error Profiling Enable. */
-#define TMS570_FLASH_EECTRL1_EE_EPEN BSP_FLD32(8)
+#define TMS570_FLASH_EECTRL1_EE_EPEN BSP_BIT32(8)
 
 
-/*--------------------TMS570_FLASHEECTRL2--------------------*/
+/*--------------------TMS570_FLASH_EECTRL2--------------------*/
 /* field: EE_SEC_THRESHOLD - EEPROM Emulation Single Error Correction Threshold */
 #define TMS570_FLASH_EECTRL2_EE_SEC_THRESHOLD(val) BSP_FLD32(val,0, 15)
 #define TMS570_FLASH_EECTRL2_EE_SEC_THRESHOLD_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_FLASH_EECTRL2_EE_SEC_THRESHOLD_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*------------------TMS570_FLASHEECORERRCNT------------------*/
+/*------------------TMS570_FLASH_EECORERRCNT------------------*/
 /* field: EE_ERRCNT - Single Error Correction Count */
 #define TMS570_FLASH_EECORERRCNT_EE_ERRCNT(val) BSP_FLD32(val,0, 15)
 #define TMS570_FLASH_EECORERRCNT_EE_ERRCNT_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_FLASH_EECORERRCNT_EE_ERRCNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*------------------TMS570_FLASHEECORERRADD------------------*/
+/*------------------TMS570_FLASH_EECORERRADD------------------*/
 /* field: COR_ERR_ADD - Correctable Error Address */
 #define TMS570_FLASH_EECORERRADD_COR_ERR_ADD(val) BSP_FLD32(val,3, 31)
 #define TMS570_FLASH_EECORERRADD_COR_ERR_ADD_GET(reg) BSP_FLD32GET(reg,3, 31)
@@ -623,9 +611,9 @@ typedef struct{
 #define TMS570_FLASH_EECORERRADD_B_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
 
 
-/*------------------TMS570_FLASHEECORERRPOS------------------*/
+/*------------------TMS570_FLASH_EECORERRPOS------------------*/
 /* field: TYPE - ErrorType */
-#define TMS570_FLASH_EECORERRPOS_TYPE BSP_FLD32(8)
+#define TMS570_FLASH_EECORERRPOS_TYPE BSP_BIT32(8)
 
 /* field: EE_ERR_POS - The bit address of the single bit error */
 #define TMS570_FLASH_EECORERRPOS_EE_ERR_POS(val) BSP_FLD32(val,0, 7)
@@ -633,33 +621,33 @@ typedef struct{
 #define TMS570_FLASH_EECORERRPOS_EE_ERR_POS_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*--------------------TMS570_FLASHEESTATUS--------------------*/
+/*-------------------TMS570_FLASH_EESTATUS-------------------*/
 /* field: EE_D_UNC_ERR - Diagnostic Mode Uncorrectable Error Status Flag */
-#define TMS570_FLASH_EESTATUS_EE_D_UNC_ERR BSP_FLD32(12)
+#define TMS570_FLASH_EESTATUS_EE_D_UNC_ERR BSP_BIT32(12)
 
 /* field: EE_UNC_ERR - EEPROM Emulation Uncorrectable Error Flag */
-#define TMS570_FLASH_EESTATUS_EE_UNC_ERR BSP_FLD32(8)
+#define TMS570_FLASH_EESTATUS_EE_UNC_ERR BSP_BIT32(8)
 
 /* field: EE_CMG - EEPROM Emulation Compare Malfunction Good */
-#define TMS570_FLASH_EESTATUS_EE_CMG BSP_FLD32(6)
+#define TMS570_FLASH_EESTATUS_EE_CMG BSP_BIT32(6)
 
 /* field: EE_CME - . */
-#define TMS570_FLASH_EESTATUS_EE_CME BSP_FLD32(4)
+#define TMS570_FLASH_EESTATUS_EE_CME BSP_BIT32(4)
 
 /* field: EE_D_COR_ERR - Diagnostic Correctable Error Flag */
-#define TMS570_FLASH_EESTATUS_EE_D_COR_ERR BSP_FLD32(3)
+#define TMS570_FLASH_EESTATUS_EE_D_COR_ERR BSP_BIT32(3)
 
 /* field: EE_ERR_ONE_FLG - Error on One Fail Error Flag */
-#define TMS570_FLASH_EESTATUS_EE_ERR_ONE_FLG BSP_FLD32(2)
+#define TMS570_FLASH_EESTATUS_EE_ERR_ONE_FLG BSP_BIT32(2)
 
 /* field: EE_ERR_ZERO_FLG - Error on Zero Fail Error Flag */
-#define TMS570_FLASH_EESTATUS_EE_ERR_ZERO_FLG BSP_FLD32(1)
+#define TMS570_FLASH_EESTATUS_EE_ERR_ZERO_FLG BSP_BIT32(1)
 
 /* field: EE_ERR_PRF_FLG - Error Profiling Error Flag */
-#define TMS570_FLASH_EESTATUS_EE_ERR_PRF_FLG BSP_FLD32(0)
+#define TMS570_FLASH_EESTATUS_EE_ERR_PRF_FLG BSP_BIT32(0)
 
 
-/*------------------TMS570_FLASHEEUNCERRADD------------------*/
+/*------------------TMS570_FLASH_EEUNCERRADD------------------*/
 /* field: UNC_ERR_ADD - Un-correctable Error Address */
 #define TMS570_FLASH_EEUNCERRADD_UNC_ERR_ADD(val) BSP_FLD32(val,3, 31)
 #define TMS570_FLASH_EEUNCERRADD_UNC_ERR_ADD_GET(reg) BSP_FLD32GET(reg,3, 31)
@@ -671,7 +659,7 @@ typedef struct{
 #define TMS570_FLASH_EEUNCERRADD_B_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
 
 
-/*--------------------TMS570_FLASHFCFGBANK--------------------*/
+/*-------------------TMS570_FLASH_FCFGBANK-------------------*/
 /* field: EE_BANK_WIDTH - Bank 7 width (144 bits wide) */
 #define TMS570_FLASH_FCFGBANK_EE_BANK_WIDTH(val) BSP_FLD32(val,20, 31)
 #define TMS570_FLASH_FCFGBANK_EE_BANK_WIDTH_GET(reg) BSP_FLD32GET(reg,20, 31)
@@ -684,4 +672,4 @@ typedef struct{
 
 
 
-#endif /* LIBBSP_ARM_tms570_FLASH */
+#endif /* LIBBSP_ARM_TMS570_FLASH */

c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_flex_ray.h

@@ -36,8 +36,8 @@
  * of the authors and should not be interpreted as representing official policies,
  * either expressed or implied, of the FreeBSD Project.
 */
-#ifndef LIBBSP_ARM_tms570_FLEX_RAY
+#ifndef LIBBSP_ARM_TMS570_FLEX_RAY
-#define LIBBSP_ARM_tms570_FLEX_RAY
+#define LIBBSP_ARM_TMS570_FLEX_RAY
 
 #include <bsp/utility.h>
 
@@ -121,7 +121,7 @@ typedef struct{
 } tms570_flex_ray_t;
 
 
-/*--------------------TMS570_FLEX_RAYGSN0--------------------*/
+/*--------------------TMS570_FLEX_RAY_GSN0--------------------*/
 /* field: Data_A - Data_A(15-0) */
 #define TMS570_FLEX_RAY_GSN0_Data_A(val) BSP_FLD32(val,16, 31)
 #define TMS570_FLEX_RAY_GSN0_Data_A_GET(reg) BSP_FLD32GET(reg,16, 31)
@@ -133,7 +133,7 @@ typedef struct{
 #define TMS570_FLEX_RAY_GSN0_Data_B_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*--------------------TMS570_FLEX_RAYGSN1--------------------*/
+/*--------------------TMS570_FLEX_RAY_GSN1--------------------*/
 /* field: Data_C - Data_C(15-0) */
 #define TMS570_FLEX_RAY_GSN1_Data_C(val) BSP_FLD32(val,16, 31)
 #define TMS570_FLEX_RAY_GSN1_Data_C_GET(reg) BSP_FLD32GET(reg,16, 31)
@@ -145,12 +145,12 @@ typedef struct{
 #define TMS570_FLEX_RAY_GSN1_Data_D_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_FLEX_RAYGCS---------------------*/
+/*--------------------TMS570_FLEX_RAY_GCS--------------------*/
 /* field: ENDVBM - Endianness Correction on VBusp Master */
-#define TMS570_FLEX_RAY_GCS_ENDVBM BSP_FLD32(31)
+#define TMS570_FLEX_RAY_GCS_ENDVBM BSP_BIT32(31)
 
 /* field: ENDVBS - Endianness correction on VBusp Slave */
-#define TMS570_FLEX_RAY_GCS_ENDVBS BSP_FLD32(30)
+#define TMS570_FLEX_RAY_GCS_ENDVBS BSP_BIT32(30)
 
 /* field: ENDRx - Endianness Correction for No (header or payload) Data Sink Access */
 #define TMS570_FLEX_RAY_GCS_ENDRx(val) BSP_FLD32(val,28, 29)
@@ -168,10 +168,10 @@ typedef struct{
 #define TMS570_FLEX_RAY_GCS_ENDPx_SET(reg,val) BSP_FLD32SET(reg, val,24, 25)
 
 /* field: PRIO - Transfer Priority */
-#define TMS570_FLEX_RAY_GCS_PRIO BSP_FLD32(21)
+#define TMS570_FLEX_RAY_GCS_PRIO BSP_BIT32(21)
 
 /* field: PEFT - Parity for Test */
-#define TMS570_FLEX_RAY_GCS_PEFT BSP_FLD32(20)
+#define TMS570_FLEX_RAY_GCS_PEFT BSP_BIT32(20)
 
 /* field: PELx - Parity Lock */
 #define TMS570_FLEX_RAY_GCS_PELx(val) BSP_FLD32(val,16, 19)
@@ -179,36 +179,36 @@ typedef struct{
 #define TMS570_FLEX_RAY_GCS_PELx_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
 
 /* field: CETESM - Clear ETESM Register */
-#define TMS570_FLEX_RAY_GCS_CETESM BSP_FLD32(14)
+#define TMS570_FLEX_RAY_GCS_CETESM BSP_BIT32(14)
 
 /* field: CTTCC - Clear TTCC Register */
-#define TMS570_FLEX_RAY_GCS_CTTCC BSP_FLD32(13)
+#define TMS570_FLEX_RAY_GCS_CTTCC BSP_BIT32(13)
 
 /* field: CTTSM - Clear TTSM Register */
-#define TMS570_FLEX_RAY_GCS_CTTSM BSP_FLD32(12)
+#define TMS570_FLEX_RAY_GCS_CTTSM BSP_BIT32(12)
 
 /* field: ETSM - Enable Transfer Status Mirrored */
-#define TMS570_FLEX_RAY_GCS_ETSM BSP_FLD32(8)
+#define TMS570_FLEX_RAY_GCS_ETSM BSP_BIT32(8)
 
 /* field: SILE - Status Interrupt Line Enable */
-#define TMS570_FLEX_RAY_GCS_SILE BSP_FLD32(5)
+#define TMS570_FLEX_RAY_GCS_SILE BSP_BIT32(5)
 
 /* field: EILE - Error Interrupt Line Enable */
-#define TMS570_FLEX_RAY_GCS_EILE BSP_FLD32(4)
+#define TMS570_FLEX_RAY_GCS_EILE BSP_BIT32(4)
 
 /* field: TUH - Transfer Unit Halted */
-#define TMS570_FLEX_RAY_GCS_TUH BSP_FLD32(1)
+#define TMS570_FLEX_RAY_GCS_TUH BSP_BIT32(1)
 
 /* field: TUE - Transfer Unit Enabled */
-#define TMS570_FLEX_RAY_GCS_TUE BSP_FLD32(0)
+#define TMS570_FLEX_RAY_GCS_TUE BSP_BIT32(0)
 
 
-/*---------------------TMS570_FLEX_RAYGCR---------------------*/
+/*--------------------TMS570_FLEX_RAY_GCR--------------------*/
 /* field: ENDVBM - Endianness Correction on VBusp Master */
-#define TMS570_FLEX_RAY_GCR_ENDVBM BSP_FLD32(31)
+#define TMS570_FLEX_RAY_GCR_ENDVBM BSP_BIT32(31)
 
 /* field: ENDVBS - Endianness correction on VBusp Slave */
-#define TMS570_FLEX_RAY_GCR_ENDVBS BSP_FLD32(30)
+#define TMS570_FLEX_RAY_GCR_ENDVBS BSP_BIT32(30)
 
 /* field: ENDRx - Endianness Correction for No (header or payload) Data Sink Access */
 #define TMS570_FLEX_RAY_GCR_ENDRx(val) BSP_FLD32(val,28, 29)
@@ -226,10 +226,10 @@ typedef struct{
 #define TMS570_FLEX_RAY_GCR_ENDPx_SET(reg,val) BSP_FLD32SET(reg, val,24, 25)
 
 /* field: PRIO - Transfer Priority */
-#define TMS570_FLEX_RAY_GCR_PRIO BSP_FLD32(21)
+#define TMS570_FLEX_RAY_GCR_PRIO BSP_BIT32(21)
 
 /* field: PEFT - Parity for Test */
-#define TMS570_FLEX_RAY_GCR_PEFT BSP_FLD32(20)
+#define TMS570_FLEX_RAY_GCR_PEFT BSP_BIT32(20)
 
 /* field: PELx - Parity Lock */
 #define TMS570_FLEX_RAY_GCR_PELx(val) BSP_FLD32(val,16, 19)
@@ -237,41 +237,41 @@ typedef struct{
 #define TMS570_FLEX_RAY_GCR_PELx_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
 
 /* field: CETESM - Clear ETESM Register */
-#define TMS570_FLEX_RAY_GCR_CETESM BSP_FLD32(14)
+#define TMS570_FLEX_RAY_GCR_CETESM BSP_BIT32(14)
 
 /* field: CTTCC - Clear TTCC Register */
-#define TMS570_FLEX_RAY_GCR_CTTCC BSP_FLD32(13)
+#define TMS570_FLEX_RAY_GCR_CTTCC BSP_BIT32(13)
 
 /* field: CTTSM - Clear TTSM Register */
-#define TMS570_FLEX_RAY_GCR_CTTSM BSP_FLD32(12)
+#define TMS570_FLEX_RAY_GCR_CTTSM BSP_BIT32(12)
 
 /* field: ETSM - Enable Transfer Status Mirrored */
-#define TMS570_FLEX_RAY_GCR_ETSM BSP_FLD32(8)
+#define TMS570_FLEX_RAY_GCR_ETSM BSP_BIT32(8)
 
 /* field: SILE - Status Interrupt Line Enable */
-#define TMS570_FLEX_RAY_GCR_SILE BSP_FLD32(5)
+#define TMS570_FLEX_RAY_GCR_SILE BSP_BIT32(5)
 
 /* field: EILE - Error Interrupt Line Enable */
-#define TMS570_FLEX_RAY_GCR_EILE BSP_FLD32(4)
+#define TMS570_FLEX_RAY_GCR_EILE BSP_BIT32(4)
 
 /* field: TUH - Transfer Unit Halted */
-#define TMS570_FLEX_RAY_GCR_TUH BSP_FLD32(1)
+#define TMS570_FLEX_RAY_GCR_TUH BSP_BIT32(1)
 
 /* field: TUE - Transfer Unit Enabled */
-#define TMS570_FLEX_RAY_GCR_TUE BSP_FLD32(0)
+#define TMS570_FLEX_RAY_GCR_TUE BSP_BIT32(0)
 
 
-/*--------------------TMS570_FLEX_RAYTSCB--------------------*/
+/*--------------------TMS570_FLEX_RAY_TSCB--------------------*/
 /* field: TSMS - Transfer State Machine Status */
 #define TMS570_FLEX_RAY_TSCB_TSMS(val) BSP_FLD32(val,16, 20)
 #define TMS570_FLEX_RAY_TSCB_TSMS_GET(reg) BSP_FLD32GET(reg,16, 20)
 #define TMS570_FLEX_RAY_TSCB_TSMS_SET(reg,val) BSP_FLD32SET(reg, val,16, 20)
 
 /* field: STUH - Status of Transfer Unit State Machine for Halt Detection */
-#define TMS570_FLEX_RAY_TSCB_STUH BSP_FLD32(12)
+#define TMS570_FLEX_RAY_TSCB_STUH BSP_BIT32(12)
 
 /* field: IDLE - Detects Transfer State Machine State IDLE */
-#define TMS570_FLEX_RAY_TSCB_IDLE BSP_FLD32(8)
+#define TMS570_FLEX_RAY_TSCB_IDLE BSP_BIT32(8)
 
 /* field: BN - Buffer Number */
 #define TMS570_FLEX_RAY_TSCB_BN(val) BSP_FLD32(val,0, 6)
@@ -279,114 +279,75 @@ typedef struct{
 #define TMS570_FLEX_RAY_TSCB_BN_SET(reg,val) BSP_FLD32SET(reg, val,0, 6)
 
 
-/*--------------------TMS570_FLEX_RAYLTBCC--------------------*/
+/*-------------------TMS570_FLEX_RAY_LTBCC-------------------*/
 /* field: BN - Buffer number. */
 #define TMS570_FLEX_RAY_LTBCC_BN(val) BSP_FLD32(val,0, 6)
 #define TMS570_FLEX_RAY_LTBCC_BN_GET(reg) BSP_FLD32GET(reg,0, 6)
 #define TMS570_FLEX_RAY_LTBCC_BN_SET(reg,val) BSP_FLD32SET(reg, val,0, 6)
 
 
-/*--------------------TMS570_FLEX_RAYLTBSM--------------------*/
+/*-------------------TMS570_FLEX_RAY_LTBSM-------------------*/
 /* field: BN - Buffer number. */
 #define TMS570_FLEX_RAY_LTBSM_BN(val) BSP_FLD32(val,0, 6)
 #define TMS570_FLEX_RAY_LTBSM_BN_GET(reg) BSP_FLD32GET(reg,0, 6)
 #define TMS570_FLEX_RAY_LTBSM_BN_SET(reg,val) BSP_FLD32SET(reg, val,0, 6)
 
 
-/*---------------------TMS570_FLEX_RAYTBA---------------------*/
+/*--------------------TMS570_FLEX_RAY_TBA--------------------*/
 /* field: TBA - Transfer Base Address. */
-#define TMS570_FLEX_RAY_TBA_TBA(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TBA_TBA_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TBA_TBA_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*--------------------TMS570_FLEX_RAY_NTBA--------------------*/
-/*--------------------TMS570_FLEX_RAYNTBA--------------------*/
 /* field: nTBA - nTBA(31-0) */
-#define TMS570_FLEX_RAY_NTBA_nTBA(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_NTBA_nTBA_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_NTBA_nTBA_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*--------------------TMS570_FLEX_RAY_BAMS--------------------*/
-/*--------------------TMS570_FLEX_RAYBAMS--------------------*/
 /* field: BAMS - Base Address of Mirrored Status32-bit base pointer, 2 LSB are not significant (32-bit */
-#define TMS570_FLEX_RAY_BAMS_BAMS(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_BAMS_BAMS_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_BAMS_BAMS_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*--------------------TMS570_FLEX_RAY_SAMP--------------------*/
-/*--------------------TMS570_FLEX_RAYSAMP--------------------*/
 /* field: SAMP - Start Address Memory Protection. */
-#define TMS570_FLEX_RAY_SAMP_SAMP(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_SAMP_SAMP_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_SAMP_SAMP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*--------------------TMS570_FLEX_RAY_EAMP--------------------*/
-/*--------------------TMS570_FLEX_RAYEAMP--------------------*/
 /* field: EAMP - End Address Memory Protection. */
-#define TMS570_FLEX_RAY_EAMP_EAMP(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_EAMP_EAMP_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_EAMP_EAMP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_FLEX_RAY_TSMO1-------------------*/
-/*--------------------TMS570_FLEX_RAYTSMO1--------------------*/
 /* field: TSMO1 - Transfer to System Memory Occurred Register 1. */
-#define TMS570_FLEX_RAY_TSMO1_TSMO1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TSMO1_TSMO1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TSMO1_TSMO1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_FLEX_RAY_TSMO2-------------------*/
-/*--------------------TMS570_FLEX_RAYTSMO2--------------------*/
 /* field: TSMO1 - Transfer to System Memory Occurred Register 1. */
-#define TMS570_FLEX_RAY_TSMO2_TSMO1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TSMO2_TSMO1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TSMO2_TSMO1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_FLEX_RAY_TSMO3-------------------*/
-/*--------------------TMS570_FLEX_RAYTSMO3--------------------*/
 /* field: TSMO1 - Transfer to System Memory Occurred Register 1. */
-#define TMS570_FLEX_RAY_TSMO3_TSMO1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TSMO3_TSMO1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TSMO3_TSMO1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_FLEX_RAY_TSMO4-------------------*/
-/*--------------------TMS570_FLEX_RAYTSMO4--------------------*/
 /* field: TSMO1 - Transfer to System Memory Occurred Register 1. */
-#define TMS570_FLEX_RAY_TSMO4_TSMO1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TSMO4_TSMO1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TSMO4_TSMO1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_FLEX_RAY_TCCO1-------------------*/
-/*--------------------TMS570_FLEX_RAYTCCO1--------------------*/
 /* field: TCCO1 - Transfer to Communication Controller Occurred Register 1. */
-#define TMS570_FLEX_RAY_TCCO1_TCCO1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TCCO1_TCCO1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TCCO1_TCCO1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_FLEX_RAY_TCCO2-------------------*/
-/*--------------------TMS570_FLEX_RAYTCCO2--------------------*/
 /* field: TCCO1 - Transfer to Communication Controller Occurred Register 1. */
-#define TMS570_FLEX_RAY_TCCO2_TCCO1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TCCO2_TCCO1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TCCO2_TCCO1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_FLEX_RAY_TCCO3-------------------*/
-/*--------------------TMS570_FLEX_RAYTCCO3--------------------*/
 /* field: TCCO1 - Transfer to Communication Controller Occurred Register 1. */
-#define TMS570_FLEX_RAY_TCCO3_TCCO1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TCCO3_TCCO1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TCCO3_TCCO1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_FLEX_RAY_TCCO4-------------------*/
-/*--------------------TMS570_FLEX_RAYTCCO4--------------------*/
 /* field: TCCO1 - Transfer to Communication Controller Occurred Register 1. */
-#define TMS570_FLEX_RAY_TCCO4_TCCO1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TCCO4_TCCO1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TCCO4_TCCO1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_FLEX_RAY_TOOFF-------------------*/
-/*--------------------TMS570_FLEX_RAYTOOFF--------------------*/
 /* field: TDIR - Transfer Direction. */
-#define TMS570_FLEX_RAY_TOOFF_TDIR BSP_FLD32(8)
+#define TMS570_FLEX_RAY_TOOFF_TDIR BSP_BIT32(8)
 
 /* field: OFF - Offset Vector */
 #define TMS570_FLEX_RAY_TOOFF_OFF(val) BSP_FLD32(val,0, 7)
@@ -394,19 +355,19 @@ typedef struct{
 #define TMS570_FLEX_RAY_TOOFF_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*--------------------TMS570_FLEX_RAYPEADR--------------------*/
+/*-------------------TMS570_FLEX_RAY_PEADR-------------------*/
 /* field: ADR - Address of failing TCR location. */
 #define TMS570_FLEX_RAY_PEADR_ADR(val) BSP_FLD32(val,0, 8)
 #define TMS570_FLEX_RAY_PEADR_ADR_GET(reg) BSP_FLD32GET(reg,0, 8)
 #define TMS570_FLEX_RAY_PEADR_ADR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
 
 
-/*--------------------TMS570_FLEX_RAYTEIF--------------------*/
+/*--------------------TMS570_FLEX_RAY_TEIF--------------------*/
 /* field: MPV - Memory Protection Violation. */
-#define TMS570_FLEX_RAY_TEIF_MPV BSP_FLD32(17)
+#define TMS570_FLEX_RAY_TEIF_MPV BSP_BIT32(17)
 
 /* field: PE - Parity Error. The flag signals a parity error to the host. */
-#define TMS570_FLEX_RAY_TEIF_PE BSP_FLD32(16)
+#define TMS570_FLEX_RAY_TEIF_PE BSP_BIT32(16)
 
 /* field: RSTAT - Status of VBUS on read transfers. */
 #define TMS570_FLEX_RAY_TEIF_RSTAT(val) BSP_FLD32(val,8, 10)
@@ -419,13 +380,13 @@ typedef struct{
 #define TMS570_FLEX_RAY_TEIF_WSTAT_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
 
 /* field: TNR - Transfer Not Ready. */
-#define TMS570_FLEX_RAY_TEIF_TNR BSP_FLD32(1)
+#define TMS570_FLEX_RAY_TEIF_TNR BSP_BIT32(1)
 
 /* field: FAC - Forbidden Access. */
-#define TMS570_FLEX_RAY_TEIF_FAC BSP_FLD32(0)
+#define TMS570_FLEX_RAY_TEIF_FAC BSP_BIT32(0)
 
 
-/*-------------------TMS570_FLEX_RAYTEIRES-------------------*/
+/*-------------------TMS570_FLEX_RAY_TEIRES-------------------*/
 /* field: RSTATE - Read Error Interrupt Generation (interrupt generation on VBUS read transfer errors). */
 #define TMS570_FLEX_RAY_TEIRES_RSTATE(val) BSP_FLD32(val,8, 10)
 #define TMS570_FLEX_RAY_TEIRES_RSTATE_GET(reg) BSP_FLD32GET(reg,8, 10)
@@ -437,13 +398,13 @@ typedef struct{
 #define TMS570_FLEX_RAY_TEIRES_WSTATE_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
 
 /* field: TNRE - Transfer Not Ready Enable. */
-#define TMS570_FLEX_RAY_TEIRES_TNRE BSP_FLD32(1)
+#define TMS570_FLEX_RAY_TEIRES_TNRE BSP_BIT32(1)
 
 /* field: FACE - Forbidden Access Enable. */
-#define TMS570_FLEX_RAY_TEIRES_FACE BSP_FLD32(0)
+#define TMS570_FLEX_RAY_TEIRES_FACE BSP_BIT32(0)
 
 
-/*-------------------TMS570_FLEX_RAYTEIRER-------------------*/
+/*-------------------TMS570_FLEX_RAY_TEIRER-------------------*/
 /* field: RSTATE - Read Error Interrupt Generation (interrupt generation on VBUS read transfer errors). */
 #define TMS570_FLEX_RAY_TEIRER_RSTATE(val) BSP_FLD32(val,8, 10)
 #define TMS570_FLEX_RAY_TEIRER_RSTATE_GET(reg) BSP_FLD32GET(reg,8, 10)
@@ -455,347 +416,203 @@ typedef struct{
 #define TMS570_FLEX_RAY_TEIRER_WSTATE_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
 
 /* field: TNRE - Transfer Not Ready Enable. */
-#define TMS570_FLEX_RAY_TEIRER_TNRE BSP_FLD32(1)
+#define TMS570_FLEX_RAY_TEIRER_TNRE BSP_BIT32(1)
 
 /* field: FACE - Forbidden Access Enable. */
-#define TMS570_FLEX_RAY_TEIRER_FACE BSP_FLD32(0)
+#define TMS570_FLEX_RAY_TEIRER_FACE BSP_BIT32(0)
 
 
-/*-------------------TMS570_FLEX_RAYTTSMS1-------------------*/
+/*-------------------TMS570_FLEX_RAY_TTSMS1-------------------*/
 /* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */
-#define TMS570_FLEX_RAY_TTSMS1_TTSMS1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TTSMS1_TTSMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TTSMS1_TTSMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_FLEX_RAY_TTSMR1-------------------*/
-/*-------------------TMS570_FLEX_RAYTTSMR1-------------------*/
 /* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */
-#define TMS570_FLEX_RAY_TTSMR1_TTSMS1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TTSMR1_TTSMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TTSMR1_TTSMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_FLEX_RAY_TTSMS2-------------------*/
-/*-------------------TMS570_FLEX_RAYTTSMS2-------------------*/
 /* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */
-#define TMS570_FLEX_RAY_TTSMS2_TTSMS1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TTSMS2_TTSMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TTSMS2_TTSMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_FLEX_RAY_TTSMR2-------------------*/
-/*-------------------TMS570_FLEX_RAYTTSMR2-------------------*/
 /* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */
-#define TMS570_FLEX_RAY_TTSMR2_TTSMS1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TTSMR2_TTSMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TTSMR2_TTSMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_FLEX_RAY_TTSMS3-------------------*/
-/*-------------------TMS570_FLEX_RAYTTSMS3-------------------*/
 /* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */
-#define TMS570_FLEX_RAY_TTSMS3_TTSMS1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TTSMS3_TTSMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TTSMS3_TTSMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_FLEX_RAY_TTSMR3-------------------*/
-/*-------------------TMS570_FLEX_RAYTTSMR3-------------------*/
 /* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */
-#define TMS570_FLEX_RAY_TTSMR3_TTSMS1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TTSMR3_TTSMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TTSMR3_TTSMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_FLEX_RAY_TTSMS4-------------------*/
-/*-------------------TMS570_FLEX_RAYTTSMS4-------------------*/
 /* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */
-#define TMS570_FLEX_RAY_TTSMS4_TTSMS1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TTSMS4_TTSMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TTSMS4_TTSMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_FLEX_RAY_TTSMR4-------------------*/
-/*-------------------TMS570_FLEX_RAYTTSMR4-------------------*/
 /* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */
-#define TMS570_FLEX_RAY_TTSMR4_TTSMS1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TTSMR4_TTSMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TTSMR4_TTSMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_FLEX_RAY_TTCCS1-------------------*/
-/*-------------------TMS570_FLEX_RAYTTCCS1-------------------*/
 /* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */
-#define TMS570_FLEX_RAY_TTCCS1_TTCCS1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TTCCS1_TTCCS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TTCCS1_TTCCS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_FLEX_RAY_TTCCR1-------------------*/
-/*-------------------TMS570_FLEX_RAYTTCCR1-------------------*/
 /* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */
-#define TMS570_FLEX_RAY_TTCCR1_TTCCS1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TTCCR1_TTCCS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TTCCR1_TTCCS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_FLEX_RAY_TTCCS2-------------------*/
-/*-------------------TMS570_FLEX_RAYTTCCS2-------------------*/
 /* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */
-#define TMS570_FLEX_RAY_TTCCS2_TTCCS1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TTCCS2_TTCCS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TTCCS2_TTCCS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_FLEX_RAY_TTCCR2-------------------*/
-/*-------------------TMS570_FLEX_RAYTTCCR2-------------------*/
 /* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */
-#define TMS570_FLEX_RAY_TTCCR2_TTCCS1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TTCCR2_TTCCS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TTCCR2_TTCCS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_FLEX_RAY_TTCCS3-------------------*/
-/*-------------------TMS570_FLEX_RAYTTCCS3-------------------*/
 /* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */
-#define TMS570_FLEX_RAY_TTCCS3_TTCCS1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TTCCS3_TTCCS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TTCCS3_TTCCS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_FLEX_RAY_TTCCR3-------------------*/
-/*-------------------TMS570_FLEX_RAYTTCCR3-------------------*/
 /* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */
-#define TMS570_FLEX_RAY_TTCCR3_TTCCS1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TTCCR3_TTCCS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TTCCR3_TTCCS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_FLEX_RAY_TTCCS4-------------------*/
-/*-------------------TMS570_FLEX_RAYTTCCS4-------------------*/
 /* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */
-#define TMS570_FLEX_RAY_TTCCS4_TTCCS1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TTCCS4_TTCCS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TTCCS4_TTCCS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_FLEX_RAY_TTCCR4-------------------*/
-/*-------------------TMS570_FLEX_RAYTTCCR4-------------------*/
 /* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */
-#define TMS570_FLEX_RAY_TTCCR4_TTCCS1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TTCCR4_TTCCS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TTCCR4_TTCCS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_FLEX_RAY_ETESMS1------------------*/
-/*-------------------TMS570_FLEX_RAYETESMS1-------------------*/
 /* field: ETESMS1 - Enable Transfer on Event to System Memory Set 1. */
-#define TMS570_FLEX_RAY_ETESMS1_ETESMS1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_ETESMS1_ETESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_ETESMS1_ETESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_FLEX_RAY_ETESMR1------------------*/
-/*-------------------TMS570_FLEX_RAYETESMR1-------------------*/
 /* field: ETESMS1 - Enable Transfer on Event to System Memory Set 1. */
-#define TMS570_FLEX_RAY_ETESMR1_ETESMS1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_ETESMR1_ETESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_ETESMR1_ETESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_FLEX_RAY_ETESMS2------------------*/
-/*-------------------TMS570_FLEX_RAYETESMS2-------------------*/
 /* field: ETESMS1 - Enable Transfer on Event to System Memory Set 1. */
-#define TMS570_FLEX_RAY_ETESMS2_ETESMS1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_ETESMS2_ETESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_ETESMS2_ETESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_FLEX_RAY_ETESMR2------------------*/
-/*-------------------TMS570_FLEX_RAYETESMR2-------------------*/
 /* field: ETESMS1 - message buffers 0 to 31. */
-#define TMS570_FLEX_RAY_ETESMR2_ETESMS1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_ETESMR2_ETESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_ETESMR2_ETESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_FLEX_RAY_ETESMS3------------------*/
-/*-------------------TMS570_FLEX_RAYETESMS3-------------------*/
 /* field: ETESMS1 - Enable Transfer on Event to System Memory Set 1. */
-#define TMS570_FLEX_RAY_ETESMS3_ETESMS1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_ETESMS3_ETESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_ETESMS3_ETESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_FLEX_RAY_ETESMR3------------------*/
-/*-------------------TMS570_FLEX_RAYETESMR3-------------------*/
 /* field: ETESMS1 - Enable Transfer on Event to System Memory Set 1. */
-#define TMS570_FLEX_RAY_ETESMR3_ETESMS1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_ETESMR3_ETESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_ETESMR3_ETESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_FLEX_RAY_ETESMS4------------------*/
-/*-------------------TMS570_FLEX_RAYETESMS4-------------------*/
 /* field: ETESMS1 - Enable Transfer on Event to System Memory Set 1. */
-#define TMS570_FLEX_RAY_ETESMS4_ETESMS1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_ETESMS4_ETESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_ETESMS4_ETESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_FLEX_RAY_ETESMR4------------------*/
-/*-------------------TMS570_FLEX_RAYETESMR4-------------------*/
 /* field: ETESMS1 - message buffers 0 to 31. */
-#define TMS570_FLEX_RAY_ETESMR4_ETESMS1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_ETESMR4_ETESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_ETESMR4_ETESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_FLEX_RAY_CESMS1-------------------*/
-/*-------------------TMS570_FLEX_RAYCESMS1-------------------*/
 /* field: CESMS1 - Clear on Event to System Memory Set 1. */
-#define TMS570_FLEX_RAY_CESMS1_CESMS1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_CESMS1_CESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_CESMS1_CESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_FLEX_RAY_CESMR1-------------------*/
-/*-------------------TMS570_FLEX_RAYCESMR1-------------------*/
 /* field: CESMS1 - Clear on Event to System Memory Set 1. */
-#define TMS570_FLEX_RAY_CESMR1_CESMS1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_CESMR1_CESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_CESMR1_CESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_FLEX_RAY_CESMS2-------------------*/
-/*-------------------TMS570_FLEX_RAYCESMS2-------------------*/
 /* field: CESMS1 - Clear on Event to System Memory Set 1. */
-#define TMS570_FLEX_RAY_CESMS2_CESMS1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_CESMS2_CESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_CESMS2_CESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_FLEX_RAY_CESMR2-------------------*/
-/*-------------------TMS570_FLEX_RAYCESMR2-------------------*/
 /* field: CESMS1 - Clear on Event to System Memory Set 1. */
-#define TMS570_FLEX_RAY_CESMR2_CESMS1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_CESMR2_CESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_CESMR2_CESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_FLEX_RAY_CESMS3-------------------*/
-/*-------------------TMS570_FLEX_RAYCESMS3-------------------*/
 /* field: CESMS1 - Clear on Event to System Memory Set 1. */
-#define TMS570_FLEX_RAY_CESMS3_CESMS1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_CESMS3_CESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_CESMS3_CESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_FLEX_RAY_CESMR3-------------------*/
-/*-------------------TMS570_FLEX_RAYCESMR3-------------------*/
 /* field: CESMS1 - CESMS1(31-0) */
-#define TMS570_FLEX_RAY_CESMR3_CESMS1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_CESMR3_CESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_CESMR3_CESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_FLEX_RAY_CESMS4-------------------*/
-/*-------------------TMS570_FLEX_RAYCESMS4-------------------*/
 /* field: CESMS1 - Clear on Event to System Memory Set 1. */
-#define TMS570_FLEX_RAY_CESMS4_CESMS1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_CESMS4_CESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_CESMS4_CESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_FLEX_RAY_CESMR4-------------------*/
-/*-------------------TMS570_FLEX_RAYCESMR4-------------------*/
 /* field: CESMS1 - Clear on Event to System Memory Set 1. */
-#define TMS570_FLEX_RAY_CESMR4_CESMS1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_CESMR4_CESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_CESMR4_CESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_FLEX_RAY_TSMIES1------------------*/
-/*-------------------TMS570_FLEX_RAYTSMIES1-------------------*/
 /* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */
-#define TMS570_FLEX_RAY_TSMIES1_TTSMIES1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TSMIES1_TTSMIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TSMIES1_TTSMIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_FLEX_RAY_TSMIER1------------------*/
-/*-------------------TMS570_FLEX_RAYTSMIER1-------------------*/
 /* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */
-#define TMS570_FLEX_RAY_TSMIER1_TTSMIES1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TSMIER1_TTSMIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TSMIER1_TTSMIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_FLEX_RAY_TSMIES2------------------*/
-/*-------------------TMS570_FLEX_RAYTSMIES2-------------------*/
 /* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */
-#define TMS570_FLEX_RAY_TSMIES2_TTSMIES1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TSMIES2_TTSMIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TSMIES2_TTSMIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_FLEX_RAY_TSMIER2------------------*/
-/*-------------------TMS570_FLEX_RAYTSMIER2-------------------*/
 /* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */
-#define TMS570_FLEX_RAY_TSMIER2_TTSMIES1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TSMIER2_TTSMIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TSMIER2_TTSMIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_FLEX_RAY_TSMIES3------------------*/
-/*-------------------TMS570_FLEX_RAYTSMIES3-------------------*/
 /* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */
-#define TMS570_FLEX_RAY_TSMIES3_TTSMIES1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TSMIES3_TTSMIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TSMIES3_TTSMIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_FLEX_RAY_TSMIER3------------------*/
-/*-------------------TMS570_FLEX_RAYTSMIER3-------------------*/
 /* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */
-#define TMS570_FLEX_RAY_TSMIER3_TTSMIES1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TSMIER3_TTSMIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TSMIER3_TTSMIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_FLEX_RAY_TSMIES4------------------*/
-/*-------------------TMS570_FLEX_RAYTSMIES4-------------------*/
 /* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */
-#define TMS570_FLEX_RAY_TSMIES4_TTSMIES1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TSMIES4_TTSMIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TSMIES4_TTSMIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_FLEX_RAY_TSMIER4------------------*/
-/*-------------------TMS570_FLEX_RAYTSMIER4-------------------*/
 /* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */
-#define TMS570_FLEX_RAY_TSMIER4_TTSMIES1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TSMIER4_TTSMIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TSMIER4_TTSMIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_FLEX_RAY_TCCIES1------------------*/
-/*-------------------TMS570_FLEX_RAYTCCIES1-------------------*/
 /* field: TCCIES1 - Transfer to Communication Controller Interrupt Enable Set 1. */
-#define TMS570_FLEX_RAY_TCCIES1_TCCIES1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TCCIES1_TCCIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TCCIES1_TCCIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_FLEX_RAY_TCCIER1------------------*/
-/*-------------------TMS570_FLEX_RAYTCCIER1-------------------*/
 /* field: TCCIES1 - Transfer to Communication Controller Interrupt Enable Set 1. */
-#define TMS570_FLEX_RAY_TCCIER1_TCCIES1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TCCIER1_TCCIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TCCIER1_TCCIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_FLEX_RAY_TCCIES2------------------*/
-/*-------------------TMS570_FLEX_RAYTCCIES2-------------------*/
 /* field: TCCIES1 - Transfer to Communication Controller Interrupt Enable Set 1. */
-#define TMS570_FLEX_RAY_TCCIES2_TCCIES1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TCCIES2_TCCIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TCCIES2_TCCIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_FLEX_RAY_TCCIER2------------------*/
-/*-------------------TMS570_FLEX_RAYTCCIER2-------------------*/
 /* field: TCCIES1 - to message buffers 0 to 31. */
-#define TMS570_FLEX_RAY_TCCIER2_TCCIES1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TCCIER2_TCCIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TCCIER2_TCCIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_FLEX_RAY_TCCIES3------------------*/
-/*-------------------TMS570_FLEX_RAYTCCIES3-------------------*/
 /* field: TCCIES1 - Transfer to Communication Controller Interrupt Enable Set 1. */
-#define TMS570_FLEX_RAY_TCCIES3_TCCIES1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TCCIES3_TCCIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TCCIES3_TCCIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_FLEX_RAY_TCCIER3------------------*/
-/*-------------------TMS570_FLEX_RAYTCCIER3-------------------*/
 /* field: TCCIES1 - Transfer to Communication Controller Interrupt Enable Set 1. */
-#define TMS570_FLEX_RAY_TCCIER3_TCCIES1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TCCIER3_TCCIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TCCIER3_TCCIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_FLEX_RAY_TCCIES4------------------*/
-/*-------------------TMS570_FLEX_RAYTCCIES4-------------------*/
 /* field: TCCIES1 - Transfer to Communication Controller Interrupt Enable Set 1. */
-#define TMS570_FLEX_RAY_TCCIES4_TCCIES1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TCCIES4_TCCIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TCCIES4_TCCIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_FLEX_RAY_TCCIER4------------------*/
-/*-------------------TMS570_FLEX_RAYTCCIER4-------------------*/
 /* field: TCCIES1 - Transfer to Communication Controller Interrupt Enable Set 1. */
-#define TMS570_FLEX_RAY_TCCIER4_TCCIES1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_FLEX_RAY_TCCIER4_TCCIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TCCIER4_TCCIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
 
-
+#endif /* LIBBSP_ARM_TMS570_FLEX_RAY */
-#endif /* LIBBSP_ARM_tms570_FLEX_RAY */

c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_gio.h

@@ -36,8 +36,8 @@
  * of the authors and should not be interpreted as representing official policies,
  * either expressed or implied, of the FreeBSD Project.
 */
-#ifndef LIBBSP_ARM_tms570_GIO
+#ifndef LIBBSP_ARM_TMS570_GIO
-#define LIBBSP_ARM_tms570_GIO
+#define LIBBSP_ARM_TMS570_GIO
 
 #include <bsp/utility.h>
 
@@ -70,68 +70,68 @@ typedef struct{
 } tms570_gio_t;
 
 
-/*-----------------------TMS570_GIODIR-----------------------*/
+/*-----------------------TMS570_GIO_DIR-----------------------*/
 /* field: GIODIR - GIO data direction, pins [7:0] */
 #define TMS570_GIO_DIR_GIODIR(val) BSP_FLD32(val,0, 7)
 #define TMS570_GIO_DIR_GIODIR_GET(reg) BSP_FLD32GET(reg,0, 7)
 #define TMS570_GIO_DIR_GIODIR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*-----------------------TMS570_GIODIN-----------------------*/
+/*-----------------------TMS570_GIO_DIN-----------------------*/
 /* field: GIODIN - GIO data input, pins [7:0] */
 #define TMS570_GIO_DIN_GIODIN(val) BSP_FLD32(val,0, 7)
 #define TMS570_GIO_DIN_GIODIN_GET(reg) BSP_FLD32GET(reg,0, 7)
 #define TMS570_GIO_DIN_GIODIN_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*-----------------------TMS570_GIODOUT-----------------------*/
+/*----------------------TMS570_GIO_DOUT----------------------*/
 /* field: GIODOUT - IO data output, pins[7:0]. */
 #define TMS570_GIO_DOUT_GIODOUT(val) BSP_FLD32(val,0, 7)
 #define TMS570_GIO_DOUT_GIODOUT_GET(reg) BSP_FLD32GET(reg,0, 7)
 #define TMS570_GIO_DOUT_GIODOUT_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*-----------------------TMS570_GIODSET-----------------------*/
+/*----------------------TMS570_GIO_DSET----------------------*/
 /* field: GIODSET - GIO data set, pins[7:0]. This bit drives the output of GIO pin high. */
 #define TMS570_GIO_DSET_GIODSET(val) BSP_FLD32(val,0, 7)
 #define TMS570_GIO_DSET_GIODSET_GET(reg) BSP_FLD32GET(reg,0, 7)
 #define TMS570_GIO_DSET_GIODSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*-----------------------TMS570_GIODCLR-----------------------*/
+/*----------------------TMS570_GIO_DCLR----------------------*/
 /* field: GIODCLR - GIO data clear, pins[7:0]. This bit drives the output of GIO pin low. */
 #define TMS570_GIO_DCLR_GIODCLR(val) BSP_FLD32(val,0, 7)
 #define TMS570_GIO_DCLR_GIODCLR_GET(reg) BSP_FLD32GET(reg,0, 7)
 #define TMS570_GIO_DCLR_GIODCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*-----------------------TMS570_GIOPDR-----------------------*/
+/*-----------------------TMS570_GIO_PDR-----------------------*/
 /* field: 7_0 - GIOPDRH GIO open drain, pins[7:0] */
 #define TMS570_GIO_PDR_7_0(val) BSP_FLD32(val,0, 7)
 #define TMS570_GIO_PDR_7_0_GET(reg) BSP_FLD32GET(reg,0, 7)
 #define TMS570_GIO_PDR_7_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*----------------------TMS570_GIOPULDIS----------------------*/
+/*---------------------TMS570_GIO_PULDIS---------------------*/
 /* field: GIOPULDIS - GIO pull disable, pins[7:0]. */
 #define TMS570_GIO_PULDIS_GIOPULDIS(val) BSP_FLD32(val,0, 7)
 #define TMS570_GIO_PULDIS_GIOPULDIS_GET(reg) BSP_FLD32GET(reg,0, 7)
 #define TMS570_GIO_PULDIS_GIOPULDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*-----------------------TMS570_GIOPSL-----------------------*/
+/*-----------------------TMS570_GIO_PSL-----------------------*/
 /* field: GIOPSL - GIO pull select, pins[7:0] */
 #define TMS570_GIO_PSL_GIOPSL(val) BSP_FLD32(val,0, 7)
 #define TMS570_GIO_PSL_GIOPSL_GET(reg) BSP_FLD32GET(reg,0, 7)
 #define TMS570_GIO_PSL_GIOPSL_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*-----------------------TMS570_GIOGCR0-----------------------*/
+/*----------------------TMS570_GIO_GCR0----------------------*/
 /* field: RESET - GIO reset. */
-#define TMS570_GIO_GCR0_RESET BSP_FLD32(0)
+#define TMS570_GIO_GCR0_RESET BSP_BIT32(0)
 
 
-/*----------------------TMS570_GIOINTDET----------------------*/
+/*---------------------TMS570_GIO_INTDET---------------------*/
 /* field: GIOINTDET_3 - Interrupt detection select for pins GIOD[7:0] */
 #define TMS570_GIO_INTDET_GIOINTDET_3(val) BSP_FLD32(val,24, 31)
 #define TMS570_GIO_INTDET_GIOINTDET_3_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -153,7 +153,7 @@ typedef struct{
 #define TMS570_GIO_INTDET_GIOINTDET_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*-----------------------TMS570_GIOPOL-----------------------*/
+/*-----------------------TMS570_GIO_POL-----------------------*/
 /* field: GIOPOL_3 - Interrupt polarity select for pins GIOD[7:0] */
 #define TMS570_GIO_POL_GIOPOL_3(val) BSP_FLD32(val,24, 31)
 #define TMS570_GIO_POL_GIOPOL_3_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -175,7 +175,7 @@ typedef struct{
 #define TMS570_GIO_POL_GIOPOL_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*----------------------TMS570_GIOENASET----------------------*/
+/*---------------------TMS570_GIO_ENASET---------------------*/
 /* field: GIOENASET_3 - nterrupt enable for pins GIOD[7:0] */
 #define TMS570_GIO_ENASET_GIOENASET_3(val) BSP_FLD32(val,24, 31)
 #define TMS570_GIO_ENASET_GIOENASET_3_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -197,7 +197,7 @@ typedef struct{
 #define TMS570_GIO_ENASET_GIOENASET_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*----------------------TMS570_GIOENACLR----------------------*/
+/*---------------------TMS570_GIO_ENACLR---------------------*/
 /* field: GIOENACLR_3 - Interrupt enable for pins GIOD[7:0] */
 #define TMS570_GIO_ENACLR_GIOENACLR_3(val) BSP_FLD32(val,24, 31)
 #define TMS570_GIO_ENACLR_GIOENACLR_3_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -219,7 +219,7 @@ typedef struct{
 #define TMS570_GIO_ENACLR_GIOENACLR_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*----------------------TMS570_GIOLVLSET----------------------*/
+/*---------------------TMS570_GIO_LVLSET---------------------*/
 /* field: GIOLVLSET_3 - GIO high priority interrupt for pins GIOD[7:0]. */
 #define TMS570_GIO_LVLSET_GIOLVLSET_3(val) BSP_FLD32(val,24, 31)
 #define TMS570_GIO_LVLSET_GIOLVLSET_3_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -241,7 +241,7 @@ typedef struct{
 #define TMS570_GIO_LVLSET_GIOLVLSET_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*----------------------TMS570_GIOLVLCLR----------------------*/
+/*---------------------TMS570_GIO_LVLCLR---------------------*/
 /* field: GIOLVLCLR_3 - GIO low priority interrupt for pins GIOD[7:0] */
 #define TMS570_GIO_LVLCLR_GIOLVLCLR_3(val) BSP_FLD32(val,24, 31)
 #define TMS570_GIO_LVLCLR_GIOLVLCLR_3_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -263,7 +263,7 @@ typedef struct{
 #define TMS570_GIO_LVLCLR_GIOLVLCLR_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*-----------------------TMS570_GIOFLG-----------------------*/
+/*-----------------------TMS570_GIO_FLG-----------------------*/
 /* field: GIOFLG_3 - GIO flag for pins GIOD[7:0]. */
 #define TMS570_GIO_FLG_GIOFLG_3(val) BSP_FLD32(val,24, 31)
 #define TMS570_GIO_FLG_GIOFLG_3_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -285,35 +285,35 @@ typedef struct{
 #define TMS570_GIO_FLG_GIOFLG_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*-----------------------TMS570_GIOOFF1-----------------------*/
+/*----------------------TMS570_GIO_OFF1----------------------*/
 /* field: GIOOFF1 - GIO offset 1. These bits index the currently pending high-priority interrupt. */
 #define TMS570_GIO_OFF1_GIOOFF1(val) BSP_FLD32(val,0, 5)
 #define TMS570_GIO_OFF1_GIOOFF1_GET(reg) BSP_FLD32GET(reg,0, 5)
 #define TMS570_GIO_OFF1_GIOOFF1_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
 
 
-/*-----------------------TMS570_GIOOFF2-----------------------*/
+/*----------------------TMS570_GIO_OFF2----------------------*/
 /* field: GIOOFF2 - GIO offset 2. These bits index the currently pending low-priority interrupt. */
 #define TMS570_GIO_OFF2_GIOOFF2(val) BSP_FLD32(val,0, 5)
 #define TMS570_GIO_OFF2_GIOOFF2_GET(reg) BSP_FLD32GET(reg,0, 5)
 #define TMS570_GIO_OFF2_GIOOFF2_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
 
 
-/*-----------------------TMS570_GIOEMU1-----------------------*/
+/*----------------------TMS570_GIO_EMU1----------------------*/
 /* field: GIOEMU1 - GIO offset emulation 1. These bits index the currently pending high-priority interrupt. */
 #define TMS570_GIO_EMU1_GIOEMU1(val) BSP_FLD32(val,0, 5)
 #define TMS570_GIO_EMU1_GIOEMU1_GET(reg) BSP_FLD32GET(reg,0, 5)
 #define TMS570_GIO_EMU1_GIOEMU1_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
 
 
-/*-----------------------TMS570_GIOEMU2-----------------------*/
+/*----------------------TMS570_GIO_EMU2----------------------*/
 /* field: GIOEMU2 - GIO offset emulation 2. These bits index the currently pending low-priority interrupt. */
 #define TMS570_GIO_EMU2_GIOEMU2(val) BSP_FLD32(val,0, 5)
 #define TMS570_GIO_EMU2_GIOEMU2_GET(reg) BSP_FLD32GET(reg,0, 5)
 #define TMS570_GIO_EMU2_GIOEMU2_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
 
 
-/*----------------------TMS570_GIOports----------------------*/
+/*----------------------TMS570_GIO_ports----------------------*/
 /* field: GIOEMU2 - GIO offset emulation 2. These bits index the currently pending low-priority interrupt. */
 #define TMS570_GIO_ports_GIOEMU2(val) BSP_FLD32(val,0, 5)
 #define TMS570_GIO_ports_GIOEMU2_GET(reg) BSP_FLD32GET(reg,0, 5)
@@ -321,4 +321,4 @@ typedef struct{
 
 
 
-#endif /* LIBBSP_ARM_tms570_GIO */
+#endif /* LIBBSP_ARM_TMS570_GIO */

c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_htu.h

@@ -36,8 +36,8 @@
  * of the authors and should not be interpreted as representing official policies,
  * either expressed or implied, of the FreeBSD Project.
 */
-#ifndef LIBBSP_ARM_tms570_HTU
+#ifndef LIBBSP_ARM_TMS570_HTU
-#define LIBBSP_ARM_tms570_HTU
+#define LIBBSP_ARM_TMS570_HTU
 
 #include <bsp/utility.h>
 
@@ -75,114 +75,114 @@ typedef struct{
 } tms570_htu_t;
 
 
-/*------------------------TMS570_HTUGC------------------------*/
+/*-----------------------TMS570_HTU_GC-----------------------*/
 /* field: VBUSHOLD - Hold the VBUS bus */
-#define TMS570_HTU_GC_VBUSHOLD BSP_FLD32(24)
+#define TMS570_HTU_GC_VBUSHOLD BSP_BIT32(24)
 
 /* field: HTUEN - Transfer Unit Enable Bit */
-#define TMS570_HTU_GC_HTUEN BSP_FLD32(16)
+#define TMS570_HTU_GC_HTUEN BSP_BIT32(16)
 
 /* field: DEBM - Debug Mode */
-#define TMS570_HTU_GC_DEBM BSP_FLD32(8)
+#define TMS570_HTU_GC_DEBM BSP_BIT32(8)
 
 /* field: HTURES - HTU Software Reset Request */
-#define TMS570_HTU_GC_HTURES BSP_FLD32(0)
+#define TMS570_HTU_GC_HTURES BSP_BIT32(0)
 
 
-/*----------------------TMS570_HTUCPENA----------------------*/
+/*----------------------TMS570_HTU_CPENA----------------------*/
 /* field: CPENA - CP Enable Bits */
 #define TMS570_HTU_CPENA_CPENA(val) BSP_FLD32(val,0, 15)
 #define TMS570_HTU_CPENA_CPENA_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_HTU_CPENA_CPENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*----------------------TMS570_HTUBUSY0----------------------*/
+/*----------------------TMS570_HTU_BUSY0----------------------*/
 /* field: BUSY0A - Busy Flag for CP A of DCP 0 */
-#define TMS570_HTU_BUSY0_BUSY0A BSP_FLD32(24)
+#define TMS570_HTU_BUSY0_BUSY0A BSP_BIT32(24)
 
 /* field: BUSY0B - Busy Flag for CP B of DCP 0 */
-#define TMS570_HTU_BUSY0_BUSY0B BSP_FLD32(16)
+#define TMS570_HTU_BUSY0_BUSY0B BSP_BIT32(16)
 
 /* field: BUSY1A - Busy Flag for CP A of DCP 1 */
-#define TMS570_HTU_BUSY0_BUSY1A BSP_FLD32(8)
+#define TMS570_HTU_BUSY0_BUSY1A BSP_BIT32(8)
 
 /* field: BUSY1B - Busy Flag for CP B of DCP 1 */
-#define TMS570_HTU_BUSY0_BUSY1B BSP_FLD32(0)
+#define TMS570_HTU_BUSY0_BUSY1B BSP_BIT32(0)
 
 
-/*----------------------TMS570_HTUBUSY1----------------------*/
+/*----------------------TMS570_HTU_BUSY1----------------------*/
 /* field: BUSY2A - Busy Flag for CP A of DCP 2 */
-#define TMS570_HTU_BUSY1_BUSY2A BSP_FLD32(24)
+#define TMS570_HTU_BUSY1_BUSY2A BSP_BIT32(24)
 
 /* field: BUSY2B - Busy Flag for CP B of DCP 2 */
-#define TMS570_HTU_BUSY1_BUSY2B BSP_FLD32(16)
+#define TMS570_HTU_BUSY1_BUSY2B BSP_BIT32(16)
 
 /* field: BUSY3A - Busy Flag for CP A of DCP 3 */
-#define TMS570_HTU_BUSY1_BUSY3A BSP_FLD32(8)
+#define TMS570_HTU_BUSY1_BUSY3A BSP_BIT32(8)
 
 /* field: BUSY3B - Busy Flag for CP B of DCP 3 */
-#define TMS570_HTU_BUSY1_BUSY3B BSP_FLD32(0)
+#define TMS570_HTU_BUSY1_BUSY3B BSP_BIT32(0)
 
 
-/*----------------------TMS570_HTUBUSY2----------------------*/
+/*----------------------TMS570_HTU_BUSY2----------------------*/
 /* field: BUSY4A - Busy Flag for CP A of DCP 4 */
-#define TMS570_HTU_BUSY2_BUSY4A BSP_FLD32(24)
+#define TMS570_HTU_BUSY2_BUSY4A BSP_BIT32(24)
 
 /* field: BUSY4B - Busy Flag for CP B of DCP 4 */
-#define TMS570_HTU_BUSY2_BUSY4B BSP_FLD32(16)
+#define TMS570_HTU_BUSY2_BUSY4B BSP_BIT32(16)
 
 /* field: BUSY5A - Busy Flag for CP A of DCP 5 */
-#define TMS570_HTU_BUSY2_BUSY5A BSP_FLD32(8)
+#define TMS570_HTU_BUSY2_BUSY5A BSP_BIT32(8)
 
 /* field: BUSY5B - Busy Flag for CP B of DCP 5 */
-#define TMS570_HTU_BUSY2_BUSY5B BSP_FLD32(0)
+#define TMS570_HTU_BUSY2_BUSY5B BSP_BIT32(0)
 
 
-/*----------------------TMS570_HTUBUSY3----------------------*/
+/*----------------------TMS570_HTU_BUSY3----------------------*/
 /* field: BUSY6A - Busy Flag for CP A of DCP 6 */
-#define TMS570_HTU_BUSY3_BUSY6A BSP_FLD32(24)
+#define TMS570_HTU_BUSY3_BUSY6A BSP_BIT32(24)
 
 /* field: BUSY6B - Busy Flag for CP B of DCP 6 */
-#define TMS570_HTU_BUSY3_BUSY6B BSP_FLD32(16)
+#define TMS570_HTU_BUSY3_BUSY6B BSP_BIT32(16)
 
 /* field: BUSY7A - Busy Flag for CP A of DCP 7 */
-#define TMS570_HTU_BUSY3_BUSY7A BSP_FLD32(8)
+#define TMS570_HTU_BUSY3_BUSY7A BSP_BIT32(8)
 
 /* field: BUSY7B - Busy Flag for CP B of DCP 7 */
-#define TMS570_HTU_BUSY3_BUSY7B BSP_FLD32(0)
+#define TMS570_HTU_BUSY3_BUSY7B BSP_BIT32(0)
 
 
-/*-----------------------TMS570_HTUACPE-----------------------*/
+/*----------------------TMS570_HTU_ACPE----------------------*/
 /* field: ERRF - Error Flag */
-#define TMS570_HTU_ACPE_ERRF BSP_FLD32(31)
+#define TMS570_HTU_ACPE_ERRF BSP_BIT32(31)
 
 
-/*---------------------TMS570_HTURLBECTRL---------------------*/
+/*--------------------TMS570_HTU_RLBECTRL--------------------*/
 /* field: BERINTENA - Bus Error Interrupt Enable Bit */
-#define TMS570_HTU_RLBECTRL_BERINTENA BSP_FLD32(16)
+#define TMS570_HTU_RLBECTRL_BERINTENA BSP_BIT32(16)
 
 /* field: CORL - Continue On Request Lost Error */
-#define TMS570_HTU_RLBECTRL_CORL BSP_FLD32(8)
+#define TMS570_HTU_RLBECTRL_CORL BSP_BIT32(8)
 
 /* field: RLINTENA - Request Lost Interrupt Enable Bit */
-#define TMS570_HTU_RLBECTRL_RLINTENA BSP_FLD32(0)
+#define TMS570_HTU_RLBECTRL_RLINTENA BSP_BIT32(0)
 
 
-/*----------------------TMS570_HTUBFINTS----------------------*/
+/*---------------------TMS570_HTU_BFINTS---------------------*/
 /* field: BFINTENA - Bus Full Interrupt Enable Bits. */
 #define TMS570_HTU_BFINTS_BFINTENA(val) BSP_FLD32(val,0, 15)
 #define TMS570_HTU_BFINTS_BFINTENA_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_HTU_BFINTS_BFINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*----------------------TMS570_HTUBFINTC----------------------*/
+/*---------------------TMS570_HTU_BFINTC---------------------*/
 /* field: BFINTDIS -  */
 #define TMS570_HTU_BFINTC_BFINTDIS(val) BSP_FLD32(val,0, 15)
 #define TMS570_HTU_BFINTC_BFINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_HTU_BFINTC_BFINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_HTUINTOFF0---------------------*/
+/*---------------------TMS570_HTU_INTOFF0---------------------*/
 /* field: INTTYPE0 - Interrupt Type of Interrupt Line 0. */
 #define TMS570_HTU_INTOFF0_INTTYPE0(val) BSP_FLD32(val,8, 10)
 #define TMS570_HTU_INTOFF0_INTTYPE0_GET(reg) BSP_FLD32GET(reg,8, 10)
@@ -194,7 +194,7 @@ typedef struct{
 #define TMS570_HTU_INTOFF0_CPOFF0_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
 
 
-/*---------------------TMS570_HTUINTOFF1---------------------*/
+/*---------------------TMS570_HTU_INTOFF1---------------------*/
 /* field: INTTYPE1 - INTTYPE1 Interrupt Type of Interrupt Line 1. */
 #define TMS570_HTU_INTOFF1_INTTYPE1(val) BSP_FLD32(val,8, 10)
 #define TMS570_HTU_INTOFF1_INTTYPE1_GET(reg) BSP_FLD32GET(reg,8, 10)
@@ -206,76 +206,64 @@ typedef struct{
 #define TMS570_HTU_INTOFF1_CPOFF1_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
 
 
-/*-----------------------TMS570_HTUBIM-----------------------*/
+/*-----------------------TMS570_HTU_BIM-----------------------*/
 /* field: BIM - Buffer Initialization Mode */
 #define TMS570_HTU_BIM_BIM(val) BSP_FLD32(val,0, 7)
 #define TMS570_HTU_BIM_BIM_GET(reg) BSP_FLD32GET(reg,0, 7)
 #define TMS570_HTU_BIM_BIM_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*---------------------TMS570_HTURLOSTFL---------------------*/
+/*---------------------TMS570_HTU_RLOSTFL---------------------*/
 /* field: CPRLFL - CP Request Lost Flags */
 #define TMS570_HTU_RLOSTFL_CPRLFL(val) BSP_FLD32(val,0, 15)
 #define TMS570_HTU_RLOSTFL_CPRLFL_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_HTU_RLOSTFL_CPRLFL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_HTUBFINTFL---------------------*/
+/*---------------------TMS570_HTU_BFINTFL---------------------*/
 /* field: BFINTFL - Buffer Full Interrupt Flags */
 #define TMS570_HTU_BFINTFL_BFINTFL(val) BSP_FLD32(val,0, 15)
 #define TMS570_HTU_BFINTFL_BFINTFL_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_HTU_BFINTFL_BFINTFL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_HTUBERINTFL---------------------*/
+/*--------------------TMS570_HTU_BERINTFL--------------------*/
 /* field: BERINTFL - Bus Error Interrupt Flags */
 #define TMS570_HTU_BERINTFL_BERINTFL(val) BSP_FLD32(val,0, 15)
 #define TMS570_HTU_BERINTFL_BERINTFL_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_HTU_BERINTFL_BERINTFL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*-----------------------TMS570_HTUMP1S-----------------------*/
+/*----------------------TMS570_HTU_MP1S----------------------*/
 /* field: STARTADDRESS1 - he start address defines at which main memory address the region begins. */
-#define TMS570_HTU_MP1S_STARTADDRESS1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_HTU_MP1S_STARTADDRESS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_HTU_MP1S_STARTADDRESS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*----------------------TMS570_HTU_MP1E----------------------*/
-/*-----------------------TMS570_HTUMP1E-----------------------*/
 /* field: ENDADDRESS1 - The end address defines at which address the region ends. */
-#define TMS570_HTU_MP1E_ENDADDRESS1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_HTU_MP1E_ENDADDRESS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_HTU_MP1E_ENDADDRESS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*----------------------TMS570_HTU_DCTRL----------------------*/
-/*----------------------TMS570_HTUDCTRL----------------------*/
 /* field: CPNUM - CP Number. These bit fields indicate the CP which should cause the watch point to match. */
 #define TMS570_HTU_DCTRL_CPNUM(val) BSP_FLD32(val,24, 27)
 #define TMS570_HTU_DCTRL_CPNUM_GET(reg) BSP_FLD32GET(reg,24, 27)
 #define TMS570_HTU_DCTRL_CPNUM_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
 
 /* field: HTUDBGS - HTU Debug Status. */
-#define TMS570_HTU_DCTRL_HTUDBGS BSP_FLD32(16)
+#define TMS570_HTU_DCTRL_HTUDBGS BSP_BIT32(16)
 
 /* field: DBREN - Debug Request Enable */
-#define TMS570_HTU_DCTRL_DBREN BSP_FLD32(0)
+#define TMS570_HTU_DCTRL_DBREN BSP_BIT32(0)
 
 
-/*-----------------------TMS570_HTUWPR-----------------------*/
+/*-----------------------TMS570_HTU_WPR-----------------------*/
 /* field: WP - Watch Point Register */
-#define TMS570_HTU_WPR_WP(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_HTU_WPR_WP_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_HTU_WPR_WP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-----------------------TMS570_HTU_WMR-----------------------*/
-/*-----------------------TMS570_HTUWMR-----------------------*/
 /* field: WM - Watch Mask Register */
-#define TMS570_HTU_WMR_WM(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_HTU_WMR_WM_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_HTU_WMR_WM_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-----------------------TMS570_HTU_ID-----------------------*/
-/*------------------------TMS570_HTUID------------------------*/
 /* field: CLASS - Module Class */
 #define TMS570_HTU_ID_CLASS(val) BSP_FLD32(val,16, 23)
 #define TMS570_HTU_ID_CLASS_GET(reg) BSP_FLD32GET(reg,16, 23)
@@ -292,12 +280,12 @@ typedef struct{
 #define TMS570_HTU_ID_REV_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*-----------------------TMS570_HTUPCR-----------------------*/
+/*-----------------------TMS570_HTU_PCR-----------------------*/
 /* field: COPE - Continue on Parity Error */
-#define TMS570_HTU_PCR_COPE BSP_FLD32(16)
+#define TMS570_HTU_PCR_COPE BSP_BIT32(16)
 
 /* field: TEST - Test. */
-#define TMS570_HTU_PCR_TEST BSP_FLD32(8)
+#define TMS570_HTU_PCR_TEST BSP_BIT32(8)
 
 /* field: PARITY_ENA - Enable/Disable Parity Checking. */
 #define TMS570_HTU_PCR_PARITY_ENA(val) BSP_FLD32(val,0, 3)
@@ -305,9 +293,9 @@ typedef struct{
 #define TMS570_HTU_PCR_PARITY_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*-----------------------TMS570_HTUPAR-----------------------*/
+/*-----------------------TMS570_HTU_PAR-----------------------*/
 /* field: PEFT - Parity Error Fault Flag. */
-#define TMS570_HTU_PAR_PEFT BSP_FLD32(16)
+#define TMS570_HTU_PAR_PEFT BSP_BIT32(16)
 
 /* field: PAOFF - PAOFF */
 #define TMS570_HTU_PAR_PAOFF(val) BSP_FLD32(val,0, 8)
@@ -315,17 +303,17 @@ typedef struct{
 #define TMS570_HTU_PAR_PAOFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
 
 
-/*-----------------------TMS570_HTUMPCS-----------------------*/
+/*----------------------TMS570_HTU_MPCS----------------------*/
 /* field: CPNUM0 - Control Packet Number for single memory protection region configuration. */
 #define TMS570_HTU_MPCS_CPNUM0(val) BSP_FLD32(val,24, 27)
 #define TMS570_HTU_MPCS_CPNUM0_GET(reg) BSP_FLD32GET(reg,24, 27)
 #define TMS570_HTU_MPCS_CPNUM0_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
 
 /* field: MPEFT1 - MPEFT1 */
-#define TMS570_HTU_MPCS_MPEFT1 BSP_FLD32(17)
+#define TMS570_HTU_MPCS_MPEFT1 BSP_BIT32(17)
 
 /* field: MPEFT0 - Memory Protection Error Fault Flag 0. */
-#define TMS570_HTU_MPCS_MPEFT0 BSP_FLD32(16)
+#define TMS570_HTU_MPCS_MPEFT0 BSP_BIT32(16)
 
 /* field: CPNUM1 - Control Packet Number for single memory protection region configuration. */
 #define TMS570_HTU_MPCS_CPNUM1(val) BSP_FLD32(val,8, 11)
@@ -333,19 +321,13 @@ typedef struct{
 #define TMS570_HTU_MPCS_CPNUM1_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
 
 
-/*-----------------------TMS570_HTUMP0S-----------------------*/
+/*----------------------TMS570_HTU_MP0S----------------------*/
 /* field: ISTARTADDRESS0 - The start address defines at which main memory address the region begins. */
-#define TMS570_HTU_MP0S_ISTARTADDRESS0(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_HTU_MP0S_ISTARTADDRESS0_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_HTU_MP0S_ISTARTADDRESS0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*----------------------TMS570_HTU_MP0E----------------------*/
-/*-----------------------TMS570_HTUMP0E-----------------------*/
 /* field: ENDADDRESS0 - The end address defines at which address the region ends. */
-#define TMS570_HTU_MP0E_ENDADDRESS0(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_HTU_MP0E_ENDADDRESS0_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_HTU_MP0E_ENDADDRESS0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
 
-
+#endif /* LIBBSP_ARM_TMS570_HTU */
-#endif /* LIBBSP_ARM_tms570_HTU */

c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_i2c.h

@@ -36,8 +36,8 @@
  * of the authors and should not be interpreted as representing official policies,
  * either expressed or implied, of the FreeBSD Project.
 */
-#ifndef LIBBSP_ARM_tms570_I2C
+#ifndef LIBBSP_ARM_TMS570_I2C
-#define LIBBSP_ARM_tms570_I2C
+#define LIBBSP_ARM_TMS570_I2C
 
 #include <bsp/utility.h>
 
@@ -72,155 +72,155 @@ typedef struct{
 } tms570_i2c_t;
 
 
-/*-----------------------TMS570_I2COAR-----------------------*/
+/*-----------------------TMS570_I2C_OAR-----------------------*/
 /* field: OA - Own address */
 #define TMS570_I2C_OAR_OA(val) BSP_FLD32(val,0, 9)
 #define TMS570_I2C_OAR_OA_GET(reg) BSP_FLD32GET(reg,0, 9)
 #define TMS570_I2C_OAR_OA_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
 
 
-/*-----------------------TMS570_I2CIMR-----------------------*/
+/*-----------------------TMS570_I2C_IMR-----------------------*/
 /* field: AASEN - Address As Slave Interrupt Enable */
-#define TMS570_I2C_IMR_AASEN BSP_FLD32(6)
+#define TMS570_I2C_IMR_AASEN BSP_BIT32(6)
 
 /* field: SCDEN - Stop Condition Interrupt Enable */
-#define TMS570_I2C_IMR_SCDEN BSP_FLD32(5)
+#define TMS570_I2C_IMR_SCDEN BSP_BIT32(5)
 
 /* field: TXRDYEN - Transmit Data Ready Interrupt Enable */
-#define TMS570_I2C_IMR_TXRDYEN BSP_FLD32(4)
+#define TMS570_I2C_IMR_TXRDYEN BSP_BIT32(4)
 
 /* field: RXRDYEN - Receive Data Ready Interrupt Enable */
-#define TMS570_I2C_IMR_RXRDYEN BSP_FLD32(3)
+#define TMS570_I2C_IMR_RXRDYEN BSP_BIT32(3)
 
 /* field: ARDYEN - Register Access Ready Interrupt Enable */
-#define TMS570_I2C_IMR_ARDYEN BSP_FLD32(2)
+#define TMS570_I2C_IMR_ARDYEN BSP_BIT32(2)
 
 /* field: NACKEN - No Acknowledgement Interrupt Enable */
-#define TMS570_I2C_IMR_NACKEN BSP_FLD32(1)
+#define TMS570_I2C_IMR_NACKEN BSP_BIT32(1)
 
 /* field: ALEN - Arbitration Lost Interrupt Enable */
-#define TMS570_I2C_IMR_ALEN BSP_FLD32(0)
+#define TMS570_I2C_IMR_ALEN BSP_BIT32(0)
 
 
-/*-----------------------TMS570_I2CSTR-----------------------*/
+/*-----------------------TMS570_I2C_STR-----------------------*/
 /* field: SDIR - Slave direction */
-#define TMS570_I2C_STR_SDIR BSP_FLD32(14)
+#define TMS570_I2C_STR_SDIR BSP_BIT32(14)
 
 /* field: NACKSNT - No acknowledge sent */
-#define TMS570_I2C_STR_NACKSNT BSP_FLD32(13)
+#define TMS570_I2C_STR_NACKSNT BSP_BIT32(13)
 
 /* field: BB - Bus busy */
-#define TMS570_I2C_STR_BB BSP_FLD32(12)
+#define TMS570_I2C_STR_BB BSP_BIT32(12)
 
 /* field: RSFULL - Receiver shift full */
-#define TMS570_I2C_STR_RSFULL BSP_FLD32(11)
+#define TMS570_I2C_STR_RSFULL BSP_BIT32(11)
 
 /* field: XSMT - XSMT */
-#define TMS570_I2C_STR_XSMT BSP_FLD32(10)
+#define TMS570_I2C_STR_XSMT BSP_BIT32(10)
 
 /* field: AAS - Address as slave */
-#define TMS570_I2C_STR_AAS BSP_FLD32(9)
+#define TMS570_I2C_STR_AAS BSP_BIT32(9)
 
 /* field: AD0 - Address zero status */
-#define TMS570_I2C_STR_AD0 BSP_FLD32(8)
+#define TMS570_I2C_STR_AD0 BSP_BIT32(8)
 
 /* field: SCD - SCD */
-#define TMS570_I2C_STR_SCD BSP_FLD32(5)
+#define TMS570_I2C_STR_SCD BSP_BIT32(5)
 
 /* field: TXRDY - Transmit data ready interrupt flag */
-#define TMS570_I2C_STR_TXRDY BSP_FLD32(4)
+#define TMS570_I2C_STR_TXRDY BSP_BIT32(4)
 
 /* field: RXRDY - Receive data ready interrupt flag */
-#define TMS570_I2C_STR_RXRDY BSP_FLD32(3)
+#define TMS570_I2C_STR_RXRDY BSP_BIT32(3)
 
 /* field: ARDY - Register access ready interrupt flag */
-#define TMS570_I2C_STR_ARDY BSP_FLD32(2)
+#define TMS570_I2C_STR_ARDY BSP_BIT32(2)
 
 /* field: NACK - No acknowledgement interrupt */
-#define TMS570_I2C_STR_NACK BSP_FLD32(1)
+#define TMS570_I2C_STR_NACK BSP_BIT32(1)
 
 /* field: AL - Arbitration lost interrupt flag */
-#define TMS570_I2C_STR_AL BSP_FLD32(0)
+#define TMS570_I2C_STR_AL BSP_BIT32(0)
 
 
-/*-----------------------TMS570_I2CCKL-----------------------*/
+/*-----------------------TMS570_I2C_CKL-----------------------*/
 /* field: CLKL - Low time clock division factor */
 #define TMS570_I2C_CKL_CLKL(val) BSP_FLD32(val,0, 15)
 #define TMS570_I2C_CKL_CLKL_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_I2C_CKL_CLKL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*-----------------------TMS570_I2CCKH-----------------------*/
+/*-----------------------TMS570_I2C_CKH-----------------------*/
 /* field: CLKH - High time clock division factor */
 #define TMS570_I2C_CKH_CLKH(val) BSP_FLD32(val,0, 15)
 #define TMS570_I2C_CKH_CLKH_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_I2C_CKH_CLKH_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*-----------------------TMS570_I2CCNT-----------------------*/
+/*-----------------------TMS570_I2C_CNT-----------------------*/
 /* field: CNT - Data counter */
 #define TMS570_I2C_CNT_CNT(val) BSP_FLD32(val,0, 15)
 #define TMS570_I2C_CNT_CNT_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_I2C_CNT_CNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*-----------------------TMS570_I2CDRR-----------------------*/
+/*-----------------------TMS570_I2C_DRR-----------------------*/
 /* field: DATARX - Receive data */
 #define TMS570_I2C_DRR_DATARX(val) BSP_FLD32(val,0, 7)
 #define TMS570_I2C_DRR_DATARX_GET(reg) BSP_FLD32GET(reg,0, 7)
 #define TMS570_I2C_DRR_DATARX_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*-----------------------TMS570_I2CSAR-----------------------*/
+/*-----------------------TMS570_I2C_SAR-----------------------*/
 /* field: SA - 7- or 10-bit programmable slave address */
 #define TMS570_I2C_SAR_SA(val) BSP_FLD32(val,0, 9)
 #define TMS570_I2C_SAR_SA_GET(reg) BSP_FLD32GET(reg,0, 9)
 #define TMS570_I2C_SAR_SA_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
 
 
-/*-----------------------TMS570_I2CDXR-----------------------*/
+/*-----------------------TMS570_I2C_DXR-----------------------*/
 /* field: DATATX - Transmit data */
 #define TMS570_I2C_DXR_DATATX(val) BSP_FLD32(val,0, 7)
 #define TMS570_I2C_DXR_DATATX_GET(reg) BSP_FLD32GET(reg,0, 7)
 #define TMS570_I2C_DXR_DATATX_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*-----------------------TMS570_I2CMDR-----------------------*/
+/*-----------------------TMS570_I2C_MDR-----------------------*/
 /* field: NACKMOD - No-acknowledge (NACK) mode */
-#define TMS570_I2C_MDR_NACKMOD BSP_FLD32(15)
+#define TMS570_I2C_MDR_NACKMOD BSP_BIT32(15)
 
 /* field: FREE - Free running bit */
-#define TMS570_I2C_MDR_FREE BSP_FLD32(14)
+#define TMS570_I2C_MDR_FREE BSP_BIT32(14)
 
 /* field: STT - Start condition */
-#define TMS570_I2C_MDR_STT BSP_FLD32(13)
+#define TMS570_I2C_MDR_STT BSP_BIT32(13)
 
 /* field: STP - Stop condition */
-#define TMS570_I2C_MDR_STP BSP_FLD32(11)
+#define TMS570_I2C_MDR_STP BSP_BIT32(11)
 
 /* field: MST - Master/slave mode bit */
-#define TMS570_I2C_MDR_MST BSP_FLD32(10)
+#define TMS570_I2C_MDR_MST BSP_BIT32(10)
 
 /* field: TRX - Transmit/receive bit */
-#define TMS570_I2C_MDR_TRX BSP_FLD32(9)
+#define TMS570_I2C_MDR_TRX BSP_BIT32(9)
 
 /* field: XA - Expand address enable bit */
-#define TMS570_I2C_MDR_XA BSP_FLD32(8)
+#define TMS570_I2C_MDR_XA BSP_BIT32(8)
 
 /* field: RM - RM */
-#define TMS570_I2C_MDR_RM BSP_FLD32(7)
+#define TMS570_I2C_MDR_RM BSP_BIT32(7)
 
 /* field: DLB - Digital loop back enable bit */
-#define TMS570_I2C_MDR_DLB BSP_FLD32(6)
+#define TMS570_I2C_MDR_DLB BSP_BIT32(6)
 
 /* field: nIRS - I2C reset enable bit */
-#define TMS570_I2C_MDR_nIRS BSP_FLD32(5)
+#define TMS570_I2C_MDR_nIRS BSP_BIT32(5)
 
 /* field: STB - Start byte mode enable bit (Master mode only) */
-#define TMS570_I2C_MDR_STB BSP_FLD32(4)
+#define TMS570_I2C_MDR_STB BSP_BIT32(4)
 
 /* field: FDF - Free data format enable bit */
-#define TMS570_I2C_MDR_FDF BSP_FLD32(3)
+#define TMS570_I2C_MDR_FDF BSP_BIT32(3)
 
 /* field: BC - Bit count */
 #define TMS570_I2C_MDR_BC(val) BSP_FLD32(val,0, 2)
@@ -228,7 +228,7 @@ typedef struct{
 #define TMS570_I2C_MDR_BC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
 
 
-/*-----------------------TMS570_I2CIVR-----------------------*/
+/*-----------------------TMS570_I2C_IVR-----------------------*/
 /* field: TESTMD - Reserved for internal testing. */
 #define TMS570_I2C_IVR_TESTMD(val) BSP_FLD32(val,8, 11)
 #define TMS570_I2C_IVR_TESTMD_GET(reg) BSP_FLD32GET(reg,8, 11)
@@ -240,22 +240,22 @@ typedef struct{
 #define TMS570_I2C_IVR_INTCODE_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
 
 
-/*-----------------------TMS570_I2CEMDR-----------------------*/
+/*----------------------TMS570_I2C_EMDR----------------------*/
 /* field: IGNACK - Ignore NACK mode */
-#define TMS570_I2C_EMDR_IGNACK BSP_FLD32(1)
+#define TMS570_I2C_EMDR_IGNACK BSP_BIT32(1)
 
 /* field: BCM - Backwards compatibility mode */
-#define TMS570_I2C_EMDR_BCM BSP_FLD32(0)
+#define TMS570_I2C_EMDR_BCM BSP_BIT32(0)
 
 
-/*-----------------------TMS570_I2CPSC-----------------------*/
+/*-----------------------TMS570_I2C_PSC-----------------------*/
 /* field: PSC - Prescale */
 #define TMS570_I2C_PSC_PSC(val) BSP_FLD32(val,0, 7)
 #define TMS570_I2C_PSC_PSC_GET(reg) BSP_FLD32GET(reg,0, 7)
 #define TMS570_I2C_PSC_PSC_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*----------------------TMS570_I2CPID11----------------------*/
+/*----------------------TMS570_I2C_PID11----------------------*/
 /* field: CLASS - Peripheral class */
 #define TMS570_I2C_PID11_CLASS(val) BSP_FLD32(val,8, 15)
 #define TMS570_I2C_PID11_CLASS_GET(reg) BSP_FLD32GET(reg,8, 15)
@@ -267,97 +267,97 @@ typedef struct{
 #define TMS570_I2C_PID11_REVISION_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*----------------------TMS570_I2CPID12----------------------*/
+/*----------------------TMS570_I2C_PID12----------------------*/
 /* field: TYPE - Peripheral type */
 #define TMS570_I2C_PID12_TYPE(val) BSP_FLD32(val,0, 7)
 #define TMS570_I2C_PID12_TYPE_GET(reg) BSP_FLD32GET(reg,0, 7)
 #define TMS570_I2C_PID12_TYPE_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*----------------------TMS570_I2CDMACR----------------------*/
+/*----------------------TMS570_I2C_DMACR----------------------*/
 /* field: TXDMAEN - Transmitter DMA enable */
-#define TMS570_I2C_DMACR_TXDMAEN BSP_FLD32(1)
+#define TMS570_I2C_DMACR_TXDMAEN BSP_BIT32(1)
 
 /* field: RXDMAEN - Receive DMA enable */
-#define TMS570_I2C_DMACR_RXDMAEN BSP_FLD32(0)
+#define TMS570_I2C_DMACR_RXDMAEN BSP_BIT32(0)
 
 
-/*-----------------------TMS570_I2CPFNC-----------------------*/
+/*----------------------TMS570_I2C_PFNC----------------------*/
 /* field: PINFUNC - SDA and SCL Pin Function */
-#define TMS570_I2C_PFNC_PINFUNC BSP_FLD32(0)
+#define TMS570_I2C_PFNC_PINFUNC BSP_BIT32(0)
 
 
-/*-----------------------TMS570_I2CDIR-----------------------*/
+/*-----------------------TMS570_I2C_DIR-----------------------*/
 /* field: SDADIR - SDA direction */
-#define TMS570_I2C_DIR_SDADIR BSP_FLD32(1)
+#define TMS570_I2C_DIR_SDADIR BSP_BIT32(1)
 
 /* field: SCLDIR - SCL direction */
-#define TMS570_I2C_DIR_SCLDIR BSP_FLD32(0)
+#define TMS570_I2C_DIR_SCLDIR BSP_BIT32(0)
 
 
-/*-----------------------TMS570_I2CDIN-----------------------*/
+/*-----------------------TMS570_I2C_DIN-----------------------*/
 /* field: SDAIN - Serial data in */
-#define TMS570_I2C_DIN_SDAIN BSP_FLD32(1)
+#define TMS570_I2C_DIN_SDAIN BSP_BIT32(1)
 
 /* field: SCLIN - Serial clock data in */
-#define TMS570_I2C_DIN_SCLIN BSP_FLD32(0)
+#define TMS570_I2C_DIN_SCLIN BSP_BIT32(0)
 
 
-/*-----------------------TMS570_I2CDOUT-----------------------*/
+/*----------------------TMS570_I2C_DOUT----------------------*/
 /* field: SDAOUT - SDA Data Output */
-#define TMS570_I2C_DOUT_SDAOUT BSP_FLD32(1)
+#define TMS570_I2C_DOUT_SDAOUT BSP_BIT32(1)
 
 /* field: SCLOUT - SCL Data Output */
-#define TMS570_I2C_DOUT_SCLOUT BSP_FLD32(0)
+#define TMS570_I2C_DOUT_SCLOUT BSP_BIT32(0)
 
 
-/*-----------------------TMS570_I2CSET-----------------------*/
+/*-----------------------TMS570_I2C_SET-----------------------*/
 /* field: SDASET - Serial Data Set */
-#define TMS570_I2C_SET_SDASET BSP_FLD32(1)
+#define TMS570_I2C_SET_SDASET BSP_BIT32(1)
 
 /* field: SCLSET - Serial Clock Set */
-#define TMS570_I2C_SET_SCLSET BSP_FLD32(0)
+#define TMS570_I2C_SET_SCLSET BSP_BIT32(0)
 
 
-/*-----------------------TMS570_I2CCLR-----------------------*/
+/*-----------------------TMS570_I2C_CLR-----------------------*/
 /* field: SDACLR - Serial Data Clear */
-#define TMS570_I2C_CLR_SDACLR BSP_FLD32(1)
+#define TMS570_I2C_CLR_SDACLR BSP_BIT32(1)
 
 /* field: SCLCLR - Serial Clock Clear */
-#define TMS570_I2C_CLR_SCLCLR BSP_FLD32(0)
+#define TMS570_I2C_CLR_SCLCLR BSP_BIT32(0)
 
 
-/*-----------------------TMS570_I2CPDR-----------------------*/
+/*-----------------------TMS570_I2C_PDR-----------------------*/
 /* field: SDAPDR - SDA pin open drain enable */
-#define TMS570_I2C_PDR_SDAPDR BSP_FLD32(1)
+#define TMS570_I2C_PDR_SDAPDR BSP_BIT32(1)
 
 /* field: SCLPDR - SCL pin open drain enable */
-#define TMS570_I2C_PDR_SCLPDR BSP_FLD32(0)
+#define TMS570_I2C_PDR_SCLPDR BSP_BIT32(0)
 
 
-/*-----------------------TMS570_I2CPDIS-----------------------*/
+/*----------------------TMS570_I2C_PDIS----------------------*/
 /* field: SDAPDIS - SDA pull disable */
-#define TMS570_I2C_PDIS_SDAPDIS BSP_FLD32(1)
+#define TMS570_I2C_PDIS_SDAPDIS BSP_BIT32(1)
 
 /* field: SCLPDIS - SCL pull disable */
-#define TMS570_I2C_PDIS_SCLPDIS BSP_FLD32(0)
+#define TMS570_I2C_PDIS_SCLPDIS BSP_BIT32(0)
 
 
-/*-----------------------TMS570_I2CPSEL-----------------------*/
+/*----------------------TMS570_I2C_PSEL----------------------*/
 /* field: SDAPSEL - SDA pull select */
-#define TMS570_I2C_PSEL_SDAPSEL BSP_FLD32(1)
+#define TMS570_I2C_PSEL_SDAPSEL BSP_BIT32(1)
 
 /* field: SCLPSEL - SCL pull select */
-#define TMS570_I2C_PSEL_SCLPSEL BSP_FLD32(0)
+#define TMS570_I2C_PSEL_SCLPSEL BSP_BIT32(0)
 
 
-/*-----------------------TMS570_I2CpSRS-----------------------*/
+/*----------------------TMS570_I2C_pSRS----------------------*/
 /* field: SDASRS - SDA Slew Rate select */
-#define TMS570_I2C_pSRS_SDASRS BSP_FLD32(1)
+#define TMS570_I2C_pSRS_SDASRS BSP_BIT32(1)
 
 /* field: SCLSRS - SCL Slew Rate select */
-#define TMS570_I2C_pSRS_SCLSRS BSP_FLD32(0)
+#define TMS570_I2C_pSRS_SCLSRS BSP_BIT32(0)
 
 
 
-#endif /* LIBBSP_ARM_tms570_I2C */
+#endif /* LIBBSP_ARM_TMS570_I2C */

c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_iomm.h

@@ -36,8 +36,8 @@
  * of the authors and should not be interpreted as representing official policies,
  * either expressed or implied, of the FreeBSD Project.
 */
-#ifndef LIBBSP_ARM_tms570_IOMM
+#ifndef LIBBSP_ARM_TMS570_IOMM
-#define LIBBSP_ARM_tms570_IOMM
+#define LIBBSP_ARM_TMS570_IOMM
 
 #include <bsp/utility.h>
 
@@ -96,29 +96,29 @@ typedef struct{
 } tms570_iomm_t;
 
 
-/*---------------------TMS570_IOMMPINMMR0---------------------*/
+/*--------------------TMS570_IOMM_PINMMRx--------------------*/
 /* field: PINMMRx24To31 - Each of these byte-fields control the functionality on a given ball/pin. */
-#define TMS570_IOMM_PINMMR0_PINMMRx24To31(val) BSP_FLD32(val,24, 31)
+#define TMS570_IOMM_PINMMRx_PINMMRx24To31(val) BSP_FLD32(val,24, 31)
-#define TMS570_IOMM_PINMMR0_PINMMRx24To31_GET(reg) BSP_FLD32GET(reg,24, 31)
+#define TMS570_IOMM_PINMMRx_PINMMRx24To31_GET(reg) BSP_FLD32GET(reg,24, 31)
-#define TMS570_IOMM_PINMMR0_PINMMRx24To31_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
+#define TMS570_IOMM_PINMMRx_PINMMRx24To31_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
 
 /* field: PINMMRx16To23 - Each of these byte-fields control the functionality on a given ball/pin. */
-#define TMS570_IOMM_PINMMR0_PINMMRx16To23(val) BSP_FLD32(val,16, 23)
+#define TMS570_IOMM_PINMMRx_PINMMRx16To23(val) BSP_FLD32(val,16, 23)
-#define TMS570_IOMM_PINMMR0_PINMMRx16To23_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_IOMM_PINMMRx_PINMMRx16To23_GET(reg) BSP_FLD32GET(reg,16, 23)
-#define TMS570_IOMM_PINMMR0_PINMMRx16To23_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+#define TMS570_IOMM_PINMMRx_PINMMRx16To23_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
 
 /* field: PINMMRx8To16 - Each of these byte-fields control the functionality on a given ball/pin. */
-#define TMS570_IOMM_PINMMR0_PINMMRx8To16(val) BSP_FLD32(val,8, 15)
+#define TMS570_IOMM_PINMMRx_PINMMRx8To16(val) BSP_FLD32(val,8, 15)
-#define TMS570_IOMM_PINMMR0_PINMMRx8To16_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_IOMM_PINMMRx_PINMMRx8To16_GET(reg) BSP_FLD32GET(reg,8, 15)
-#define TMS570_IOMM_PINMMR0_PINMMRx8To16_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+#define TMS570_IOMM_PINMMRx_PINMMRx8To16_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
 
 /* field: PINMMRx0To7 - Each of these byte-fields control the functionality on a given ball/pin. */
-#define TMS570_IOMM_PINMMR0_PINMMRx0To7(val) BSP_FLD32(val,0, 7)
+#define TMS570_IOMM_PINMMRx_PINMMRx0To7(val) BSP_FLD32(val,0, 7)
-#define TMS570_IOMM_PINMMR0_PINMMRx0To7_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_IOMM_PINMMRx_PINMMRx0To7_GET(reg) BSP_FLD32GET(reg,0, 7)
-#define TMS570_IOMM_PINMMR0_PINMMRx0To7_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+#define TMS570_IOMM_PINMMRx_PINMMRx0To7_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*------------------TMS570_IOMMREVISION_REG------------------*/
+/*------------------TMS570_IOMM_REVISION_REG------------------*/
 /* field: REV_SCHEME - Revision Scheme */
 #define TMS570_IOMM_REVISION_REG_REV_SCHEME(val) BSP_FLD32(val,30, 31)
 #define TMS570_IOMM_REVISION_REG_REV_SCHEME_GET(reg) BSP_FLD32GET(reg,30, 31)
@@ -150,65 +150,56 @@ typedef struct{
 #define TMS570_IOMM_REVISION_REG_REV_MINOR_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
 
 
-/*-------------------TMS570_IOMMENDIAN_REG-------------------*/
+/*-------------------TMS570_IOMM_ENDIAN_REG-------------------*/
 /* field: ENDIAN - Device endianness */
-#define TMS570_IOMM_ENDIAN_REG_ENDIAN BSP_FLD32(0)
+#define TMS570_IOMM_ENDIAN_REG_ENDIAN BSP_BIT32(0)
 
 
-/*--------------------TMS570_IOMMKICK_REG0--------------------*/
+/*-------------------TMS570_IOMM_KICK_REG0-------------------*/
 /* field: KICK0 - Kicker 0 Register. */
-#define TMS570_IOMM_KICK_REG0_KICK0(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_IOMM_KICK_REG0_KICK0_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_IOMM_KICK_REG0_KICK0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_IOMM_KICK_REG1-------------------*/
-/*--------------------TMS570_IOMMKICK_REG1--------------------*/
 /* field: KICK1 - Kicker 1 Register. */
-#define TMS570_IOMM_KICK_REG1_KICK1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_IOMM_KICK_REG1_KICK1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_IOMM_KICK_REG1_KICK1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*---------------TMS570_IOMM_ERR_RAW_STATUS_REG---------------*/
-/*---------------TMS570_IOMMERR_RAW_STATUS_REG---------------*/
 /* field: ADDR_ERR - Addressing Error Status and Error Signaling Enable. */
-#define TMS570_IOMM_ERR_RAW_STATUS_REG_ADDR_ERR BSP_FLD32(1)
+#define TMS570_IOMM_ERR_RAW_STATUS_REG_ADDR_ERR BSP_BIT32(1)
 
 /* field: PROT_ERR - register inside the IOMM is written in the CPU's user mode of operation. */
-#define TMS570_IOMM_ERR_RAW_STATUS_REG_PROT_ERR BSP_FLD32(0)
+#define TMS570_IOMM_ERR_RAW_STATUS_REG_PROT_ERR BSP_BIT32(0)
 
 
-/*-------------TMS570_IOMMERR_ENABLED_STATUS_REG-------------*/
+/*-------------TMS570_IOMM_ERR_ENABLED_STATUS_REG-------------*/
 /* field: ENABLED_ADDR_ERR - Addressing Error Signaling Enable Status and Status Clear */
-#define TMS570_IOMM_ERR_ENABLED_STATUS_REG_ENABLED_ADDR_ERR BSP_FLD32(1)
+#define TMS570_IOMM_ERR_ENABLED_STATUS_REG_ENABLED_ADDR_ERR BSP_BIT32(1)
 
 /* field: ENABLED_PROT_ERR - Protection Error Signaling Enable Status and Status Clear */
-#define TMS570_IOMM_ERR_ENABLED_STATUS_REG_ENABLED_PROT_ERR BSP_FLD32(0)
+#define TMS570_IOMM_ERR_ENABLED_STATUS_REG_ENABLED_PROT_ERR BSP_BIT32(0)
 
 
-/*-----------------TMS570_IOMMERR_ENABLE_REG-----------------*/
+/*-----------------TMS570_IOMM_ERR_ENABLE_REG-----------------*/
 /* field: ADDR_ERR_EN - Addressing Error Signaling Enable */
-#define TMS570_IOMM_ERR_ENABLE_REG_ADDR_ERR_EN BSP_FLD32(1)
+#define TMS570_IOMM_ERR_ENABLE_REG_ADDR_ERR_EN BSP_BIT32(1)
 
 /* field: PROT_ERR_EN - Protection ErrorSignaling Enable */
-#define TMS570_IOMM_ERR_ENABLE_REG_PROT_ERR_EN BSP_FLD32(0)
+#define TMS570_IOMM_ERR_ENABLE_REG_PROT_ERR_EN BSP_BIT32(0)
 
 
-/*---------------TMS570_IOMMERR_ENABLE_CLR_REG---------------*/
+/*---------------TMS570_IOMM_ERR_ENABLE_CLR_REG---------------*/
 /* field: ADDR_ERR_EN_CLR - Addressing Error Signaling Enable Clear */
-#define TMS570_IOMM_ERR_ENABLE_CLR_REG_ADDR_ERR_EN_CLR BSP_FLD32(1)
+#define TMS570_IOMM_ERR_ENABLE_CLR_REG_ADDR_ERR_EN_CLR BSP_BIT32(1)
 
 /* field: PROT_ERR_EN_CLR - Protection Error Signaling Enable Clear */
-#define TMS570_IOMM_ERR_ENABLE_CLR_REG_PROT_ERR_EN_CLR BSP_FLD32(0)
+#define TMS570_IOMM_ERR_ENABLE_CLR_REG_PROT_ERR_EN_CLR BSP_BIT32(0)
 
 
-/*----------------TMS570_IOMMFAULT_ADDRESS_REG----------------*/
+/*---------------TMS570_IOMM_FAULT_ADDRESS_REG---------------*/
 /* field: FAULT_ADDR - Fault Address. */
-#define TMS570_IOMM_FAULT_ADDRESS_REG_FAULT_ADDR(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_IOMM_FAULT_ADDRESS_REG_FAULT_ADDR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_IOMM_FAULT_ADDRESS_REG_FAULT_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*----------------TMS570_IOMM_FAULT_STATUS_REG----------------*/
-/*----------------TMS570_IOMMFAULT_STATUS_REG----------------*/
 /* field: FAULT_ID - Faulting Transaction ID */
 #define TMS570_IOMM_FAULT_STATUS_REG_FAULT_ID(val) BSP_FLD32(val,24, 27)
 #define TMS570_IOMM_FAULT_STATUS_REG_FAULT_ID_GET(reg) BSP_FLD32GET(reg,24, 27)
@@ -230,15 +221,15 @@ typedef struct{
 #define TMS570_IOMM_FAULT_STATUS_REG_FAULT_TYPE_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
 
 
-/*-----------------TMS570_IOMMFAULT_CLEAR_REG-----------------*/
+/*----------------TMS570_IOMM_FAULT_CLEAR_REG----------------*/
 /* field: FAULT_CLEAR - Fault Clear */
-#define TMS570_IOMM_FAULT_CLEAR_REG_FAULT_CLEAR BSP_FLD32(0)
+#define TMS570_IOMM_FAULT_CLEAR_REG_FAULT_CLEAR BSP_BIT32(0)
 
 
-/*---------------------TMS570_IOMMPINMUX---------------------*/
+/*---------------------TMS570_IOMM_PINMUX---------------------*/
 /* field: FAULT_CLEAR - Fault Clear */
-#define TMS570_IOMM_PINMUX_FAULT_CLEAR BSP_FLD32(0)
+#define TMS570_IOMM_PINMUX_FAULT_CLEAR BSP_BIT32(0)
 
 
 
-#endif /* LIBBSP_ARM_tms570_IOMM */
+#endif /* LIBBSP_ARM_TMS570_IOMM */

c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_lin.h

@@ -36,8 +36,8 @@
  * of the authors and should not be interpreted as representing official policies,
  * either expressed or implied, of the FreeBSD Project.
 */
-#ifndef LIBBSP_ARM_tms570_LIN
+#ifndef LIBBSP_ARM_TMS570_LIN
-#define LIBBSP_ARM_tms570_LIN
+#define LIBBSP_ARM_TMS570_LIN
 
 #include <bsp/utility.h>
 
@@ -79,350 +79,350 @@ typedef struct{
 } tms570_lin_t;
 
 
-/*-----------------------TMS570_LINGCR0-----------------------*/
+/*----------------------TMS570_LIN_GCR0----------------------*/
 /* field: Reserved - Read returns 0. Writes have no effect. */
 #define TMS570_LIN_GCR0_Reserved(val) BSP_FLD32(val,1, 31)
 #define TMS570_LIN_GCR0_Reserved_GET(reg) BSP_FLD32GET(reg,1, 31)
 #define TMS570_LIN_GCR0_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,1, 31)
 
 /* field: RESET - This bit resets the SCI module. */
-#define TMS570_LIN_GCR0_RESET BSP_FLD32(0)
+#define TMS570_LIN_GCR0_RESET BSP_BIT32(0)
 
 
-/*-----------------------TMS570_LINGCR1-----------------------*/
+/*----------------------TMS570_LIN_GCR1----------------------*/
 /* field: TXENA - Transmit enable. */
-#define TMS570_LIN_GCR1_TXENA BSP_FLD32(25)
+#define TMS570_LIN_GCR1_TXENA BSP_BIT32(25)
 
 /* field: RXENA - Receive enable. RXENA allows or prevents the transfer of data from SCIRXSHF to SCIRD. */
-#define TMS570_LIN_GCR1_RXENA BSP_FLD32(24)
+#define TMS570_LIN_GCR1_RXENA BSP_BIT32(24)
 
 /* field: CONT - Continue on suspend. */
-#define TMS570_LIN_GCR1_CONT BSP_FLD32(17)
+#define TMS570_LIN_GCR1_CONT BSP_BIT32(17)
 
 /* field: LOOP_BACK - Loopback bit. The self-checking option for the SCI can be selected with this bit. */
-#define TMS570_LIN_GCR1_LOOP_BACK BSP_FLD32(16)
+#define TMS570_LIN_GCR1_LOOP_BACK BSP_BIT32(16)
 
 /* field: POWERDOWN - If the POWERDOWN bit is set while the receiver is actively receiving data and the wake-up */
-#define TMS570_LIN_GCR1_POWERDOWN BSP_FLD32(9)
+#define TMS570_LIN_GCR1_POWERDOWN BSP_BIT32(9)
 
 /* field: SLEEP - SCI sleep. In a multiprocessor configuration, this bit controls the receive sleep function. */
-#define TMS570_LIN_GCR1_SLEEP BSP_FLD32(8)
+#define TMS570_LIN_GCR1_SLEEP BSP_BIT32(8)
 
 /* field: SWnRST - Software reset (active low). This bit is effective in LIN and SCI modes. */
-#define TMS570_LIN_GCR1_SWnRST BSP_FLD32(7)
+#define TMS570_LIN_GCR1_SWnRST BSP_BIT32(7)
 
 /* field: CLOCK - CLOCK */
-#define TMS570_LIN_GCR1_CLOCK BSP_FLD32(5)
+#define TMS570_LIN_GCR1_CLOCK BSP_BIT32(5)
 
 /* field: STOP - SCI number of stop bits per frame. */
-#define TMS570_LIN_GCR1_STOP BSP_FLD32(4)
+#define TMS570_LIN_GCR1_STOP BSP_BIT32(4)
 
 /* field: PARITY - SCI parity odd/even selection. If the PARITY ENA bit is set, PARITY designates odd or even parity. */
-#define TMS570_LIN_GCR1_PARITY BSP_FLD32(3)
+#define TMS570_LIN_GCR1_PARITY BSP_BIT32(3)
 
 /* field: PARITY_ENA - Parity enable. This bit enables or disables the parity function. */
-#define TMS570_LIN_GCR1_PARITY_ENA BSP_FLD32(2)
+#define TMS570_LIN_GCR1_PARITY_ENA BSP_BIT32(2)
 
 /* field: TIMING_MODE - SCI timing mode bit. */
-#define TMS570_LIN_GCR1_TIMING_MODE BSP_FLD32(1)
+#define TMS570_LIN_GCR1_TIMING_MODE BSP_BIT32(1)
 
 /* field: COMM_MODE - SCI communication mode bit. */
-#define TMS570_LIN_GCR1_COMM_MODE BSP_FLD32(0)
+#define TMS570_LIN_GCR1_COMM_MODE BSP_BIT32(0)
 
 
-/*-----------------------TMS570_LINGCR2-----------------------*/
+/*----------------------TMS570_LIN_GCR2----------------------*/
 /* field: CC - Compare checksum. LIN mode only. */
-#define TMS570_LIN_GCR2_CC BSP_FLD32(17)
+#define TMS570_LIN_GCR2_CC BSP_BIT32(17)
 
 /* field: SC - Send checksum byte. This bit is effective in LIN mode only. */
-#define TMS570_LIN_GCR2_SC BSP_FLD32(16)
+#define TMS570_LIN_GCR2_SC BSP_BIT32(16)
 
 /* field: GEN_WU - Generate wakeup signal. This bit is effective in LIN mode only. */
-#define TMS570_LIN_GCR2_GEN_WU BSP_FLD32(8)
+#define TMS570_LIN_GCR2_GEN_WU BSP_BIT32(8)
 
 /* field: POWERDOWN - Power down. This bit is effective in LIN or SCI mode. */
-#define TMS570_LIN_GCR2_POWERDOWN BSP_FLD32(0)
+#define TMS570_LIN_GCR2_POWERDOWN BSP_BIT32(0)
 
 
-/*----------------------TMS570_LINSETINT----------------------*/
+/*---------------------TMS570_LIN_SETINT---------------------*/
 /* field: SET_FE_INT -  */
-#define TMS570_LIN_SETINT_SET_FE_INT BSP_FLD32(26)
+#define TMS570_LIN_SETINT_SET_FE_INT BSP_BIT32(26)
 
 /* field: SET_OE_INT - SET OE INT */
-#define TMS570_LIN_SETINT_SET_OE_INT BSP_FLD32(25)
+#define TMS570_LIN_SETINT_SET_OE_INT BSP_BIT32(25)
 
 /* field: SET_PE_INT - Set parity interrupt. */
-#define TMS570_LIN_SETINT_SET_PE_INT BSP_FLD32(24)
+#define TMS570_LIN_SETINT_SET_PE_INT BSP_BIT32(24)
 
 /* field: SET_RX_DMA_ALL - SET RX DMA ALL */
-#define TMS570_LIN_SETINT_SET_RX_DMA_ALL BSP_FLD32(18)
+#define TMS570_LIN_SETINT_SET_RX_DMA_ALL BSP_BIT32(18)
 
 /* field: SET_RX_DMA - SET RX DMA */
-#define TMS570_LIN_SETINT_SET_RX_DMA BSP_FLD32(17)
+#define TMS570_LIN_SETINT_SET_RX_DMA BSP_BIT32(17)
 
 /* field: SET_TX_DMA - Set transmit DMA. To enable DMA requests for the transmitter, this bit must be set. */
-#define TMS570_LIN_SETINT_SET_TX_DMA BSP_FLD32(16)
+#define TMS570_LIN_SETINT_SET_TX_DMA BSP_BIT32(16)
 
 /* field: SET_RX_INT - SET RX INT */
-#define TMS570_LIN_SETINT_SET_RX_INT BSP_FLD32(9)
+#define TMS570_LIN_SETINT_SET_RX_INT BSP_BIT32(9)
 
 /* field: SET_TX_INT - Set transmitter interrupt. */
-#define TMS570_LIN_SETINT_SET_TX_INT BSP_FLD32(8)
+#define TMS570_LIN_SETINT_SET_TX_INT BSP_BIT32(8)
 
 /* field: SET_WAKEUP_INT - Set wakeup interrupt. */
-#define TMS570_LIN_SETINT_SET_WAKEUP_INT BSP_FLD32(1)
+#define TMS570_LIN_SETINT_SET_WAKEUP_INT BSP_BIT32(1)
 
 /* field: SET_BRKDT_INT - Set breakdetect interrupt. */
-#define TMS570_LIN_SETINT_SET_BRKDT_INT BSP_FLD32(0)
+#define TMS570_LIN_SETINT_SET_BRKDT_INT BSP_BIT32(0)
 
 
-/*---------------------TMS570_LINCLEARINT---------------------*/
+/*--------------------TMS570_LIN_CLEARINT--------------------*/
 /* field: CLR_FE_INT - Clear framing-error interrupt. This bit disables the framing-error interrupt when set. */
-#define TMS570_LIN_CLEARINT_CLR_FE_INT BSP_FLD32(26)
+#define TMS570_LIN_CLEARINT_CLR_FE_INT BSP_BIT32(26)
 
 /* field: CLR_CE_INT - Clear overrun-error interrupt. This bit disables the SCI overrun error interrupt when set. */
-#define TMS570_LIN_CLEARINT_CLR_CE_INT BSP_FLD32(25)
+#define TMS570_LIN_CLEARINT_CLR_CE_INT BSP_BIT32(25)
 
 /* field: CLR_PE_INT - Clear parity interrupt. This bit disables the parity error interrupt when set. */
-#define TMS570_LIN_CLEARINT_CLR_PE_INT BSP_FLD32(24)
+#define TMS570_LIN_CLEARINT_CLR_PE_INT BSP_BIT32(24)
 
 /* field: CLR_RX_DMA_ALL - Clear receive DMA all. This bit clears the receive DMA request for address frames when set. */
-#define TMS570_LIN_CLEARINT_CLR_RX_DMA_ALL BSP_FLD32(18)
+#define TMS570_LIN_CLEARINT_CLR_RX_DMA_ALL BSP_BIT32(18)
 
 /* field: CLR_RX_DMA - Clear receive DMA request. This bit disables the receive DMA request when set. */
-#define TMS570_LIN_CLEARINT_CLR_RX_DMA BSP_FLD32(17)
+#define TMS570_LIN_CLEARINT_CLR_RX_DMA BSP_BIT32(17)
 
 /* field: CLR_TX_DMA - CLR TX DMA */
-#define TMS570_LIN_CLEARINT_CLR_TX_DMA BSP_FLD32(16)
+#define TMS570_LIN_CLEARINT_CLR_TX_DMA BSP_BIT32(16)
 
 /* field: CLR_RX_INT - Clear receiver interrupt. This bit disables the receiver interrupt when set. */
-#define TMS570_LIN_CLEARINT_CLR_RX_INT BSP_FLD32(9)
+#define TMS570_LIN_CLEARINT_CLR_RX_INT BSP_BIT32(9)
 
 /* field: CLR_TX_INT - Clear transmitter interrupt. This bit disables the transmitter interrupt when set. */
-#define TMS570_LIN_CLEARINT_CLR_TX_INT BSP_FLD32(8)
+#define TMS570_LIN_CLEARINT_CLR_TX_INT BSP_BIT32(8)
 
 /* field: CLR_WAKEUP_INT - Clear wakeup interrupt. This bit disables the wakeup interrupt when set. */
-#define TMS570_LIN_CLEARINT_CLR_WAKEUP_INT BSP_FLD32(1)
+#define TMS570_LIN_CLEARINT_CLR_WAKEUP_INT BSP_BIT32(1)
 
 /* field: CLR_BRKDT_INT - Clear breakdetect interrupt. This bit disables the break-detect interrupt when set. */
-#define TMS570_LIN_CLEARINT_CLR_BRKDT_INT BSP_FLD32(0)
+#define TMS570_LIN_CLEARINT_CLR_BRKDT_INT BSP_BIT32(0)
 
 
-/*--------------------TMS570_LINSETINTLVL--------------------*/
+/*--------------------TMS570_LIN_SETINTLVL--------------------*/
 /* field: SET_FE_INT_LVL - Set framing-error interrupt level. */
-#define TMS570_LIN_SETINTLVL_SET_FE_INT_LVL BSP_FLD32(26)
+#define TMS570_LIN_SETINTLVL_SET_FE_INT_LVL BSP_BIT32(26)
 
 /* field: SET_CE_INT_LVL - Set overrun-error interrupt level. */
-#define TMS570_LIN_SETINTLVL_SET_CE_INT_LVL BSP_FLD32(25)
+#define TMS570_LIN_SETINTLVL_SET_CE_INT_LVL BSP_BIT32(25)
 
 /* field: SET_PE_INT_LVL - Set parity error interrupt level. */
-#define TMS570_LIN_SETINTLVL_SET_PE_INT_LVL BSP_FLD32(24)
+#define TMS570_LIN_SETINTLVL_SET_PE_INT_LVL BSP_BIT32(24)
 
 /* field: SET_RX_DMA_ALL_LVL - Set receive DMA all interrupt levels. */
-#define TMS570_LIN_SETINTLVL_SET_RX_DMA_ALL_LVL BSP_FLD32(18)
+#define TMS570_LIN_SETINTLVL_SET_RX_DMA_ALL_LVL BSP_BIT32(18)
 
 /* field: SET_RX_INT_LVL - Set receiver interrupt level. */
-#define TMS570_LIN_SETINTLVL_SET_RX_INT_LVL BSP_FLD32(9)
+#define TMS570_LIN_SETINTLVL_SET_RX_INT_LVL BSP_BIT32(9)
 
 /* field: SET_TX_INT_LVL - Set transmitter interrupt level. */
-#define TMS570_LIN_SETINTLVL_SET_TX_INT_LVL BSP_FLD32(8)
+#define TMS570_LIN_SETINTLVL_SET_TX_INT_LVL BSP_BIT32(8)
 
 /* field: SET_WAKEUP_INT_LVL - Set wakeup interrupt level. */
-#define TMS570_LIN_SETINTLVL_SET_WAKEUP_INT_LVL BSP_FLD32(1)
+#define TMS570_LIN_SETINTLVL_SET_WAKEUP_INT_LVL BSP_BIT32(1)
 
 /* field: SET_BRKDT_INT_LVL - SET BRKDT INT LVL */
-#define TMS570_LIN_SETINTLVL_SET_BRKDT_INT_LVL BSP_FLD32(0)
+#define TMS570_LIN_SETINTLVL_SET_BRKDT_INT_LVL BSP_BIT32(0)
 
 
-/*-------------------TMS570_LINCLEARINTLVL-------------------*/
+/*-------------------TMS570_LIN_CLEARINTLVL-------------------*/
 /* field: CLR_FE_INT_LVL - Clear framing-error interrupt. */
-#define TMS570_LIN_CLEARINTLVL_CLR_FE_INT_LVL BSP_FLD32(26)
+#define TMS570_LIN_CLEARINTLVL_CLR_FE_INT_LVL BSP_BIT32(26)
 
 /* field: CLR_CE_INT_LVL - CLR CE INT LVL */
-#define TMS570_LIN_CLEARINTLVL_CLR_CE_INT_LVL BSP_FLD32(25)
+#define TMS570_LIN_CLEARINTLVL_CLR_CE_INT_LVL BSP_BIT32(25)
 
 /* field: CLR_CE_INT_LVL - CLR CE INT LVL */
-#define TMS570_LIN_CLEARINTLVL_CLR_CE_INT_LVL BSP_FLD32(25)
+#define TMS570_LIN_CLEARINTLVL_CLR_CE_INT_LVL BSP_BIT32(25)
 
 /* field: CLR_PE_INT_LVL -  */
-#define TMS570_LIN_CLEARINTLVL_CLR_PE_INT_LVL BSP_FLD32(24)
+#define TMS570_LIN_CLEARINTLVL_CLR_PE_INT_LVL BSP_BIT32(24)
 
 /* field: CLR_RX_DMA_ALL_LVL - Clear receive DMA interrupt level. */
-#define TMS570_LIN_CLEARINTLVL_CLR_RX_DMA_ALL_LVL BSP_FLD32(18)
+#define TMS570_LIN_CLEARINTLVL_CLR_RX_DMA_ALL_LVL BSP_BIT32(18)
 
 /* field: CLR_RX_INT_LVL - Clear receiver interrupt. */
-#define TMS570_LIN_CLEARINTLVL_CLR_RX_INT_LVL BSP_FLD32(9)
+#define TMS570_LIN_CLEARINTLVL_CLR_RX_INT_LVL BSP_BIT32(9)
 
 /* field: 8 - CLR TX INT LVL Clear transmitter interrupt. */
-#define TMS570_LIN_CLEARINTLVL_8 BSP_FLD32(8)
+#define TMS570_LIN_CLEARINTLVL_8 BSP_BIT32(8)
 
 /* field: CLR_WAKEUP_INT_LVL - Clear wakeup interrupt. */
-#define TMS570_LIN_CLEARINTLVL_CLR_WAKEUP_INT_LVL BSP_FLD32(1)
+#define TMS570_LIN_CLEARINTLVL_CLR_WAKEUP_INT_LVL BSP_BIT32(1)
 
 /* field: CLR_BRKDT_INT_LVL - Clear breakdetect interrupt. */
-#define TMS570_LIN_CLEARINTLVL_CLR_BRKDT_INT_LVL BSP_FLD32(0)
+#define TMS570_LIN_CLEARINTLVL_CLR_BRKDT_INT_LVL BSP_BIT32(0)
 
 
-/*-----------------------TMS570_LINFLR-----------------------*/
+/*-----------------------TMS570_LIN_FLR-----------------------*/
 /* field: FE - Framing error flag. This bit is effective in LIN or SCI-compatible mode. */
-#define TMS570_LIN_FLR_FE BSP_FLD32(26)
+#define TMS570_LIN_FLR_FE BSP_BIT32(26)
 
 /* field: OE - Overrun error flag. */
-#define TMS570_LIN_FLR_OE BSP_FLD32(25)
+#define TMS570_LIN_FLR_OE BSP_BIT32(25)
 
 /* field: PE - Parity error flag. This bit is set when a parity error is detected in the received data. */
-#define TMS570_LIN_FLR_PE BSP_FLD32(24)
+#define TMS570_LIN_FLR_PE BSP_BIT32(24)
 
 /* field: RXWAKE - Receiver wakeup detect flag. */
-#define TMS570_LIN_FLR_RXWAKE BSP_FLD32(12)
+#define TMS570_LIN_FLR_RXWAKE BSP_BIT32(12)
 
 /* field: TX_EMPTY - Transmitter empty flag. */
-#define TMS570_LIN_FLR_TX_EMPTY BSP_FLD32(11)
+#define TMS570_LIN_FLR_TX_EMPTY BSP_BIT32(11)
 
 /* field: TXWAKE - Transmitter wakeup method select. */
-#define TMS570_LIN_FLR_TXWAKE BSP_FLD32(10)
+#define TMS570_LIN_FLR_TXWAKE BSP_BIT32(10)
 
 /* field: RXRDY - Receiver ready flag. */
-#define TMS570_LIN_FLR_RXRDY BSP_FLD32(9)
+#define TMS570_LIN_FLR_RXRDY BSP_BIT32(9)
 
 /* field: TXRDY - Transmitter buffer register ready flag. */
-#define TMS570_LIN_FLR_TXRDY BSP_FLD32(8)
+#define TMS570_LIN_FLR_TXRDY BSP_BIT32(8)
 
 /* field: BUSY - Bus busy flag. TThis bit indicates whether the receiver is in the process of receiving a frame. */
-#define TMS570_LIN_FLR_BUSY BSP_FLD32(3)
+#define TMS570_LIN_FLR_BUSY BSP_BIT32(3)
 
 /* field: IDLE - SCI receiver in idle state. */
-#define TMS570_LIN_FLR_IDLE BSP_FLD32(2)
+#define TMS570_LIN_FLR_IDLE BSP_BIT32(2)
 
 /* field: WAKEUP - Wakeup flag. */
-#define TMS570_LIN_FLR_WAKEUP BSP_FLD32(1)
+#define TMS570_LIN_FLR_WAKEUP BSP_BIT32(1)
 
 /* field: BRKDT - SCI break-detect flag. This bit is set when the SCI detects a break condition on the LINRX pin. */
-#define TMS570_LIN_FLR_BRKDT BSP_FLD32(0)
+#define TMS570_LIN_FLR_BRKDT BSP_BIT32(0)
 
 
-/*---------------------TMS570_LININTVECT0---------------------*/
+/*--------------------TMS570_LIN_INTVECT0--------------------*/
 /* field: INVECT0 - Interrupt vector offset for INT0. This register indicates the offset for interrupt line INT0. */
 #define TMS570_LIN_INTVECT0_INVECT0(val) BSP_FLD32(val,0, 3)
 #define TMS570_LIN_INTVECT0_INVECT0_GET(reg) BSP_FLD32GET(reg,0, 3)
 #define TMS570_LIN_INTVECT0_INVECT0_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*---------------------TMS570_LININTVECT1---------------------*/
+/*--------------------TMS570_LIN_INTVECT1--------------------*/
 /* field: INVECT1 - Interrupt vector offset for INT1. This register indicates the offset for interrupt line INT1. */
 #define TMS570_LIN_INTVECT1_INVECT1(val) BSP_FLD32(val,0, 3)
 #define TMS570_LIN_INTVECT1_INVECT1_GET(reg) BSP_FLD32GET(reg,0, 3)
 #define TMS570_LIN_INTVECT1_INVECT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*----------------------TMS570_LINFORMAT----------------------*/
+/*---------------------TMS570_LIN_FORMAT---------------------*/
 /* field: CHAR - Character length control bits. These bits set the SCI character length from 1 to 8 bits. */
 #define TMS570_LIN_FORMAT_CHAR(val) BSP_FLD32(val,0, 2)
 #define TMS570_LIN_FORMAT_CHAR_GET(reg) BSP_FLD32GET(reg,0, 2)
 #define TMS570_LIN_FORMAT_CHAR_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
 
 
-/*-----------------------TMS570_LINBRS-----------------------*/
+/*-----------------------TMS570_LIN_BRS-----------------------*/
 /* field: BAUD - SCI 24-bit baud selection. */
 #define TMS570_LIN_BRS_BAUD(val) BSP_FLD32(val,0, 23)
 #define TMS570_LIN_BRS_BAUD_GET(reg) BSP_FLD32GET(reg,0, 23)
 #define TMS570_LIN_BRS_BAUD_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
 
 
-/*------------------------TMS570_LINED------------------------*/
+/*-----------------------TMS570_LIN_ED-----------------------*/
 /* field: ED - Emulator data. Reading SCIED[7:0] does not clear the RXRDY flag, unlike reading SCIRD. */
 #define TMS570_LIN_ED_ED(val) BSP_FLD32(val,0, 7)
 #define TMS570_LIN_ED_ED_GET(reg) BSP_FLD32GET(reg,0, 7)
 #define TMS570_LIN_ED_ED_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*------------------------TMS570_LINRD------------------------*/
+/*-----------------------TMS570_LIN_RD-----------------------*/
 /* field: RD - Receiver data. */
 #define TMS570_LIN_RD_RD(val) BSP_FLD32(val,0, 7)
 #define TMS570_LIN_RD_RD_GET(reg) BSP_FLD32GET(reg,0, 7)
 #define TMS570_LIN_RD_RD_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*------------------------TMS570_LINTD------------------------*/
+/*-----------------------TMS570_LIN_TD-----------------------*/
 /* field: TD - Transmit data. Data to be transmitted is written to the SCITD register. */
 #define TMS570_LIN_TD_TD(val) BSP_FLD32(val,0, 7)
 #define TMS570_LIN_TD_TD_GET(reg) BSP_FLD32GET(reg,0, 7)
 #define TMS570_LIN_TD_TD_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*-----------------------TMS570_LINPIO0-----------------------*/
+/*----------------------TMS570_LIN_PIO0----------------------*/
 /* field: TX_FUNC - Transfer function. This bit defines the function of pin SCITX. */
-#define TMS570_LIN_PIO0_TX_FUNC BSP_FLD32(2)
+#define TMS570_LIN_PIO0_TX_FUNC BSP_BIT32(2)
 
 /* field: RX_FUNC - Receive function.This bit defines the function of pin SCIRX. */
-#define TMS570_LIN_PIO0_RX_FUNC BSP_FLD32(1)
+#define TMS570_LIN_PIO0_RX_FUNC BSP_BIT32(1)
 
 
-/*-----------------------TMS570_LINPIO1-----------------------*/
+/*----------------------TMS570_LIN_PIO1----------------------*/
 /* field: TX_DIR - Transmit pin direction. */
-#define TMS570_LIN_PIO1_TX_DIR BSP_FLD32(2)
+#define TMS570_LIN_PIO1_TX_DIR BSP_BIT32(2)
 
 /* field: RX_DIR - Receive pin direction. */
-#define TMS570_LIN_PIO1_RX_DIR BSP_FLD32(1)
+#define TMS570_LIN_PIO1_RX_DIR BSP_BIT32(1)
 
 
-/*-----------------------TMS570_LINPIO2-----------------------*/
+/*----------------------TMS570_LIN_PIO2----------------------*/
 /* field: TX_IN - Transmit pin in. This bit contains the current value on the SCITX pin. */
-#define TMS570_LIN_PIO2_TX_IN BSP_FLD32(2)
+#define TMS570_LIN_PIO2_TX_IN BSP_BIT32(2)
 
 /* field: RX_IN - Receive pin in. This bit contains the current value on the SCIRX pin. */
-#define TMS570_LIN_PIO2_RX_IN BSP_FLD32(1)
+#define TMS570_LIN_PIO2_RX_IN BSP_BIT32(1)
 
 
-/*-----------------------TMS570_LINPIO3-----------------------*/
+/*----------------------TMS570_LIN_PIO3----------------------*/
 /* field: TX_OUT - Transmit pin out. */
-#define TMS570_LIN_PIO3_TX_OUT BSP_FLD32(2)
+#define TMS570_LIN_PIO3_TX_OUT BSP_BIT32(2)
 
 /* field: RX_OUT - Receive pin out. */
-#define TMS570_LIN_PIO3_RX_OUT BSP_FLD32(1)
+#define TMS570_LIN_PIO3_RX_OUT BSP_BIT32(1)
 
 
-/*-----------------------TMS570_LINPIO4-----------------------*/
+/*----------------------TMS570_LIN_PIO4----------------------*/
 /* field: TX_SET - Transmit pin set. */
-#define TMS570_LIN_PIO4_TX_SET BSP_FLD32(2)
+#define TMS570_LIN_PIO4_TX_SET BSP_BIT32(2)
 
 /* field: RX_SET - Receive pin set. */
-#define TMS570_LIN_PIO4_RX_SET BSP_FLD32(1)
+#define TMS570_LIN_PIO4_RX_SET BSP_BIT32(1)
 
 
-/*-----------------------TMS570_LINPIO5-----------------------*/
+/*----------------------TMS570_LIN_PIO5----------------------*/
 /* field: TX_CLR - Transmit pin clear. */
-#define TMS570_LIN_PIO5_TX_CLR BSP_FLD32(2)
+#define TMS570_LIN_PIO5_TX_CLR BSP_BIT32(2)
 
 /* field: RX_CLR - Receive pin clear. */
-#define TMS570_LIN_PIO5_RX_CLR BSP_FLD32(1)
+#define TMS570_LIN_PIO5_RX_CLR BSP_BIT32(1)
 
 
-/*-----------------------TMS570_LINPIO6-----------------------*/
+/*----------------------TMS570_LIN_PIO6----------------------*/
 /* field: TX_PDR - Transmit pin open drain enable. */
-#define TMS570_LIN_PIO6_TX_PDR BSP_FLD32(2)
+#define TMS570_LIN_PIO6_TX_PDR BSP_BIT32(2)
 
 /* field: RX_PDR - Receive pin open drain enable. */
-#define TMS570_LIN_PIO6_RX_PDR BSP_FLD32(1)
+#define TMS570_LIN_PIO6_RX_PDR BSP_BIT32(1)
 
 
-/*-----------------------TMS570_LINPIO7-----------------------*/
+/*----------------------TMS570_LIN_PIO7----------------------*/
 /* field: TX_PD - Transmit pin pull control disable. This bit disables pull control capability on the input pin SCITX. */
-#define TMS570_LIN_PIO7_TX_PD BSP_FLD32(2)
+#define TMS570_LIN_PIO7_TX_PD BSP_BIT32(2)
 
 /* field: RX_PD - Receive pin pull control disable. This bit disables pull control capability on the input pin SCIRX. */
-#define TMS570_LIN_PIO7_RX_PD BSP_FLD32(1)
+#define TMS570_LIN_PIO7_RX_PD BSP_BIT32(1)
 
 
-/*-----------------------TMS570_LINPIO8-----------------------*/
+/*----------------------TMS570_LIN_PIO8----------------------*/
 /* field: TX_PSL - TX pin pull select. This bit selects pull type in the input pin SCITX. */
-#define TMS570_LIN_PIO8_TX_PSL BSP_FLD32(2)
+#define TMS570_LIN_PIO8_TX_PSL BSP_BIT32(2)
 
 /* field: RX_PSL - RX pin pull select. This bit selects pull type in the input pin SCIRX. */
-#define TMS570_LIN_PIO8_RX_PSL BSP_FLD32(1)
+#define TMS570_LIN_PIO8_RX_PSL BSP_BIT32(1)
 
 
-/*-----------------------TMS570_LINCOMP-----------------------*/
+/*----------------------TMS570_LIN_COMP----------------------*/
 /* field: SDEL - 2-bit synch delimiter compare. These bits are effective in LIN mode only. */
 #define TMS570_LIN_COMP_SDEL(val) BSP_FLD32(val,8, 9)
 #define TMS570_LIN_COMP_SDEL_GET(reg) BSP_FLD32GET(reg,8, 9)
@@ -434,7 +434,7 @@ typedef struct{
 #define TMS570_LIN_COMP_SBREAK_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
 
 
-/*-----------------------TMS570_LINRD0-----------------------*/
+/*-----------------------TMS570_LIN_RD0-----------------------*/
 /* field: RD0 - Receive buffer 0. Byte 0 of the response data byte. */
 #define TMS570_LIN_RD0_RD0(val) BSP_FLD32(val,24, 31)
 #define TMS570_LIN_RD0_RD0_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -456,7 +456,7 @@ typedef struct{
 #define TMS570_LIN_RD0_RD3_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*-----------------------TMS570_LINRD1-----------------------*/
+/*-----------------------TMS570_LIN_RD1-----------------------*/
 /* field: RD4 - Receive buffer 4. Byte 4 of the response data byte. */
 #define TMS570_LIN_RD1_RD4(val) BSP_FLD32(val,24, 31)
 #define TMS570_LIN_RD1_RD4_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -478,7 +478,7 @@ typedef struct{
 #define TMS570_LIN_RD1_RD7_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*-----------------------TMS570_LINMASK-----------------------*/
+/*----------------------TMS570_LIN_MASK----------------------*/
 /* field: RX_ID_MASK - Receive ID mask. These bits are effective in LIN mode only. */
 #define TMS570_LIN_MASK_RX_ID_MASK(val) BSP_FLD32(val,16, 23)
 #define TMS570_LIN_MASK_RX_ID_MASK_GET(reg) BSP_FLD32GET(reg,16, 23)
@@ -490,7 +490,7 @@ typedef struct{
 #define TMS570_LIN_MASK_TX_ID_MASK_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*------------------------TMS570_LINID------------------------*/
+/*-----------------------TMS570_LIN_ID-----------------------*/
 /* field: RECEIVED_ID - Received identification. These bits are effective in LIN mode only. */
 #define TMS570_LIN_ID_RECEIVED_ID(val) BSP_FLD32(val,16, 23)
 #define TMS570_LIN_ID_RECEIVED_ID_GET(reg) BSP_FLD32GET(reg,16, 23)
@@ -507,7 +507,7 @@ typedef struct{
 #define TMS570_LIN_ID_ID_BYTE_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*-----------------------TMS570_LINTD0-----------------------*/
+/*-----------------------TMS570_LIN_TD0-----------------------*/
 /* field: TD0 - 8-Bit transmit buffer 0. */
 #define TMS570_LIN_TD0_TD0(val) BSP_FLD32(val,24, 31)
 #define TMS570_LIN_TD0_TD0_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -529,7 +529,7 @@ typedef struct{
 #define TMS570_LIN_TD0_TD3_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*-----------------------TMS570_LINTD1-----------------------*/
+/*-----------------------TMS570_LIN_TD1-----------------------*/
 /* field: TD4 - 8-Bit transmit buffer 4. */
 #define TMS570_LIN_TD1_TD4(val) BSP_FLD32(val,24, 31)
 #define TMS570_LIN_TD1_TD4_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -551,22 +551,22 @@ typedef struct{
 #define TMS570_LIN_TD1_TD7_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*----------------------TMS570_LINMBRSR----------------------*/
+/*----------------------TMS570_LIN_MBRSR----------------------*/
 /* field: MBR - Maximum baud rate prescaler. This bit is effective in LIN mode only. */
 #define TMS570_LIN_MBRSR_MBR(val) BSP_FLD32(val,0, 12)
 #define TMS570_LIN_MBRSR_MBR_GET(reg) BSP_FLD32GET(reg,0, 12)
 #define TMS570_LIN_MBRSR_MBR_SET(reg,val) BSP_FLD32SET(reg, val,0, 12)
 
 
-/*--------------------TMS570_LINIODFTCTRL--------------------*/
+/*--------------------TMS570_LIN_IODFTCTRL--------------------*/
 /* field: FEN - Frame error enable. This bit is used to create a frame error. */
-#define TMS570_LIN_IODFTCTRL_FEN BSP_FLD32(26)
+#define TMS570_LIN_IODFTCTRL_FEN BSP_BIT32(26)
 
 /* field: PEN - Parity error enable. This bit is used to create a parity error. */
-#define TMS570_LIN_IODFTCTRL_PEN BSP_FLD32(25)
+#define TMS570_LIN_IODFTCTRL_PEN BSP_BIT32(25)
 
 /* field: BRKD_TENA - Break detect error enable. This bit is used to create a BRKDT error. */
-#define TMS570_LIN_IODFTCTRL_BRKD_TENA BSP_FLD32(24)
+#define TMS570_LIN_IODFTCTRL_BRKD_TENA BSP_BIT32(24)
 
 /* field: PIN_SAMPLE_MASK - Pin sample mask. */
 #define TMS570_LIN_IODFTCTRL_PIN_SAMPLE_MASK(val) BSP_FLD32(val,19, 20)
@@ -584,11 +584,11 @@ typedef struct{
 #define TMS570_LIN_IODFTCTRL_IODFTENA_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
 
 /* field: LPBENA - Module loopback enable. Write access permitted in Privilege mode only. */
-#define TMS570_LIN_IODFTCTRL_LPBENA BSP_FLD32(1)
+#define TMS570_LIN_IODFTCTRL_LPBENA BSP_BIT32(1)
 
 /* field: RXPENA - Module analog loopback through receive pin enable. */
-#define TMS570_LIN_IODFTCTRL_RXPENA BSP_FLD32(0)
+#define TMS570_LIN_IODFTCTRL_RXPENA BSP_BIT32(0)
 
 
 
-#endif /* LIBBSP_ARM_tms570_LIN */
+#endif /* LIBBSP_ARM_TMS570_LIN */

c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_mdio.h

@@ -36,8 +36,8 @@
  * of the authors and should not be interpreted as representing official policies,
  * either expressed or implied, of the FreeBSD Project.
 */
-#ifndef LIBBSP_ARM_tms570_MDIO
+#ifndef LIBBSP_ARM_TMS570_MDIO
-#define LIBBSP_ARM_tms570_MDIO
+#define LIBBSP_ARM_TMS570_MDIO
 
 #include <bsp/utility.h>
 
@@ -61,19 +61,16 @@ typedef struct{
 } tms570_mdio_t;
 
 
-/*----------------------TMS570_MDIOREVID----------------------*/
+/*---------------------TMS570_MDIO_REVID---------------------*/
 /* field: REV - Identifies the MDIO Module revision. */
-#define TMS570_MDIO_REVID_REV(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_MDIO_REVID_REV_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_MDIO_REVID_REV_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*--------------------TMS570_MDIO_CONTROL--------------------*/
-/*---------------------TMS570_MDIOCONTROL---------------------*/
 /* field: IDLE - State machine IDLE status bit. */
-#define TMS570_MDIO_CONTROL_IDLE BSP_FLD32(31)
+#define TMS570_MDIO_CONTROL_IDLE BSP_BIT32(31)
 
 /* field: ENABLE - State machine enable control bit. */
-#define TMS570_MDIO_CONTROL_ENABLE BSP_FLD32(30)
+#define TMS570_MDIO_CONTROL_ENABLE BSP_BIT32(30)
 
 /* field: HIGHEST_USER_CHANNEL - Highest user channel that is available in the module. It is currently set to 1. */
 #define TMS570_MDIO_CONTROL_HIGHEST_USER_CHANNEL(val) BSP_FLD32(val,24, 28)
@@ -81,13 +78,13 @@ typedef struct{
 #define TMS570_MDIO_CONTROL_HIGHEST_USER_CHANNEL_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
 
 /* field: PREAMBLE - Preamble disable */
-#define TMS570_MDIO_CONTROL_PREAMBLE BSP_FLD32(20)
+#define TMS570_MDIO_CONTROL_PREAMBLE BSP_BIT32(20)
 
 /* field: FAULT - Fault indicator. */
-#define TMS570_MDIO_CONTROL_FAULT BSP_FLD32(19)
+#define TMS570_MDIO_CONTROL_FAULT BSP_BIT32(19)
 
 /* field: FAULTENB - Fault detect enable. */
-#define TMS570_MDIO_CONTROL_FAULTENB BSP_FLD32(18)
+#define TMS570_MDIO_CONTROL_FAULTENB BSP_BIT32(18)
 
 /* field: CLKDIV - Clock Divider bits. */
 #define TMS570_MDIO_CONTROL_CLKDIV(val) BSP_FLD32(val,0, 15)
@@ -95,77 +92,71 @@ typedef struct{
 #define TMS570_MDIO_CONTROL_CLKDIV_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*----------------------TMS570_MDIOALIVE----------------------*/
+/*---------------------TMS570_MDIO_ALIVE---------------------*/
 /* field: ALIVE - MDIO Alive bits. */
-#define TMS570_MDIO_ALIVE_ALIVE(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_MDIO_ALIVE_ALIVE_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_MDIO_ALIVE_ALIVE_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*----------------------TMS570_MDIO_LINK----------------------*/
-/*----------------------TMS570_MDIOLINK----------------------*/
 /* field: LINK - MDIO Link state bits. This register is updated after a read of the generic status register of a PHY. */
-#define TMS570_MDIO_LINK_LINK(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_MDIO_LINK_LINK_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_MDIO_LINK_LINK_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_MDIO_LINKINTRAW-------------------*/
-/*-------------------TMS570_MDIOLINKINTRAW-------------------*/
 /* field: USERPHY1 - MDIO Link change event, raw value. */
-#define TMS570_MDIO_LINKINTRAW_USERPHY1 BSP_FLD32(1)
+#define TMS570_MDIO_LINKINTRAW_USERPHY1 BSP_BIT32(1)
 
 /* field: USERPHY0 - MDIO Link change event, raw value. */
-#define TMS570_MDIO_LINKINTRAW_USERPHY0 BSP_FLD32(0)
+#define TMS570_MDIO_LINKINTRAW_USERPHY0 BSP_BIT32(0)
 
 
-/*------------------TMS570_MDIOLINKINTMASKED------------------*/
+/*-----------------TMS570_MDIO_LINKINTMASKED-----------------*/
 /* field: USERPHY1 - MDIO Link change interrupt, masked value. */
-#define TMS570_MDIO_LINKINTMASKED_USERPHY1 BSP_FLD32(1)
+#define TMS570_MDIO_LINKINTMASKED_USERPHY1 BSP_BIT32(1)
 
 /* field: USERPHY0 - MDIO Link change interrupt, masked value. */
-#define TMS570_MDIO_LINKINTMASKED_USERPHY0 BSP_FLD32(0)
+#define TMS570_MDIO_LINKINTMASKED_USERPHY0 BSP_BIT32(0)
 
 
-/*-------------------TMS570_MDIOUSERINTRAW-------------------*/
+/*-------------------TMS570_MDIO_USERINTRAW-------------------*/
 /* field: USERACCESS1 - MDIO User command complete event bit. */
-#define TMS570_MDIO_USERINTRAW_USERACCESS1 BSP_FLD32(1)
+#define TMS570_MDIO_USERINTRAW_USERACCESS1 BSP_BIT32(1)
 
 /* field: USERACCESS0 - MDIO User command complete event bit. */
-#define TMS570_MDIO_USERINTRAW_USERACCESS0 BSP_FLD32(0)
+#define TMS570_MDIO_USERINTRAW_USERACCESS0 BSP_BIT32(0)
 
 
-/*------------------TMS570_MDIOUSERINTMASKED------------------*/
+/*-----------------TMS570_MDIO_USERINTMASKED-----------------*/
 /* field: USERACCESS1 - Masked value of MDIO User command complete interrupt. */
-#define TMS570_MDIO_USERINTMASKED_USERACCESS1 BSP_FLD32(1)
+#define TMS570_MDIO_USERINTMASKED_USERACCESS1 BSP_BIT32(1)
 
 /* field: USERACCESS0 - Masked value of MDIO User command complete interrupt. */
-#define TMS570_MDIO_USERINTMASKED_USERACCESS0 BSP_FLD32(0)
+#define TMS570_MDIO_USERINTMASKED_USERACCESS0 BSP_BIT32(0)
 
 
-/*-----------------TMS570_MDIOUSERINTMASKSET-----------------*/
+/*-----------------TMS570_MDIO_USERINTMASKSET-----------------*/
 /* field: USERACCESS1 - MDIO user interrupt mask set for USERINTMASKED[1]. */
-#define TMS570_MDIO_USERINTMASKSET_USERACCESS1 BSP_FLD32(1)
+#define TMS570_MDIO_USERINTMASKSET_USERACCESS1 BSP_BIT32(1)
 
 /* field: USERACCESS0 - MDIO user interrupt mask set for USERINTMASKED[0]. */
-#define TMS570_MDIO_USERINTMASKSET_USERACCESS0 BSP_FLD32(0)
+#define TMS570_MDIO_USERINTMASKSET_USERACCESS0 BSP_BIT32(0)
 
 
-/*----------------TMS570_MDIOUSERINTMASKCLEAR----------------*/
+/*----------------TMS570_MDIO_USERINTMASKCLEAR----------------*/
 /* field: USERACCESS1 - MDIO user command complete interrupt mask clear for USERINTMASKED[1]. */
-#define TMS570_MDIO_USERINTMASKCLEAR_USERACCESS1 BSP_FLD32(1)
+#define TMS570_MDIO_USERINTMASKCLEAR_USERACCESS1 BSP_BIT32(1)
 
 /* field: USERACCESS0 - MDIO user command complete interrupt mask clear for USERINTMASKED[0]. */
-#define TMS570_MDIO_USERINTMASKCLEAR_USERACCESS0 BSP_FLD32(0)
+#define TMS570_MDIO_USERINTMASKCLEAR_USERACCESS0 BSP_BIT32(0)
 
 
-/*-------------------TMS570_MDIOUSERACCESS0-------------------*/
+/*------------------TMS570_MDIO_USERACCESS0------------------*/
 /* field: GO - Go bit. */
-#define TMS570_MDIO_USERACCESS0_GO BSP_FLD32(31)
+#define TMS570_MDIO_USERACCESS0_GO BSP_BIT32(31)
 
 /* field: WRITE - Write enable bit. */
-#define TMS570_MDIO_USERACCESS0_WRITE BSP_FLD32(30)
+#define TMS570_MDIO_USERACCESS0_WRITE BSP_BIT32(30)
 
 /* field: ACK - Acknowledge bit. This bit is set if the PHY acknowledged the read transaction. */
-#define TMS570_MDIO_USERACCESS0_ACK BSP_FLD32(29)
+#define TMS570_MDIO_USERACCESS0_ACK BSP_BIT32(29)
 
 /* field: REGADR - Register address bits. */
 #define TMS570_MDIO_USERACCESS0_REGADR(val) BSP_FLD32(val,21, 25)
@@ -183,12 +174,12 @@ typedef struct{
 #define TMS570_MDIO_USERACCESS0_DATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*-------------------TMS570_MDIOUSERPHYSEL0-------------------*/
+/*------------------TMS570_MDIO_USERPHYSEL0------------------*/
 /* field: LINKSEL - Link status determination select bit. */
-#define TMS570_MDIO_USERPHYSEL0_LINKSEL BSP_FLD32(7)
+#define TMS570_MDIO_USERPHYSEL0_LINKSEL BSP_BIT32(7)
 
 /* field: LINKINTENB - Link change interrupt enable. */
-#define TMS570_MDIO_USERPHYSEL0_LINKINTENB BSP_FLD32(6)
+#define TMS570_MDIO_USERPHYSEL0_LINKINTENB BSP_BIT32(6)
 
 /* field: PHYADRMON - PHY address whose link status is to be monitored. */
 #define TMS570_MDIO_USERPHYSEL0_PHYADRMON(val) BSP_FLD32(val,0, 4)
@@ -196,15 +187,15 @@ typedef struct{
 #define TMS570_MDIO_USERPHYSEL0_PHYADRMON_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
 
 
-/*-------------------TMS570_MDIOUSERACCESS1-------------------*/
+/*------------------TMS570_MDIO_USERACCESS1------------------*/
 /* field: GO - Go bit. */
-#define TMS570_MDIO_USERACCESS1_GO BSP_FLD32(31)
+#define TMS570_MDIO_USERACCESS1_GO BSP_BIT32(31)
 
 /* field: WRITE - Write enable bit. */
-#define TMS570_MDIO_USERACCESS1_WRITE BSP_FLD32(30)
+#define TMS570_MDIO_USERACCESS1_WRITE BSP_BIT32(30)
 
 /* field: ACK - Acknowledge bit. This bit is set if the PHY acknowledged the read transaction. */
-#define TMS570_MDIO_USERACCESS1_ACK BSP_FLD32(29)
+#define TMS570_MDIO_USERACCESS1_ACK BSP_BIT32(29)
 
 /* field: REGADR - Register address bits. */
 #define TMS570_MDIO_USERACCESS1_REGADR(val) BSP_FLD32(val,21, 25)
@@ -222,12 +213,12 @@ typedef struct{
 #define TMS570_MDIO_USERACCESS1_DATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*-------------------TMS570_MDIOUSERPHYSEL1-------------------*/
+/*------------------TMS570_MDIO_USERPHYSEL1------------------*/
 /* field: LINKSEL - Link status determination select bit. */
-#define TMS570_MDIO_USERPHYSEL1_LINKSEL BSP_FLD32(7)
+#define TMS570_MDIO_USERPHYSEL1_LINKSEL BSP_BIT32(7)
 
 /* field: LINKINTENB - Link change interrupt enable. */
-#define TMS570_MDIO_USERPHYSEL1_LINKINTENB BSP_FLD32(6)
+#define TMS570_MDIO_USERPHYSEL1_LINKINTENB BSP_BIT32(6)
 
 /* field: PHYADRMON - PHY address whose link status is to be monitored. */
 #define TMS570_MDIO_USERPHYSEL1_PHYADRMON(val) BSP_FLD32(val,0, 4)
@@ -236,4 +227,4 @@ typedef struct{
 
 
 
-#endif /* LIBBSP_ARM_tms570_MDIO */
+#endif /* LIBBSP_ARM_TMS570_MDIO */

c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_n2het.h

@@ -36,8 +36,8 @@
  * of the authors and should not be interpreted as representing official policies,
  * either expressed or implied, of the FreeBSD Project.
 */
-#ifndef LIBBSP_ARM_tms570_NHET
+#ifndef LIBBSP_ARM_TMS570_NHET
-#define LIBBSP_ARM_tms570_NHET
+#define LIBBSP_ARM_TMS570_NHET
 
 #include <bsp/utility.h>
 
@@ -82,9 +82,9 @@ typedef struct{
 } tms570_nhet_t;
 
 
-/*-----------------------TMS570_NHETGCR-----------------------*/
+/*----------------------TMS570_NHET_GCR----------------------*/
 /* field: HET_PIN_ENA - Enables the output buffers of the pin structures depending on the value of nDIS and DIR. */
-#define TMS570_NHET_GCR_HET_PIN_ENA BSP_FLD32(24)
+#define TMS570_NHET_GCR_HET_PIN_ENA BSP_BIT32(24)
 
 /* field: MP - Master Priority */
 #define TMS570_NHET_GCR_MP(val) BSP_FLD32(val,21, 22)
@@ -92,16 +92,16 @@ typedef struct{
 #define TMS570_NHET_GCR_MP_SET(reg,val) BSP_FLD32SET(reg, val,21, 22)
 
 /* field: PPF - Protect Program Fields */
-#define TMS570_NHET_GCR_PPF BSP_FLD32(18)
+#define TMS570_NHET_GCR_PPF BSP_BIT32(18)
 
 /* field: IS - Ignore Suspend */
-#define TMS570_NHET_GCR_IS BSP_FLD32(17)
+#define TMS570_NHET_GCR_IS BSP_BIT32(17)
 
 /* field: CMS - Clk_master/slave */
-#define TMS570_NHET_GCR_CMS BSP_FLD32(16)
+#define TMS570_NHET_GCR_CMS BSP_BIT32(16)
 
 
-/*-----------------------TMS570_NHETPFR-----------------------*/
+/*----------------------TMS570_NHET_PFR----------------------*/
 /* field: LRPFC - oop Resolution Pre-scale Factor Code */
 #define TMS570_NHET_PFR_LRPFC(val) BSP_FLD32(val,8, 10)
 #define TMS570_NHET_PFR_LRPFC_GET(reg) BSP_FLD32GET(reg,8, 10)
@@ -113,125 +113,113 @@ typedef struct{
 #define TMS570_NHET_PFR_HRPFC_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
 
 
-/*----------------------TMS570_NHETADDR----------------------*/
+/*----------------------TMS570_NHET_ADDR----------------------*/
 /* field: HETADDR - N2HET Current Address */
 #define TMS570_NHET_ADDR_HETADDR(val) BSP_FLD32(val,0, 8)
 #define TMS570_NHET_ADDR_HETADDR_GET(reg) BSP_FLD32GET(reg,0, 8)
 #define TMS570_NHET_ADDR_HETADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
 
 
-/*----------------------TMS570_NHETOFF1----------------------*/
+/*----------------------TMS570_NHET_OFF1----------------------*/
 /* field: OFFSET1 - HETOFF1[5:0] indexes the currently pending high-priority interrupt. */
 #define TMS570_NHET_OFF1_OFFSET1(val) BSP_FLD32(val,0, 5)
 #define TMS570_NHET_OFF1_OFFSET1_GET(reg) BSP_FLD32GET(reg,0, 5)
 #define TMS570_NHET_OFF1_OFFSET1_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
 
 
-/*----------------------TMS570_NHETOFF2----------------------*/
+/*----------------------TMS570_NHET_OFF2----------------------*/
 /* field: OFFSET2 - HETOFF2[5:0] indexes the currently pending low-priority interrupt. */
 #define TMS570_NHET_OFF2_OFFSET2(val) BSP_FLD32(val,0, 5)
 #define TMS570_NHET_OFF2_OFFSET2_GET(reg) BSP_FLD32GET(reg,0, 5)
 #define TMS570_NHET_OFF2_OFFSET2_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
 
 
-/*---------------------TMS570_NHETINTENAS---------------------*/
+/*--------------------TMS570_NHET_INTENAS--------------------*/
 /* field: HETINTENAS - Interrupt Enable Set bits. HETINTENAS is readable and writable in any operation mode. */
-#define TMS570_NHET_INTENAS_HETINTENAS(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_NHET_INTENAS_HETINTENAS_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_NHET_INTENAS_HETINTENAS_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*--------------------TMS570_NHET_INTENAC--------------------*/
-/*---------------------TMS570_NHETINTENAC---------------------*/
 /* field: HETINTENAC - Interrupt Enable Clear bits. HETINTENAC is readable and writable in any operation mode. */
-#define TMS570_NHET_INTENAC_HETINTENAC(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_NHET_INTENAC_HETINTENAC_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_NHET_INTENAC_HETINTENAC_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*----------------------TMS570_NHET_EXC1----------------------*/
-/*----------------------TMS570_NHETEXC1----------------------*/
 /* field: APCNT_OVRFL_ENA - APCNT Overflow Enable */
-#define TMS570_NHET_EXC1_APCNT_OVRFL_ENA BSP_FLD32(24)
+#define TMS570_NHET_EXC1_APCNT_OVRFL_ENA BSP_BIT32(24)
 
 /* field: APCNT_UNRFL_ENA - APCNT Underflow Enable */
-#define TMS570_NHET_EXC1_APCNT_UNRFL_ENA BSP_FLD32(16)
+#define TMS570_NHET_EXC1_APCNT_UNRFL_ENA BSP_BIT32(16)
 
 /* field: PRGM_OVRFL_ENA - Program Overflow Enable */
-#define TMS570_NHET_EXC1_PRGM_OVRFL_ENA BSP_FLD32(8)
+#define TMS570_NHET_EXC1_PRGM_OVRFL_ENA BSP_BIT32(8)
 
 /* field: APCNT_OVRFL_PRY - APCNT Overflow Exception Interrupt Priority */
-#define TMS570_NHET_EXC1_APCNT_OVRFL_PRY BSP_FLD32(2)
+#define TMS570_NHET_EXC1_APCNT_OVRFL_PRY BSP_BIT32(2)
 
 /* field: APCNT_UNRFL_PRY - APCNT Underflow Exception Interrupt Priority */
-#define TMS570_NHET_EXC1_APCNT_UNRFL_PRY BSP_FLD32(1)
+#define TMS570_NHET_EXC1_APCNT_UNRFL_PRY BSP_BIT32(1)
 
 /* field: PRGM_OVRFL_PRY - ProgramOverflow Exception Interrupt Priority */
-#define TMS570_NHET_EXC1_PRGM_OVRFL_PRY BSP_FLD32(0)
+#define TMS570_NHET_EXC1_PRGM_OVRFL_PRY BSP_BIT32(0)
 
 
-/*----------------------TMS570_NHETEXC2----------------------*/
+/*----------------------TMS570_NHET_EXC2----------------------*/
 /* field: DEBUG_STATUS_FLAG - Debug Status Flag. */
-#define TMS570_NHET_EXC2_DEBUG_STATUS_FLAG BSP_FLD32(8)
+#define TMS570_NHET_EXC2_DEBUG_STATUS_FLAG BSP_BIT32(8)
 
 /* field: APCNT_OVRFL_FLAG - APCNT Overflow Flag */
-#define TMS570_NHET_EXC2_APCNT_OVRFL_FLAG BSP_FLD32(2)
+#define TMS570_NHET_EXC2_APCNT_OVRFL_FLAG BSP_BIT32(2)
 
 /* field: APCNT_UNDFL_FLAG - APCNT Underflow Flag */
-#define TMS570_NHET_EXC2_APCNT_UNDFL_FLAG BSP_FLD32(1)
+#define TMS570_NHET_EXC2_APCNT_UNDFL_FLAG BSP_BIT32(1)
 
 /* field: PRGM_OVERFL_FLAG - Program Overflow Flag */
-#define TMS570_NHET_EXC2_PRGM_OVERFL_FLAG BSP_FLD32(0)
+#define TMS570_NHET_EXC2_PRGM_OVERFL_FLAG BSP_BIT32(0)
 
 
-/*-----------------------TMS570_NHETPRY-----------------------*/
+/*----------------------TMS570_NHET_PRY----------------------*/
 /* field: HETPRY - HET Interrupt Priority Level bits */
-#define TMS570_NHET_PRY_HETPRY(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_NHET_PRY_HETPRY_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_NHET_PRY_HETPRY_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*----------------------TMS570_NHET_FLG----------------------*/
-/*-----------------------TMS570_NHETFLG-----------------------*/
 /* field: HETFLAG - Interrupt Flag Register Bits */
-#define TMS570_NHET_FLG_HETFLAG(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_NHET_FLG_HETFLAG_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_NHET_FLG_HETFLAG_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*----------------------TMS570_NHET_AND----------------------*/
-/*-----------------------TMS570_NHETAND-----------------------*/
 /* field: AND_SHARE - AND Share Enable */
 #define TMS570_NHET_AND_AND_SHARE(val) BSP_FLD32(val,0, 15)
 #define TMS570_NHET_AND_AND_SHARE_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_NHET_AND_AND_SHARE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*----------------------TMS570_NHETHRSH----------------------*/
+/*----------------------TMS570_NHET_HRSH----------------------*/
 /* field: HR_SHARE - HR Share Bits */
 #define TMS570_NHET_HRSH_HR_SHARE(val) BSP_FLD32(val,0, 15)
 #define TMS570_NHET_HRSH_HR_SHARE_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_NHET_HRSH_HR_SHARE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*-----------------------TMS570_NHETXOR-----------------------*/
+/*----------------------TMS570_NHET_XOR----------------------*/
 /* field: XOR_SHARE - XOR Share Enable */
 #define TMS570_NHET_XOR_XOR_SHARE(val) BSP_FLD32(val,0, 15)
 #define TMS570_NHET_XOR_XOR_SHARE_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_NHET_XOR_XOR_SHARE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_NHETREQENS---------------------*/
+/*---------------------TMS570_NHET_REQENS---------------------*/
 /* field: REQ_ENA_n - Request Enable Bits */
 #define TMS570_NHET_REQENS_REQ_ENA_n(val) BSP_FLD32(val,0, 7)
 #define TMS570_NHET_REQENS_REQ_ENA_n_GET(reg) BSP_FLD32GET(reg,0, 7)
 #define TMS570_NHET_REQENS_REQ_ENA_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*---------------------TMS570_NHETREQENC---------------------*/
+/*---------------------TMS570_NHET_REQENC---------------------*/
 /* field: REQ_DIS_n - Request Disable Bits */
 #define TMS570_NHET_REQENC_REQ_DIS_n(val) BSP_FLD32(val,0, 7)
 #define TMS570_NHET_REQENC_REQ_DIS_n_GET(reg) BSP_FLD32GET(reg,0, 7)
 #define TMS570_NHET_REQENC_REQ_DIS_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*----------------------TMS570_NHETREQDS----------------------*/
+/*---------------------TMS570_NHET_REQDS---------------------*/
 /* field: TDBS_n - HTU, DMA or Both Select Bits */
 #define TMS570_NHET_REQDS_TDBS_n(val) BSP_FLD32(val,16, 23)
 #define TMS570_NHET_REQDS_TDBS_n_GET(reg) BSP_FLD32GET(reg,16, 23)
@@ -243,65 +231,41 @@ typedef struct{
 #define TMS570_NHET_REQDS_TDS_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*-----------------------TMS570_NHETDIR-----------------------*/
+/*----------------------TMS570_NHET_DIR----------------------*/
 /* field: HETDIR_n - Data direction of NHET pins */
-#define TMS570_NHET_DIR_HETDIR_n(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_NHET_DIR_HETDIR_n_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_NHET_DIR_HETDIR_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*----------------------TMS570_NHET_DIN----------------------*/
-/*-----------------------TMS570_NHETDIN-----------------------*/
 /* field: HETDIN_n - Data input. This bit displays the logic state of the pin. */
-#define TMS570_NHET_DIN_HETDIN_n(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_NHET_DIN_HETDIN_n_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_NHET_DIN_HETDIN_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*----------------------TMS570_NHET_DOUT----------------------*/
-/*----------------------TMS570_NHETDOUT----------------------*/
 /* field: HETDOUT_n - Data out write. Writes to this bit will only take effect when the pin is configured as an output. */
-#define TMS570_NHET_DOUT_HETDOUT_n(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_NHET_DOUT_HETDOUT_n_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_NHET_DOUT_HETDOUT_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*----------------------TMS570_NHET_DSET----------------------*/
-/*----------------------TMS570_NHETDSET----------------------*/
 /* field: HETDSET_n - This register allows bits of HETDOUT to be set while avoiding the pitfalls of a readmodify- write */
-#define TMS570_NHET_DSET_HETDSET_n(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_NHET_DSET_HETDSET_n_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_NHET_DSET_HETDSET_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*----------------------TMS570_NHET_DCLR----------------------*/
-/*----------------------TMS570_NHETDCLR----------------------*/
 /* field: HETDCLR_n - This register allows bits of HETDOUT to be cleared while avoiding the pitfalls of a read-modifywrite */
-#define TMS570_NHET_DCLR_HETDCLR_n(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_NHET_DCLR_HETDCLR_n_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_NHET_DCLR_HETDCLR_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*----------------------TMS570_NHET_PDR----------------------*/
-/*-----------------------TMS570_NHETPDR-----------------------*/
 /* field: HETPDR_n - Open drain control for HET[n] pins */
-#define TMS570_NHET_PDR_HETPDR_n(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_NHET_PDR_HETPDR_n_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_NHET_PDR_HETPDR_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*---------------------TMS570_NHET_PULDIS---------------------*/
-/*---------------------TMS570_NHETPULDIS---------------------*/
 /* field: HETPULDIS_n - Pull disable for N2HET pins */
-#define TMS570_NHET_PULDIS_HETPULDIS_n(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_NHET_PULDIS_HETPULDIS_n_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_NHET_PULDIS_HETPULDIS_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*----------------------TMS570_NHET_PSL----------------------*/
-/*-----------------------TMS570_NHETPSL-----------------------*/
 /* field: HETPSL_n - Pull select for NHET pins */
-#define TMS570_NHET_PSL_HETPSL_n(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_NHET_PSL_HETPSL_n_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_NHET_PSL_HETPSL_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*----------------------TMS570_NHET_PCR----------------------*/
-/*-----------------------TMS570_NHETPCR-----------------------*/
 /* field: TEST - Test Bit. */
-#define TMS570_NHET_PCR_TEST BSP_FLD32(8)
+#define TMS570_NHET_PCR_TEST BSP_BIT32(8)
 
 /* field: PARITY_ENA - Enable/disable parity checking. */
 #define TMS570_NHET_PCR_PARITY_ENA(val) BSP_FLD32(val,0, 3)
@@ -309,21 +273,18 @@ typedef struct{
 #define TMS570_NHET_PCR_PARITY_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*-----------------------TMS570_NHETPAR-----------------------*/
+/*----------------------TMS570_NHET_PAR----------------------*/
 /* field: PAOFF - Parity Error Address Offset. */
 #define TMS570_NHET_PAR_PAOFF(val) BSP_FLD32(val,2, 12)
 #define TMS570_NHET_PAR_PAOFF_GET(reg) BSP_FLD32GET(reg,2, 12)
 #define TMS570_NHET_PAR_PAOFF_SET(reg,val) BSP_FLD32SET(reg, val,2, 12)
 
 
-/*-----------------------TMS570_NHETPPR-----------------------*/
+/*----------------------TMS570_NHET_PPR----------------------*/
 /* field: HETPPR_n - NHET Parity Pin Select Bits - Allows HET[n] pins to be configured to drive to a known state when */
-#define TMS570_NHET_PPR_HETPPR_n(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_NHET_PPR_HETPPR_n_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_NHET_PPR_HETPPR_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*---------------------TMS570_NHET_SFPRLD---------------------*/
-/*---------------------TMS570_NHETSFPRLD---------------------*/
 /* field: CCDIV - Counter Clock Divider */
 #define TMS570_NHET_SFPRLD_CCDIV(val) BSP_FLD32(val,16, 17)
 #define TMS570_NHET_SFPRLD_CCDIV_GET(reg) BSP_FLD32GET(reg,16, 17)
@@ -335,14 +296,11 @@ typedef struct{
 #define TMS570_NHET_SFPRLD_CPRLD_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
 
 
-/*----------------------TMS570_NHETSFENA----------------------*/
+/*---------------------TMS570_NHET_SFENA---------------------*/
 /* field: HETSFENA_n - Suppression Filter Enable Bits */
-#define TMS570_NHET_SFENA_HETSFENA_n(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_NHET_SFENA_HETSFENA_n_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_NHET_SFENA_HETSFENA_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*---------------------TMS570_NHET_LBPSEL---------------------*/
-/*---------------------TMS570_NHETLBPSEL---------------------*/
 /* field: LBPTYPE - Loop Back Pair Type Select Bits */
 #define TMS570_NHET_LBPSEL_LBPTYPE(val) BSP_FLD32(val,16, 31)
 #define TMS570_NHET_LBPSEL_LBPTYPE_GET(reg) BSP_FLD32GET(reg,16, 31)
@@ -354,7 +312,7 @@ typedef struct{
 #define TMS570_NHET_LBPSEL_LBPSEL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_NHETLBPDIR---------------------*/
+/*---------------------TMS570_NHET_LBPDIR---------------------*/
 /* field: LBPTSTENA - Loopback Test Enable Key */
 #define TMS570_NHET_LBPDIR_LBPTSTENA(val) BSP_FLD32(val,16, 19)
 #define TMS570_NHET_LBPDIR_LBPTSTENA_GET(reg) BSP_FLD32GET(reg,16, 19)
@@ -366,12 +324,9 @@ typedef struct{
 #define TMS570_NHET_LBPDIR_LBPDIR_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_NHETPINDIS---------------------*/
+/*---------------------TMS570_NHET_PINDIS---------------------*/
 /* field: HETPINDIS_n - N2HET Pin Disable Bits */
-#define TMS570_NHET_PINDIS_HETPINDIS_n(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_NHET_PINDIS_HETPINDIS_n_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_NHET_PINDIS_HETPINDIS_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
 
-
+#endif /* LIBBSP_ARM_TMS570_NHET */
-#endif /* LIBBSP_ARM_tms570_NHET */

c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pbist.h

@@ -36,8 +36,8 @@
  * of the authors and should not be interpreted as representing official policies,
  * either expressed or implied, of the FreeBSD Project.
 */
-#ifndef LIBBSP_ARM_tms570_PBIST
+#ifndef LIBBSP_ARM_TMS570_PBIST
-#define LIBBSP_ARM_tms570_PBIST
+#define LIBBSP_ARM_TMS570_PBIST
 
 #include <bsp/utility.h>
 
@@ -67,14 +67,11 @@ typedef struct{
 } tms570_pbist_t;
 
 
-/*----------------------TMS570_PBISTDNW----------------------*/
+/*----------------------TMS570_PBIST_DNW----------------------*/
 /* field: Reserved - Do not write */
-#define TMS570_PBIST_DNW_Reserved(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_PBIST_DNW_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_PBIST_DNW_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*---------------------TMS570_PBIST_RAMT---------------------*/
-/*----------------------TMS570_PBISTRAMT----------------------*/
 /* field: RGS - Ram Group Select. Refer Table 2-5 for information on the RGS value for each memory. */
 #define TMS570_PBIST_RAMT_RGS(val) BSP_FLD32(val,24, 31)
 #define TMS570_PBIST_RAMT_RGS_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -106,108 +103,93 @@ typedef struct{
 #define TMS570_PBIST_RAMT_RLS_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
 
 
-/*----------------------TMS570_PBISTDLR----------------------*/
+/*----------------------TMS570_PBIST_DLR----------------------*/
 /* field: DLR4 - Config access: setting this bit allows the host processor to configure the PBIST controller registers */
-#define TMS570_PBIST_DLR_DLR4 BSP_FLD32(4)
+#define TMS570_PBIST_DLR_DLR4 BSP_BIT32(4)
 
 /* field: DLR2 - ROM-based testing: setting this bit enables the PBIST controller to execute test algorithms that are */
-#define TMS570_PBIST_DLR_DLR2 BSP_FLD32(2)
+#define TMS570_PBIST_DLR_DLR2 BSP_BIT32(2)
 
 
-/*----------------------TMS570_PBISTPACT----------------------*/
+/*---------------------TMS570_PBIST_PACT---------------------*/
 /* field: PACT1 - PBIST Activate */
-#define TMS570_PBIST_PACT_PACT1 BSP_FLD32(1)
+#define TMS570_PBIST_PACT_PACT1 BSP_BIT32(1)
 
 /* field: PACT0 - ROM Clock Enable Register */
-#define TMS570_PBIST_PACT_PACT0 BSP_FLD32(0)
+#define TMS570_PBIST_PACT_PACT0 BSP_BIT32(0)
 
 
-/*--------------------TMS570_PBISTPBISTID--------------------*/
+/*--------------------TMS570_PBIST_PBISTID--------------------*/
 /* field: PBIST_ID - This is a unique ID assigned to each PBIST controller in a device with multiple PBIST controllers. */
 #define TMS570_PBIST_PBISTID_PBIST_ID(val) BSP_FLD32(val,0, 7)
 #define TMS570_PBIST_PBISTID_PBIST_ID_GET(reg) BSP_FLD32GET(reg,0, 7)
 #define TMS570_PBIST_PBISTID_PBIST_ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*----------------------TMS570_PBISTOVER----------------------*/
+/*---------------------TMS570_PBIST_OVER---------------------*/
 /* field: OVER0 - RINFO Override Bit */
-#define TMS570_PBIST_OVER_OVER0 BSP_FLD32(0)
+#define TMS570_PBIST_OVER_OVER0 BSP_BIT32(0)
 
 
-/*---------------------TMS570_PBISTFSRF0---------------------*/
+/*---------------------TMS570_PBIST_FSRF0---------------------*/
 /* field: FSRF0 - Fail Status 0. */
-#define TMS570_PBIST_FSRF0_FSRF0 BSP_FLD32(0)
+#define TMS570_PBIST_FSRF0_FSRF0 BSP_BIT32(0)
 
 
-/*---------------------TMS570_PBISTFSRC0---------------------*/
+/*---------------------TMS570_PBIST_FSRC0---------------------*/
 /* field: FSRC0 - Fail Status Count 0. Indicates the number of failures on port 0. */
 #define TMS570_PBIST_FSRC0_FSRC0(val) BSP_FLD32(val,0, 7)
 #define TMS570_PBIST_FSRC0_FSRC0_GET(reg) BSP_FLD32GET(reg,0, 7)
 #define TMS570_PBIST_FSRC0_FSRC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*---------------------TMS570_PBISTFSRC1---------------------*/
+/*---------------------TMS570_PBIST_FSRC1---------------------*/
 /* field: FSRC1 - Fail Status Count 1. Indicates the number of failures on port 1. */
 #define TMS570_PBIST_FSRC1_FSRC1(val) BSP_FLD32(val,0, 7)
 #define TMS570_PBIST_FSRC1_FSRC1_GET(reg) BSP_FLD32GET(reg,0, 7)
 #define TMS570_PBIST_FSRC1_FSRC1_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*---------------------TMS570_PBISTFSRA0---------------------*/
+/*---------------------TMS570_PBIST_FSRA0---------------------*/
 /* field: FSRA0 - Fail Status Address 0. Contains the address of the first failure. */
 #define TMS570_PBIST_FSRA0_FSRA0(val) BSP_FLD32(val,0, 15)
 #define TMS570_PBIST_FSRA0_FSRA0_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_PBIST_FSRA0_FSRA0_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_PBISTFSRA1---------------------*/
+/*---------------------TMS570_PBIST_FSRA1---------------------*/
 /* field: FSRA1 - Fail Status Address 1. Contains the address of the first failure. */
 #define TMS570_PBIST_FSRA1_FSRA1(val) BSP_FLD32(val,0, 15)
 #define TMS570_PBIST_FSRA1_FSRA1_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_PBIST_FSRA1_FSRA1_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_PBISTFSRDL0---------------------*/
+/*--------------------TMS570_PBIST_FSRDL0--------------------*/
 /* field: FSRDL1 - Failure data on port 1 */
-#define TMS570_PBIST_FSRDL0_FSRDL1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_PBIST_FSRDL0_FSRDL1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_PBIST_FSRDL0_FSRDL1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*--------------------TMS570_PBIST_FSRDL1--------------------*/
-/*---------------------TMS570_PBISTFSRDL1---------------------*/
 /* field: FSRDL1 - Failure data on port 1 */
-#define TMS570_PBIST_FSRDL1_FSRDL1(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_PBIST_FSRDL1_FSRDL1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_PBIST_FSRDL1_FSRDL1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*----------------------TMS570_PBIST_ROM----------------------*/
-/*----------------------TMS570_PBISTROM----------------------*/
 /* field: ROM - ROM Mask */
 #define TMS570_PBIST_ROM_ROM(val) BSP_FLD32(val,0, 1)
 #define TMS570_PBIST_ROM_ROM_GET(reg) BSP_FLD32GET(reg,0, 1)
 #define TMS570_PBIST_ROM_ROM_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
 
 
-/*----------------------TMS570_PBISTALGO----------------------*/
+/*---------------------TMS570_PBIST_ALGO---------------------*/
 /* field: ROM_ALG_MASK - Each bit corresponds to a specific algorithm */
-#define TMS570_PBIST_ALGO_ROM_ALG_MASK(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_PBIST_ALGO_ROM_ALG_MASK_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_PBIST_ALGO_ROM_ALG_MASK_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*--------------------TMS570_PBIST_RINFOL--------------------*/
-/*---------------------TMS570_PBISTRINFOL---------------------*/
 /* field: RAM_ALG_MASK_LOW - Each bit corresponds to a specific algorithm */
-#define TMS570_PBIST_RINFOL_RAM_ALG_MASK_LOW(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_PBIST_RINFOL_RAM_ALG_MASK_LOW_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_PBIST_RINFOL_RAM_ALG_MASK_LOW_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*--------------------TMS570_PBIST_RINFOUL--------------------*/
-/*--------------------TMS570_PBISTRINFOUL--------------------*/
 /* field: RAM_ALG_MASK_UP - Each bit corresponds to a specific algorithm */
-#define TMS570_PBIST_RINFOUL_RAM_ALG_MASK_UP(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_PBIST_RINFOUL_RAM_ALG_MASK_UP_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_PBIST_RINFOUL_RAM_ALG_MASK_UP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
 
-
+#endif /* LIBBSP_ARM_TMS570_PBIST */
-#endif /* LIBBSP_ARM_tms570_PBIST */

c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pcr.h

@@ -36,8 +36,8 @@
  * of the authors and should not be interpreted as representing official policies,
  * either expressed or implied, of the FreeBSD Project.
 */
-#ifndef LIBBSP_ARM_tms570_PCR
+#ifndef LIBBSP_ARM_TMS570_PCR
-#define LIBBSP_ARM_tms570_PCR
+#define LIBBSP_ARM_TMS570_PCR
 
 #include <bsp/utility.h>
 
@@ -76,75 +76,45 @@ typedef struct{
 } tms570_pcr_t;
 
 
-/*--------------------TMS570_PCRPMPROTSET0--------------------*/
+/*-------------------TMS570_PCR_PMPROTSET0-------------------*/
 /* field: PCSPROTSET - Peripheral memory frame protection set. */
-#define TMS570_PCR_PMPROTSET0_PCSPROTSET(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_PCR_PMPROTSET0_PCSPROTSET_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_PCR_PMPROTSET0_PCSPROTSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_PCR_PMPROTSET1-------------------*/
-/*--------------------TMS570_PCRPMPROTSET1--------------------*/
 /* field: PCSPROTSET - Peripheral memory frame protection set. */
-#define TMS570_PCR_PMPROTSET1_PCSPROTSET(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_PCR_PMPROTSET1_PCSPROTSET_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_PCR_PMPROTSET1_PCSPROTSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_PCR_PMPROTCLR0-------------------*/
-/*--------------------TMS570_PCRPMPROTCLR0--------------------*/
 /* field: PCSPROTCLR - Peripheral memory frame protection clear. */
-#define TMS570_PCR_PMPROTCLR0_PCSPROTCLR(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_PCR_PMPROTCLR0_PCSPROTCLR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_PCR_PMPROTCLR0_PCSPROTCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_PCR_PMPROTCLR1-------------------*/
-/*--------------------TMS570_PCRPMPROTCLR1--------------------*/
 /* field: PCSPROTCLR - Peripheral memory frame protection clear. */
-#define TMS570_PCR_PMPROTCLR1_PCSPROTCLR(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_PCR_PMPROTCLR1_PCSPROTCLR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_PCR_PMPROTCLR1_PCSPROTCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*--------------------TMS570_PCR_PPROTSETx--------------------*/
-/*--------------------TMS570_PCRPPROTSET0--------------------*/
 /* field: PROTSET - Peripheral select quadrant protection set. */
-#define TMS570_PCR_PPROTSET0_PROTSET(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_PCR_PPROTSET0_PROTSET_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_PCR_PPROTSET0_PROTSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*--------------------TMS570_PCR_PPROTCLRx--------------------*/
-/*--------------------TMS570_PCRPPROTCLR0--------------------*/
 /* field: PROTCLR - Peripheral select quadrant protection clear. */
-#define TMS570_PCR_PPROTCLR0_PROTCLR(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_PCR_PPROTCLR0_PROTCLR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_PCR_PPROTCLR0_PROTCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_PCR_PCSPWRDWNSETx------------------*/
-/*------------------TMS570_PCRPCSPWRDWNSET0------------------*/
 /* field: PWRDNSET - Peripheral memory clock power-down set. */
-#define TMS570_PCR_PCSPWRDWNSET0_PWRDNSET(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_PCR_PCSPWRDWNSET0_PWRDNSET_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_PCR_PCSPWRDWNSET0_PWRDNSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_PCR_PCSPWRDWNCLRx------------------*/
-/*------------------TMS570_PCRPCSPWRDWNCLR0------------------*/
 /* field: PWRDNCLR - Peripheral memory clock power-down clear. */
-#define TMS570_PCR_PCSPWRDWNCLR0_PWRDNCLR(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_PCR_PCSPWRDWNCLR0_PWRDNCLR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_PCR_PCSPWRDWNCLR0_PWRDNCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_PCR_PSPWRDWNSETx------------------*/
-/*-------------------TMS570_PCRPSPWRDWNSET0-------------------*/
 /* field: PWRDWNSET - Peripheral select quadrant clock power-down set. */
-#define TMS570_PCR_PSPWRDWNSET0_PWRDWNSET(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_PCR_PSPWRDWNSET0_PWRDWNSET_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_PCR_PSPWRDWNSET0_PWRDWNSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_PCR_PSPWRDWNCLRx------------------*/
-/*-------------------TMS570_PCRPSPWRDWNCLR0-------------------*/
 /* field: PWRDWNCLR - Peripheral select quadrant clock power-down clear. */
-#define TMS570_PCR_PSPWRDWNCLR0_PWRDWNCLR(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_PCR_PSPWRDWNCLR0_PWRDWNCLR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_PCR_PSPWRDWNCLR0_PWRDWNCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
 
-
+#endif /* LIBBSP_ARM_TMS570_PCR */
-#endif /* LIBBSP_ARM_tms570_PCR */

c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pll.h

@@ -36,8 +36,8 @@
  * of the authors and should not be interpreted as representing official policies,
  * either expressed or implied, of the FreeBSD Project.
 */
-#ifndef LIBBSP_ARM_tms570_PLL
+#ifndef LIBBSP_ARM_TMS570_PLL
-#define LIBBSP_ARM_tms570_PLL
+#define LIBBSP_ARM_TMS570_PLL
 
 #include <bsp/utility.h>
 
@@ -67,7 +67,7 @@ typedef struct{
 } tms570_pll_t;
 
 
-/*---------------------TMS570_PLLPLLCTL3---------------------*/
+/*---------------------TMS570_PLL_PLLCTL3---------------------*/
 /* field: ODPLL2 - Internal PLL Output Divider */
 #define TMS570_PLL_PLLCTL3_ODPLL2(val) BSP_FLD32(val,29, 31)
 #define TMS570_PLL_PLLCTL3_ODPLL2_GET(reg) BSP_FLD32GET(reg,29, 31)
@@ -89,7 +89,7 @@ typedef struct{
 #define TMS570_PLL_PLLCTL3_PLLMUL2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_PLLCLKSLIP---------------------*/
+/*---------------------TMS570_PLL_CLKSLIP---------------------*/
 /* field: PLL1_SLIP_FILTER_COUNT - Configure the count for the filtered PLL slip. Count is on 10M clock. */
 #define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_COUNT(val) BSP_FLD32(val,8, 13)
 #define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_COUNT_GET(reg) BSP_FLD32GET(reg,8, 13)
@@ -101,20 +101,20 @@ typedef struct{
 #define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*---------------------TMS570_PLLSSWPLL1---------------------*/
+/*---------------------TMS570_PLL_SSWPLL1---------------------*/
 /* field: CAPTURE_WINDOW_INDEX - The capture counter present in the PLL wrapper will count the PLL clock edges when */
 #define TMS570_PLL_SSWPLL1_CAPTURE_WINDOW_INDEX(val) BSP_FLD32(val,8, 15)
 #define TMS570_PLL_SSWPLL1_CAPTURE_WINDOW_INDEX_GET(reg) BSP_FLD32GET(reg,8, 15)
 #define TMS570_PLL_SSWPLL1_CAPTURE_WINDOW_INDEX_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
 
 /* field: COUNTER_READ_READY - Counter read ready. */
-#define TMS570_PLL_SSWPLL1_COUNTER_READ_READY BSP_FLD32(6)
+#define TMS570_PLL_SSWPLL1_COUNTER_READ_READY BSP_BIT32(6)
 
 /* field: COUNTER_RESET - Counter reset. */
-#define TMS570_PLL_SSWPLL1_COUNTER_RESET BSP_FLD32(5)
+#define TMS570_PLL_SSWPLL1_COUNTER_RESET BSP_BIT32(5)
 
 /* field: COUNTER_EN - Counter enable. */
-#define TMS570_PLL_SSWPLL1_COUNTER_EN BSP_FLD32(4)
+#define TMS570_PLL_SSWPLL1_COUNTER_EN BSP_BIT32(4)
 
 /* field: TAP_COUNTER_DIS - The value in this register is used to program a particular bit in CLKOUT counter. */
 #define TMS570_PLL_SSWPLL1_TAP_COUNTER_DIS(val) BSP_FLD32(val,1, 3)
@@ -122,24 +122,18 @@ typedef struct{
 #define TMS570_PLL_SSWPLL1_TAP_COUNTER_DIS_SET(reg,val) BSP_FLD32SET(reg, val,1, 3)
 
 /* field: EXT_COUNTER_EN - Modulation Depth Measurement mode */
-#define TMS570_PLL_SSWPLL1_EXT_COUNTER_EN BSP_FLD32(0)
+#define TMS570_PLL_SSWPLL1_EXT_COUNTER_EN BSP_BIT32(0)
 
 
-/*---------------------TMS570_PLLSSWPLL2---------------------*/
+/*---------------------TMS570_PLL_SSWPLL2---------------------*/
 /* field: SSW_CAPTURE_COUNT - Capture count. This register returns the value of the capture count. */
-#define TMS570_PLL_SSWPLL2_SSW_CAPTURE_COUNT(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_PLL_SSWPLL2_SSW_CAPTURE_COUNT_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_PLL_SSWPLL2_SSW_CAPTURE_COUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*---------------------TMS570_PLL_SSWPLL3---------------------*/
-/*---------------------TMS570_PLLSSWPLL3---------------------*/
 /* field: SSW_CAPTURE_COUNT - Value of CLKout count register. */
-#define TMS570_PLL_SSWPLL3_SSW_CAPTURE_COUNT(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_PLL_SSWPLL3_SSW_CAPTURE_COUNT_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_PLL_SSWPLL3_SSW_CAPTURE_COUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*----------------------TMS570_PLL_CSDIS----------------------*/
-/*----------------------TMS570_PLLCSDIS----------------------*/
 /* field: CLKSR_7_3_OFF - Clock source[7-3] off. */
 #define TMS570_PLL_CSDIS_CLKSR_7_3_OFF(val) BSP_FLD32(val,3, 7)
 #define TMS570_PLL_CSDIS_CLKSR_7_3_OFF_GET(reg) BSP_FLD32GET(reg,3, 7)
@@ -151,7 +145,7 @@ typedef struct{
 #define TMS570_PLL_CSDIS_CLKSR_1_0_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
 
 
-/*---------------------TMS570_PLLCSDISSET---------------------*/
+/*--------------------TMS570_PLL_CSDISSET--------------------*/
 /* field: SETCLKSR_7_3_OFF - Set clock source[7-3] to the disabled state. */
 #define TMS570_PLL_CSDISSET_SETCLKSR_7_3_OFF(val) BSP_FLD32(val,3, 7)
 #define TMS570_PLL_CSDISSET_SETCLKSR_7_3_OFF_GET(reg) BSP_FLD32GET(reg,3, 7)
@@ -163,7 +157,7 @@ typedef struct{
 #define TMS570_PLL_CSDISSET_SETCLKSR_1_0_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
 
 
-/*---------------------TMS570_PLLCSDISCLR---------------------*/
+/*--------------------TMS570_PLL_CSDISCLR--------------------*/
 /* field: CLRCLKSR_7_3_OFF - Enables clock source[7-3]. */
 #define TMS570_PLL_CSDISCLR_CLRCLKSR_7_3_OFF(val) BSP_FLD32(val,3, 7)
 #define TMS570_PLL_CSDISCLR_CLRCLKSR_7_3_OFF_GET(reg) BSP_FLD32GET(reg,3, 7)
@@ -175,7 +169,7 @@ typedef struct{
 #define TMS570_PLL_CSDISCLR_CLRCLKSR_1_0_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
 
 
-/*---------------------TMS570_PLLCSVSTAT---------------------*/
+/*---------------------TMS570_PLL_CSVSTAT---------------------*/
 /* field: CLKSR_7_3V - Clock source[7-0] valid. */
 #define TMS570_PLL_CSVSTAT_CLKSR_7_3V(val) BSP_FLD32(val,3, 7)
 #define TMS570_PLL_CSVSTAT_CLKSR_7_3V_GET(reg) BSP_FLD32GET(reg,3, 7)
@@ -187,9 +181,9 @@ typedef struct{
 #define TMS570_PLL_CSVSTAT_CLKSR_1_0V_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
 
 
-/*---------------------TMS570_PLLPLLCTL1---------------------*/
+/*---------------------TMS570_PLL_PLLCTL1---------------------*/
 /* field: ROS - Reset on PLL Slip */
-#define TMS570_PLL_PLLCTL1_ROS BSP_FLD32(31)
+#define TMS570_PLL_PLLCTL1_ROS BSP_BIT32(31)
 
 /* field: MASK_SLIP - Mask detection of PLL slip */
 #define TMS570_PLL_PLLCTL1_MASK_SLIP(val) BSP_FLD32(val,29, 30)
@@ -202,7 +196,7 @@ typedef struct{
 #define TMS570_PLL_PLLCTL1_PLLDIV_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
 
 /* field: ROF - Reset on Oscillator Fail */
-#define TMS570_PLL_PLLCTL1_ROF BSP_FLD32(23)
+#define TMS570_PLL_PLLCTL1_ROF BSP_BIT32(23)
 
 /* field: REFCLKDIV - Reference Clock Divider */
 #define TMS570_PLL_PLLCTL1_REFCLKDIV(val) BSP_FLD32(val,16, 21)
@@ -215,9 +209,9 @@ typedef struct{
 #define TMS570_PLL_PLLCTL1_PLLMUL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_PLLPLLCTL2---------------------*/
+/*---------------------TMS570_PLL_PLLCTL2---------------------*/
 /* field: FMENA - Frequency Modulation Enable. */
-#define TMS570_PLL_PLLCTL2_FMENA BSP_FLD32(31)
+#define TMS570_PLL_PLLCTL2_FMENA BSP_BIT32(31)
 
 /* field: SPREADINGRATE - NS = SPREADINGRATE + 1 */
 #define TMS570_PLL_PLLCTL2_SPREADINGRATE(val) BSP_FLD32(val,22, 30)
@@ -240,12 +234,12 @@ typedef struct{
 #define TMS570_PLL_PLLCTL2_SPR_AMOUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
 
 
-/*--------------------TMS570_PLLLPOMONCTL--------------------*/
+/*--------------------TMS570_PLL_LPOMONCTL--------------------*/
 /* field: BIAS_ENABLE - Bias enable. */
-#define TMS570_PLL_LPOMONCTL_BIAS_ENABLE BSP_FLD32(24)
+#define TMS570_PLL_LPOMONCTL_BIAS_ENABLE BSP_BIT32(24)
 
 /* field: OSCFRQCONFIGCNT - Configures the counter based on OSC frequency. */
-#define TMS570_PLL_LPOMONCTL_OSCFRQCONFIGCNT BSP_FLD32(16)
+#define TMS570_PLL_LPOMONCTL_OSCFRQCONFIGCNT BSP_BIT32(16)
 
 /* field: HFTRIM - High frequency oscillator trim value. */
 #define TMS570_PLL_LPOMONCTL_HFTRIM(val) BSP_FLD32(val,8, 12)
@@ -253,15 +247,15 @@ typedef struct{
 #define TMS570_PLL_LPOMONCTL_HFTRIM_SET(reg,val) BSP_FLD32SET(reg, val,8, 12)
 
 
-/*---------------------TMS570_PLLCLKTEST---------------------*/
+/*---------------------TMS570_PLL_CLKTEST---------------------*/
 /* field: ALTLIMPCLOCKENABLE - This bit selects a clock driven by the GIOB[0] pin as an alternate limp clock to the clock */
-#define TMS570_PLL_CLKTEST_ALTLIMPCLOCKENABLE BSP_FLD32(26)
+#define TMS570_PLL_CLKTEST_ALTLIMPCLOCKENABLE BSP_BIT32(26)
 
 /* field: RANGEDETCTRL - Range detection control. */
-#define TMS570_PLL_CLKTEST_RANGEDETCTRL BSP_FLD32(25)
+#define TMS570_PLL_CLKTEST_RANGEDETCTRL BSP_BIT32(25)
 
 /* field: RANGEDETENASSEL - Selects range detection enable. This bit resets asynchronously on power on reset. */
-#define TMS570_PLL_CLKTEST_RANGEDETENASSEL BSP_FLD32(24)
+#define TMS570_PLL_CLKTEST_RANGEDETENASSEL BSP_BIT32(24)
 
 /* field: CLK_TEST_EN - Clock test enable. This bit enables the clock going to the ECLK pin. */
 #define TMS570_PLL_CLKTEST_CLK_TEST_EN(val) BSP_FLD32(val,16, 19)
@@ -269,9 +263,9 @@ typedef struct{
 #define TMS570_PLL_CLKTEST_CLK_TEST_EN_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
 
 
-/*----------------------TMS570_PLLGPREG1----------------------*/
+/*---------------------TMS570_PLL_GPREG1---------------------*/
 /* field: EMIF_FUNC - Enable EMIF functions to be output. */
-#define TMS570_PLL_GPREG1_EMIF_FUNC BSP_FLD32(31)
+#define TMS570_PLL_GPREG1_EMIF_FUNC BSP_BIT32(31)
 
 /* field: PLL1_FBSLIP_FILTER__COUNT - FBSLIP down counter programmed value. */
 #define TMS570_PLL_GPREG1_PLL1_FBSLIP_FILTER__COUNT(val) BSP_FLD32(val,20, 25)
@@ -289,16 +283,16 @@ typedef struct{
 #define TMS570_PLL_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_PLLGLBSTAT---------------------*/
+/*---------------------TMS570_PLL_GLBSTAT---------------------*/
 /* field: FBSLIP - PLL over cycle slip detection. */
-#define TMS570_PLL_GLBSTAT_FBSLIP BSP_FLD32(9)
+#define TMS570_PLL_GLBSTAT_FBSLIP BSP_BIT32(9)
 
 /* field: RFSLIP - PLL under cycle slip detection. */
-#define TMS570_PLL_GLBSTAT_RFSLIP BSP_FLD32(8)
+#define TMS570_PLL_GLBSTAT_RFSLIP BSP_BIT32(8)
 
 /* field: OSCFAIL - Oscillator fail flag bit. */
-#define TMS570_PLL_GLBSTAT_OSCFAIL BSP_FLD32(0)
+#define TMS570_PLL_GLBSTAT_OSCFAIL BSP_BIT32(0)
 
 
 
-#endif /* LIBBSP_ARM_tms570_PLL */
+#endif /* LIBBSP_ARM_TMS570_PLL */

c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pmm.h

@@ -36,8 +36,8 @@
  * of the authors and should not be interpreted as representing official policies,
  * either expressed or implied, of the FreeBSD Project.
 */
-#ifndef LIBBSP_ARM_tms570_PMM
+#ifndef LIBBSP_ARM_TMS570_PMM
-#define LIBBSP_ARM_tms570_PMM
+#define LIBBSP_ARM_TMS570_PMM
 
 #include <bsp/utility.h>
 
@@ -66,7 +66,7 @@ typedef struct{
 } tms570_pmm_t;
 
 
-/*-----------------TMS570_PMMLOGICPDPWRCTRL0-----------------*/
+/*-----------------TMS570_PMM_LOGICPDPWRCTRL0-----------------*/
 /* field: LOGICPDON0 - Read in User and Privileged Mode. Write in Privileged Mode only. */
 #define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON0(val) BSP_FLD32(val,24, 27)
 #define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON0_GET(reg) BSP_FLD32GET(reg,24, 27)
@@ -88,7 +88,7 @@ typedef struct{
 #define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON3_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*------------------TMS570_PMMMEMPDPWRCTRL0------------------*/
+/*------------------TMS570_PMM_MEMPDPWRCTRL0------------------*/
 /* field: MEMPDON0 - Read in User and Privileged Mode. Write in Privileged Mode only. */
 #define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON0(val) BSP_FLD32(val,24, 27)
 #define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON0_GET(reg) BSP_FLD32GET(reg,24, 27)
@@ -105,57 +105,57 @@ typedef struct{
 #define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON2_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
 
 
-/*-------------------TMS570_PMMPDCLKDISREG-------------------*/
+/*-------------------TMS570_PMM_PDCLKDISREG-------------------*/
 /* field: PDCLK_DIS_3 - Read in User and Privileged Mode returns the current value of PDCLK_DIS[3]. */
-#define TMS570_PMM_PDCLKDISREG_PDCLK_DIS_3 BSP_FLD32(3)
+#define TMS570_PMM_PDCLKDISREG_PDCLK_DIS_3 BSP_BIT32(3)
 
 /* field: PDCLK_DIS_2 - Read in User and Privileged Mode returns the current value of PDCLK_DIS[2]. */
-#define TMS570_PMM_PDCLKDISREG_PDCLK_DIS_2 BSP_FLD32(2)
+#define TMS570_PMM_PDCLKDISREG_PDCLK_DIS_2 BSP_BIT32(2)
 
 /* field: PDCLK_DIS_1 - ead in User and Privileged Mode returns the current value of PDCLK_DIS[1]. */
-#define TMS570_PMM_PDCLKDISREG_PDCLK_DIS_1 BSP_FLD32(1)
+#define TMS570_PMM_PDCLKDISREG_PDCLK_DIS_1 BSP_BIT32(1)
 
 /* field: PDCLK_DIS_0 - Read in User and Privileged Mode returns the current value of PDCLK_DIS[0]. */
-#define TMS570_PMM_PDCLKDISREG_PDCLK_DIS_0 BSP_FLD32(0)
+#define TMS570_PMM_PDCLKDISREG_PDCLK_DIS_0 BSP_BIT32(0)
 
 
-/*------------------TMS570_PMMPDCLKDISSETREG------------------*/
+/*-----------------TMS570_PMM_PDCLKDISSETREG-----------------*/
 /* field: PDCLK_DISSET_3 - Read in User and Privileged Mode returns the current value of PDCLK_DISSET[3]. */
-#define TMS570_PMM_PDCLKDISSETREG_PDCLK_DISSET_3 BSP_FLD32(3)
+#define TMS570_PMM_PDCLKDISSETREG_PDCLK_DISSET_3 BSP_BIT32(3)
 
 /* field: PDCLK_DISSET_2 - Privileged Mode only. */
-#define TMS570_PMM_PDCLKDISSETREG_PDCLK_DISSET_2 BSP_FLD32(2)
+#define TMS570_PMM_PDCLKDISSETREG_PDCLK_DISSET_2 BSP_BIT32(2)
 
 /* field: PDCLK_DISSET_1 - Read in User and Privileged Mode returns the current value of PDCLK_DISSET[1]. */
-#define TMS570_PMM_PDCLKDISSETREG_PDCLK_DISSET_1 BSP_FLD32(1)
+#define TMS570_PMM_PDCLKDISSETREG_PDCLK_DISSET_1 BSP_BIT32(1)
 
 /* field: PDCLK_DISSET_0 - Read in User and Privileged Mode returns the current value of PDCLK_DISSET[0]. */
-#define TMS570_PMM_PDCLKDISSETREG_PDCLK_DISSET_0 BSP_FLD32(0)
+#define TMS570_PMM_PDCLKDISSETREG_PDCLK_DISSET_0 BSP_BIT32(0)
 
 
-/*------------------TMS570_PMMPDCLKDISCLRREG------------------*/
+/*-----------------TMS570_PMM_PDCLKDISCLRREG-----------------*/
 /* field: PDCLK_DISCLR_3 - PDCLK_DISCLR[3] */
-#define TMS570_PMM_PDCLKDISCLRREG_PDCLK_DISCLR_3 BSP_FLD32(3)
+#define TMS570_PMM_PDCLKDISCLRREG_PDCLK_DISCLR_3 BSP_BIT32(3)
 
 /* field: PDCLK_DISCLR_2 - Read in User and Privileged Mode returns the current value of PDCLK_DIS[2]. */
-#define TMS570_PMM_PDCLKDISCLRREG_PDCLK_DISCLR_2 BSP_FLD32(2)
+#define TMS570_PMM_PDCLKDISCLRREG_PDCLK_DISCLR_2 BSP_BIT32(2)
 
 /* field: PDCLK_DISCLR_1 - Read in User and Privileged Mode returns the current value of PDCLK_DIS[1]. */
-#define TMS570_PMM_PDCLKDISCLRREG_PDCLK_DISCLR_1 BSP_FLD32(1)
+#define TMS570_PMM_PDCLKDISCLRREG_PDCLK_DISCLR_1 BSP_BIT32(1)
 
 /* field: PDCLK_DISCLR_0 - Read in User and Privileged Mode returns the current value of PDCLK_DIS[0]. */
-#define TMS570_PMM_PDCLKDISCLRREG_PDCLK_DISCLR_0 BSP_FLD32(0)
+#define TMS570_PMM_PDCLKDISCLRREG_PDCLK_DISCLR_0 BSP_BIT32(0)
 
 
-/*------------------TMS570_PMMLOGICPDPWRSTAT------------------*/
+/*-----------------TMS570_PMM_LOGICPDPWRSTAT-----------------*/
 /* field: LOGIC_IN_TRANS0 - Logic in transition status for power domain PD2. */
-#define TMS570_PMM_LOGICPDPWRSTAT_LOGIC_IN_TRANS0 BSP_FLD32(24)
+#define TMS570_PMM_LOGICPDPWRSTAT_LOGIC_IN_TRANS0 BSP_BIT32(24)
 
 /* field: MEM_IN_TRANS0 - Memory in transition status for power domain PD2. */
-#define TMS570_PMM_LOGICPDPWRSTAT_MEM_IN_TRANS0 BSP_FLD32(16)
+#define TMS570_PMM_LOGICPDPWRSTAT_MEM_IN_TRANS0 BSP_BIT32(16)
 
 /* field: DOMAIN_ON0 - Current state of power domain PD2. */
-#define TMS570_PMM_LOGICPDPWRSTAT_DOMAIN_ON0 BSP_FLD32(8)
+#define TMS570_PMM_LOGICPDPWRSTAT_DOMAIN_ON0 BSP_BIT32(8)
 
 /* field: LOGICPDPWR_STAT0 - Logic power domain PD2 power state. */
 #define TMS570_PMM_LOGICPDPWRSTAT_LOGICPDPWR_STAT0(val) BSP_FLD32(val,0, 1)
@@ -163,15 +163,15 @@ typedef struct{
 #define TMS570_PMM_LOGICPDPWRSTAT_LOGICPDPWR_STAT0_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
 
 
-/*-------------------TMS570_PMMMEMPDPWRSTAT-------------------*/
+/*------------------TMS570_PMM_MEMPDPWRSTAT------------------*/
 /* field: LOGIC_IN_TRANS0 - Logic in transition status for power domain RAM_PD1. */
-#define TMS570_PMM_MEMPDPWRSTAT_LOGIC_IN_TRANS0 BSP_FLD32(24)
+#define TMS570_PMM_MEMPDPWRSTAT_LOGIC_IN_TRANS0 BSP_BIT32(24)
 
 /* field: MEM_IN_TRANS0 - Memory in transition status for power domain RAM_PD1. */
-#define TMS570_PMM_MEMPDPWRSTAT_MEM_IN_TRANS0 BSP_FLD32(16)
+#define TMS570_PMM_MEMPDPWRSTAT_MEM_IN_TRANS0 BSP_BIT32(16)
 
 /* field: DOMAIN_ON0 - Current state of power domain RAM_PD1. */
-#define TMS570_PMM_MEMPDPWRSTAT_DOMAIN_ON0 BSP_FLD32(8)
+#define TMS570_PMM_MEMPDPWRSTAT_DOMAIN_ON0 BSP_BIT32(8)
 
 /* field: MEMPDPWR_STAT0 - Memory power domain RAM_PD1 power state. */
 #define TMS570_PMM_MEMPDPWRSTAT_MEMPDPWR_STAT0(val) BSP_FLD32(val,0, 1)
@@ -179,27 +179,27 @@ typedef struct{
 #define TMS570_PMM_MEMPDPWRSTAT_MEMPDPWR_STAT0_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
 
 
-/*-------------------TMS570_PMMGLOBALCTRL1-------------------*/
+/*-------------------TMS570_PMM_GLOBALCTRL1-------------------*/
 /* field: PMCTRL_PWRDN - PMC/PSCON Power Down */
-#define TMS570_PMM_GLOBALCTRL1_PMCTRL_PWRDN BSP_FLD32(8)
+#define TMS570_PMM_GLOBALCTRL1_PMCTRL_PWRDN BSP_BIT32(8)
 
 /* field: AUTO_CLK_WAKE_ENA - Automatic Clock Enable on Wake Up */
-#define TMS570_PMM_GLOBALCTRL1_AUTO_CLK_WAKE_ENA BSP_FLD32(0)
+#define TMS570_PMM_GLOBALCTRL1_AUTO_CLK_WAKE_ENA BSP_BIT32(0)
 
 
-/*--------------------TMS570_PMMGLOBALSTAT--------------------*/
+/*-------------------TMS570_PMM_GLOBALSTAT-------------------*/
 /* field: PMCTRL_IDLE - State of PMC and all PSCONs. */
-#define TMS570_PMM_GLOBALSTAT_PMCTRL_IDLE BSP_FLD32(0)
+#define TMS570_PMM_GLOBALSTAT_PMCTRL_IDLE BSP_BIT32(0)
 
 
-/*--------------------TMS570_PMMPRCKEYREG--------------------*/
+/*--------------------TMS570_PMM_PRCKEYREG--------------------*/
 /* field: MKEY - Diagnostic PSCON Mode Key. The mode key is applied to all individual PSCON compare units. */
 #define TMS570_PMM_PRCKEYREG_MKEY(val) BSP_FLD32(val,0, 3)
 #define TMS570_PMM_PRCKEYREG_MKEY_GET(reg) BSP_FLD32GET(reg,0, 3)
 #define TMS570_PMM_PRCKEYREG_MKEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*--------------------TMS570_PMMLPDDCSTAT1--------------------*/
+/*-------------------TMS570_PMM_LPDDCSTAT1-------------------*/
 /* field: LCMPE - Logic Power Domain Compare Error */
 #define TMS570_PMM_LPDDCSTAT1_LCMPE(val) BSP_FLD32(val,16, 19)
 #define TMS570_PMM_LPDDCSTAT1_LCMPE_GET(reg) BSP_FLD32GET(reg,16, 19)
@@ -211,7 +211,7 @@ typedef struct{
 #define TMS570_PMM_LPDDCSTAT1_LSTC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*--------------------TMS570_PMMLPDDCSTAT2--------------------*/
+/*-------------------TMS570_PMM_LPDDCSTAT2-------------------*/
 /* field: LSTET - Logic Power Domain Self-test Error Type */
 #define TMS570_PMM_LPDDCSTAT2_LSTET(val) BSP_FLD32(val,16, 19)
 #define TMS570_PMM_LPDDCSTAT2_LSTET_GET(reg) BSP_FLD32GET(reg,16, 19)
@@ -223,7 +223,7 @@ typedef struct{
 #define TMS570_PMM_LPDDCSTAT2_LSTE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*--------------------TMS570_PMMMPDDCSTAT1--------------------*/
+/*-------------------TMS570_PMM_MPDDCSTAT1-------------------*/
 /* field: MCMPE - Memory Power Domain Compare Error */
 #define TMS570_PMM_MPDDCSTAT1_MCMPE(val) BSP_FLD32(val,16, 18)
 #define TMS570_PMM_MPDDCSTAT1_MCMPE_GET(reg) BSP_FLD32GET(reg,16, 18)
@@ -235,7 +235,7 @@ typedef struct{
 #define TMS570_PMM_MPDDCSTAT1_MSTC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
 
 
-/*--------------------TMS570_PMMMPDDCSTAT2--------------------*/
+/*-------------------TMS570_PMM_MPDDCSTAT2-------------------*/
 /* field: MSTET - Memory Power Domain Self-test Error Type */
 #define TMS570_PMM_MPDDCSTAT2_MSTET(val) BSP_FLD32(val,16, 18)
 #define TMS570_PMM_MPDDCSTAT2_MSTET_GET(reg) BSP_FLD32GET(reg,16, 18)
@@ -247,7 +247,7 @@ typedef struct{
 #define TMS570_PMM_MPDDCSTAT2_MSTE_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
 
 
-/*-------------------TMS570_PMMISODIAGSTAT-------------------*/
+/*-------------------TMS570_PMM_ISODIAGSTAT-------------------*/
 /* field: ISO_DIAG - Isolation Diagnostic */
 #define TMS570_PMM_ISODIAGSTAT_ISO_DIAG(val) BSP_FLD32(val,0, 3)
 #define TMS570_PMM_ISODIAGSTAT_ISO_DIAG_GET(reg) BSP_FLD32GET(reg,0, 3)
@@ -255,4 +255,4 @@ typedef struct{
 
 
 
-#endif /* LIBBSP_ARM_tms570_PMM */
+#endif /* LIBBSP_ARM_TMS570_PMM */

c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pom.h

@@ -36,8 +36,8 @@
  * of the authors and should not be interpreted as representing official policies,
  * either expressed or implied, of the FreeBSD Project.
 */
-#ifndef LIBBSP_ARM_tms570_POM
+#ifndef LIBBSP_ARM_TMS570_POM
-#define LIBBSP_ARM_tms570_POM
+#define LIBBSP_ARM_TMS570_POM
 
 #include <bsp/utility.h>
 
@@ -82,28 +82,28 @@ typedef struct{
 } tms570_pom_t;
 
 
-/*--------------------TMS570_POMPROGSTART--------------------*/
+/*--------------------TMS570_POM_PROGSTART--------------------*/
 /* field: STARTADDRESS - Defines the start address of the program memory region. */
 #define TMS570_POM_PROGSTART_STARTADDRESS(val) BSP_FLD32(val,0, 22)
 #define TMS570_POM_PROGSTART_STARTADDRESS_GET(reg) BSP_FLD32GET(reg,0, 22)
 #define TMS570_POM_PROGSTART_STARTADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,0, 22)
 
 
-/*---------------------TMS570_POMOVLSTART---------------------*/
+/*--------------------TMS570_POM_OVLSTART--------------------*/
 /* field: STARTADDRESS - Defines the start address of the overlay memory region. */
 #define TMS570_POM_OVLSTART_STARTADDRESS(val) BSP_FLD32(val,0, 22)
 #define TMS570_POM_OVLSTART_STARTADDRESS_GET(reg) BSP_FLD32GET(reg,0, 22)
 #define TMS570_POM_OVLSTART_STARTADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,0, 22)
 
 
-/*---------------------TMS570_POMREGSIZE---------------------*/
+/*---------------------TMS570_POM_REGSIZE---------------------*/
 /* field: SIZE - Region size */
 #define TMS570_POM_REGSIZE_SIZE(val) BSP_FLD32(val,0, 3)
 #define TMS570_POM_REGSIZE_SIZE_GET(reg) BSP_FLD32GET(reg,0, 3)
 #define TMS570_POM_REGSIZE_SIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*---------------------TMS570_POMGLBCTRL---------------------*/
+/*---------------------TMS570_POM_GLBCTRL---------------------*/
 /* field: OTADDR - Overlay target Address. */
 #define TMS570_POM_GLBCTRL_OTADDR(val) BSP_FLD32(val,23, 31)
 #define TMS570_POM_GLBCTRL_OTADDR_GET(reg) BSP_FLD32GET(reg,23, 31)
@@ -120,7 +120,7 @@ typedef struct{
 #define TMS570_POM_GLBCTRL_ON_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*-----------------------TMS570_POMREV-----------------------*/
+/*-----------------------TMS570_POM_REV-----------------------*/
 /* field: SCHEME - Used to distinguish between different ID schemes. */
 #define TMS570_POM_REV_SCHEME(val) BSP_FLD32(val,30, 31)
 #define TMS570_POM_REV_SCHEME_GET(reg) BSP_FLD32GET(reg,30, 31)
@@ -152,68 +152,53 @@ typedef struct{
 #define TMS570_POM_REV_5_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
 
 
-/*---------------------TMS570_POMCLKCTRL---------------------*/
+/*---------------------TMS570_POM_CLKCTRL---------------------*/
 /* field: CLK_GATE_OFF - Do not modify this bit. Leave it in its reset state. */
-#define TMS570_POM_CLKCTRL_CLK_GATE_OFF BSP_FLD32(0)
+#define TMS570_POM_CLKCTRL_CLK_GATE_OFF BSP_BIT32(0)
 
 
-/*-----------------------TMS570_POMFLG-----------------------*/
+/*-----------------------TMS570_POM_FLG-----------------------*/
 /* field: TO - Timeout. */
-#define TMS570_POM_FLG_TO BSP_FLD32(0)
+#define TMS570_POM_FLG_TO BSP_BIT32(0)
 
 
-/*----------------------TMS570_POMITCTRL----------------------*/
+/*---------------------TMS570_POM_ITCTRL---------------------*/
 /* field: Reserved - Read returns 0. Writes have no effect. */
-#define TMS570_POM_ITCTRL_Reserved(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_POM_ITCTRL_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_POM_ITCTRL_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*--------------------TMS570_POM_CLAIMSET--------------------*/
-/*---------------------TMS570_POMCLAIMSET---------------------*/
 /* field: SET1 - The module is claimed */
-#define TMS570_POM_CLAIMSET_SET1 BSP_FLD32(1)
+#define TMS570_POM_CLAIMSET_SET1 BSP_BIT32(1)
 
 /* field: SET0 - The module is claimed */
-#define TMS570_POM_CLAIMSET_SET0 BSP_FLD32(0)
+#define TMS570_POM_CLAIMSET_SET0 BSP_BIT32(0)
 
 
-/*---------------------TMS570_POMCLAIMCLR---------------------*/
+/*--------------------TMS570_POM_CLAIMCLR--------------------*/
 /* field: CLR1 - The module is claimed */
-#define TMS570_POM_CLAIMCLR_CLR1 BSP_FLD32(1)
+#define TMS570_POM_CLAIMCLR_CLR1 BSP_BIT32(1)
 
 /* field: CLR0 - The module is claimed */
-#define TMS570_POM_CLAIMCLR_CLR0 BSP_FLD32(0)
+#define TMS570_POM_CLAIMCLR_CLR0 BSP_BIT32(0)
 
 
-/*--------------------TMS570_POMLOCKACCESS--------------------*/
+/*-------------------TMS570_POM_LOCKACCESS-------------------*/
 /* field: Reserved - Read returns 0. Writes have no effect. */
-#define TMS570_POM_LOCKACCESS_Reserved(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_POM_LOCKACCESS_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_POM_LOCKACCESS_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_POM_LOCKSTATUS-------------------*/
-/*--------------------TMS570_POMLOCKSTATUS--------------------*/
 /* field: Reserved - Read returns 0. Writes have no effect. */
-#define TMS570_POM_LOCKSTATUS_Reserved(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_POM_LOCKSTATUS_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_POM_LOCKSTATUS_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_POM_AUTHSTATUS-------------------*/
-/*--------------------TMS570_POMAUTHSTATUS--------------------*/
 /* field: Reserved - Read returns 0. Writes have no effect. */
-#define TMS570_POM_AUTHSTATUS_Reserved(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_POM_AUTHSTATUS_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_POM_AUTHSTATUS_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*----------------------TMS570_POM_DEVID----------------------*/
-/*----------------------TMS570_POMDEVID----------------------*/
 /* field: Reserved - Read returns 0. Writes have no effect. */
-#define TMS570_POM_DEVID_Reserved(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_POM_DEVID_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_POM_DEVID_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*---------------------TMS570_POM_DEVTYPE---------------------*/
-/*---------------------TMS570_POMDEVTYPE---------------------*/
 /* field: Sub_Type - Other */
 #define TMS570_POM_DEVTYPE_Sub_Type(val) BSP_FLD32(val,4, 7)
 #define TMS570_POM_DEVTYPE_Sub_Type_GET(reg) BSP_FLD32GET(reg,4, 7)
@@ -225,7 +210,7 @@ typedef struct{
 #define TMS570_POM_DEVTYPE_Major_Type_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*------------------TMS570_POMPERIPHERALID4------------------*/
+/*------------------TMS570_POM_PERIPHERALID4------------------*/
 /* field: 4KB_Count - Only 4KB implemented */
 #define TMS570_POM_PERIPHERALID4_4KB_Count(val) BSP_FLD32(val,4, 7)
 #define TMS570_POM_PERIPHERALID4_4KB_Count_GET(reg) BSP_FLD32GET(reg,4, 7)
@@ -237,35 +222,26 @@ typedef struct{
 #define TMS570_POM_PERIPHERALID4_JEP_Continuation_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*------------------TMS570_POMPERIPHERALID5------------------*/
+/*------------------TMS570_POM_PERIPHERALID5------------------*/
 /* field: Reserved - Read returns 0. Writes have no effect. */
-#define TMS570_POM_PERIPHERALID5_Reserved(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_POM_PERIPHERALID5_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_POM_PERIPHERALID5_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_POM_PERIPHERALID6------------------*/
-/*------------------TMS570_POMPERIPHERALID6------------------*/
 /* field: Reserved - Read returns 0. Writes have no effect. */
-#define TMS570_POM_PERIPHERALID6_Reserved(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_POM_PERIPHERALID6_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_POM_PERIPHERALID6_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_POM_PERIPHERALID7------------------*/
-/*------------------TMS570_POMPERIPHERALID7------------------*/
 /* field: Reserved - Read returns 0. Writes have no effect. */
-#define TMS570_POM_PERIPHERALID7_Reserved(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_POM_PERIPHERALID7_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_POM_PERIPHERALID7_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_POM_PERIPHERALID0------------------*/
-/*------------------TMS570_POMPERIPHERALID0------------------*/
 /* field: Part_Number - Reads 0, since POMREV defines the module */
 #define TMS570_POM_PERIPHERALID0_Part_Number(val) BSP_FLD32(val,0, 7)
 #define TMS570_POM_PERIPHERALID0_Part_Number_GET(reg) BSP_FLD32GET(reg,0, 7)
 #define TMS570_POM_PERIPHERALID0_Part_Number_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*------------------TMS570_POMPERIPHERALID1------------------*/
+/*------------------TMS570_POM_PERIPHERALID1------------------*/
 /* field: JEP106_Identity - Part of TI JEDEC number */
 #define TMS570_POM_PERIPHERALID1_JEP106_Identity(val) BSP_FLD32(val,4, 7)
 #define TMS570_POM_PERIPHERALID1_JEP106_Identity_GET(reg) BSP_FLD32GET(reg,4, 7)
@@ -277,14 +253,14 @@ typedef struct{
 #define TMS570_POM_PERIPHERALID1_Part_Number_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*------------------TMS570_POMPERIPHERALID2------------------*/
+/*------------------TMS570_POM_PERIPHERALID2------------------*/
 /* field: Revision - Reads 0, since POMREV defines the module */
 #define TMS570_POM_PERIPHERALID2_Revision(val) BSP_FLD32(val,4, 7)
 #define TMS570_POM_PERIPHERALID2_Revision_GET(reg) BSP_FLD32GET(reg,4, 7)
 #define TMS570_POM_PERIPHERALID2_Revision_SET(reg,val) BSP_FLD32SET(reg, val,4, 7)
 
 /* field: JEDEC - Indicates JEDEC assigned value */
-#define TMS570_POM_PERIPHERALID2_JEDEC BSP_FLD32(3)
+#define TMS570_POM_PERIPHERALID2_JEDEC BSP_BIT32(3)
 
 /* field: JEP106_Identity - JEDEC+JEP106 Identity Code (POMPERIPHERALID2)+JEP106 Identity Code */
 #define TMS570_POM_PERIPHERALID2_JEP106_Identity(val) BSP_FLD32(val,0, 2)
@@ -292,21 +268,18 @@ typedef struct{
 #define TMS570_POM_PERIPHERALID2_JEP106_Identity_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
 
 
-/*------------------TMS570_POMPERIPHERALID3------------------*/
+/*------------------TMS570_POM_PERIPHERALID3------------------*/
 /* field: Reserved - Read returns 0. Writes have no effect. */
-#define TMS570_POM_PERIPHERALID3_Reserved(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_POM_PERIPHERALID3_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_POM_PERIPHERALID3_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_POM_COMPONENTID0------------------*/
-/*-------------------TMS570_POMCOMPONENTID0-------------------*/
 /* field: Preamble - Preamble */
 #define TMS570_POM_COMPONENTID0_Preamble(val) BSP_FLD32(val,0, 7)
 #define TMS570_POM_COMPONENTID0_Preamble_GET(reg) BSP_FLD32GET(reg,0, 7)
 #define TMS570_POM_COMPONENTID0_Preamble_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*-------------------TMS570_POMCOMPONENTID1-------------------*/
+/*------------------TMS570_POM_COMPONENTID1------------------*/
 /* field: Component_Class - CoreSight Component */
 #define TMS570_POM_COMPONENTID1_Component_Class(val) BSP_FLD32(val,4, 7)
 #define TMS570_POM_COMPONENTID1_Component_Class_GET(reg) BSP_FLD32GET(reg,4, 7)
@@ -318,14 +291,14 @@ typedef struct{
 #define TMS570_POM_COMPONENTID1_Preamble_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*-------------------TMS570_POMCOMPONENTID2-------------------*/
+/*------------------TMS570_POM_COMPONENTID2------------------*/
 /* field: Preamble - Preamble */
 #define TMS570_POM_COMPONENTID2_Preamble(val) BSP_FLD32(val,0, 7)
 #define TMS570_POM_COMPONENTID2_Preamble_GET(reg) BSP_FLD32GET(reg,0, 7)
 #define TMS570_POM_COMPONENTID2_Preamble_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*-------------------TMS570_POMCOMPONENTID3-------------------*/
+/*------------------TMS570_POM_COMPONENTID3------------------*/
 /* field: Preamble - Preamble */
 #define TMS570_POM_COMPONENTID3_Preamble(val) BSP_FLD32(val,0, 7)
 #define TMS570_POM_COMPONENTID3_Preamble_GET(reg) BSP_FLD32GET(reg,0, 7)
@@ -333,4 +306,4 @@ typedef struct{
 
 
 
-#endif /* LIBBSP_ARM_tms570_POM */
+#endif /* LIBBSP_ARM_TMS570_POM */

c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_rti.h

@@ -36,8 +36,8 @@
  * of the authors and should not be interpreted as representing official policies,
  * either expressed or implied, of the FreeBSD Project.
 */
-#ifndef LIBBSP_ARM_tms570_RTI
+#ifndef LIBBSP_ARM_TMS570_RTI
-#define LIBBSP_ARM_tms570_RTI
+#define LIBBSP_ARM_TMS570_RTI
 
 #include <bsp/utility.h>
 
@@ -85,275 +85,239 @@ typedef struct{
 } tms570_rti_t;
 
 
-/*----------------------TMS570_RTICOMPx----------------------*/
+/*----------------------TMS570_RTI_COMPx----------------------*/
 /* field: COMPx - Compare x. */
-#define TMS570_RTI_COMPx_COMPx(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_RTI_COMPx_COMPx_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_RTI_COMPx_COMPx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*----------------------TMS570_RTI_UDCPx----------------------*/
-/*----------------------TMS570_RTIUDCPx----------------------*/
 /* field: UDCPx - Update compare x. */
-#define TMS570_RTI_UDCPx_UDCPx(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_RTI_UDCPx_UDCPx_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_RTI_UDCPx_UDCPx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*----------------------TMS570_RTI_FRCx----------------------*/
-/*-----------------------TMS570_RTIFRCx-----------------------*/
 /* field: FRC0 - FRC0 */
-#define TMS570_RTI_FRCx_FRC0(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_RTI_FRCx_FRC0_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_RTI_FRCx_FRC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-----------------------TMS570_RTI_UCx-----------------------*/
-/*-----------------------TMS570_RTIUCx-----------------------*/
 /* field: UC0 - Up counter 0. */
-#define TMS570_RTI_UCx_UC0(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_RTI_UCx_UC0_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_RTI_UCx_UC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*----------------------TMS570_RTI_CPUCx----------------------*/
-/*----------------------TMS570_RTICPUCx----------------------*/
 /* field: CPUC0 - Compare up counter 0. This register holds the value that is compared with the up counter 0. */
-#define TMS570_RTI_CPUCx_CPUC0(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_RTI_CPUCx_CPUC0_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_RTI_CPUCx_CPUC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*---------------------TMS570_RTI_CAFRCx---------------------*/
-/*----------------------TMS570_RTICAFRCx----------------------*/
 /* field: CAFRC0 - Capture free running counter 0. */
-#define TMS570_RTI_CAFRCx_CAFRC0(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_RTI_CAFRCx_CAFRC0_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_RTI_CAFRCx_CAFRC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*----------------------TMS570_RTI_CAUCx----------------------*/
-/*----------------------TMS570_RTICAUCx----------------------*/
 /* field: CAUC0 - Capture up counter 0. */
-#define TMS570_RTI_CAUCx_CAUC0(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_RTI_CAUCx_CAUC0_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_RTI_CAUCx_CAUC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*----------------------TMS570_RTI_rsvd----------------------*/
-/*-----------------------TMS570_RTIrsvd-----------------------*/
 /* field: CAUC0 - Capture up counter 0. */
-#define TMS570_RTI_rsvd_CAUC0(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_RTI_rsvd_CAUC0_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_RTI_rsvd_CAUC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*----------------------TMS570_RTI_GCTRL----------------------*/
-/*----------------------TMS570_RTIGCTRL----------------------*/
 /* field: NTUSEL - Select NTU signal. */
 #define TMS570_RTI_GCTRL_NTUSEL(val) BSP_FLD32(val,16, 19)
 #define TMS570_RTI_GCTRL_NTUSEL_GET(reg) BSP_FLD32GET(reg,16, 19)
 #define TMS570_RTI_GCTRL_NTUSEL_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
 
 /* field: COS - Continue on suspend. */
-#define TMS570_RTI_GCTRL_COS BSP_FLD32(15)
+#define TMS570_RTI_GCTRL_COS BSP_BIT32(15)
 
 /* field: CNT1EN - Counter 1 enable. This bit starts and stops counter block 1 (RTIUC1 and RTIFRC1). */
-#define TMS570_RTI_GCTRL_CNT1EN BSP_FLD32(1)
+#define TMS570_RTI_GCTRL_CNT1EN BSP_BIT32(1)
 
 /* field: CNT0EN - Counter 0 enable. This bit starts and stops counter block 0 (RTIUC0 and RTIFRC0). */
-#define TMS570_RTI_GCTRL_CNT0EN BSP_FLD32(0)
+#define TMS570_RTI_GCTRL_CNT0EN BSP_BIT32(0)
 
 
-/*----------------------TMS570_RTITBCTRL----------------------*/
+/*---------------------TMS570_RTI_TBCTRL---------------------*/
 /* field: INC - Increment free running counter 0. */
-#define TMS570_RTI_TBCTRL_INC BSP_FLD32(1)
+#define TMS570_RTI_TBCTRL_INC BSP_BIT32(1)
 
 /* field: TBEXT - Timebase external. */
-#define TMS570_RTI_TBCTRL_TBEXT BSP_FLD32(0)
+#define TMS570_RTI_TBCTRL_TBEXT BSP_BIT32(0)
 
 
-/*---------------------TMS570_RTICAPCTRL---------------------*/
+/*---------------------TMS570_RTI_CAPCTRL---------------------*/
 /* field: CAPCNTR1 - Capture counter 1. */
-#define TMS570_RTI_CAPCTRL_CAPCNTR1 BSP_FLD32(1)
+#define TMS570_RTI_CAPCTRL_CAPCNTR1 BSP_BIT32(1)
 
 /* field: CAPCNTR0 - Capture counter 0. */
-#define TMS570_RTI_CAPCTRL_CAPCNTR0 BSP_FLD32(0)
+#define TMS570_RTI_CAPCTRL_CAPCNTR0 BSP_BIT32(0)
 
 
-/*---------------------TMS570_RTICOMPCTRL---------------------*/
+/*--------------------TMS570_RTI_COMPCTRL--------------------*/
 /* field: COMPSEL3 - Compare select 3. */
-#define TMS570_RTI_COMPCTRL_COMPSEL3 BSP_FLD32(12)
+#define TMS570_RTI_COMPCTRL_COMPSEL3 BSP_BIT32(12)
 
 /* field: COMPSEL2 - Compare select 2. */
-#define TMS570_RTI_COMPCTRL_COMPSEL2 BSP_FLD32(8)
+#define TMS570_RTI_COMPCTRL_COMPSEL2 BSP_BIT32(8)
 
 /* field: COMPSEL1 - Compare select 1. */
-#define TMS570_RTI_COMPCTRL_COMPSEL1 BSP_FLD32(4)
+#define TMS570_RTI_COMPCTRL_COMPSEL1 BSP_BIT32(4)
 
 /* field: COMPSEL0 - Compare select 0. */
-#define TMS570_RTI_COMPCTRL_COMPSEL0 BSP_FLD32(0)
+#define TMS570_RTI_COMPCTRL_COMPSEL0 BSP_BIT32(0)
 
 
-/*---------------------TMS570_RTITBLCOMP---------------------*/
+/*---------------------TMS570_RTI_TBLCOMP---------------------*/
 /* field: TBLCOMP - Timebase low compare value. */
-#define TMS570_RTI_TBLCOMP_TBLCOMP(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_RTI_TBLCOMP_TBLCOMP_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_RTI_TBLCOMP_TBLCOMP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*---------------------TMS570_RTI_TBHCOMP---------------------*/
-/*---------------------TMS570_RTITBHCOMP---------------------*/
 /* field: TBHCOMP - Timebase high compare value. */
-#define TMS570_RTI_TBHCOMP_TBHCOMP(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_RTI_TBHCOMP_TBHCOMP_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_RTI_TBHCOMP_TBHCOMP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*--------------------TMS570_RTI_SETINTENA--------------------*/
-/*--------------------TMS570_RTISETINTENA--------------------*/
 /* field: SETOVL1INT - Set free running counter 1 overflow interrupt. */
-#define TMS570_RTI_SETINTENA_SETOVL1INT BSP_FLD32(18)
+#define TMS570_RTI_SETINTENA_SETOVL1INT BSP_BIT32(18)
 
 /* field: SETOVL0INT - Set free running counter 0 overflow interrupt. */
-#define TMS570_RTI_SETINTENA_SETOVL0INT BSP_FLD32(17)
+#define TMS570_RTI_SETINTENA_SETOVL0INT BSP_BIT32(17)
 
 /* field: SETTBINT - Set timebase interrupt. */
-#define TMS570_RTI_SETINTENA_SETTBINT BSP_FLD32(16)
+#define TMS570_RTI_SETINTENA_SETTBINT BSP_BIT32(16)
 
 /* field: SETDMA3 - Set compare DMA request 3. */
-#define TMS570_RTI_SETINTENA_SETDMA3 BSP_FLD32(11)
+#define TMS570_RTI_SETINTENA_SETDMA3 BSP_BIT32(11)
 
 /* field: SETDMA2 - Set compare DMA request 2. */
-#define TMS570_RTI_SETINTENA_SETDMA2 BSP_FLD32(10)
+#define TMS570_RTI_SETINTENA_SETDMA2 BSP_BIT32(10)
 
 /* field: SETDMA1 - Set compare DMA request 1. */
-#define TMS570_RTI_SETINTENA_SETDMA1 BSP_FLD32(9)
+#define TMS570_RTI_SETINTENA_SETDMA1 BSP_BIT32(9)
 
 /* field: SETDMA0 - Set compare DMA request 0. */
-#define TMS570_RTI_SETINTENA_SETDMA0 BSP_FLD32(8)
+#define TMS570_RTI_SETINTENA_SETDMA0 BSP_BIT32(8)
 
 /* field: SETINT3 - Set compare interrupt 3. */
-#define TMS570_RTI_SETINTENA_SETINT3 BSP_FLD32(3)
+#define TMS570_RTI_SETINTENA_SETINT3 BSP_BIT32(3)
 
 /* field: SETINT2 - Set compare interrupt 2. */
-#define TMS570_RTI_SETINTENA_SETINT2 BSP_FLD32(2)
+#define TMS570_RTI_SETINTENA_SETINT2 BSP_BIT32(2)
 
 /* field: SETINT1 - Set compare interrupt 1. */
-#define TMS570_RTI_SETINTENA_SETINT1 BSP_FLD32(1)
+#define TMS570_RTI_SETINTENA_SETINT1 BSP_BIT32(1)
 
 /* field: SETINT0 - Set compare interrupt 0. */
-#define TMS570_RTI_SETINTENA_SETINT0 BSP_FLD32(0)
+#define TMS570_RTI_SETINTENA_SETINT0 BSP_BIT32(0)
 
 
-/*-------------------TMS570_RTICLEARINTENA-------------------*/
+/*-------------------TMS570_RTI_CLEARINTENA-------------------*/
 /* field: CLEAROVL1INT - Clear free running counter 1 overflow interrupt. */
-#define TMS570_RTI_CLEARINTENA_CLEAROVL1INT BSP_FLD32(18)
+#define TMS570_RTI_CLEARINTENA_CLEAROVL1INT BSP_BIT32(18)
 
 /* field: CLEAROVL0INT - Clear free running counter 0 overflow interrupt. */
-#define TMS570_RTI_CLEARINTENA_CLEAROVL0INT BSP_FLD32(17)
+#define TMS570_RTI_CLEARINTENA_CLEAROVL0INT BSP_BIT32(17)
 
 /* field: CLEARTBINT - Clear timebase interrupt. */
-#define TMS570_RTI_CLEARINTENA_CLEARTBINT BSP_FLD32(16)
+#define TMS570_RTI_CLEARINTENA_CLEARTBINT BSP_BIT32(16)
 
 /* field: CLEARDMA3 - Clear compare DMA request 3. */
-#define TMS570_RTI_CLEARINTENA_CLEARDMA3 BSP_FLD32(11)
+#define TMS570_RTI_CLEARINTENA_CLEARDMA3 BSP_BIT32(11)
 
 /* field: CLEARDMA2 - Clear compare DMA request 2. */
-#define TMS570_RTI_CLEARINTENA_CLEARDMA2 BSP_FLD32(10)
+#define TMS570_RTI_CLEARINTENA_CLEARDMA2 BSP_BIT32(10)
 
 /* field: CLEARDMA1 - Clear compare DMA request 1. */
-#define TMS570_RTI_CLEARINTENA_CLEARDMA1 BSP_FLD32(9)
+#define TMS570_RTI_CLEARINTENA_CLEARDMA1 BSP_BIT32(9)
 
 /* field: CLEARDMA0 - Clear compare DMA request 0. */
-#define TMS570_RTI_CLEARINTENA_CLEARDMA0 BSP_FLD32(8)
+#define TMS570_RTI_CLEARINTENA_CLEARDMA0 BSP_BIT32(8)
 
 /* field: CLEARINT3 - Clear compare interrupt 3. */
-#define TMS570_RTI_CLEARINTENA_CLEARINT3 BSP_FLD32(3)
+#define TMS570_RTI_CLEARINTENA_CLEARINT3 BSP_BIT32(3)
 
 /* field: CLEARINT2 - Clear compare interrupt 2. */
-#define TMS570_RTI_CLEARINTENA_CLEARINT2 BSP_FLD32(2)
+#define TMS570_RTI_CLEARINTENA_CLEARINT2 BSP_BIT32(2)
 
 /* field: CLEARINT1 - Clear compare interrupt 1. */
-#define TMS570_RTI_CLEARINTENA_CLEARINT1 BSP_FLD32(1)
+#define TMS570_RTI_CLEARINTENA_CLEARINT1 BSP_BIT32(1)
 
 /* field: CLEARINT0 - Clear compare interrupt 0. */
-#define TMS570_RTI_CLEARINTENA_CLEARINT0 BSP_FLD32(0)
+#define TMS570_RTI_CLEARINTENA_CLEARINT0 BSP_BIT32(0)
 
 
-/*---------------------TMS570_RTIINTFLAG---------------------*/
+/*---------------------TMS570_RTI_INTFLAG---------------------*/
 /* field: OVL1INT - Free running counter 1 overflow interrupt flag. This bit determines if an interrupt is pending. */
-#define TMS570_RTI_INTFLAG_OVL1INT BSP_FLD32(18)
+#define TMS570_RTI_INTFLAG_OVL1INT BSP_BIT32(18)
 
 /* field: OVL0INT - Free running counter 0 overflow interrupt flag. This bit determines if an interrupt is pending. */
-#define TMS570_RTI_INTFLAG_OVL0INT BSP_FLD32(17)
+#define TMS570_RTI_INTFLAG_OVL0INT BSP_BIT32(17)
 
 /* field: TBINT - Timebase interrupt flag. */
-#define TMS570_RTI_INTFLAG_TBINT BSP_FLD32(16)
+#define TMS570_RTI_INTFLAG_TBINT BSP_BIT32(16)
 
 /* field: INT3 - Interrupt flag 3. These bits determine if an interrupt due to a Compare 3 match is pending. */
-#define TMS570_RTI_INTFLAG_INT3 BSP_FLD32(3)
+#define TMS570_RTI_INTFLAG_INT3 BSP_BIT32(3)
 
 /* field: INT2 - Interrupt flag 2. These bits determine if an interrupt due to a Compare 2 match is pending. */
-#define TMS570_RTI_INTFLAG_INT2 BSP_FLD32(2)
+#define TMS570_RTI_INTFLAG_INT2 BSP_BIT32(2)
 
 /* field: INT1 - Interrupt flag 1. These bits determine if an interrupt due to a Compare 1 match is pending. */
-#define TMS570_RTI_INTFLAG_INT1 BSP_FLD32(1)
+#define TMS570_RTI_INTFLAG_INT1 BSP_BIT32(1)
 
 /* field: INT0 - Interrupt flag 0. These bits determine if an interrupt due to a Compare 0 match is pending. */
-#define TMS570_RTI_INTFLAG_INT0 BSP_FLD32(0)
+#define TMS570_RTI_INTFLAG_INT0 BSP_BIT32(0)
 
 
-/*---------------------TMS570_RTIDWDCTRL---------------------*/
+/*---------------------TMS570_RTI_DWDCTRL---------------------*/
 /* field: DWDCTRL - DWDCTRL Digital Watchdog Control. */
-#define TMS570_RTI_DWDCTRL_DWDCTRL(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_RTI_DWDCTRL_DWDCTRL_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_RTI_DWDCTRL_DWDCTRL_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*---------------------TMS570_RTI_DWDPRLD---------------------*/
-/*---------------------TMS570_RTIDWDPRLD---------------------*/
 /* field: DWDPRLD - Digital Watchdog Preload Value. */
 #define TMS570_RTI_DWDPRLD_DWDPRLD(val) BSP_FLD32(val,0, 15)
 #define TMS570_RTI_DWDPRLD_DWDPRLD_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_RTI_DWDPRLD_DWDPRLD_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_RTIWDSTATUS---------------------*/
+/*--------------------TMS570_RTI_WDSTATUS--------------------*/
 /* field: DWWD_ST - Windowed Watchdog Status */
-#define TMS570_RTI_WDSTATUS_DWWD_ST BSP_FLD32(5)
+#define TMS570_RTI_WDSTATUS_DWWD_ST BSP_BIT32(5)
 
 /* field: END_TIME_VIOL - Windowed Watchdog End Time Violation Status. */
-#define TMS570_RTI_WDSTATUS_END_TIME_VIOL BSP_FLD32(4)
+#define TMS570_RTI_WDSTATUS_END_TIME_VIOL BSP_BIT32(4)
 
 /* field: START_TIME_VIOL - Windowed Watchdog Start Time Violation Status. */
-#define TMS570_RTI_WDSTATUS_START_TIME_VIOL BSP_FLD32(3)
+#define TMS570_RTI_WDSTATUS_START_TIME_VIOL BSP_BIT32(3)
 
 /* field: KEY_ST - Watchdog key status. */
-#define TMS570_RTI_WDSTATUS_KEY_ST BSP_FLD32(2)
+#define TMS570_RTI_WDSTATUS_KEY_ST BSP_BIT32(2)
 
 /* field: DWD_ST - DWD status. */
-#define TMS570_RTI_WDSTATUS_DWD_ST BSP_FLD32(1)
+#define TMS570_RTI_WDSTATUS_DWD_ST BSP_BIT32(1)
 
 
-/*----------------------TMS570_RTIWDKEY----------------------*/
+/*----------------------TMS570_RTI_WDKEY----------------------*/
 /* field: WDKEY - Watchdog key. These bits provide the key sequence location. */
 #define TMS570_RTI_WDKEY_WDKEY(val) BSP_FLD32(val,0, 15)
 #define TMS570_RTI_WDKEY_WDKEY_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_RTI_WDKEY_WDKEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_RTIDWDCNTR---------------------*/
+/*---------------------TMS570_RTI_DWDCNTR---------------------*/
 /* field: DWDCNTR - DWD down counter. */
 #define TMS570_RTI_DWDCNTR_DWDCNTR(val) BSP_FLD32(val,0, 24)
 #define TMS570_RTI_DWDCNTR_DWDCNTR_GET(reg) BSP_FLD32GET(reg,0, 24)
 #define TMS570_RTI_DWDCNTR_DWDCNTR_SET(reg,val) BSP_FLD32SET(reg, val,0, 24)
 
 
-/*--------------------TMS570_RTIWWDRXNCTRL--------------------*/
+/*-------------------TMS570_RTI_WWDRXNCTRL-------------------*/
 /* field: WWDRXN - The DWWD reaction */
 #define TMS570_RTI_WWDRXNCTRL_WWDRXN(val) BSP_FLD32(val,0, 3)
 #define TMS570_RTI_WWDRXNCTRL_WWDRXN_GET(reg) BSP_FLD32GET(reg,0, 3)
 #define TMS570_RTI_WWDRXNCTRL_WWDRXN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*-------------------TMS570_RTIWWDSIZECTRL-------------------*/
+/*-------------------TMS570_RTI_WWDSIZECTRL-------------------*/
 /* field: WWDSIZE - The DWWD window size */
-#define TMS570_RTI_WWDSIZECTRL_WWDSIZE(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_RTI_WWDSIZECTRL_WWDSIZE_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_RTI_WWDSIZECTRL_WWDSIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_RTI_INTCLRENABLE------------------*/
-/*-------------------TMS570_RTIINTCLRENABLE-------------------*/
 /* field: INTCLRENABLE3 - Enables the auto-clear functionality on the compare 3 interrupt. */
 #define TMS570_RTI_INTCLRENABLE_INTCLRENABLE3(val) BSP_FLD32(val,24, 27)
 #define TMS570_RTI_INTCLRENABLE_INTCLRENABLE3_GET(reg) BSP_FLD32GET(reg,24, 27)
@@ -375,33 +339,21 @@ typedef struct{
 #define TMS570_RTI_INTCLRENABLE_INTCLRENABLE0_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*---------------------TMS570_RTICOMP0CLR---------------------*/
+/*--------------------TMS570_RTI_COMP0CLR--------------------*/
 /* field: CMP0CLR - Compare 0 clear. */
-#define TMS570_RTI_COMP0CLR_CMP0CLR(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_RTI_COMP0CLR_CMP0CLR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_RTI_COMP0CLR_CMP0CLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*--------------------TMS570_RTI_COMP1CLR--------------------*/
-/*---------------------TMS570_RTICOMP1CLR---------------------*/
 /* field: CMP0CLR - Compare 1 clear. */
-#define TMS570_RTI_COMP1CLR_CMP0CLR(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_RTI_COMP1CLR_CMP0CLR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_RTI_COMP1CLR_CMP0CLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*--------------------TMS570_RTI_COMP2CLR--------------------*/
-/*---------------------TMS570_RTICOMP2CLR---------------------*/
 /* field: CMP2CLR - Compare 2 clear. */
-#define TMS570_RTI_COMP2CLR_CMP2CLR(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_RTI_COMP2CLR_CMP2CLR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_RTI_COMP2CLR_CMP2CLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*--------------------TMS570_RTI_COMP3CLR--------------------*/
-/*---------------------TMS570_RTICOMP3CLR---------------------*/
 /* field: CMP3CLR - Compare 3 clear. */
-#define TMS570_RTI_COMP3CLR_CMP3CLR(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_RTI_COMP3CLR_CMP3CLR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_RTI_COMP3CLR_CMP3CLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
 
-
+#endif /* LIBBSP_ARM_TMS570_RTI */
-#endif /* LIBBSP_ARM_tms570_RTI */

c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_rtp.h

@@ -36,8 +36,8 @@
  * of the authors and should not be interpreted as representing official policies,
  * either expressed or implied, of the FreeBSD Project.
 */
-#ifndef LIBBSP_ARM_tms570_RTP
+#ifndef LIBBSP_ARM_TMS570_RTP
-#define LIBBSP_ARM_tms570_RTP
+#define LIBBSP_ARM_TMS570_RTP
 
 #include <bsp/utility.h>
 
@@ -66,9 +66,9 @@ typedef struct{
 } tms570_rtp_t;
 
 
-/*---------------------TMS570_RTPGLBCTRL---------------------*/
+/*---------------------TMS570_RTP_GLBCTRL---------------------*/
 /* field: TEST - By setting the bit, the FIFO RAM will be mapped into the SYSTEM Peripheral frame starting at */
-#define TMS570_RTP_GLBCTRL_TEST BSP_FLD32(24)
+#define TMS570_RTP_GLBCTRL_TEST BSP_BIT32(24)
 
 /* field: PRESCALER - The prescaler divides HCLK down to the desired RTPCLK frequency. */
 #define TMS570_RTP_GLBCTRL_PRESCALER(val) BSP_FLD32(val,16, 18)
@@ -81,10 +81,10 @@ typedef struct{
 #define TMS570_RTP_GLBCTRL_DDM_WIDTH_SET(reg,val) BSP_FLD32SET(reg, val,12, 13)
 
 /* field: DDM_RW -  */
-#define TMS570_RTP_GLBCTRL_DDM_RW BSP_FLD32(11)
+#define TMS570_RTP_GLBCTRL_DDM_RW BSP_BIT32(11)
 
 /* field: TM_DDM - Trace Mode or Direct Data Mode */
-#define TMS570_RTP_GLBCTRL_TM_DDM BSP_FLD32(10)
+#define TMS570_RTP_GLBCTRL_TM_DDM BSP_BIT32(10)
 
 /* field: PW - Port width. This bit field configures the RTP to the desired port width. */
 #define TMS570_RTP_GLBCTRL_PW(val) BSP_FLD32(val,8, 9)
@@ -92,16 +92,16 @@ typedef struct{
 #define TMS570_RTP_GLBCTRL_PW_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
 
 /* field: RESET - This bit resets the state machine and the registers to their reset value. */
-#define TMS570_RTP_GLBCTRL_RESET BSP_FLD32(7)
+#define TMS570_RTP_GLBCTRL_RESET BSP_BIT32(7)
 
 /* field: CONTCLK - Continuous RTPCLK enable. */
-#define TMS570_RTP_GLBCTRL_CONTCLK BSP_FLD32(6)
+#define TMS570_RTP_GLBCTRL_CONTCLK BSP_BIT32(6)
 
 /* field: HOVF - Halt on overflow. */
-#define TMS570_RTP_GLBCTRL_HOVF BSP_FLD32(5)
+#define TMS570_RTP_GLBCTRL_HOVF BSP_BIT32(5)
 
 /* field: INV_RGN - Trace inside or outside of defined trace regions. */
-#define TMS570_RTP_GLBCTRL_INV_RGN BSP_FLD32(4)
+#define TMS570_RTP_GLBCTRL_INV_RGN BSP_BIT32(4)
 
 /* field: ON_OFF - ON/Off switch. */
 #define TMS570_RTP_GLBCTRL_ON_OFF(val) BSP_FLD32(val,0, 3)
@@ -109,122 +109,119 @@ typedef struct{
 #define TMS570_RTP_GLBCTRL_ON_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*----------------------TMS570_RTPTRENA----------------------*/
+/*----------------------TMS570_RTP_TRENA----------------------*/
 /* field: ENA4 - Enable tracing for peripherals. */
-#define TMS570_RTP_TRENA_ENA4 BSP_FLD32(24)
+#define TMS570_RTP_TRENA_ENA4 BSP_BIT32(24)
 
 /* field: ENA2 - Enable tracing for RAM block 2. */
-#define TMS570_RTP_TRENA_ENA2 BSP_FLD32(8)
+#define TMS570_RTP_TRENA_ENA2 BSP_BIT32(8)
 
 /* field: ENA1 -  */
-#define TMS570_RTP_TRENA_ENA1 BSP_FLD32(0)
+#define TMS570_RTP_TRENA_ENA1 BSP_BIT32(0)
 
 
-/*-----------------------TMS570_RTPGSR-----------------------*/
+/*-----------------------TMS570_RTP_GSR-----------------------*/
 /* field: EMPTYSER - Serializer empty. This bit determines if there is data left in the serializer. */
-#define TMS570_RTP_GSR_EMPTYSER BSP_FLD32(12)
+#define TMS570_RTP_GSR_EMPTYSER BSP_BIT32(12)
 
 /* field: EMPTYPER - Peripheral FIFO empty. This bit determines if there are entries left in the FIFO. */
-#define TMS570_RTP_GSR_EMPTYPER BSP_FLD32(11)
+#define TMS570_RTP_GSR_EMPTYPER BSP_BIT32(11)
 
 /* field: EMPTY2 - RAM block 2 FIFO empty. This bit determines if there are entries left in the FIFO. */
-#define TMS570_RTP_GSR_EMPTY2 BSP_FLD32(9)
+#define TMS570_RTP_GSR_EMPTY2 BSP_BIT32(9)
 
 /* field: EMPTY1 - RAM block 1 FIFO empty. This bit determines if there are entries left in the FIFO. */
-#define TMS570_RTP_GSR_EMPTY1 BSP_FLD32(8)
+#define TMS570_RTP_GSR_EMPTY1 BSP_BIT32(8)
 
 /* field: OVFPER - Overflow peripheral FIFO. */
-#define TMS570_RTP_GSR_OVFPER BSP_FLD32(3)
+#define TMS570_RTP_GSR_OVFPER BSP_BIT32(3)
 
 /* field: OVF2 - Overflow RAM block 2 FIFO. */
-#define TMS570_RTP_GSR_OVF2 BSP_FLD32(1)
+#define TMS570_RTP_GSR_OVF2 BSP_BIT32(1)
 
 /* field: OVF1 - Overflow RAM block 1 FIFO. */
-#define TMS570_RTP_GSR_OVF1 BSP_FLD32(0)
+#define TMS570_RTP_GSR_OVF1 BSP_BIT32(0)
 
 
-/*---------------------TMS570_RTPRAM1REG1---------------------*/
+/*--------------------TMS570_RTP_RAM1REGx--------------------*/
 /* field: CPU_DMA - CPU and/or other master access. */
-#define TMS570_RTP_RAM1REG1_CPU_DMA(val) BSP_FLD32(val,29, 30)
+#define TMS570_RTP_RAM1REGx_CPU_DMA(val) BSP_FLD32(val,29, 30)
-#define TMS570_RTP_RAM1REG1_CPU_DMA_GET(reg) BSP_FLD32GET(reg,29, 30)
+#define TMS570_RTP_RAM1REGx_CPU_DMA_GET(reg) BSP_FLD32GET(reg,29, 30)
-#define TMS570_RTP_RAM1REG1_CPU_DMA_SET(reg,val) BSP_FLD32SET(reg, val,29, 30)
+#define TMS570_RTP_RAM1REGx_CPU_DMA_SET(reg,val) BSP_FLD32SET(reg, val,29, 30)
 
 /* field: RW - Read/Write. */
-#define TMS570_RTP_RAM1REG1_RW BSP_FLD32(28)
+#define TMS570_RTP_RAM1REGx_RW BSP_BIT32(28)
 
 /* field: BLOCKSIZE - These bits define the length of the trace region. */
-#define TMS570_RTP_RAM1REG1_BLOCKSIZE(val) BSP_FLD32(val,24, 27)
+#define TMS570_RTP_RAM1REGx_BLOCKSIZE(val) BSP_FLD32(val,24, 27)
-#define TMS570_RTP_RAM1REG1_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,24, 27)
+#define TMS570_RTP_RAM1REGx_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,24, 27)
-#define TMS570_RTP_RAM1REG1_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
+#define TMS570_RTP_RAM1REGx_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
 
 /* field: STARTADDR - These bits define the starting address of the address region that should be traced. */
-#define TMS570_RTP_RAM1REG1_STARTADDR(val) BSP_FLD32(val,0, 17)
+#define TMS570_RTP_RAM1REGx_STARTADDR(val) BSP_FLD32(val,0, 17)
-#define TMS570_RTP_RAM1REG1_STARTADDR_GET(reg) BSP_FLD32GET(reg,0, 17)
+#define TMS570_RTP_RAM1REGx_STARTADDR_GET(reg) BSP_FLD32GET(reg,0, 17)
-#define TMS570_RTP_RAM1REG1_STARTADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 17)
+#define TMS570_RTP_RAM1REGx_STARTADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 17)
 
 
-/*---------------------TMS570_RTPRAM2REG1---------------------*/
+/*--------------------TMS570_RTP_RAM2REGx--------------------*/
 /* field: CPU_DMA - CPU and/or other master access. */
-#define TMS570_RTP_RAM2REG1_CPU_DMA(val) BSP_FLD32(val,29, 30)
+#define TMS570_RTP_RAM2REGx_CPU_DMA(val) BSP_FLD32(val,29, 30)
-#define TMS570_RTP_RAM2REG1_CPU_DMA_GET(reg) BSP_FLD32GET(reg,29, 30)
+#define TMS570_RTP_RAM2REGx_CPU_DMA_GET(reg) BSP_FLD32GET(reg,29, 30)
-#define TMS570_RTP_RAM2REG1_CPU_DMA_SET(reg,val) BSP_FLD32SET(reg, val,29, 30)
+#define TMS570_RTP_RAM2REGx_CPU_DMA_SET(reg,val) BSP_FLD32SET(reg, val,29, 30)
 
 /* field: RW - Read/Write. */
-#define TMS570_RTP_RAM2REG1_RW BSP_FLD32(28)
+#define TMS570_RTP_RAM2REGx_RW BSP_BIT32(28)
 
 /* field: BLOCKSIZE - These bits define the length of the trace region. */
-#define TMS570_RTP_RAM2REG1_BLOCKSIZE(val) BSP_FLD32(val,24, 27)
+#define TMS570_RTP_RAM2REGx_BLOCKSIZE(val) BSP_FLD32(val,24, 27)
-#define TMS570_RTP_RAM2REG1_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,24, 27)
+#define TMS570_RTP_RAM2REGx_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,24, 27)
-#define TMS570_RTP_RAM2REG1_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
+#define TMS570_RTP_RAM2REGx_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
 
 /* field: STARTADDR - These bits define the starting address of the address region that should be traced. */
-#define TMS570_RTP_RAM2REG1_STARTADDR(val) BSP_FLD32(val,0, 23)
+#define TMS570_RTP_RAM2REGx_STARTADDR(val) BSP_FLD32(val,0, 23)
-#define TMS570_RTP_RAM2REG1_STARTADDR_GET(reg) BSP_FLD32GET(reg,0, 23)
+#define TMS570_RTP_RAM2REGx_STARTADDR_GET(reg) BSP_FLD32GET(reg,0, 23)
-#define TMS570_RTP_RAM2REG1_STARTADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
+#define TMS570_RTP_RAM2REGx_STARTADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
 
 
-/*---------------------TMS570_RTPPERREG1---------------------*/
+/*---------------------TMS570_RTP_PERREGx---------------------*/
 /* field: CPU_DMA - CPU and/or other master access. */
-#define TMS570_RTP_PERREG1_CPU_DMA(val) BSP_FLD32(val,29, 30)
+#define TMS570_RTP_PERREGx_CPU_DMA(val) BSP_FLD32(val,29, 30)
-#define TMS570_RTP_PERREG1_CPU_DMA_GET(reg) BSP_FLD32GET(reg,29, 30)
+#define TMS570_RTP_PERREGx_CPU_DMA_GET(reg) BSP_FLD32GET(reg,29, 30)
-#define TMS570_RTP_PERREG1_CPU_DMA_SET(reg,val) BSP_FLD32SET(reg, val,29, 30)
+#define TMS570_RTP_PERREGx_CPU_DMA_SET(reg,val) BSP_FLD32SET(reg, val,29, 30)
 
 /* field: RW - Read/Write. */
-#define TMS570_RTP_PERREG1_RW BSP_FLD32(28)
+#define TMS570_RTP_PERREGx_RW BSP_BIT32(28)
 
 /* field: BLOCKSIZE - These bits define the length of the trace region. */
-#define TMS570_RTP_PERREG1_BLOCKSIZE(val) BSP_FLD32(val,24, 27)
+#define TMS570_RTP_PERREGx_BLOCKSIZE(val) BSP_FLD32(val,24, 27)
-#define TMS570_RTP_PERREG1_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,24, 27)
+#define TMS570_RTP_PERREGx_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,24, 27)
-#define TMS570_RTP_PERREG1_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
+#define TMS570_RTP_PERREGx_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
 
 /* field: STARTADDR - These bits define the starting address of the address region that should be traced. */
-#define TMS570_RTP_PERREG1_STARTADDR(val) BSP_FLD32(val,0, 23)
+#define TMS570_RTP_PERREGx_STARTADDR(val) BSP_FLD32(val,0, 23)
-#define TMS570_RTP_PERREG1_STARTADDR_GET(reg) BSP_FLD32GET(reg,0, 23)
+#define TMS570_RTP_PERREGx_STARTADDR_GET(reg) BSP_FLD32GET(reg,0, 23)
-#define TMS570_RTP_PERREG1_STARTADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
+#define TMS570_RTP_PERREGx_STARTADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
 
 
-/*-----------------------TMS570_RTPDDMW-----------------------*/
+/*----------------------TMS570_RTP_DDMW----------------------*/
 /* field: DATA - This register must be written to in a Direct Data Mode write operation to store the data into */
-#define TMS570_RTP_DDMW_DATA(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_RTP_DDMW_DATA_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_RTP_DDMW_DATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-----------------------TMS570_RTP_PCx-----------------------*/
-/*-----------------------TMS570_RTPPC0-----------------------*/
 /* field: ENAFUNC - Functional mode of RTPENA pin. */
-#define TMS570_RTP_PC0_ENAFUNC BSP_FLD32(18)
+#define TMS570_RTP_PCx_ENAFUNC BSP_BIT32(18)
 
 /* field: CLKFUNC - Functional mode of RTPCLK pin. */
-#define TMS570_RTP_PC0_CLKFUNC BSP_FLD32(17)
+#define TMS570_RTP_PCx_CLKFUNC BSP_BIT32(17)
 
 /* field: SYNCFUNC - Functional mode of RTPSYNC pin. */
-#define TMS570_RTP_PC0_SYNCFUNC BSP_FLD32(16)
+#define TMS570_RTP_PCx_SYNCFUNC BSP_BIT32(16)
 
 /* field: DATAFUNC - Functional mode of RTPDATA[15:0] pins. */
-#define TMS570_RTP_PC0_DATAFUNC(val) BSP_FLD32(val,0, 15)
+#define TMS570_RTP_PCx_DATAFUNC(val) BSP_FLD32(val,0, 15)
-#define TMS570_RTP_PC0_DATAFUNC_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_RTP_PCx_DATAFUNC_GET(reg) BSP_FLD32GET(reg,0, 15)
-#define TMS570_RTP_PC0_DATAFUNC_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+#define TMS570_RTP_PCx_DATAFUNC_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
 
-#endif /* LIBBSP_ARM_tms570_RTP */
+#endif /* LIBBSP_ARM_TMS570_RTP */

c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_sci.h

@@ -36,8 +36,8 @@
  * of the authors and should not be interpreted as representing official policies,
  * either expressed or implied, of the FreeBSD Project.
 */
-#ifndef LIBBSP_ARM_tms570_SCI
+#ifndef LIBBSP_ARM_TMS570_SCI
-#define LIBBSP_ARM_tms570_SCI
+#define LIBBSP_ARM_TMS570_SCI
 
 #include <bsp/utility.h>
 
@@ -71,358 +71,358 @@ typedef struct{
 } tms570_sci_t;
 
 
-/*-----------------------TMS570_SCIGCR0-----------------------*/
+/*----------------------TMS570_SCI_GCR0----------------------*/
 /* field: Reserved - Read returns 0. Writes have no effect. */
 #define TMS570_SCI_GCR0_Reserved(val) BSP_FLD32(val,1, 31)
 #define TMS570_SCI_GCR0_Reserved_GET(reg) BSP_FLD32GET(reg,1, 31)
 #define TMS570_SCI_GCR0_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,1, 31)
 
 /* field: RESET - This bit resets the SCI module. */
-#define TMS570_SCI_GCR0_RESET BSP_FLD32(0)
+#define TMS570_SCI_GCR0_RESET BSP_BIT32(0)
 
 
-/*-----------------------TMS570_SCIGCR1-----------------------*/
+/*----------------------TMS570_SCI_GCR1----------------------*/
 /* field: TXENA - Transmit enable. */
-#define TMS570_SCI_GCR1_TXENA BSP_FLD32(25)
+#define TMS570_SCI_GCR1_TXENA BSP_BIT32(25)
 
 /* field: RXENA - Receive enable. RXENA allows or prevents the transfer of data from SCIRXSHF to SCIRD. */
-#define TMS570_SCI_GCR1_RXENA BSP_FLD32(24)
+#define TMS570_SCI_GCR1_RXENA BSP_BIT32(24)
 
 /* field: CONT - Continue on suspend. */
-#define TMS570_SCI_GCR1_CONT BSP_FLD32(17)
+#define TMS570_SCI_GCR1_CONT BSP_BIT32(17)
 
 /* field: LOOP_BACK - Loopback bit. The self-checking option for the SCI can be selected with this bit. */
-#define TMS570_SCI_GCR1_LOOP_BACK BSP_FLD32(16)
+#define TMS570_SCI_GCR1_LOOP_BACK BSP_BIT32(16)
 
 /* field: POWERDOWN - If the POWERDOWN bit is set while the receiver is actively receiving data and the wake-up */
-#define TMS570_SCI_GCR1_POWERDOWN BSP_FLD32(9)
+#define TMS570_SCI_GCR1_POWERDOWN BSP_BIT32(9)
 
 /* field: SLEEP - SCI sleep. In a multiprocessor configuration, this bit controls the receive sleep function. */
-#define TMS570_SCI_GCR1_SLEEP BSP_FLD32(8)
+#define TMS570_SCI_GCR1_SLEEP BSP_BIT32(8)
 
 /* field: SWnRST - Software reset (active low). This bit is effective in LIN and SCI modes. */
-#define TMS570_SCI_GCR1_SWnRST BSP_FLD32(7)
+#define TMS570_SCI_GCR1_SWnRST BSP_BIT32(7)
 
 /* field: CLOCK - CLOCK */
-#define TMS570_SCI_GCR1_CLOCK BSP_FLD32(5)
+#define TMS570_SCI_GCR1_CLOCK BSP_BIT32(5)
 
 /* field: STOP - SCI number of stop bits per frame. */
-#define TMS570_SCI_GCR1_STOP BSP_FLD32(4)
+#define TMS570_SCI_GCR1_STOP BSP_BIT32(4)
 
 /* field: PARITY - SCI parity odd/even selection. If the PARITY ENA bit is set, PARITY designates odd or even parity. */
-#define TMS570_SCI_GCR1_PARITY BSP_FLD32(3)
+#define TMS570_SCI_GCR1_PARITY BSP_BIT32(3)
 
 /* field: PARITY_ENA - Parity enable. This bit enables or disables the parity function. */
-#define TMS570_SCI_GCR1_PARITY_ENA BSP_FLD32(2)
+#define TMS570_SCI_GCR1_PARITY_ENA BSP_BIT32(2)
 
 /* field: TIMING_MODE - SCI timing mode bit. */
-#define TMS570_SCI_GCR1_TIMING_MODE BSP_FLD32(1)
+#define TMS570_SCI_GCR1_TIMING_MODE BSP_BIT32(1)
 
 /* field: COMM_MODE - SCI communication mode bit. */
-#define TMS570_SCI_GCR1_COMM_MODE BSP_FLD32(0)
+#define TMS570_SCI_GCR1_COMM_MODE BSP_BIT32(0)
 
 
-/*-----------------------TMS570_SCIGCR2-----------------------*/
+/*----------------------TMS570_SCI_GCR2----------------------*/
 /* field: CC - Compare checksum. LIN mode only. */
-#define TMS570_SCI_GCR2_CC BSP_FLD32(17)
+#define TMS570_SCI_GCR2_CC BSP_BIT32(17)
 
 /* field: SC - Send checksum byte. This bit is effective in LIN mode only. */
-#define TMS570_SCI_GCR2_SC BSP_FLD32(16)
+#define TMS570_SCI_GCR2_SC BSP_BIT32(16)
 
 /* field: GEN_WU - Generate wakeup signal. This bit is effective in LIN mode only. */
-#define TMS570_SCI_GCR2_GEN_WU BSP_FLD32(8)
+#define TMS570_SCI_GCR2_GEN_WU BSP_BIT32(8)
 
 /* field: POWERDOWN - Power down. This bit is effective in LIN or SCI mode. */
-#define TMS570_SCI_GCR2_POWERDOWN BSP_FLD32(0)
+#define TMS570_SCI_GCR2_POWERDOWN BSP_BIT32(0)
 
 
-/*----------------------TMS570_SCISETINT----------------------*/
+/*---------------------TMS570_SCI_SETINT---------------------*/
 /* field: SET_FE_INT -  */
-#define TMS570_SCI_SETINT_SET_FE_INT BSP_FLD32(26)
+#define TMS570_SCI_SETINT_SET_FE_INT BSP_BIT32(26)
 
 /* field: SET_OE_INT - SET OE INT */
-#define TMS570_SCI_SETINT_SET_OE_INT BSP_FLD32(25)
+#define TMS570_SCI_SETINT_SET_OE_INT BSP_BIT32(25)
 
 /* field: SET_PE_INT - Set parity interrupt. */
-#define TMS570_SCI_SETINT_SET_PE_INT BSP_FLD32(24)
+#define TMS570_SCI_SETINT_SET_PE_INT BSP_BIT32(24)
 
 /* field: SET_RX_DMA_ALL - SET RX DMA ALL */
-#define TMS570_SCI_SETINT_SET_RX_DMA_ALL BSP_FLD32(18)
+#define TMS570_SCI_SETINT_SET_RX_DMA_ALL BSP_BIT32(18)
 
 /* field: SET_RX_DMA - SET RX DMA */
-#define TMS570_SCI_SETINT_SET_RX_DMA BSP_FLD32(17)
+#define TMS570_SCI_SETINT_SET_RX_DMA BSP_BIT32(17)
 
 /* field: SET_TX_DMA - Set transmit DMA. To enable DMA requests for the transmitter, this bit must be set. */
-#define TMS570_SCI_SETINT_SET_TX_DMA BSP_FLD32(16)
+#define TMS570_SCI_SETINT_SET_TX_DMA BSP_BIT32(16)
 
 /* field: SET_RX_INT - SET RX INT */
-#define TMS570_SCI_SETINT_SET_RX_INT BSP_FLD32(9)
+#define TMS570_SCI_SETINT_SET_RX_INT BSP_BIT32(9)
 
 /* field: SET_TX_INT - Set transmitter interrupt. */
-#define TMS570_SCI_SETINT_SET_TX_INT BSP_FLD32(8)
+#define TMS570_SCI_SETINT_SET_TX_INT BSP_BIT32(8)
 
 /* field: SET_WAKEUP_INT - Set wakeup interrupt. */
-#define TMS570_SCI_SETINT_SET_WAKEUP_INT BSP_FLD32(1)
+#define TMS570_SCI_SETINT_SET_WAKEUP_INT BSP_BIT32(1)
 
 /* field: SET_BRKDT_INT - Set breakdetect interrupt. */
-#define TMS570_SCI_SETINT_SET_BRKDT_INT BSP_FLD32(0)
+#define TMS570_SCI_SETINT_SET_BRKDT_INT BSP_BIT32(0)
 
 
-/*---------------------TMS570_SCICLEARINT---------------------*/
+/*--------------------TMS570_SCI_CLEARINT--------------------*/
 /* field: CLR_FE_INT - Clear framing-error interrupt. This bit disables the framing-error interrupt when set. */
-#define TMS570_SCI_CLEARINT_CLR_FE_INT BSP_FLD32(26)
+#define TMS570_SCI_CLEARINT_CLR_FE_INT BSP_BIT32(26)
 
 /* field: CLR_CE_INT - Clear overrun-error interrupt. This bit disables the SCI overrun error interrupt when set. */
-#define TMS570_SCI_CLEARINT_CLR_CE_INT BSP_FLD32(25)
+#define TMS570_SCI_CLEARINT_CLR_CE_INT BSP_BIT32(25)
 
 /* field: CLR_PE_INT - Clear parity interrupt. This bit disables the parity error interrupt when set. */
-#define TMS570_SCI_CLEARINT_CLR_PE_INT BSP_FLD32(24)
+#define TMS570_SCI_CLEARINT_CLR_PE_INT BSP_BIT32(24)
 
 /* field: CLR_RX_DMA_ALL - Clear receive DMA all. This bit clears the receive DMA request for address frames when set. */
-#define TMS570_SCI_CLEARINT_CLR_RX_DMA_ALL BSP_FLD32(18)
+#define TMS570_SCI_CLEARINT_CLR_RX_DMA_ALL BSP_BIT32(18)
 
 /* field: CLR_RX_DMA - Clear receive DMA request. This bit disables the receive DMA request when set. */
-#define TMS570_SCI_CLEARINT_CLR_RX_DMA BSP_FLD32(17)
+#define TMS570_SCI_CLEARINT_CLR_RX_DMA BSP_BIT32(17)
 
 /* field: CLR_TX_DMA - CLR TX DMA */
-#define TMS570_SCI_CLEARINT_CLR_TX_DMA BSP_FLD32(16)
+#define TMS570_SCI_CLEARINT_CLR_TX_DMA BSP_BIT32(16)
 
 /* field: CLR_RX_INT - Clear receiver interrupt. This bit disables the receiver interrupt when set. */
-#define TMS570_SCI_CLEARINT_CLR_RX_INT BSP_FLD32(9)
+#define TMS570_SCI_CLEARINT_CLR_RX_INT BSP_BIT32(9)
 
 /* field: CLR_TX_INT - Clear transmitter interrupt. This bit disables the transmitter interrupt when set. */
-#define TMS570_SCI_CLEARINT_CLR_TX_INT BSP_FLD32(8)
+#define TMS570_SCI_CLEARINT_CLR_TX_INT BSP_BIT32(8)
 
 /* field: CLR_WAKEUP_INT - Clear wakeup interrupt. This bit disables the wakeup interrupt when set. */
-#define TMS570_SCI_CLEARINT_CLR_WAKEUP_INT BSP_FLD32(1)
+#define TMS570_SCI_CLEARINT_CLR_WAKEUP_INT BSP_BIT32(1)
 
 /* field: CLR_BRKDT_INT - Clear breakdetect interrupt. This bit disables the break-detect interrupt when set. */
-#define TMS570_SCI_CLEARINT_CLR_BRKDT_INT BSP_FLD32(0)
+#define TMS570_SCI_CLEARINT_CLR_BRKDT_INT BSP_BIT32(0)
 
 
-/*--------------------TMS570_SCISETINTLVL--------------------*/
+/*--------------------TMS570_SCI_SETINTLVL--------------------*/
 /* field: SET_FE_INT_LVL - Set framing-error interrupt level. */
-#define TMS570_SCI_SETINTLVL_SET_FE_INT_LVL BSP_FLD32(26)
+#define TMS570_SCI_SETINTLVL_SET_FE_INT_LVL BSP_BIT32(26)
 
 /* field: SET_CE_INT_LVL - Set overrun-error interrupt level. */
-#define TMS570_SCI_SETINTLVL_SET_CE_INT_LVL BSP_FLD32(25)
+#define TMS570_SCI_SETINTLVL_SET_CE_INT_LVL BSP_BIT32(25)
 
 /* field: SET_PE_INT_LVL - Set parity error interrupt level. */
-#define TMS570_SCI_SETINTLVL_SET_PE_INT_LVL BSP_FLD32(24)
+#define TMS570_SCI_SETINTLVL_SET_PE_INT_LVL BSP_BIT32(24)
 
 /* field: SET_RX_DMA_ALL_LVL - Set receive DMA all interrupt levels. */
-#define TMS570_SCI_SETINTLVL_SET_RX_DMA_ALL_LVL BSP_FLD32(18)
+#define TMS570_SCI_SETINTLVL_SET_RX_DMA_ALL_LVL BSP_BIT32(18)
 
 /* field: SET_RX_INT_LVL - Set receiver interrupt level. */
-#define TMS570_SCI_SETINTLVL_SET_RX_INT_LVL BSP_FLD32(9)
+#define TMS570_SCI_SETINTLVL_SET_RX_INT_LVL BSP_BIT32(9)
 
 /* field: SET_TX_INT_LVL - Set transmitter interrupt level. */
-#define TMS570_SCI_SETINTLVL_SET_TX_INT_LVL BSP_FLD32(8)
+#define TMS570_SCI_SETINTLVL_SET_TX_INT_LVL BSP_BIT32(8)
 
 /* field: SET_WAKEUP_INT_LVL - Set wakeup interrupt level. */
-#define TMS570_SCI_SETINTLVL_SET_WAKEUP_INT_LVL BSP_FLD32(1)
+#define TMS570_SCI_SETINTLVL_SET_WAKEUP_INT_LVL BSP_BIT32(1)
 
 /* field: SET_BRKDT_INT_LVL - SET BRKDT INT LVL */
-#define TMS570_SCI_SETINTLVL_SET_BRKDT_INT_LVL BSP_FLD32(0)
+#define TMS570_SCI_SETINTLVL_SET_BRKDT_INT_LVL BSP_BIT32(0)
 
 
-/*-------------------TMS570_SCICLEARINTLVL-------------------*/
+/*-------------------TMS570_SCI_CLEARINTLVL-------------------*/
 /* field: CLR_FE_INT_LVL - Clear framing-error interrupt. */
-#define TMS570_SCI_CLEARINTLVL_CLR_FE_INT_LVL BSP_FLD32(26)
+#define TMS570_SCI_CLEARINTLVL_CLR_FE_INT_LVL BSP_BIT32(26)
 
 /* field: CLR_CE_INT_LVL - CLR CE INT LVL */
-#define TMS570_SCI_CLEARINTLVL_CLR_CE_INT_LVL BSP_FLD32(25)
+#define TMS570_SCI_CLEARINTLVL_CLR_CE_INT_LVL BSP_BIT32(25)
 
 /* field: CLR_CE_INT_LVL - CLR CE INT LVL */
-#define TMS570_SCI_CLEARINTLVL_CLR_CE_INT_LVL BSP_FLD32(25)
+#define TMS570_SCI_CLEARINTLVL_CLR_CE_INT_LVL BSP_BIT32(25)
 
 /* field: CLR_PE_INT_LVL -  */
-#define TMS570_SCI_CLEARINTLVL_CLR_PE_INT_LVL BSP_FLD32(24)
+#define TMS570_SCI_CLEARINTLVL_CLR_PE_INT_LVL BSP_BIT32(24)
 
 /* field: CLR_RX_DMA_ALL_LVL - Clear receive DMA interrupt level. */
-#define TMS570_SCI_CLEARINTLVL_CLR_RX_DMA_ALL_LVL BSP_FLD32(18)
+#define TMS570_SCI_CLEARINTLVL_CLR_RX_DMA_ALL_LVL BSP_BIT32(18)
 
 /* field: CLR_RX_INT_LVL - Clear receiver interrupt. */
-#define TMS570_SCI_CLEARINTLVL_CLR_RX_INT_LVL BSP_FLD32(9)
+#define TMS570_SCI_CLEARINTLVL_CLR_RX_INT_LVL BSP_BIT32(9)
 
 /* field: 8 - CLR TX INT LVL Clear transmitter interrupt. */
-#define TMS570_SCI_CLEARINTLVL_8 BSP_FLD32(8)
+#define TMS570_SCI_CLEARINTLVL_8 BSP_BIT32(8)
 
 /* field: CLR_WAKEUP_INT_LVL - Clear wakeup interrupt. */
-#define TMS570_SCI_CLEARINTLVL_CLR_WAKEUP_INT_LVL BSP_FLD32(1)
+#define TMS570_SCI_CLEARINTLVL_CLR_WAKEUP_INT_LVL BSP_BIT32(1)
 
 /* field: CLR_BRKDT_INT_LVL - Clear breakdetect interrupt. */
-#define TMS570_SCI_CLEARINTLVL_CLR_BRKDT_INT_LVL BSP_FLD32(0)
+#define TMS570_SCI_CLEARINTLVL_CLR_BRKDT_INT_LVL BSP_BIT32(0)
 
 
-/*-----------------------TMS570_SCIFLR-----------------------*/
+/*-----------------------TMS570_SCI_FLR-----------------------*/
 /* field: FE - Framing error flag. This bit is effective in LIN or SCI-compatible mode. */
-#define TMS570_SCI_FLR_FE BSP_FLD32(26)
+#define TMS570_SCI_FLR_FE BSP_BIT32(26)
 
 /* field: OE - Overrun error flag. */
-#define TMS570_SCI_FLR_OE BSP_FLD32(25)
+#define TMS570_SCI_FLR_OE BSP_BIT32(25)
 
 /* field: PE - Parity error flag. This bit is set when a parity error is detected in the received data. */
-#define TMS570_SCI_FLR_PE BSP_FLD32(24)
+#define TMS570_SCI_FLR_PE BSP_BIT32(24)
 
 /* field: RXWAKE - Receiver wakeup detect flag. */
-#define TMS570_SCI_FLR_RXWAKE BSP_FLD32(12)
+#define TMS570_SCI_FLR_RXWAKE BSP_BIT32(12)
 
 /* field: TX_EMPTY - Transmitter empty flag. */
-#define TMS570_SCI_FLR_TX_EMPTY BSP_FLD32(11)
+#define TMS570_SCI_FLR_TX_EMPTY BSP_BIT32(11)
 
 /* field: TXWAKE - Transmitter wakeup method select. */
-#define TMS570_SCI_FLR_TXWAKE BSP_FLD32(10)
+#define TMS570_SCI_FLR_TXWAKE BSP_BIT32(10)
 
 /* field: RXRDY - Receiver ready flag. */
-#define TMS570_SCI_FLR_RXRDY BSP_FLD32(9)
+#define TMS570_SCI_FLR_RXRDY BSP_BIT32(9)
 
 /* field: TXRDY - Transmitter buffer register ready flag. */
-#define TMS570_SCI_FLR_TXRDY BSP_FLD32(8)
+#define TMS570_SCI_FLR_TXRDY BSP_BIT32(8)
 
 /* field: BUSY - Bus busy flag. TThis bit indicates whether the receiver is in the process of receiving a frame. */
-#define TMS570_SCI_FLR_BUSY BSP_FLD32(3)
+#define TMS570_SCI_FLR_BUSY BSP_BIT32(3)
 
 /* field: IDLE - SCI receiver in idle state. */
-#define TMS570_SCI_FLR_IDLE BSP_FLD32(2)
+#define TMS570_SCI_FLR_IDLE BSP_BIT32(2)
 
 /* field: WAKEUP - Wakeup flag. */
-#define TMS570_SCI_FLR_WAKEUP BSP_FLD32(1)
+#define TMS570_SCI_FLR_WAKEUP BSP_BIT32(1)
 
 /* field: BRKDT - SCI break-detect flag. This bit is set when the SCI detects a break condition on the LINRX pin. */
-#define TMS570_SCI_FLR_BRKDT BSP_FLD32(0)
+#define TMS570_SCI_FLR_BRKDT BSP_BIT32(0)
 
 
-/*---------------------TMS570_SCIINTVECT0---------------------*/
+/*--------------------TMS570_SCI_INTVECT0--------------------*/
 /* field: INVECT0 - Interrupt vector offset for INT0. This register indicates the offset for interrupt line INT0. */
 #define TMS570_SCI_INTVECT0_INVECT0(val) BSP_FLD32(val,0, 3)
 #define TMS570_SCI_INTVECT0_INVECT0_GET(reg) BSP_FLD32GET(reg,0, 3)
 #define TMS570_SCI_INTVECT0_INVECT0_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*---------------------TMS570_SCIINTVECT1---------------------*/
+/*--------------------TMS570_SCI_INTVECT1--------------------*/
 /* field: INVECT1 - Interrupt vector offset for INT1. This register indicates the offset for interrupt line INT1. */
 #define TMS570_SCI_INTVECT1_INVECT1(val) BSP_FLD32(val,0, 3)
 #define TMS570_SCI_INTVECT1_INVECT1_GET(reg) BSP_FLD32GET(reg,0, 3)
 #define TMS570_SCI_INTVECT1_INVECT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*----------------------TMS570_SCIFORMAT----------------------*/
+/*---------------------TMS570_SCI_FORMAT---------------------*/
 /* field: CHAR - Character length control bits. These bits set the SCI character length from 1 to 8 bits. */
 #define TMS570_SCI_FORMAT_CHAR(val) BSP_FLD32(val,0, 2)
 #define TMS570_SCI_FORMAT_CHAR_GET(reg) BSP_FLD32GET(reg,0, 2)
 #define TMS570_SCI_FORMAT_CHAR_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
 
 
-/*-----------------------TMS570_SCIBRS-----------------------*/
+/*-----------------------TMS570_SCI_BRS-----------------------*/
 /* field: BAUD - SCI 24-bit baud selection. */
 #define TMS570_SCI_BRS_BAUD(val) BSP_FLD32(val,0, 23)
 #define TMS570_SCI_BRS_BAUD_GET(reg) BSP_FLD32GET(reg,0, 23)
 #define TMS570_SCI_BRS_BAUD_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
 
 
-/*------------------------TMS570_SCIED------------------------*/
+/*-----------------------TMS570_SCI_ED-----------------------*/
 /* field: ED - Emulator data. Reading SCIED[7:0] does not clear the RXRDY flag, unlike reading SCIRD. */
 #define TMS570_SCI_ED_ED(val) BSP_FLD32(val,0, 7)
 #define TMS570_SCI_ED_ED_GET(reg) BSP_FLD32GET(reg,0, 7)
 #define TMS570_SCI_ED_ED_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*------------------------TMS570_SCIRD------------------------*/
+/*-----------------------TMS570_SCI_RD-----------------------*/
 /* field: RD - Receiver data. */
 #define TMS570_SCI_RD_RD(val) BSP_FLD32(val,0, 7)
 #define TMS570_SCI_RD_RD_GET(reg) BSP_FLD32GET(reg,0, 7)
 #define TMS570_SCI_RD_RD_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*------------------------TMS570_SCITD------------------------*/
+/*-----------------------TMS570_SCI_TD-----------------------*/
 /* field: TD - Transmit data. Data to be transmitted is written to the SCITD register. */
 #define TMS570_SCI_TD_TD(val) BSP_FLD32(val,0, 7)
 #define TMS570_SCI_TD_TD_GET(reg) BSP_FLD32GET(reg,0, 7)
 #define TMS570_SCI_TD_TD_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*-----------------------TMS570_SCIPIO0-----------------------*/
+/*----------------------TMS570_SCI_PIO0----------------------*/
 /* field: TX_FUNC - Transfer function. This bit defines the function of pin SCITX. */
-#define TMS570_SCI_PIO0_TX_FUNC BSP_FLD32(2)
+#define TMS570_SCI_PIO0_TX_FUNC BSP_BIT32(2)
 
 /* field: RX_FUNC - Receive function.This bit defines the function of pin SCIRX. */
-#define TMS570_SCI_PIO0_RX_FUNC BSP_FLD32(1)
+#define TMS570_SCI_PIO0_RX_FUNC BSP_BIT32(1)
 
 
-/*-----------------------TMS570_SCIPIO1-----------------------*/
+/*----------------------TMS570_SCI_PIO1----------------------*/
 /* field: TX_DIR - Transmit pin direction. */
-#define TMS570_SCI_PIO1_TX_DIR BSP_FLD32(2)
+#define TMS570_SCI_PIO1_TX_DIR BSP_BIT32(2)
 
 /* field: RX_DIR - Receive pin direction. */
-#define TMS570_SCI_PIO1_RX_DIR BSP_FLD32(1)
+#define TMS570_SCI_PIO1_RX_DIR BSP_BIT32(1)
 
 
-/*-----------------------TMS570_SCIPIO2-----------------------*/
+/*----------------------TMS570_SCI_PIO2----------------------*/
 /* field: TX_IN - Transmit pin in. This bit contains the current value on the SCITX pin. */
-#define TMS570_SCI_PIO2_TX_IN BSP_FLD32(2)
+#define TMS570_SCI_PIO2_TX_IN BSP_BIT32(2)
 
 /* field: RX_IN - Receive pin in. This bit contains the current value on the SCIRX pin. */
-#define TMS570_SCI_PIO2_RX_IN BSP_FLD32(1)
+#define TMS570_SCI_PIO2_RX_IN BSP_BIT32(1)
 
 
-/*-----------------------TMS570_SCIPIO3-----------------------*/
+/*----------------------TMS570_SCI_PIO3----------------------*/
 /* field: TX_OUT - Transmit pin out. */
-#define TMS570_SCI_PIO3_TX_OUT BSP_FLD32(2)
+#define TMS570_SCI_PIO3_TX_OUT BSP_BIT32(2)
 
 /* field: RX_OUT - Receive pin out. */
-#define TMS570_SCI_PIO3_RX_OUT BSP_FLD32(1)
+#define TMS570_SCI_PIO3_RX_OUT BSP_BIT32(1)
 
 
-/*-----------------------TMS570_SCIPIO4-----------------------*/
+/*----------------------TMS570_SCI_PIO4----------------------*/
 /* field: TX_SET - Transmit pin set. */
-#define TMS570_SCI_PIO4_TX_SET BSP_FLD32(2)
+#define TMS570_SCI_PIO4_TX_SET BSP_BIT32(2)
 
 /* field: RX_SET - Receive pin set. */
-#define TMS570_SCI_PIO4_RX_SET BSP_FLD32(1)
+#define TMS570_SCI_PIO4_RX_SET BSP_BIT32(1)
 
 
-/*-----------------------TMS570_SCIPIO5-----------------------*/
+/*----------------------TMS570_SCI_PIO5----------------------*/
 /* field: TX_CLR - Transmit pin clear. */
-#define TMS570_SCI_PIO5_TX_CLR BSP_FLD32(2)
+#define TMS570_SCI_PIO5_TX_CLR BSP_BIT32(2)
 
 /* field: RX_CLR - Receive pin clear. */
-#define TMS570_SCI_PIO5_RX_CLR BSP_FLD32(1)
+#define TMS570_SCI_PIO5_RX_CLR BSP_BIT32(1)
 
 
-/*-----------------------TMS570_SCIPIO6-----------------------*/
+/*----------------------TMS570_SCI_PIO6----------------------*/
 /* field: TX_PDR - Transmit pin open drain enable. */
-#define TMS570_SCI_PIO6_TX_PDR BSP_FLD32(2)
+#define TMS570_SCI_PIO6_TX_PDR BSP_BIT32(2)
 
 /* field: RX_PDR - Receive pin open drain enable. */
-#define TMS570_SCI_PIO6_RX_PDR BSP_FLD32(1)
+#define TMS570_SCI_PIO6_RX_PDR BSP_BIT32(1)
 
 
-/*-----------------------TMS570_SCIPIO7-----------------------*/
+/*----------------------TMS570_SCI_PIO7----------------------*/
 /* field: TX_PD - Transmit pin pull control disable. This bit disables pull control capability on the input pin SCITX. */
-#define TMS570_SCI_PIO7_TX_PD BSP_FLD32(2)
+#define TMS570_SCI_PIO7_TX_PD BSP_BIT32(2)
 
 /* field: RX_PD - Receive pin pull control disable. This bit disables pull control capability on the input pin SCIRX. */
-#define TMS570_SCI_PIO7_RX_PD BSP_FLD32(1)
+#define TMS570_SCI_PIO7_RX_PD BSP_BIT32(1)
 
 
-/*-----------------------TMS570_SCIPIO8-----------------------*/
+/*----------------------TMS570_SCI_PIO8----------------------*/
 /* field: TX_PSL - TX pin pull select. This bit selects pull type in the input pin SCITX. */
-#define TMS570_SCI_PIO8_TX_PSL BSP_FLD32(2)
+#define TMS570_SCI_PIO8_TX_PSL BSP_BIT32(2)
 
 /* field: RX_PSL - RX pin pull select. This bit selects pull type in the input pin SCIRX. */
-#define TMS570_SCI_PIO8_RX_PSL BSP_FLD32(1)
+#define TMS570_SCI_PIO8_RX_PSL BSP_BIT32(1)
 
 
-/*--------------------TMS570_SCIIODFTCTRL--------------------*/
+/*--------------------TMS570_SCI_IODFTCTRL--------------------*/
 /* field: FEN - Frame error enable. This bit is used to create a frame error. */
-#define TMS570_SCI_IODFTCTRL_FEN BSP_FLD32(26)
+#define TMS570_SCI_IODFTCTRL_FEN BSP_BIT32(26)
 
 /* field: PEN - Parity error enable. This bit is used to create a parity error. */
-#define TMS570_SCI_IODFTCTRL_PEN BSP_FLD32(25)
+#define TMS570_SCI_IODFTCTRL_PEN BSP_BIT32(25)
 
 /* field: BRKD_TENA - Break detect error enable. This bit is used to create a BRKDT error. */
-#define TMS570_SCI_IODFTCTRL_BRKD_TENA BSP_FLD32(24)
+#define TMS570_SCI_IODFTCTRL_BRKD_TENA BSP_BIT32(24)
 
 /* field: PIN_SAMPLE_MASK - Pin sample mask. */
 #define TMS570_SCI_IODFTCTRL_PIN_SAMPLE_MASK(val) BSP_FLD32(val,19, 20)
@@ -440,11 +440,11 @@ typedef struct{
 #define TMS570_SCI_IODFTCTRL_IODFTENA_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
 
 /* field: LPBENA - Module loopback enable. Write access permitted in Privilege mode only. */
-#define TMS570_SCI_IODFTCTRL_LPBENA BSP_FLD32(1)
+#define TMS570_SCI_IODFTCTRL_LPBENA BSP_BIT32(1)
 
 /* field: RXPENA - Module analog loopback through receive pin enable. */
-#define TMS570_SCI_IODFTCTRL_RXPENA BSP_FLD32(0)
+#define TMS570_SCI_IODFTCTRL_RXPENA BSP_BIT32(0)
 
 
 
-#endif /* LIBBSP_ARM_tms570_SCI */
+#endif /* LIBBSP_ARM_TMS570_SCI */

c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_spi.h

@@ -36,8 +36,8 @@
  * of the authors and should not be interpreted as representing official policies,
  * either expressed or implied, of the FreeBSD Project.
 */
-#ifndef LIBBSP_ARM_tms570_SPI
+#ifndef LIBBSP_ARM_TMS570_SPI
-#define LIBBSP_ARM_tms570_SPI
+#define LIBBSP_ARM_TMS570_SPI
 
 #include <bsp/utility.h>
 
@@ -95,92 +95,92 @@ typedef struct{
 } tms570_spi_t;
 
 
-/*-----------------------TMS570_SPIGCR0-----------------------*/
+/*----------------------TMS570_SPI_GCR0----------------------*/
 /* field: nRESET - This is the local reset control for the module. */
-#define TMS570_SPI_GCR0_nRESET BSP_FLD32(0)
+#define TMS570_SPI_GCR0_nRESET BSP_BIT32(0)
 
 
-/*-----------------------TMS570_SPIGCR1-----------------------*/
+/*----------------------TMS570_SPI_GCR1----------------------*/
 /* field: SPIEN - SPI enable. This bit enables SPI transfers. */
-#define TMS570_SPI_GCR1_SPIEN BSP_FLD32(24)
+#define TMS570_SPI_GCR1_SPIEN BSP_BIT32(24)
 
 /* field: LOOPBACK - Internal loop-back test mode. The internal self-test option can be enabled by setting this bit. */
-#define TMS570_SPI_GCR1_LOOPBACK BSP_FLD32(16)
+#define TMS570_SPI_GCR1_LOOPBACK BSP_BIT32(16)
 
 /* field: POWERDOWN - When active, the SPI state machine enters a power-down state. */
-#define TMS570_SPI_GCR1_POWERDOWN BSP_FLD32(8)
+#define TMS570_SPI_GCR1_POWERDOWN BSP_BIT32(8)
 
 /* field: CLKMOD - Clock mode. This bit selects either an internal or external clock source. */
-#define TMS570_SPI_GCR1_CLKMOD BSP_FLD32(1)
+#define TMS570_SPI_GCR1_CLKMOD BSP_BIT32(1)
 
 /* field: MASTER - SPISIMO/SPISOMI pin direction determination. */
-#define TMS570_SPI_GCR1_MASTER BSP_FLD32(0)
+#define TMS570_SPI_GCR1_MASTER BSP_BIT32(0)
 
 
-/*-----------------------TMS570_SPIINT0-----------------------*/
+/*----------------------TMS570_SPI_INT0----------------------*/
 /* field: ENABLEHIGHZ - SPIENA pin high-impedance enable. */
-#define TMS570_SPI_INT0_ENABLEHIGHZ BSP_FLD32(24)
+#define TMS570_SPI_INT0_ENABLEHIGHZ BSP_BIT32(24)
 
 /* field: DMAREQEN - DMA request enable. */
-#define TMS570_SPI_INT0_DMAREQEN BSP_FLD32(16)
+#define TMS570_SPI_INT0_DMAREQEN BSP_BIT32(16)
 
 
-/*-----------------------TMS570_SPILVL-----------------------*/
+/*-----------------------TMS570_SPI_LVL-----------------------*/
 /* field: TXINTLVL - Transmit interrupt level. */
-#define TMS570_SPI_LVL_TXINTLVL BSP_FLD32(9)
+#define TMS570_SPI_LVL_TXINTLVL BSP_BIT32(9)
 
 /* field: RXINTLVL - Receive interrupt level. */
-#define TMS570_SPI_LVL_RXINTLVL BSP_FLD32(8)
+#define TMS570_SPI_LVL_RXINTLVL BSP_BIT32(8)
 
 /* field: RXOVRNINTLVL - Receive overrun interrupt level. */
-#define TMS570_SPI_LVL_RXOVRNINTLVL BSP_FLD32(6)
+#define TMS570_SPI_LVL_RXOVRNINTLVL BSP_BIT32(6)
 
 /* field: BITERRLVL - Bit error interrupt level. */
-#define TMS570_SPI_LVL_BITERRLVL BSP_FLD32(4)
+#define TMS570_SPI_LVL_BITERRLVL BSP_BIT32(4)
 
 /* field: DESYNCLVL - Desynchronized slave interrupt level. (master mode only). */
-#define TMS570_SPI_LVL_DESYNCLVL BSP_FLD32(3)
+#define TMS570_SPI_LVL_DESYNCLVL BSP_BIT32(3)
 
 /* field: PARERRLVL - Parity error interrupt level. */
-#define TMS570_SPI_LVL_PARERRLVL BSP_FLD32(2)
+#define TMS570_SPI_LVL_PARERRLVL BSP_BIT32(2)
 
 /* field: TIMEOUTLVL - SPIENA pin time-out interrupt level. */
-#define TMS570_SPI_LVL_TIMEOUTLVL BSP_FLD32(1)
+#define TMS570_SPI_LVL_TIMEOUTLVL BSP_BIT32(1)
 
 /* field: DLENERRLVL - Data length error interrupt level (line) select. */
-#define TMS570_SPI_LVL_DLENERRLVL BSP_FLD32(0)
+#define TMS570_SPI_LVL_DLENERRLVL BSP_BIT32(0)
 
 
-/*-----------------------TMS570_SPIFLG-----------------------*/
+/*-----------------------TMS570_SPI_FLG-----------------------*/
 /* field: BUFINITACTIVE - Indicates the status of multi-buffer initialization process. */
-#define TMS570_SPI_FLG_BUFINITACTIVE BSP_FLD32(24)
+#define TMS570_SPI_FLG_BUFINITACTIVE BSP_BIT32(24)
 
 /* field: TXINTFLG - Transmitter-empty interrupt flag. */
-#define TMS570_SPI_FLG_TXINTFLG BSP_FLD32(9)
+#define TMS570_SPI_FLG_TXINTFLG BSP_BIT32(9)
 
 /* field: RXINTFLG - Receiver-full interrupt flag. */
-#define TMS570_SPI_FLG_RXINTFLG BSP_FLD32(8)
+#define TMS570_SPI_FLG_RXINTFLG BSP_BIT32(8)
 
 /* field: RXOVRNINTFLG - Receiver overrun flag. */
-#define TMS570_SPI_FLG_RXOVRNINTFLG BSP_FLD32(6)
+#define TMS570_SPI_FLG_RXOVRNINTFLG BSP_BIT32(6)
 
 /* field: BITERRFLG - Mismatch of internal transmit data and transmitted data. */
-#define TMS570_SPI_FLG_BITERRFLG BSP_FLD32(4)
+#define TMS570_SPI_FLG_BITERRFLG BSP_BIT32(4)
 
 /* field: DESYNCFLG - Desynchronization of slave device. */
-#define TMS570_SPI_FLG_DESYNCFLG BSP_FLD32(3)
+#define TMS570_SPI_FLG_DESYNCFLG BSP_BIT32(3)
 
 /* field: PARITYERRFLG - Calculated parity differs from received parity bit. */
-#define TMS570_SPI_FLG_PARITYERRFLG BSP_FLD32(2)
+#define TMS570_SPI_FLG_PARITYERRFLG BSP_BIT32(2)
 
 /* field: TIMEOUTFLG - Time-out caused by nonactivation of ENA signal. */
-#define TMS570_SPI_FLG_TIMEOUTFLG BSP_FLD32(1)
+#define TMS570_SPI_FLG_TIMEOUTFLG BSP_BIT32(1)
 
 /* field: DLENERRFLG - Data-length error flag. */
-#define TMS570_SPI_FLG_DLENERRFLG BSP_FLD32(0)
+#define TMS570_SPI_FLG_DLENERRFLG BSP_BIT32(0)
 
 
-/*-----------------------TMS570_SPIPC0-----------------------*/
+/*-----------------------TMS570_SPI_PC0-----------------------*/
 /* field: SOMIFUN - Slave out, master in function. */
 #define TMS570_SPI_PC0_SOMIFUN(val) BSP_FLD32(val,24, 31)
 #define TMS570_SPI_PC0_SOMIFUN_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -192,16 +192,16 @@ typedef struct{
 #define TMS570_SPI_PC0_SIMOFUN_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
 
 /* field: SOMIFUN0 - SOMIFUN0 */
-#define TMS570_SPI_PC0_SOMIFUN0 BSP_FLD32(11)
+#define TMS570_SPI_PC0_SOMIFUN0 BSP_BIT32(11)
 
 /* field: SIMOFUN0 - Slave in, master out function. */
-#define TMS570_SPI_PC0_SIMOFUN0 BSP_FLD32(10)
+#define TMS570_SPI_PC0_SIMOFUN0 BSP_BIT32(10)
 
 /* field: CLKFUN - CLKFUN */
-#define TMS570_SPI_PC0_CLKFUN BSP_FLD32(9)
+#define TMS570_SPI_PC0_CLKFUN BSP_BIT32(9)
 
 /* field: ENAFUN - SPIENA function. */
-#define TMS570_SPI_PC0_ENAFUN BSP_FLD32(8)
+#define TMS570_SPI_PC0_ENAFUN BSP_BIT32(8)
 
 /* field: SCSFUN - SPISCSx function. */
 #define TMS570_SPI_PC0_SCSFUN(val) BSP_FLD32(val,0, 7)
@@ -209,7 +209,7 @@ typedef struct{
 #define TMS570_SPI_PC0_SCSFUN_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*-----------------------TMS570_SPIPC1-----------------------*/
+/*-----------------------TMS570_SPI_PC1-----------------------*/
 /* field: SOMIDIR - SPISOMIx direction. Controls the direction of SPISOMIx when used for general-purpose I/O. */
 #define TMS570_SPI_PC1_SOMIDIR(val) BSP_FLD32(val,24, 31)
 #define TMS570_SPI_PC1_SOMIDIR_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -221,16 +221,16 @@ typedef struct{
 #define TMS570_SPI_PC1_SIMODIR_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
 
 /* field: SOMIDIR0 - PISOMI0 direction. */
-#define TMS570_SPI_PC1_SOMIDIR0 BSP_FLD32(11)
+#define TMS570_SPI_PC1_SOMIDIR0 BSP_BIT32(11)
 
 /* field: SIMODIR0 - SPISIMO0 direction. */
-#define TMS570_SPI_PC1_SIMODIR0 BSP_FLD32(10)
+#define TMS570_SPI_PC1_SIMODIR0 BSP_BIT32(10)
 
 /* field: CLKDIR - SPICLK direction. */
-#define TMS570_SPI_PC1_CLKDIR BSP_FLD32(9)
+#define TMS570_SPI_PC1_CLKDIR BSP_BIT32(9)
 
 /* field: ENADIR - SPIENA direction. */
-#define TMS570_SPI_PC1_ENADIR BSP_FLD32(8)
+#define TMS570_SPI_PC1_ENADIR BSP_BIT32(8)
 
 /* field: SCSDIR - SPISCSx direction. */
 #define TMS570_SPI_PC1_SCSDIR(val) BSP_FLD32(val,0, 7)
@@ -238,7 +238,7 @@ typedef struct{
 #define TMS570_SPI_PC1_SCSDIR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*-----------------------TMS570_SPIPC2-----------------------*/
+/*-----------------------TMS570_SPI_PC2-----------------------*/
 /* field: SOMIDIN - SPISOMIx data in. The value of the SPISOMIx pins. */
 #define TMS570_SPI_PC2_SOMIDIN(val) BSP_FLD32(val,24, 31)
 #define TMS570_SPI_PC2_SOMIDIN_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -250,16 +250,16 @@ typedef struct{
 #define TMS570_SPI_PC2_SIMODIN_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
 
 /* field: SOMIDIN0 - SPISOMI0 data in. The value of the SPISOMI0 pin. */
-#define TMS570_SPI_PC2_SOMIDIN0 BSP_FLD32(11)
+#define TMS570_SPI_PC2_SOMIDIN0 BSP_BIT32(11)
 
 /* field: SIMODIN0 - SPISIMO0 data in. The value of the SPISIMO0 pin. */
-#define TMS570_SPI_PC2_SIMODIN0 BSP_FLD32(10)
+#define TMS570_SPI_PC2_SIMODIN0 BSP_BIT32(10)
 
 /* field: CLKDIN - Clock data in. The value of the SPICLK pin. pin. */
-#define TMS570_SPI_PC2_CLKDIN BSP_FLD32(9)
+#define TMS570_SPI_PC2_CLKDIN BSP_BIT32(9)
 
 /* field: ENADIN - SPIENA data in. The the value of the SPIENA pin. */
-#define TMS570_SPI_PC2_ENADIN BSP_FLD32(8)
+#define TMS570_SPI_PC2_ENADIN BSP_BIT32(8)
 
 /* field: SCSDIN - SPISCSx data in. The value of the SPISCSx pin. */
 #define TMS570_SPI_PC2_SCSDIN(val) BSP_FLD32(val,0, 7)
@@ -267,7 +267,7 @@ typedef struct{
 #define TMS570_SPI_PC2_SCSDIN_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*-----------------------TMS570_SPIPC3-----------------------*/
+/*-----------------------TMS570_SPI_PC3-----------------------*/
 /* field: SOMIDOUT - SPISOMIx data out write. */
 #define TMS570_SPI_PC3_SOMIDOUT(val) BSP_FLD32(val,24, 31)
 #define TMS570_SPI_PC3_SOMIDOUT_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -279,16 +279,16 @@ typedef struct{
 #define TMS570_SPI_PC3_SIMODOUT_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
 
 /* field: SOMIDOUT0 - SPISOMI0 data out write. */
-#define TMS570_SPI_PC3_SOMIDOUT0 BSP_FLD32(11)
+#define TMS570_SPI_PC3_SOMIDOUT0 BSP_BIT32(11)
 
 /* field: SIMODOUT0 - SPISIMO0 data out write. */
-#define TMS570_SPI_PC3_SIMODOUT0 BSP_FLD32(10)
+#define TMS570_SPI_PC3_SIMODOUT0 BSP_BIT32(10)
 
 /* field: CLKDOUT - SPICLK data out write. */
-#define TMS570_SPI_PC3_CLKDOUT BSP_FLD32(9)
+#define TMS570_SPI_PC3_CLKDOUT BSP_BIT32(9)
 
 /* field: ENADOUT - SPIENA data out write. */
-#define TMS570_SPI_PC3_ENADOUT BSP_FLD32(8)
+#define TMS570_SPI_PC3_ENADOUT BSP_BIT32(8)
 
 /* field: SCSDOUT - SPISCSx data out write. */
 #define TMS570_SPI_PC3_SCSDOUT(val) BSP_FLD32(val,0, 7)
@@ -296,7 +296,7 @@ typedef struct{
 #define TMS570_SPI_PC3_SCSDOUT_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*-----------------------TMS570_SPIPC4-----------------------*/
+/*-----------------------TMS570_SPI_PC4-----------------------*/
 /* field: SOMISET - SPISOMIx data out set. */
 #define TMS570_SPI_PC4_SOMISET(val) BSP_FLD32(val,24, 31)
 #define TMS570_SPI_PC4_SOMISET_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -308,16 +308,16 @@ typedef struct{
 #define TMS570_SPI_PC4_SIMOSET_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
 
 /* field: SOMISET0 - SPISOMI0 data out set. */
-#define TMS570_SPI_PC4_SOMISET0 BSP_FLD32(11)
+#define TMS570_SPI_PC4_SOMISET0 BSP_BIT32(11)
 
 /* field: SIMOSET0 - purpose */
-#define TMS570_SPI_PC4_SIMOSET0 BSP_FLD32(10)
+#define TMS570_SPI_PC4_SIMOSET0 BSP_BIT32(10)
 
 /* field: CLKSET - SPICLK data out set. */
-#define TMS570_SPI_PC4_CLKSET BSP_FLD32(9)
+#define TMS570_SPI_PC4_CLKSET BSP_BIT32(9)
 
 /* field: ENASET - SPIENA data out set. */
-#define TMS570_SPI_PC4_ENASET BSP_FLD32(8)
+#define TMS570_SPI_PC4_ENASET BSP_BIT32(8)
 
 /* field: SCSSET - SPISCSx data out set. */
 #define TMS570_SPI_PC4_SCSSET(val) BSP_FLD32(val,0, 7)
@@ -325,7 +325,7 @@ typedef struct{
 #define TMS570_SPI_PC4_SCSSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*-----------------------TMS570_SPIPC5-----------------------*/
+/*-----------------------TMS570_SPI_PC5-----------------------*/
 /* field: SOMICLR - SPISOMIx data out clear. */
 #define TMS570_SPI_PC5_SOMICLR(val) BSP_FLD32(val,24, 31)
 #define TMS570_SPI_PC5_SOMICLR_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -337,16 +337,16 @@ typedef struct{
 #define TMS570_SPI_PC5_SIMOCLR_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
 
 /* field: SOMICLR0 - SPISOMI0 data out cleart. */
-#define TMS570_SPI_PC5_SOMICLR0 BSP_FLD32(11)
+#define TMS570_SPI_PC5_SOMICLR0 BSP_BIT32(11)
 
 /* field: SIMOCLR0 - SPISIMO0 data out clear. */
-#define TMS570_SPI_PC5_SIMOCLR0 BSP_FLD32(10)
+#define TMS570_SPI_PC5_SIMOCLR0 BSP_BIT32(10)
 
 /* field: CLKCLR - SPICLK data out clear. */
-#define TMS570_SPI_PC5_CLKCLR BSP_FLD32(9)
+#define TMS570_SPI_PC5_CLKCLR BSP_BIT32(9)
 
 /* field: ENACLR - SPIENA data out clear. */
-#define TMS570_SPI_PC5_ENACLR BSP_FLD32(8)
+#define TMS570_SPI_PC5_ENACLR BSP_BIT32(8)
 
 /* field: SCSCLR - SPISCSx data out clear. */
 #define TMS570_SPI_PC5_SCSCLR(val) BSP_FLD32(val,0, 7)
@@ -354,7 +354,7 @@ typedef struct{
 #define TMS570_SPI_PC5_SCSCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*-----------------------TMS570_SPIPC6-----------------------*/
+/*-----------------------TMS570_SPI_PC6-----------------------*/
 /* field: SOMIPDR - SPISOMIx open drain enable. */
 #define TMS570_SPI_PC6_SOMIPDR(val) BSP_FLD32(val,24, 31)
 #define TMS570_SPI_PC6_SOMIPDR_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -366,16 +366,16 @@ typedef struct{
 #define TMS570_SPI_PC6_SIMOPDR_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
 
 /* field: SOMIPDR0 - SOMI0 open-drain enable. */
-#define TMS570_SPI_PC6_SOMIPDR0 BSP_FLD32(11)
+#define TMS570_SPI_PC6_SOMIPDR0 BSP_BIT32(11)
 
 /* field: SIMOPDR0 - SPISIMO0 open-drain enable. */
-#define TMS570_SPI_PC6_SIMOPDR0 BSP_FLD32(10)
+#define TMS570_SPI_PC6_SIMOPDR0 BSP_BIT32(10)
 
 /* field: CLKPDR - CLK open drain enable. */
-#define TMS570_SPI_PC6_CLKPDR BSP_FLD32(9)
+#define TMS570_SPI_PC6_CLKPDR BSP_BIT32(9)
 
 /* field: ENAPDR - SPIENA pin open drain enable. */
-#define TMS570_SPI_PC6_ENAPDR BSP_FLD32(8)
+#define TMS570_SPI_PC6_ENAPDR BSP_BIT32(8)
 
 /* field: SCSPDR - SPISCSx open drain enable. */
 #define TMS570_SPI_PC6_SCSPDR(val) BSP_FLD32(val,0, 7)
@@ -383,7 +383,7 @@ typedef struct{
 #define TMS570_SPI_PC6_SCSPDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*-----------------------TMS570_SPIPC7-----------------------*/
+/*-----------------------TMS570_SPI_PC7-----------------------*/
 /* field: SOMIDIS - SOMIx pull control enable/disable. */
 #define TMS570_SPI_PC7_SOMIDIS(val) BSP_FLD32(val,24, 31)
 #define TMS570_SPI_PC7_SOMIDIS_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -395,16 +395,16 @@ typedef struct{
 #define TMS570_SPI_PC7_SIMODIS_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
 
 /* field: SOMIPDIS0 - SPISOMI0 pull control enable/disable. */
-#define TMS570_SPI_PC7_SOMIPDIS0 BSP_FLD32(11)
+#define TMS570_SPI_PC7_SOMIPDIS0 BSP_BIT32(11)
 
 /* field: SIMOPDIS0 - SPISIMO0 pull control enable/disable. */
-#define TMS570_SPI_PC7_SIMOPDIS0 BSP_FLD32(10)
+#define TMS570_SPI_PC7_SIMOPDIS0 BSP_BIT32(10)
 
 /* field: CLKPDIS - CLK pull control enable/disable. */
-#define TMS570_SPI_PC7_CLKPDIS BSP_FLD32(9)
+#define TMS570_SPI_PC7_CLKPDIS BSP_BIT32(9)
 
 /* field: ENAPDIS - ENAPDIS ENABLE pull control enable/disable. */
-#define TMS570_SPI_PC7_ENAPDIS BSP_FLD32(8)
+#define TMS570_SPI_PC7_ENAPDIS BSP_BIT32(8)
 
 /* field: SCSPDIS - SCSx pull control enable/disable. */
 #define TMS570_SPI_PC7_SCSPDIS(val) BSP_FLD32(val,0, 7)
@@ -412,7 +412,7 @@ typedef struct{
 #define TMS570_SPI_PC7_SCSPDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*-----------------------TMS570_SPIPC8-----------------------*/
+/*-----------------------TMS570_SPI_PC8-----------------------*/
 /* field: SOMIPSEL - SPISOMIx pull select. This bit selects the type of pull logic at the SOMIx pin. */
 #define TMS570_SPI_PC8_SOMIPSEL(val) BSP_FLD32(val,24, 31)
 #define TMS570_SPI_PC8_SOMIPSEL_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -424,16 +424,16 @@ typedef struct{
 #define TMS570_SPI_PC8_SIMOPSEL_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
 
 /* field: SOMIPSEL0 - SOMI pull select. This bit selects the type of pull logic at the SOMI pin. */
-#define TMS570_SPI_PC8_SOMIPSEL0 BSP_FLD32(11)
+#define TMS570_SPI_PC8_SOMIPSEL0 BSP_BIT32(11)
 
 /* field: SIMOPSEL0 - SPISIMO pull select. This bit selects the type of pull logic at the SPISIMO pin. */
-#define TMS570_SPI_PC8_SIMOPSEL0 BSP_FLD32(10)
+#define TMS570_SPI_PC8_SIMOPSEL0 BSP_BIT32(10)
 
 /* field: CLKPSEL - CLK pull select. This bit selects the type of pull logic at the CLK pin. */
-#define TMS570_SPI_PC8_CLKPSEL BSP_FLD32(9)
+#define TMS570_SPI_PC8_CLKPSEL BSP_BIT32(9)
 
 /* field: ENAPSEL - ENABLE pull select. This bit selects the type of pull logic at the ENABLE pin. */
-#define TMS570_SPI_PC8_ENAPSEL BSP_FLD32(8)
+#define TMS570_SPI_PC8_ENAPSEL BSP_BIT32(8)
 
 /* field: SCSPSEL - SCSx pull select. This bit selects the type of pull logic at the SCSx pin. */
 #define TMS570_SPI_PC8_SCSPSEL(val) BSP_FLD32(val,0, 7)
@@ -441,19 +441,19 @@ typedef struct{
 #define TMS570_SPI_PC8_SCSPSEL_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*-----------------------TMS570_SPIDAT0-----------------------*/
+/*----------------------TMS570_SPI_DAT0----------------------*/
 /* field: TXDATA - SPI transmit data. When written, these bits will be copied to the shift register if it is empty. */
 #define TMS570_SPI_DAT0_TXDATA(val) BSP_FLD32(val,0, 15)
 #define TMS570_SPI_DAT0_TXDATA_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_SPI_DAT0_TXDATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*-----------------------TMS570_SPIDAT1-----------------------*/
+/*----------------------TMS570_SPI_DAT1----------------------*/
 /* field: CSHOLD - Chip select hold mode. */
-#define TMS570_SPI_DAT1_CSHOLD BSP_FLD32(28)
+#define TMS570_SPI_DAT1_CSHOLD BSP_BIT32(28)
 
 /* field: WDEL - Enable the delay counter at the end of the current transaction. */
-#define TMS570_SPI_DAT1_WDEL BSP_FLD32(26)
+#define TMS570_SPI_DAT1_WDEL BSP_BIT32(26)
 
 /* field: DFSEL - Data word format select */
 #define TMS570_SPI_DAT1_DFSEL(val) BSP_FLD32(val,24, 25)
@@ -471,30 +471,30 @@ typedef struct{
 #define TMS570_SPI_DAT1_TXDATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*-----------------------TMS570_SPIBUF-----------------------*/
+/*-----------------------TMS570_SPI_BUF-----------------------*/
 /* field: RXEMPTY - Receive data buffer empty. */
-#define TMS570_SPI_BUF_RXEMPTY BSP_FLD32(31)
+#define TMS570_SPI_BUF_RXEMPTY BSP_BIT32(31)
 
 /* field: RXOVR - Receive data buffer overrun. */
-#define TMS570_SPI_BUF_RXOVR BSP_FLD32(30)
+#define TMS570_SPI_BUF_RXOVR BSP_BIT32(30)
 
 /* field: TXFULL - Transmit data buffer full.This flag is a read-only flag. */
-#define TMS570_SPI_BUF_TXFULL BSP_FLD32(29)
+#define TMS570_SPI_BUF_TXFULL BSP_BIT32(29)
 
 /* field: BITERR - Bit error.There was a mismatch of internal transmit data and transmitted data. */
-#define TMS570_SPI_BUF_BITERR BSP_FLD32(28)
+#define TMS570_SPI_BUF_BITERR BSP_BIT32(28)
 
 /* field: DESYNC - Desynchronization of slave device.This bit is valid in master mode only. */
-#define TMS570_SPI_BUF_DESYNC BSP_FLD32(27)
+#define TMS570_SPI_BUF_DESYNC BSP_BIT32(27)
 
 /* field: PARITYERR - Parity error.The calculated parity differs from the received parity bit. */
-#define TMS570_SPI_BUF_PARITYERR BSP_FLD32(26)
+#define TMS570_SPI_BUF_PARITYERR BSP_BIT32(26)
 
 /* field: TIMEOUT - Time-out because of non-activation of ENA pin. */
-#define TMS570_SPI_BUF_TIMEOUT BSP_FLD32(25)
+#define TMS570_SPI_BUF_TIMEOUT BSP_BIT32(25)
 
 /* field: DLENERR - Data length error flag. */
-#define TMS570_SPI_BUF_DLENERR BSP_FLD32(24)
+#define TMS570_SPI_BUF_DLENERR BSP_BIT32(24)
 
 /* field: LCSNR - control field. It contains the chip select number that was activated during the last word transfer. */
 #define TMS570_SPI_BUF_LCSNR(val) BSP_FLD32(val,16, 23)
@@ -507,14 +507,14 @@ typedef struct{
 #define TMS570_SPI_BUF_RXDATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*-----------------------TMS570_SPIEMU-----------------------*/
+/*-----------------------TMS570_SPI_EMU-----------------------*/
 /* field: EMU_RXDATA - SPI receive data. The SPI emulation register is a mirror of the SPIBUF register. */
 #define TMS570_SPI_EMU_EMU_RXDATA(val) BSP_FLD32(val,0, 15)
 #define TMS570_SPI_EMU_EMU_RXDATA_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_SPI_EMU_EMU_RXDATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*----------------------TMS570_SPIDELAY----------------------*/
+/*----------------------TMS570_SPI_DELAY----------------------*/
 /* field: C2TDELAY - Chip-select-active to transmit-start delay. See Figure 25-45 for an example. */
 #define TMS570_SPI_DELAY_C2TDELAY(val) BSP_FLD32(val,24, 31)
 #define TMS570_SPI_DELAY_C2TDELAY_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -536,77 +536,77 @@ typedef struct{
 #define TMS570_SPI_DELAY_C2EDELAY_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*-----------------------TMS570_SPIDEF-----------------------*/
+/*-----------------------TMS570_SPI_DEF-----------------------*/
 /* field: CDEF - Chip select default pattern. Master-mode only. */
 #define TMS570_SPI_DEF_CDEF(val) BSP_FLD32(val,0, 7)
 #define TMS570_SPI_DEF_CDEF_GET(reg) BSP_FLD32GET(reg,0, 7)
 #define TMS570_SPI_DEF_CDEF_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*-----------------------TMS570_SPIFMT0-----------------------*/
+/*----------------------TMS570_SPI_FMTx----------------------*/
 /* field: WDELAY - Delay in between transmissions for data format x (x= 0,1,2,3). */
-#define TMS570_SPI_FMT0_WDELAY(val) BSP_FLD32(val,24, 31)
+#define TMS570_SPI_FMTx_WDELAY(val) BSP_FLD32(val,24, 31)
-#define TMS570_SPI_FMT0_WDELAY_GET(reg) BSP_FLD32GET(reg,24, 31)
+#define TMS570_SPI_FMTx_WDELAY_GET(reg) BSP_FLD32GET(reg,24, 31)
-#define TMS570_SPI_FMT0_WDELAY_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
+#define TMS570_SPI_FMTx_WDELAY_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
 
 /* field: PARPOL - Parity polarity: even or odd. PARPOLx can be modified in privilege mode only. */
-#define TMS570_SPI_FMT0_PARPOL BSP_FLD32(23)
+#define TMS570_SPI_FMTx_PARPOL BSP_BIT32(23)
 
 /* field: PARITYENA - Parity enable for data format x. */
-#define TMS570_SPI_FMT0_PARITYENA BSP_FLD32(22)
+#define TMS570_SPI_FMTx_PARITYENA BSP_BIT32(22)
 
 /* field: WAITENA - The master waits for the ENA signal from slave for data format x. */
-#define TMS570_SPI_FMT0_WAITENA BSP_FLD32(21)
+#define TMS570_SPI_FMTx_WAITENA BSP_BIT32(21)
 
 /* field: SHIFTDIR - Shift direction for data format x. */
-#define TMS570_SPI_FMT0_SHIFTDIR BSP_FLD32(20)
+#define TMS570_SPI_FMTx_SHIFTDIR BSP_BIT32(20)
 
 /* field: HDUPLEX_ENAx - Half Duplex transfer mode enable for Data Format x. */
-#define TMS570_SPI_FMT0_HDUPLEX_ENAx BSP_FLD32(19)
+#define TMS570_SPI_FMTx_HDUPLEX_ENAx BSP_BIT32(19)
 
 /* field: DIS_CS_TIMERS - Disable chip-select timers for this format. */
-#define TMS570_SPI_FMT0_DIS_CS_TIMERS BSP_FLD32(18)
+#define TMS570_SPI_FMTx_DIS_CS_TIMERS BSP_BIT32(18)
 
 /* field: POLARITY - POLARITY */
-#define TMS570_SPI_FMT0_POLARITY BSP_FLD32(17)
+#define TMS570_SPI_FMTx_POLARITY BSP_BIT32(17)
 
 /* field: PHASE - SPI data format x clock delay. PHASEx defines the clock delay of data format x. */
-#define TMS570_SPI_FMT0_PHASE BSP_FLD32(16)
+#define TMS570_SPI_FMTx_PHASE BSP_BIT32(16)
 
 /* field: PRESCALE - SPI data format x prescaler. */
-#define TMS570_SPI_FMT0_PRESCALE(val) BSP_FLD32(val,8, 15)
+#define TMS570_SPI_FMTx_PRESCALE(val) BSP_FLD32(val,8, 15)
-#define TMS570_SPI_FMT0_PRESCALE_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_SPI_FMTx_PRESCALE_GET(reg) BSP_FLD32GET(reg,8, 15)
-#define TMS570_SPI_FMT0_PRESCALE_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+#define TMS570_SPI_FMTx_PRESCALE_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
 
 /* field: CHARLEN - SPI data format x data-word length. CHARLENx defines the word length of data format x. */
-#define TMS570_SPI_FMT0_CHARLEN(val) BSP_FLD32(val,0, 4)
+#define TMS570_SPI_FMTx_CHARLEN(val) BSP_FLD32(val,0, 4)
-#define TMS570_SPI_FMT0_CHARLEN_GET(reg) BSP_FLD32GET(reg,0, 4)
+#define TMS570_SPI_FMTx_CHARLEN_GET(reg) BSP_FLD32GET(reg,0, 4)
-#define TMS570_SPI_FMT0_CHARLEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
+#define TMS570_SPI_FMTx_CHARLEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
 
 
-/*---------------------TMS570_SPIINTVECT0---------------------*/
+/*--------------------TMS570_SPI_INTVECT0--------------------*/
 /* field: INTVECT0 - INTVECT0. Interrupt vector for interrupt line INT0. */
 #define TMS570_SPI_INTVECT0_INTVECT0(val) BSP_FLD32(val,1, 5)
 #define TMS570_SPI_INTVECT0_INTVECT0_GET(reg) BSP_FLD32GET(reg,1, 5)
 #define TMS570_SPI_INTVECT0_INTVECT0_SET(reg,val) BSP_FLD32SET(reg, val,1, 5)
 
 /* field: SUSPEND0 - Transfer suspended / Transfer finished interrupt flag. */
-#define TMS570_SPI_INTVECT0_SUSPEND0 BSP_FLD32(0)
+#define TMS570_SPI_INTVECT0_SUSPEND0 BSP_BIT32(0)
 
 
-/*---------------------TMS570_SPIINTVECT1---------------------*/
+/*--------------------TMS570_SPI_INTVECT1--------------------*/
 /* field: INTVECT1 - INTVECT1. Interrupt vector for interrupt line INT1. */
 #define TMS570_SPI_INTVECT1_INTVECT1(val) BSP_FLD32(val,1, 5)
 #define TMS570_SPI_INTVECT1_INTVECT1_GET(reg) BSP_FLD32GET(reg,1, 5)
 #define TMS570_SPI_INTVECT1_INTVECT1_SET(reg,val) BSP_FLD32SET(reg, val,1, 5)
 
 /* field: SUSPEND1 - Transfer suspended / Transfer finished interrupt flag. */
-#define TMS570_SPI_INTVECT1_SUSPEND1 BSP_FLD32(0)
+#define TMS570_SPI_INTVECT1_SUSPEND1 BSP_BIT32(0)
 
 
-/*----------------------TMS570_SPIPMCTRL----------------------*/
+/*---------------------TMS570_SPI_PMCTRL---------------------*/
 /* field: MOD_CLK_POL_3 - Modulo mode SPICLK polarity. */
-#define TMS570_SPI_PMCTRL_MOD_CLK_POL_3 BSP_FLD32(29)
+#define TMS570_SPI_PMCTRL_MOD_CLK_POL_3 BSP_BIT32(29)
 
 /* field: MMODE_3 - These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if */
 #define TMS570_SPI_PMCTRL_MMODE_3(val) BSP_FLD32(val,26, 28)
@@ -619,7 +619,7 @@ typedef struct{
 #define TMS570_SPI_PMCTRL_PMODE_3_SET(reg,val) BSP_FLD32SET(reg, val,24, 25)
 
 /* field: MOD_CLK_POL_2 - Modulo mode SPICLK polarity. */
-#define TMS570_SPI_PMCTRL_MOD_CLK_POL_2 BSP_FLD32(21)
+#define TMS570_SPI_PMCTRL_MOD_CLK_POL_2 BSP_BIT32(21)
 
 /* field: MMODE_2 - These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if */
 #define TMS570_SPI_PMCTRL_MMODE_2(val) BSP_FLD32(val,18, 20)
@@ -632,7 +632,7 @@ typedef struct{
 #define TMS570_SPI_PMCTRL_PMODE_2_SET(reg,val) BSP_FLD32SET(reg, val,16, 17)
 
 /* field: MOD_CLK_POL_1 - Modulo mode SPICLK polarity. */
-#define TMS570_SPI_PMCTRL_MOD_CLK_POL_1 BSP_FLD32(13)
+#define TMS570_SPI_PMCTRL_MOD_CLK_POL_1 BSP_BIT32(13)
 
 /* field: MMODE_1 - These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if */
 #define TMS570_SPI_PMCTRL_MMODE_1(val) BSP_FLD32(val,10, 12)
@@ -645,7 +645,7 @@ typedef struct{
 #define TMS570_SPI_PMCTRL_PMODE_1_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
 
 /* field: MOD_CLK_POL_0 - Modulo mode SPICLK polarity. */
-#define TMS570_SPI_PMCTRL_MOD_CLK_POL_0 BSP_FLD32(5)
+#define TMS570_SPI_PMCTRL_MOD_CLK_POL_0 BSP_BIT32(5)
 
 /* field: MMODE_0 - These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if */
 #define TMS570_SPI_PMCTRL_MMODE_0(val) BSP_FLD32(val,2, 4)
@@ -658,15 +658,15 @@ typedef struct{
 #define TMS570_SPI_PMCTRL_PMODE_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
 
 
-/*---------------------TMS570_SPIMIBSPIE---------------------*/
+/*---------------------TMS570_SPI_MIBSPIE---------------------*/
 /* field: RXRAM_ACCESS - Receive-RAM access control. */
-#define TMS570_SPI_MIBSPIE_RXRAM_ACCESS BSP_FLD32(16)
+#define TMS570_SPI_MIBSPIE_RXRAM_ACCESS BSP_BIT32(16)
 
 /* field: MSPIENA - Multi-buffer mode enable. */
-#define TMS570_SPI_MIBSPIE_MSPIENA BSP_FLD32(0)
+#define TMS570_SPI_MIBSPIE_MSPIENA BSP_BIT32(0)
 
 
-/*---------------------TMS570_SPITGITENST---------------------*/
+/*--------------------TMS570_SPI_TGITENST--------------------*/
 /* field: SET_INTENRDY - TG interrupt set (enable) when transfer finished. */
 #define TMS570_SPI_TGITENST_SET_INTENRDY(val) BSP_FLD32(val,16, 31)
 #define TMS570_SPI_TGITENST_SET_INTENRDY_GET(reg) BSP_FLD32GET(reg,16, 31)
@@ -678,7 +678,7 @@ typedef struct{
 #define TMS570_SPI_TGITENST_SET_INTENSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_SPITGITENCR---------------------*/
+/*--------------------TMS570_SPI_TGITENCR--------------------*/
 /* field: CLR_INTENRDY - TG interrupt clear (disabled) when transfer finished. */
 #define TMS570_SPI_TGITENCR_CLR_INTENRDY(val) BSP_FLD32(val,16, 31)
 #define TMS570_SPI_TGITENCR_CLR_INTENRDY_GET(reg) BSP_FLD32GET(reg,16, 31)
@@ -690,7 +690,7 @@ typedef struct{
 #define TMS570_SPI_TGITENCR_CLR_INTENSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_SPITGITLVST---------------------*/
+/*--------------------TMS570_SPI_TGITLVST--------------------*/
 /* field: SET_INTLVLRDY - Transfer-group completed interrupt level set. */
 #define TMS570_SPI_TGITLVST_SET_INTLVLRDY(val) BSP_FLD32(val,16, 31)
 #define TMS570_SPI_TGITLVST_SET_INTLVLRDY_GET(reg) BSP_FLD32GET(reg,16, 31)
@@ -702,7 +702,7 @@ typedef struct{
 #define TMS570_SPI_TGITLVST_SET_INTLVLSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_SPITGITLVCR---------------------*/
+/*--------------------TMS570_SPI_TGITLVCR--------------------*/
 /* field: CLR_INTLVLRDY - Transfer-group completed interrupt level clear. */
 #define TMS570_SPI_TGITLVCR_CLR_INTLVLRDY(val) BSP_FLD32(val,16, 31)
 #define TMS570_SPI_TGITLVCR_CLR_INTLVLRDY_GET(reg) BSP_FLD32GET(reg,16, 31)
@@ -714,7 +714,7 @@ typedef struct{
 #define TMS570_SPI_TGITLVCR_CLR_INTLVLSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_SPITGINTFLG---------------------*/
+/*--------------------TMS570_SPI_TGINTFLG--------------------*/
 /* field: INTFLGRDY - Transfer-group interrupt flag for a transfer-completed interrupt. */
 #define TMS570_SPI_TGINTFLG_INTFLGRDY(val) BSP_FLD32(val,16, 31)
 #define TMS570_SPI_TGINTFLG_INTFLGRDY_GET(reg) BSP_FLD32GET(reg,16, 31)
@@ -726,12 +726,12 @@ typedef struct{
 #define TMS570_SPI_TGINTFLG_INTFLGSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_SPITICKCNT---------------------*/
+/*---------------------TMS570_SPI_TICKCNT---------------------*/
 /* field: TICKENA - Tick counter enable. */
-#define TMS570_SPI_TICKCNT_TICKENA BSP_FLD32(31)
+#define TMS570_SPI_TICKCNT_TICKENA BSP_BIT32(31)
 
 /* field: RELOAD - Pre-load the tick counter. */
-#define TMS570_SPI_TICKCNT_RELOAD BSP_FLD32(30)
+#define TMS570_SPI_TICKCNT_RELOAD BSP_BIT32(30)
 
 /* field: CLKCTRL - Tick counter clock source control. */
 #define TMS570_SPI_TICKCNT_CLKCTRL(val) BSP_FLD32(val,28, 29)
@@ -744,7 +744,7 @@ typedef struct{
 #define TMS570_SPI_TICKCNT_TICKVALUE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_SPILTGPEND---------------------*/
+/*---------------------TMS570_SPI_LTGPEND---------------------*/
 /* field: TG_IN_SERVICE - The TG number currently being serviced by the sequencer. */
 #define TMS570_SPI_LTGPEND_TG_IN_SERVICE(val) BSP_FLD32(val,24, 28)
 #define TMS570_SPI_LTGPEND_TG_IN_SERVICE_GET(reg) BSP_FLD32GET(reg,24, 28)
@@ -756,23 +756,23 @@ typedef struct{
 #define TMS570_SPI_LTGPEND_LPEND_SET(reg,val) BSP_FLD32SET(reg, val,8, 14)
 
 
-/*----------------------TMS570_SPITGCTRL----------------------*/
+/*---------------------TMS570_SPI_TGCTRL---------------------*/
 /* field: TGENA - TGx enable. */
-#define TMS570_SPI_TGCTRL_TGENA BSP_FLD32(31)
+#define TMS570_SPI_TGCTRL_TGENA BSP_BIT32(31)
 
 /* field: ONESHOTx - Single transfer for TGx. */
-#define TMS570_SPI_TGCTRL_ONESHOTx BSP_FLD32(30)
+#define TMS570_SPI_TGCTRL_ONESHOTx BSP_BIT32(30)
 
 /* field: PRSTx - TGx pointer reset mode. Configures the way to resolve trigger events during an ongoing transfer. */
-#define TMS570_SPI_TGCTRL_PRSTx BSP_FLD32(29)
+#define TMS570_SPI_TGCTRL_PRSTx BSP_BIT32(29)
 
 /* field: TGTDx - TG triggered. */
-#define TMS570_SPI_TGCTRL_TGTDx BSP_FLD32(28)
+#define TMS570_SPI_TGCTRL_TGTDx BSP_BIT32(28)
 
 
-/*---------------------TMS570_SPIDMACTRL---------------------*/
+/*---------------------TMS570_SPI_DMACTRL---------------------*/
 /* field: ONESHOT - Auto-disable of DMA channel after ICOUNT+1 transfers. */
-#define TMS570_SPI_DMACTRL_ONESHOT BSP_FLD32(31)
+#define TMS570_SPI_DMACTRL_ONESHOT BSP_BIT32(31)
 
 /* field: BUFIDx - Buffer utilized for DMA transfer. */
 #define TMS570_SPI_DMACTRL_BUFIDx(val) BSP_FLD32(val,24, 30)
@@ -790,13 +790,13 @@ typedef struct{
 #define TMS570_SPI_DMACTRL_TXDMA_MAPx_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
 
 /* field: RXDMAENAx - Receive data DMA channel enable. */
-#define TMS570_SPI_DMACTRL_RXDMAENAx BSP_FLD32(15)
+#define TMS570_SPI_DMACTRL_RXDMAENAx BSP_BIT32(15)
 
 /* field: TXDAMENAx - Transmit data DMA channel enable. */
-#define TMS570_SPI_DMACTRL_TXDAMENAx BSP_FLD32(14)
+#define TMS570_SPI_DMACTRL_TXDAMENAx BSP_BIT32(14)
 
 /* field: NOBRKx - Non-interleaved DMA block transfer. This bit is available in master mode only. */
-#define TMS570_SPI_DMACTRL_NOBRKx BSP_FLD32(13)
+#define TMS570_SPI_DMACTRL_NOBRKx BSP_BIT32(13)
 
 /* field: ICOUNTx - Initial count of DMA transfers. */
 #define TMS570_SPI_DMACTRL_ICOUNTx(val) BSP_FLD32(val,8, 12)
@@ -804,7 +804,7 @@ typedef struct{
 #define TMS570_SPI_DMACTRL_ICOUNTx_SET(reg,val) BSP_FLD32SET(reg, val,8, 12)
 
 /* field: COUNT_BIT17x - The 17th bit of the COUNT field of DMAxCOUNT register. */
-#define TMS570_SPI_DMACTRL_COUNT_BIT17x BSP_FLD32(6)
+#define TMS570_SPI_DMACTRL_COUNT_BIT17x BSP_BIT32(6)
 
 /* field: COUNTx - Actual number of remaining DMA transfers. */
 #define TMS570_SPI_DMACTRL_COUNTx(val) BSP_FLD32(val,0, 5)
@@ -812,7 +812,7 @@ typedef struct{
 #define TMS570_SPI_DMACTRL_COUNTx_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
 
 
-/*---------------------TMS570_SPIDMACOUNT---------------------*/
+/*--------------------TMS570_SPI_DMACOUNT--------------------*/
 /* field: ICOUNTx - Every time COUNTx hits zero, it is reloaded with ICOUNTx. */
 #define TMS570_SPI_DMACOUNT_ICOUNTx(val) BSP_FLD32(val,16, 31)
 #define TMS570_SPI_DMACOUNT_ICOUNTx_GET(reg) BSP_FLD32GET(reg,16, 31)
@@ -824,14 +824,14 @@ typedef struct{
 #define TMS570_SPI_DMACOUNT_COUNTx_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*--------------------TMS570_SPIDMACNTLEN--------------------*/
+/*--------------------TMS570_SPI_DMACNTLEN--------------------*/
 /* field: LARGE_COUNT - Select either the 16-bit DMAxCOUNT counters or the smaller counters in DMAxCTRL. */
-#define TMS570_SPI_DMACNTLEN_LARGE_COUNT BSP_FLD32(0)
+#define TMS570_SPI_DMACNTLEN_LARGE_COUNT BSP_BIT32(0)
 
 
-/*---------------------TMS570_SPIUERRCTRL---------------------*/
+/*--------------------TMS570_SPI_UERRCTRL--------------------*/
 /* field: PTESTEN - Parity memory test enable. */
-#define TMS570_SPI_UERRCTRL_PTESTEN BSP_FLD32(8)
+#define TMS570_SPI_UERRCTRL_PTESTEN BSP_BIT32(8)
 
 /* field: EDEN - Error detection enable. These bits enable parity error detection. */
 #define TMS570_SPI_UERRCTRL_EDEN(val) BSP_FLD32(val,0, 3)
@@ -839,53 +839,53 @@ typedef struct{
 #define TMS570_SPI_UERRCTRL_EDEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*---------------------TMS570_SPIUERRSTAT---------------------*/
+/*--------------------TMS570_SPI_UERRSTAT--------------------*/
 /* field: EDFLG1 - RXRAM. */
-#define TMS570_SPI_UERRSTAT_EDFLG1 BSP_FLD32(1)
+#define TMS570_SPI_UERRSTAT_EDFLG1 BSP_BIT32(1)
 
 /* field: EDFLG0 - Uncorrectable parity error detection flag. */
-#define TMS570_SPI_UERRSTAT_EDFLG0 BSP_FLD32(0)
+#define TMS570_SPI_UERRSTAT_EDFLG0 BSP_BIT32(0)
 
 
-/*--------------------TMS570_SPIUERRADDRRX--------------------*/
+/*-------------------TMS570_SPI_UERRADDRRX-------------------*/
 /* field: OVERADDR1 - Uncorrectable parity error address for RXRAM. */
 #define TMS570_SPI_UERRADDRRX_OVERADDR1(val) BSP_FLD32(val,0, 9)
 #define TMS570_SPI_UERRADDRRX_OVERADDR1_GET(reg) BSP_FLD32GET(reg,0, 9)
 #define TMS570_SPI_UERRADDRRX_OVERADDR1_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
 
 
-/*--------------------TMS570_SPIUERRADDRTX--------------------*/
+/*-------------------TMS570_SPI_UERRADDRTX-------------------*/
 /* field: UERRADDR0 - a parity error is generated while reading from TXRAM. */
 #define TMS570_SPI_UERRADDRTX_UERRADDR0(val) BSP_FLD32(val,0, 8)
 #define TMS570_SPI_UERRADDRTX_UERRADDR0_GET(reg) BSP_FLD32GET(reg,0, 8)
 #define TMS570_SPI_UERRADDRTX_UERRADDR0_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
 
 
-/*-----------------TMS570_SPIRXOVRN_BUF_ADDR-----------------*/
+/*-----------------TMS570_SPI_RXOVRN_BUF_ADDR-----------------*/
 /* field: RXOVRN_BUF_ADDR - Address in RXRAM at which an overwrite occurred. */
 #define TMS570_SPI_RXOVRN_BUF_ADDR_RXOVRN_BUF_ADDR(val) BSP_FLD32(val,0, 9)
 #define TMS570_SPI_RXOVRN_BUF_ADDR_RXOVRN_BUF_ADDR_GET(reg) BSP_FLD32GET(reg,0, 9)
 #define TMS570_SPI_RXOVRN_BUF_ADDR_RXOVRN_BUF_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
 
 
-/*-------------------TMS570_SPIIOLPBKTSTCR-------------------*/
+/*-------------------TMS570_SPI_IOLPBKTSTCR-------------------*/
 /* field: SCS_FAIL_FLG - Bit indicating a failure on SPISCS pin compare during analog loopback. */
-#define TMS570_SPI_IOLPBKTSTCR_SCS_FAIL_FLG BSP_FLD32(24)
+#define TMS570_SPI_IOLPBKTSTCR_SCS_FAIL_FLG BSP_BIT32(24)
 
 /* field: CTRL_BITERR - Controls inducing of BITERR during I/O loopback test mode. */
-#define TMS570_SPI_IOLPBKTSTCR_CTRL_BITERR BSP_FLD32(20)
+#define TMS570_SPI_IOLPBKTSTCR_CTRL_BITERR BSP_BIT32(20)
 
 /* field: CTRL_DESYNC - Controls inducing of the desync error during I/O loopback test mode. */
-#define TMS570_SPI_IOLPBKTSTCR_CTRL_DESYNC BSP_FLD32(19)
+#define TMS570_SPI_IOLPBKTSTCR_CTRL_DESYNC BSP_BIT32(19)
 
 /* field: CTRL_PARERR - Controls inducing of the parity errors during I/O loopback test mode. */
-#define TMS570_SPI_IOLPBKTSTCR_CTRL_PARERR BSP_FLD32(18)
+#define TMS570_SPI_IOLPBKTSTCR_CTRL_PARERR BSP_BIT32(18)
 
 /* field: CTRL_TIMEOUT - Controls inducing of the timeout error during I/O loopback test mode. */
-#define TMS570_SPI_IOLPBKTSTCR_CTRL_TIMEOUT BSP_FLD32(17)
+#define TMS570_SPI_IOLPBKTSTCR_CTRL_TIMEOUT BSP_BIT32(17)
 
 /* field: CTRL_DLENERR - Controls inducing of the data length error during I/O loopback test mode. */
-#define TMS570_SPI_IOLPBKTSTCR_CTRL_DLENERR BSP_FLD32(16)
+#define TMS570_SPI_IOLPBKTSTCR_CTRL_DLENERR BSP_BIT32(16)
 
 /* field: IOLPBKSTENA - Module I/O loopback test enable key. */
 #define TMS570_SPI_IOLPBKTSTCR_IOLPBKSTENA(val) BSP_FLD32(val,8, 11)
@@ -898,21 +898,21 @@ typedef struct{
 #define TMS570_SPI_IOLPBKTSTCR_ERR_SCS_PIN_SET(reg,val) BSP_FLD32SET(reg, val,3, 5)
 
 /* field: CTRL_SCS_PIN - Enable/disable the injection of an error on the SPISCS[3:0] pins. */
-#define TMS570_SPI_IOLPBKTSTCR_CTRL_SCS_PIN BSP_FLD32(2)
+#define TMS570_SPI_IOLPBKTSTCR_CTRL_SCS_PIN BSP_BIT32(2)
 
 /* field: LPBK_TYPE - Module I/O loopback type (analog/digital). */
-#define TMS570_SPI_IOLPBKTSTCR_LPBK_TYPE BSP_FLD32(1)
+#define TMS570_SPI_IOLPBKTSTCR_LPBK_TYPE BSP_BIT32(1)
 
 /* field: RXP_ENA - Enable analog loopback through the receive pin. */
-#define TMS570_SPI_IOLPBKTSTCR_RXP_ENA BSP_FLD32(0)
+#define TMS570_SPI_IOLPBKTSTCR_RXP_ENA BSP_BIT32(0)
 
 
-/*------------------TMS570_SPIEXT_PRESCALE1------------------*/
+/*------------------TMS570_SPI_EXT_PRESCALEx------------------*/
-/* field: EPRESCALE_FMT1 - EPRESCALE_FMT1. Extended Prescale value for SPIFMT1. */
+/* field: EPRESCALE_FMTx - EPRESCALE_FMTx. Extended Prescale value for SPIFMTx. */
-#define TMS570_SPI_EXT_PRESCALE1_EPRESCALE_FMT1(val) BSP_FLD32(val,16, 26)
+#define TMS570_SPI_EXT_PRESCALEx_EPRESCALE_FMTx(val) BSP_FLD32(val,16, 26)
-#define TMS570_SPI_EXT_PRESCALE1_EPRESCALE_FMT1_GET(reg) BSP_FLD32GET(reg,16, 26)
+#define TMS570_SPI_EXT_PRESCALEx_EPRESCALE_FMTx_GET(reg) BSP_FLD32GET(reg,16, 26)
-#define TMS570_SPI_EXT_PRESCALE1_EPRESCALE_FMT1_SET(reg,val) BSP_FLD32SET(reg, val,16, 26)
+#define TMS570_SPI_EXT_PRESCALEx_EPRESCALE_FMTx_SET(reg,val) BSP_FLD32SET(reg, val,16, 26)
 
 
 
-#endif /* LIBBSP_ARM_tms570_SPI */
+#endif /* LIBBSP_ARM_TMS570_SPI */

c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_stc.h

@@ -36,8 +36,8 @@
  * of the authors and should not be interpreted as representing official policies,
  * either expressed or implied, of the FreeBSD Project.
 */
-#ifndef LIBBSP_ARM_tms570_STC
+#ifndef LIBBSP_ARM_TMS570_STC
-#define LIBBSP_ARM_tms570_STC
+#define LIBBSP_ARM_TMS570_STC
 
 #include <bsp/utility.h>
 
@@ -61,122 +61,92 @@ typedef struct{
 } tms570_stc_t;
 
 
-/*---------------------TMS570_STCSTCGCR0---------------------*/
+/*---------------------TMS570_STC_STCGCR0---------------------*/
 /* field: INTCOUNT - Number of intervals of self-test run */
 #define TMS570_STC_STCGCR0_INTCOUNT(val) BSP_FLD32(val,16, 31)
 #define TMS570_STC_STCGCR0_INTCOUNT_GET(reg) BSP_FLD32GET(reg,16, 31)
 #define TMS570_STC_STCGCR0_INTCOUNT_SET(reg,val) BSP_FLD32SET(reg, val,16, 31)
 
 /* field: RS_CNT - Restart or Continue */
-#define TMS570_STC_STCGCR0_RS_CNT BSP_FLD32(0)
+#define TMS570_STC_STCGCR0_RS_CNT BSP_BIT32(0)
 
 
-/*---------------------TMS570_STCSTCGCR1---------------------*/
+/*---------------------TMS570_STC_STCGCR1---------------------*/
 /* field: STC_ENA - Self-test run enable key */
 #define TMS570_STC_STCGCR1_STC_ENA(val) BSP_FLD32(val,0, 3)
 #define TMS570_STC_STCGCR1_STC_ENA_GET(reg) BSP_FLD32GET(reg,0, 3)
 #define TMS570_STC_STCGCR1_STC_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*----------------------TMS570_STCSTCTPR----------------------*/
+/*---------------------TMS570_STC_STCTPR---------------------*/
 /* field: RTOD - Self-test timeout count preload */
-#define TMS570_STC_STCTPR_RTOD(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_STC_STCTPR_RTOD_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_STC_STCTPR_RTOD_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*--------------------TMS570_STC_STC_CADDR--------------------*/
-/*--------------------TMS570_STCSTC_CADDR--------------------*/
 /* field: ADDR - Current ROM Address */
-#define TMS570_STC_STC_CADDR_ADDR(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_STC_STC_CADDR_ADDR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_STC_STC_CADDR_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*---------------------TMS570_STC_STCCICR---------------------*/
-/*---------------------TMS570_STCSTCCICR---------------------*/
 /* field: N - Interval Number */
 #define TMS570_STC_STCCICR_N(val) BSP_FLD32(val,0, 15)
 #define TMS570_STC_STCCICR_N_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_STC_STCCICR_N_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_STCSTCGSTAT---------------------*/
+/*--------------------TMS570_STC_STCGSTAT--------------------*/
 /* field: TEST_FAIL - Test Fail */
-#define TMS570_STC_STCGSTAT_TEST_FAIL BSP_FLD32(1)
+#define TMS570_STC_STCGSTAT_TEST_FAIL BSP_BIT32(1)
 
 /* field: TEST_DONE - Test Done */
-#define TMS570_STC_STCGSTAT_TEST_DONE BSP_FLD32(0)
+#define TMS570_STC_STCGSTAT_TEST_DONE BSP_BIT32(0)
 
 
-/*---------------------TMS570_STCSTCFSTAT---------------------*/
+/*--------------------TMS570_STC_STCFSTAT--------------------*/
 /* field: TO_ERR - Timeout Error */
-#define TMS570_STC_STCFSTAT_TO_ERR BSP_FLD32(2)
+#define TMS570_STC_STCFSTAT_TO_ERR BSP_BIT32(2)
 
 /* field: CPU2_FAIL - CPU2 failure info */
-#define TMS570_STC_STCFSTAT_CPU2_FAIL BSP_FLD32(1)
+#define TMS570_STC_STCFSTAT_CPU2_FAIL BSP_BIT32(1)
 
 /* field: CPU1_FAIL - CPU1 failure info */
-#define TMS570_STC_STCFSTAT_CPU1_FAIL BSP_FLD32(0)
+#define TMS570_STC_STCFSTAT_CPU1_FAIL BSP_BIT32(0)
 
 
-/*------------------TMS570_STCCPU1_CURMISR3------------------*/
+/*------------------TMS570_STC_CPU1_CURMISR3------------------*/
 /* field: MISR - MISR data from CPU1 */
-#define TMS570_STC_CPU1_CURMISR3_MISR(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_STC_CPU1_CURMISR3_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_STC_CPU1_CURMISR3_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_STC_CPU1_CURMISR2------------------*/
-/*------------------TMS570_STCCPU1_CURMISR2------------------*/
 /* field: MISR - MISR data from CPU1 */
-#define TMS570_STC_CPU1_CURMISR2_MISR(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_STC_CPU1_CURMISR2_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_STC_CPU1_CURMISR2_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_STC_CPU1_CURMISR1------------------*/
-/*------------------TMS570_STCCPU1_CURMISR1------------------*/
 /* field: MISR - MISR data from CPU1 */
-#define TMS570_STC_CPU1_CURMISR1_MISR(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_STC_CPU1_CURMISR1_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_STC_CPU1_CURMISR1_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_STC_CPU1_CURMISR0------------------*/
-/*------------------TMS570_STCCPU1_CURMISR0------------------*/
 /* field: MISR - MISR data from CPU1 */
-#define TMS570_STC_CPU1_CURMISR0_MISR(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_STC_CPU1_CURMISR0_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_STC_CPU1_CURMISR0_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_STC_CPU2_CURMISR3------------------*/
-/*------------------TMS570_STCCPU2_CURMISR3------------------*/
 /* field: MISR - MISR data from CPU2 */
-#define TMS570_STC_CPU2_CURMISR3_MISR(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_STC_CPU2_CURMISR3_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_STC_CPU2_CURMISR3_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_STC_CPU2_CURMISR2------------------*/
-/*------------------TMS570_STCCPU2_CURMISR2------------------*/
 /* field: MISR - MISR data from CPU2 */
-#define TMS570_STC_CPU2_CURMISR2_MISR(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_STC_CPU2_CURMISR2_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_STC_CPU2_CURMISR2_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_STC_CPU2_CURMISR1------------------*/
-/*------------------TMS570_STCCPU2_CURMISR1------------------*/
 /* field: MISR - MISR data from CPU2 */
-#define TMS570_STC_CPU2_CURMISR1_MISR(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_STC_CPU2_CURMISR1_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_STC_CPU2_CURMISR1_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*------------------TMS570_STC_CPU2_CURMISR0------------------*/
-/*------------------TMS570_STCCPU2_CURMISR0------------------*/
 /* field: MISR - MISR data from CPU2 */
-#define TMS570_STC_CPU2_CURMISR0_MISR(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_STC_CPU2_CURMISR0_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_STC_CPU2_CURMISR0_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*--------------------TMS570_STC_STCSCSCR--------------------*/
-/*---------------------TMS570_STCSTCSCSCR---------------------*/
 /* field: FAULT_INS - Enable / Disable fault insertion. */
-#define TMS570_STC_STCSCSCR_FAULT_INS BSP_FLD32(4)
+#define TMS570_STC_STCSCSCR_FAULT_INS BSP_BIT32(4)
 
 /* field: SELF_CHECK_KEY - Signature compare logic self-check enable key */
 #define TMS570_STC_STCSCSCR_SELF_CHECK_KEY(val) BSP_FLD32(val,0, 3)
@@ -185,4 +155,4 @@ typedef struct{
 
 
 
-#endif /* LIBBSP_ARM_tms570_STC */
+#endif /* LIBBSP_ARM_TMS570_STC */

c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_sys.h

@@ -36,8 +36,8 @@
  * of the authors and should not be interpreted as representing official policies,
  * either expressed or implied, of the FreeBSD Project.
 */
-#ifndef LIBBSP_ARM_tms570_SYS1
+#ifndef LIBBSP_ARM_TMS570_SYS1
-#define LIBBSP_ARM_tms570_SYS1
+#define LIBBSP_ARM_TMS570_SYS1
 
 #include <bsp/utility.h>
 
@@ -105,12 +105,12 @@ typedef struct{
 } tms570_sys1_t;
 
 
-/*---------------------TMS570_SYS1SYSPC1---------------------*/
+/*---------------------TMS570_SYS1_SYSPCx---------------------*/
 /* field: ECPCLKFUN - ECLK function. This bit changes the function of the ECLK pin. */
-#define TMS570_SYS1_SYSPC1_ECPCLKFUN BSP_FLD32(0)
+#define TMS570_SYS1_SYSPCx_ECPCLKFUN BSP_BIT32(0)
 
 
-/*----------------------TMS570_SYS1CSDIS----------------------*/
+/*---------------------TMS570_SYS1_CSDIS---------------------*/
 /* field: CLKSROFF - Clock source[7-3] off. */
 #define TMS570_SYS1_CSDIS_CLKSROFF(val) BSP_FLD32(val,3, 7)
 #define TMS570_SYS1_CSDIS_CLKSROFF_GET(reg) BSP_FLD32GET(reg,3, 7)
@@ -122,7 +122,7 @@ typedef struct{
 #define TMS570_SYS1_CSDIS_CLKSROFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
 
 
-/*--------------------TMS570_SYS1CSDISSET--------------------*/
+/*--------------------TMS570_SYS1_CSDISSET--------------------*/
 /* field: SETCLKSR_OFF - Set clock source[7-3] to the disabled state. */
 #define TMS570_SYS1_CSDISSET_SETCLKSR_OFF(val) BSP_FLD32(val,3, 7)
 #define TMS570_SYS1_CSDISSET_SETCLKSR_OFF_GET(reg) BSP_FLD32GET(reg,3, 7)
@@ -134,7 +134,7 @@ typedef struct{
 #define TMS570_SYS1_CSDISSET_SETCLKSR_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
 
 
-/*--------------------TMS570_SYS1CSDISCLR--------------------*/
+/*--------------------TMS570_SYS1_CSDISCLR--------------------*/
 /* field: CLRCLKSR_OFF - Enables clock source[7-3]. */
 #define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF(val) BSP_FLD32(val,3, 7)
 #define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF_GET(reg) BSP_FLD32GET(reg,3, 7)
@@ -146,17 +146,17 @@ typedef struct{
 #define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
 
 
-/*----------------------TMS570_SYS1CDDIS----------------------*/
+/*---------------------TMS570_SYS1_CDDIS---------------------*/
 /* field: VCLKAOFF - VCLKA[4-3] domain off. */
 #define TMS570_SYS1_CDDIS_VCLKAOFF(val) BSP_FLD32(val,10, 11)
 #define TMS570_SYS1_CDDIS_VCLKAOFF_GET(reg) BSP_FLD32GET(reg,10, 11)
 #define TMS570_SYS1_CDDIS_VCLKAOFF_SET(reg,val) BSP_FLD32SET(reg, val,10, 11)
 
 /* field: VCLK3OFF - VCLK3 domain off. */
-#define TMS570_SYS1_CDDIS_VCLK3OFF BSP_FLD32(8)
+#define TMS570_SYS1_CDDIS_VCLK3OFF BSP_BIT32(8)
 
 /* field: RTICLK1OFF - RTICLK1 domain off. */
-#define TMS570_SYS1_CDDIS_RTICLK1OFF BSP_FLD32(6)
+#define TMS570_SYS1_CDDIS_RTICLK1OFF BSP_BIT32(6)
 
 /* field: VCLKAOFF - VCLKA[2-1] domain off. */
 #define TMS570_SYS1_CDDIS_VCLKAOFF(val) BSP_FLD32(val,4, 5)
@@ -164,84 +164,84 @@ typedef struct{
 #define TMS570_SYS1_CDDIS_VCLKAOFF_SET(reg,val) BSP_FLD32SET(reg, val,4, 5)
 
 /* field: VCLK2OFF - VCLK2 domain off. */
-#define TMS570_SYS1_CDDIS_VCLK2OFF BSP_FLD32(3)
+#define TMS570_SYS1_CDDIS_VCLK2OFF BSP_BIT32(3)
 
 /* field: VCLKPOFF - VCLK_periph domain off. */
-#define TMS570_SYS1_CDDIS_VCLKPOFF BSP_FLD32(2)
+#define TMS570_SYS1_CDDIS_VCLKPOFF BSP_BIT32(2)
 
 /* field: HCLKOFF - HCLK and VCLK_sys domains off. */
-#define TMS570_SYS1_CDDIS_HCLKOFF BSP_FLD32(1)
+#define TMS570_SYS1_CDDIS_HCLKOFF BSP_BIT32(1)
 
 /* field: GCLKOFF - GCLK domain off. */
-#define TMS570_SYS1_CDDIS_GCLKOFF BSP_FLD32(0)
+#define TMS570_SYS1_CDDIS_GCLKOFF BSP_BIT32(0)
 
 
-/*--------------------TMS570_SYS1CDDISSET--------------------*/
+/*--------------------TMS570_SYS1_CDDISSET--------------------*/
 /* field: SETVCLKA_OFF - Set VCLKA[4-3] domain. */
 #define TMS570_SYS1_CDDISSET_SETVCLKA_OFF(val) BSP_FLD32(val,10, 11)
 #define TMS570_SYS1_CDDISSET_SETVCLKA_OFF_GET(reg) BSP_FLD32GET(reg,10, 11)
 #define TMS570_SYS1_CDDISSET_SETVCLKA_OFF_SET(reg,val) BSP_FLD32SET(reg, val,10, 11)
 
 /* field: SETVCLK3OFF - Set VCLK3 domain. */
-#define TMS570_SYS1_CDDISSET_SETVCLK3OFF BSP_FLD32(8)
+#define TMS570_SYS1_CDDISSET_SETVCLK3OFF BSP_BIT32(8)
 
 /* field: SETRTI1CLKOFF - Set RTICLK1 domain. */
-#define TMS570_SYS1_CDDISSET_SETRTI1CLKOFF BSP_FLD32(6)
+#define TMS570_SYS1_CDDISSET_SETRTI1CLKOFF BSP_BIT32(6)
 
 /* field: SETTVCLKA2OFF - Set VCLKA2 domain. */
-#define TMS570_SYS1_CDDISSET_SETTVCLKA2OFF BSP_FLD32(5)
+#define TMS570_SYS1_CDDISSET_SETTVCLKA2OFF BSP_BIT32(5)
 
 /* field: SETVCLKA1OFF - Set VCLKA1 domain. */
-#define TMS570_SYS1_CDDISSET_SETVCLKA1OFF BSP_FLD32(4)
+#define TMS570_SYS1_CDDISSET_SETVCLKA1OFF BSP_BIT32(4)
 
 /* field: SETVCLK2OFF - Set VCLK2 domain. */
-#define TMS570_SYS1_CDDISSET_SETVCLK2OFF BSP_FLD32(3)
+#define TMS570_SYS1_CDDISSET_SETVCLK2OFF BSP_BIT32(3)
 
 /* field: SETVCLKPOFF - Set VCLK_periph domain. */
-#define TMS570_SYS1_CDDISSET_SETVCLKPOFF BSP_FLD32(2)
+#define TMS570_SYS1_CDDISSET_SETVCLKPOFF BSP_BIT32(2)
 
 /* field: SETHCLKOFF - Set HCLK and VCLK_sys domains. */
-#define TMS570_SYS1_CDDISSET_SETHCLKOFF BSP_FLD32(1)
+#define TMS570_SYS1_CDDISSET_SETHCLKOFF BSP_BIT32(1)
 
 /* field: SETGCLKOFF - Set GCLK domain. */
-#define TMS570_SYS1_CDDISSET_SETGCLKOFF BSP_FLD32(0)
+#define TMS570_SYS1_CDDISSET_SETGCLKOFF BSP_BIT32(0)
 
 
-/*--------------------TMS570_SYS1CDDISCLR--------------------*/
+/*--------------------TMS570_SYS1_CDDISCLR--------------------*/
 /* field: CLRVCLKAOFF - Clear VCLKA[4-3] domain. */
 #define TMS570_SYS1_CDDISCLR_CLRVCLKAOFF(val) BSP_FLD32(val,10, 11)
 #define TMS570_SYS1_CDDISCLR_CLRVCLKAOFF_GET(reg) BSP_FLD32GET(reg,10, 11)
 #define TMS570_SYS1_CDDISCLR_CLRVCLKAOFF_SET(reg,val) BSP_FLD32SET(reg, val,10, 11)
 
 /* field: Reserved - Reserved */
-#define TMS570_SYS1_CDDISCLR_Reserved BSP_FLD32(9)
+#define TMS570_SYS1_CDDISCLR_Reserved BSP_BIT32(9)
 
 /* field: CLRVCLK3OFF - Clear VCLK3 domain. */
-#define TMS570_SYS1_CDDISCLR_CLRVCLK3OFF BSP_FLD32(8)
+#define TMS570_SYS1_CDDISCLR_CLRVCLK3OFF BSP_BIT32(8)
 
 /* field: CLRRTI1CLKOFF - Clear RTICLK1 domain. */
-#define TMS570_SYS1_CDDISCLR_CLRRTI1CLKOFF BSP_FLD32(6)
+#define TMS570_SYS1_CDDISCLR_CLRRTI1CLKOFF BSP_BIT32(6)
 
 /* field: CLRTVCLKA2OFF - Clear VCLKA2 domain. */
-#define TMS570_SYS1_CDDISCLR_CLRTVCLKA2OFF BSP_FLD32(5)
+#define TMS570_SYS1_CDDISCLR_CLRTVCLKA2OFF BSP_BIT32(5)
 
 /* field: CLRVCLKA1OFF - Clear VCLKA1 domain. */
-#define TMS570_SYS1_CDDISCLR_CLRVCLKA1OFF BSP_FLD32(4)
+#define TMS570_SYS1_CDDISCLR_CLRVCLKA1OFF BSP_BIT32(4)
 
 /* field: CLRVCLK2OFF - Clear VCLK2 domain. */
-#define TMS570_SYS1_CDDISCLR_CLRVCLK2OFF BSP_FLD32(3)
+#define TMS570_SYS1_CDDISCLR_CLRVCLK2OFF BSP_BIT32(3)
 
 /* field: CLRVCLKPOFF - CLRVCLKPOFF */
-#define TMS570_SYS1_CDDISCLR_CLRVCLKPOFF BSP_FLD32(2)
+#define TMS570_SYS1_CDDISCLR_CLRVCLKPOFF BSP_BIT32(2)
 
 /* field: CLRHCLKOFF - Clear HCLK and VCLK_sys domains. */
-#define TMS570_SYS1_CDDISCLR_CLRHCLKOFF BSP_FLD32(1)
+#define TMS570_SYS1_CDDISCLR_CLRHCLKOFF BSP_BIT32(1)
 
 /* field: CLRGCLKOFF - Clear GCLK domain. */
-#define TMS570_SYS1_CDDISCLR_CLRGCLKOFF BSP_FLD32(0)
+#define TMS570_SYS1_CDDISCLR_CLRGCLKOFF BSP_BIT32(0)
 
 
-/*---------------------TMS570_SYS1GHVSRC---------------------*/
+/*---------------------TMS570_SYS1_GHVSRC---------------------*/
 /* field: GHVWAKE - GCLK, HCLK, VCLK, VCLK2 source on wakeup. */
 #define TMS570_SYS1_GHVSRC_GHVWAKE(val) BSP_FLD32(val,24, 27)
 #define TMS570_SYS1_GHVSRC_GHVWAKE_GET(reg) BSP_FLD32GET(reg,24, 27)
@@ -258,7 +258,7 @@ typedef struct{
 #define TMS570_SYS1_GHVSRC_GHVSRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*--------------------TMS570_SYS1VCLKASRC--------------------*/
+/*--------------------TMS570_SYS1_VCLKASRC--------------------*/
 /* field: VCLKA2S - Peripheral asynchronous clock2 source. */
 #define TMS570_SYS1_VCLKASRC_VCLKA2S(val) BSP_FLD32(val,8, 11)
 #define TMS570_SYS1_VCLKASRC_VCLKA2S_GET(reg) BSP_FLD32GET(reg,8, 11)
@@ -270,7 +270,7 @@ typedef struct{
 #define TMS570_SYS1_VCLKASRC_VCLKA1S_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*---------------------TMS570_SYS1RCLKSRC---------------------*/
+/*--------------------TMS570_SYS1_RCLKSRC--------------------*/
 /* field: RTI1DIV - RTI clock1 Divider. */
 #define TMS570_SYS1_RCLKSRC_RTI1DIV(val) BSP_FLD32(val,8, 9)
 #define TMS570_SYS1_RCLKSRC_RTI1DIV_GET(reg) BSP_FLD32GET(reg,8, 9)
@@ -282,7 +282,7 @@ typedef struct{
 #define TMS570_SYS1_RCLKSRC_RTI1SRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*---------------------TMS570_SYS1CSVSTAT---------------------*/
+/*--------------------TMS570_SYS1_CSVSTAT--------------------*/
 /* field: CLKSRV - Clock source[7-0] valid. */
 #define TMS570_SYS1_CSVSTAT_CLKSRV(val) BSP_FLD32(val,3, 7)
 #define TMS570_SYS1_CSVSTAT_CLKSRV_GET(reg) BSP_FLD32GET(reg,3, 7)
@@ -294,7 +294,7 @@ typedef struct{
 #define TMS570_SYS1_CSVSTAT_CLKSR_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
 
 
-/*---------------------TMS570_SYS1MSTGCR---------------------*/
+/*---------------------TMS570_SYS1_MSTGCR---------------------*/
 /* field: ROM_DIV - Prescaler divider bits for ROM clock source. */
 #define TMS570_SYS1_MSTGCR_ROM_DIV(val) BSP_FLD32(val,8, 9)
 #define TMS570_SYS1_MSTGCR_ROM_DIV_GET(reg) BSP_FLD32GET(reg,8, 9)
@@ -306,38 +306,32 @@ typedef struct{
 #define TMS570_SYS1_MSTGCR_MSTGENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*--------------------TMS570_SYS1MINITGCR--------------------*/
+/*--------------------TMS570_SYS1_MINITGCR--------------------*/
 /* field: MINITGENA - Memory hardware initialization global enable key. */
 #define TMS570_SYS1_MINITGCR_MINITGENA(val) BSP_FLD32(val,0, 3)
 #define TMS570_SYS1_MINITGCR_MINITGENA_GET(reg) BSP_FLD32GET(reg,0, 3)
 #define TMS570_SYS1_MINITGCR_MINITGENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*---------------------TMS570_SYS1MSIENA---------------------*/
+/*---------------------TMS570_SYS1_MSIENA---------------------*/
 /* field: MSIENA - PBIST controller and memory initialization enable register. */
-#define TMS570_SYS1_MSIENA_MSIENA(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_SYS1_MSIENA_MSIENA_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_SYS1_MSIENA_MSIENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_SYS1_MSTCGSTAT-------------------*/
-/*--------------------TMS570_SYS1MSTCGSTAT--------------------*/
 /* field: MINIDONE - Memory hardware initialization complete status. */
-#define TMS570_SYS1_MSTCGSTAT_MINIDONE BSP_FLD32(8)
+#define TMS570_SYS1_MSTCGSTAT_MINIDONE BSP_BIT32(8)
 
 /* field: MSTDONE - Memory self-test run complete status. */
-#define TMS570_SYS1_MSTCGSTAT_MSTDONE BSP_FLD32(0)
+#define TMS570_SYS1_MSTCGSTAT_MSTDONE BSP_BIT32(0)
 
 
-/*--------------------TMS570_SYS1MINISTAT--------------------*/
+/*--------------------TMS570_SYS1_MINISTAT--------------------*/
 /* field: MIDONE - Memory hardware initialization status bit. */
-#define TMS570_SYS1_MINISTAT_MIDONE(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_SYS1_MINISTAT_MIDONE_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_SYS1_MINISTAT_MIDONE_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*--------------------TMS570_SYS1_PLLCTL1--------------------*/
-/*---------------------TMS570_SYS1PLLCTL1---------------------*/
 /* field: ROS - Reset on PLL Slip */
-#define TMS570_SYS1_PLLCTL1_ROS BSP_FLD32(31)
+#define TMS570_SYS1_PLLCTL1_ROS BSP_BIT32(31)
 
 /* field: MASK_SLIP - Mask detection of PLL slip */
 #define TMS570_SYS1_PLLCTL1_MASK_SLIP(val) BSP_FLD32(val,29, 30)
@@ -350,7 +344,7 @@ typedef struct{
 #define TMS570_SYS1_PLLCTL1_PLLDIV_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
 
 /* field: ROF - Reset on Oscillator Fail */
-#define TMS570_SYS1_PLLCTL1_ROF BSP_FLD32(23)
+#define TMS570_SYS1_PLLCTL1_ROF BSP_BIT32(23)
 
 /* field: REFCLKDIV - Reference Clock Divider */
 #define TMS570_SYS1_PLLCTL1_REFCLKDIV(val) BSP_FLD32(val,16, 21)
@@ -363,9 +357,9 @@ typedef struct{
 #define TMS570_SYS1_PLLCTL1_PLLMUL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_SYS1PLLCTL2---------------------*/
+/*--------------------TMS570_SYS1_PLLCTL2--------------------*/
 /* field: FMENA - Frequency Modulation Enable. */
-#define TMS570_SYS1_PLLCTL2_FMENA BSP_FLD32(31)
+#define TMS570_SYS1_PLLCTL2_FMENA BSP_BIT32(31)
 
 /* field: SPREADINGRATE - NS = SPREADINGRATE + 1 */
 #define TMS570_SYS1_PLLCTL2_SPREADINGRATE(val) BSP_FLD32(val,22, 30)
@@ -388,12 +382,12 @@ typedef struct{
 #define TMS570_SYS1_PLLCTL2_SPR_AMOUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
 
 
-/*---------------------TMS570_SYS1SYSPC10---------------------*/
+/*--------------------TMS570_SYS1_SYSPC10--------------------*/
 /* field: ECPCLK_SLEW - ECPCLK slew control. This bit controls between the fast or slow slew mode. */
-#define TMS570_SYS1_SYSPC10_ECPCLK_SLEW BSP_FLD32(0)
+#define TMS570_SYS1_SYSPC10_ECPCLK_SLEW BSP_BIT32(0)
 
 
-/*---------------------TMS570_SYS1DIEIDL---------------------*/
+/*---------------------TMS570_SYS1_DIEIDL---------------------*/
 /* field: LOT - These read only bits contain the lower 10 bits of the device lot number. */
 #define TMS570_SYS1_DIEIDL_LOT(val) BSP_FLD32(val,22, 31)
 #define TMS570_SYS1_DIEIDL_LOT_GET(reg) BSP_FLD32GET(reg,22, 31)
@@ -415,19 +409,19 @@ typedef struct{
 #define TMS570_SYS1_DIEIDL_X_WAFER_COORDINATE_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*---------------------TMS570_SYS1DIEIDH---------------------*/
+/*---------------------TMS570_SYS1_DIEIDH---------------------*/
 /* field: LOT - This read-only register contains the upper 14 bits of the device lot number. */
 #define TMS570_SYS1_DIEIDH_LOT(val) BSP_FLD32(val,0, 13)
 #define TMS570_SYS1_DIEIDH_LOT_GET(reg) BSP_FLD32GET(reg,0, 13)
 #define TMS570_SYS1_DIEIDH_LOT_SET(reg,val) BSP_FLD32SET(reg, val,0, 13)
 
 
-/*--------------------TMS570_SYS1LPOMONCTL--------------------*/
+/*-------------------TMS570_SYS1_LPOMONCTL-------------------*/
 /* field: BIAS_ENABLE - Bias enable. */
-#define TMS570_SYS1_LPOMONCTL_BIAS_ENABLE BSP_FLD32(24)
+#define TMS570_SYS1_LPOMONCTL_BIAS_ENABLE BSP_BIT32(24)
 
 /* field: OSCFRQCONFIGCNT - Configures the counter based on OSC frequency. */
-#define TMS570_SYS1_LPOMONCTL_OSCFRQCONFIGCNT BSP_FLD32(16)
+#define TMS570_SYS1_LPOMONCTL_OSCFRQCONFIGCNT BSP_BIT32(16)
 
 /* field: HFTRIM - High frequency oscillator trim value. */
 #define TMS570_SYS1_LPOMONCTL_HFTRIM(val) BSP_FLD32(val,8, 12)
@@ -435,15 +429,15 @@ typedef struct{
 #define TMS570_SYS1_LPOMONCTL_HFTRIM_SET(reg,val) BSP_FLD32SET(reg, val,8, 12)
 
 
-/*---------------------TMS570_SYS1CLKTEST---------------------*/
+/*--------------------TMS570_SYS1_CLKTEST--------------------*/
 /* field: ALTLIMPCLOCKENABLE - This bit selects a clock driven by the GIOB[0] pin as an alternate limp clock to the clock */
-#define TMS570_SYS1_CLKTEST_ALTLIMPCLOCKENABLE BSP_FLD32(26)
+#define TMS570_SYS1_CLKTEST_ALTLIMPCLOCKENABLE BSP_BIT32(26)
 
 /* field: RANGEDETCTRL - Range detection control. */
-#define TMS570_SYS1_CLKTEST_RANGEDETCTRL BSP_FLD32(25)
+#define TMS570_SYS1_CLKTEST_RANGEDETCTRL BSP_BIT32(25)
 
 /* field: RANGEDETENASSEL - Selects range detection enable. This bit resets asynchronously on power on reset. */
-#define TMS570_SYS1_CLKTEST_RANGEDETENASSEL BSP_FLD32(24)
+#define TMS570_SYS1_CLKTEST_RANGEDETENASSEL BSP_BIT32(24)
 
 /* field: CLK_TEST_EN - Clock test enable. This bit enables the clock going to the ECLK pin. */
 #define TMS570_SYS1_CLKTEST_CLK_TEST_EN(val) BSP_FLD32(val,16, 19)
@@ -461,7 +455,7 @@ typedef struct{
 #define TMS570_SYS1_CLKTEST_SEL_ECP_PIN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*-------------------TMS570_SYS1DFTCTRLREG1-------------------*/
+/*------------------TMS570_SYS1_DFTCTRLREG1------------------*/
 /* field: DFTWRITE - DFT logic access. */
 #define TMS570_SYS1_DFTCTRLREG1_DFTWRITE(val) BSP_FLD32(val,12, 13)
 #define TMS570_SYS1_DFTCTRLREG1_DFTWRITE_GET(reg) BSP_FLD32GET(reg,12, 13)
@@ -478,7 +472,7 @@ typedef struct{
 #define TMS570_SYS1_DFTCTRLREG1_TEST_MODE_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*-------------------TMS570_SYS1DFTCTRLREG2-------------------*/
+/*------------------TMS570_SYS1_DFTCTRLREG2------------------*/
 /* field: IMPDF - DFT Implementation defined bits. */
 #define TMS570_SYS1_DFTCTRLREG2_IMPDF(val) BSP_FLD32(val,4, 31)
 #define TMS570_SYS1_DFTCTRLREG2_IMPDF_GET(reg) BSP_FLD32GET(reg,4, 31)
@@ -490,9 +484,9 @@ typedef struct{
 #define TMS570_SYS1_DFTCTRLREG2_TEST_MODE_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*---------------------TMS570_SYS1GPREG1---------------------*/
+/*---------------------TMS570_SYS1_GPREG1---------------------*/
 /* field: EMIF_FUNC - Enable EMIF functions to be output. */
-#define TMS570_SYS1_GPREG1_EMIF_FUNC BSP_FLD32(31)
+#define TMS570_SYS1_GPREG1_EMIF_FUNC BSP_BIT32(31)
 
 /* field: PLL1_FBSLIP_FILTER__COUNT - FBSLIP down counter programmed value. */
 #define TMS570_SYS1_GPREG1_PLL1_FBSLIP_FILTER__COUNT(val) BSP_FLD32(val,20, 25)
@@ -510,56 +504,53 @@ typedef struct{
 #define TMS570_SYS1_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*--------------------TMS570_SYS1IMPFASTS--------------------*/
+/*--------------------TMS570_SYS1_IMPFASTS--------------------*/
 /* field: ECPCLKFUN - ECLK function. This bit changes the function of the ECLK pin. */
-#define TMS570_SYS1_IMPFASTS_ECPCLKFUN BSP_FLD32(0)
+#define TMS570_SYS1_IMPFASTS_ECPCLKFUN BSP_BIT32(0)
 
 
-/*--------------------TMS570_SYS1IMPFTADD--------------------*/
+/*--------------------TMS570_SYS1_IMPFTADD--------------------*/
 /* field: IMPFTADD - These bits contain the fault address when an imprecise abort occurs. */
-#define TMS570_SYS1_IMPFTADD_IMPFTADD(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_SYS1_IMPFTADD_IMPFTADD_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_SYS1_IMPFTADD_IMPFTADD_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*---------------------TMS570_SYS1_SSIRx---------------------*/
-/*----------------------TMS570_SYS1SSIR1----------------------*/
 /* field: SSKEY1 - System software interrupt request key. A 075h written to these bits initiates IRQ/FIQ interrupts. */
-#define TMS570_SYS1_SSIR1_SSKEY1(val) BSP_FLD32(val,8, 15)
+#define TMS570_SYS1_SSIRx_SSKEY1(val) BSP_FLD32(val,8, 15)
-#define TMS570_SYS1_SSIR1_SSKEY1_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_SYS1_SSIRx_SSKEY1_GET(reg) BSP_FLD32GET(reg,8, 15)
-#define TMS570_SYS1_SSIR1_SSKEY1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+#define TMS570_SYS1_SSIRx_SSKEY1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
 
 /* field: SSDATA1 - System software interrupt data. These bits contain user read/write register bits. */
-#define TMS570_SYS1_SSIR1_SSDATA1(val) BSP_FLD32(val,0, 7)
+#define TMS570_SYS1_SSIRx_SSDATA1(val) BSP_FLD32(val,0, 7)
-#define TMS570_SYS1_SSIR1_SSDATA1_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_SYS1_SSIRx_SSDATA1_GET(reg) BSP_FLD32GET(reg,0, 7)
-#define TMS570_SYS1_SSIR1_SSDATA1_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+#define TMS570_SYS1_SSIRx_SSDATA1_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*---------------------TMS570_SYS1RAMGCR---------------------*/
+/*---------------------TMS570_SYS1_RAMGCR---------------------*/
 /* field: RAM_DFT_EN - Functional mode RAM DFT (Design For Test) port enable key. */
 #define TMS570_SYS1_RAMGCR_RAM_DFT_EN(val) BSP_FLD32(val,16, 19)
 #define TMS570_SYS1_RAMGCR_RAM_DFT_EN_GET(reg) BSP_FLD32GET(reg,16, 19)
 #define TMS570_SYS1_RAMGCR_RAM_DFT_EN_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
 
 /* field: WST_AENA0 - eSRAM data phase wait state enable bit. */
-#define TMS570_SYS1_RAMGCR_WST_AENA0 BSP_FLD32(2)
+#define TMS570_SYS1_RAMGCR_WST_AENA0 BSP_BIT32(2)
 
 /* field: WST_DENA0 - eSRAM data phase wait state enable bit. */
-#define TMS570_SYS1_RAMGCR_WST_DENA0 BSP_FLD32(0)
+#define TMS570_SYS1_RAMGCR_WST_DENA0 BSP_BIT32(0)
 
 
-/*---------------------TMS570_SYS1BMMCR1---------------------*/
+/*---------------------TMS570_SYS1_BMMCR1---------------------*/
 /* field: MEMSW - Memory swap key. */
 #define TMS570_SYS1_BMMCR1_MEMSW(val) BSP_FLD32(val,0, 3)
 #define TMS570_SYS1_BMMCR1_MEMSW_GET(reg) BSP_FLD32GET(reg,0, 3)
 #define TMS570_SYS1_BMMCR1_MEMSW_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*--------------------TMS570_SYS1CPURSTCR--------------------*/
+/*--------------------TMS570_SYS1_CPURSTCR--------------------*/
 /* field: CPU_RESET - CPU Reset. */
-#define TMS570_SYS1_CPURSTCR_CPU_RESET BSP_FLD32(0)
+#define TMS570_SYS1_CPURSTCR_CPU_RESET BSP_BIT32(0)
 
 
-/*---------------------TMS570_SYS1CLKCNTL---------------------*/
+/*--------------------TMS570_SYS1_CLKCNTL--------------------*/
 /* field: VCLK2R - VBUS clock2 ratio. */
 #define TMS570_SYS1_CLKCNTL_VCLK2R(val) BSP_FLD32(val,24, 27)
 #define TMS570_SYS1_CLKCNTL_VCLK2R_GET(reg) BSP_FLD32GET(reg,24, 27)
@@ -571,15 +562,15 @@ typedef struct{
 #define TMS570_SYS1_CLKCNTL_VCLKR_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
 
 /* field: PENA - Peripheral enable bit. */
-#define TMS570_SYS1_CLKCNTL_PENA BSP_FLD32(8)
+#define TMS570_SYS1_CLKCNTL_PENA BSP_BIT32(8)
 
 
-/*---------------------TMS570_SYS1ECPCNTL---------------------*/
+/*--------------------TMS570_SYS1_ECPCNTL--------------------*/
 /* field: ECPSSEL - This bit allows the selection between VCLK and OSCIN as the clock source for ECLK. */
-#define TMS570_SYS1_ECPCNTL_ECPSSEL BSP_FLD32(24)
+#define TMS570_SYS1_ECPCNTL_ECPSSEL BSP_BIT32(24)
 
 /* field: ECPCOS - ECP continue on suspend. */
-#define TMS570_SYS1_ECPCNTL_ECPCOS BSP_FLD32(23)
+#define TMS570_SYS1_ECPCNTL_ECPCOS BSP_BIT32(23)
 
 /* field: ECPINSEL - Select ECP input clock source. */
 #define TMS570_SYS1_ECPCNTL_ECPINSEL(val) BSP_FLD32(val,6, 17)
@@ -592,64 +583,64 @@ typedef struct{
 #define TMS570_SYS1_ECPCNTL_ECPDIV_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*---------------------TMS570_SYS1DEVCR1---------------------*/
+/*---------------------TMS570_SYS1_DEVCR1---------------------*/
 /* field: DEVPARSEL - Device parity select bit key. */
 #define TMS570_SYS1_DEVCR1_DEVPARSEL(val) BSP_FLD32(val,0, 3)
 #define TMS570_SYS1_DEVCR1_DEVPARSEL_GET(reg) BSP_FLD32GET(reg,0, 3)
 #define TMS570_SYS1_DEVCR1_DEVPARSEL_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*---------------------TMS570_SYS1SYSECR---------------------*/
+/*---------------------TMS570_SYS1_SYSECR---------------------*/
 /* field: RESET - Software reset bits. Setting RESET1 or clearing RESET0 causes a system software reset. */
 #define TMS570_SYS1_SYSECR_RESET(val) BSP_FLD32(val,14, 15)
 #define TMS570_SYS1_SYSECR_RESET_GET(reg) BSP_FLD32GET(reg,14, 15)
 #define TMS570_SYS1_SYSECR_RESET_SET(reg,val) BSP_FLD32SET(reg, val,14, 15)
 
 
-/*---------------------TMS570_SYS1SYSESR---------------------*/
+/*---------------------TMS570_SYS1_SYSESR---------------------*/
 /* field: PORST - Power-up reset. This bit is set when VCCOR (VCC Out of Range) is detected. */
-#define TMS570_SYS1_SYSESR_PORST BSP_FLD32(15)
+#define TMS570_SYS1_SYSESR_PORST BSP_BIT32(15)
 
 /* field: OSCRST - Reset caused by an oscillator failure or PLL cycle slip. */
-#define TMS570_SYS1_SYSESR_OSCRST BSP_FLD32(14)
+#define TMS570_SYS1_SYSESR_OSCRST BSP_BIT32(14)
 
 /* field: WDRST - Watchdog reset flag. */
-#define TMS570_SYS1_SYSESR_WDRST BSP_FLD32(13)
+#define TMS570_SYS1_SYSESR_WDRST BSP_BIT32(13)
 
 /* field: CPURST - CPU reset flag. This bit is set when the CPU is reset. */
-#define TMS570_SYS1_SYSESR_CPURST BSP_FLD32(5)
+#define TMS570_SYS1_SYSESR_CPURST BSP_BIT32(5)
 
 /* field: SWRST - Software reset flag. This bit is set when a software system reset has occurred. */
-#define TMS570_SYS1_SYSESR_SWRST BSP_FLD32(4)
+#define TMS570_SYS1_SYSESR_SWRST BSP_BIT32(4)
 
 /* field: EXTRST - External reset flag. This bit is set when a reset is caused by the external reset pin nRST. */
-#define TMS570_SYS1_SYSESR_EXTRST BSP_FLD32(3)
+#define TMS570_SYS1_SYSESR_EXTRST BSP_BIT32(3)
 
 /* field: MPMODE - This indicates the current memory protection unit (MPU) mode. */
-#define TMS570_SYS1_SYSESR_MPMODE BSP_FLD32(0)
+#define TMS570_SYS1_SYSESR_MPMODE BSP_BIT32(0)
 
 
-/*---------------------TMS570_SYS1SYSTASR---------------------*/
+/*--------------------TMS570_SYS1_SYSTASR--------------------*/
 /* field: EFUSE_Abort - Test Abort status flag. */
 #define TMS570_SYS1_SYSTASR_EFUSE_Abort(val) BSP_FLD32(val,0, 4)
 #define TMS570_SYS1_SYSTASR_EFUSE_Abort_GET(reg) BSP_FLD32GET(reg,0, 4)
 #define TMS570_SYS1_SYSTASR_EFUSE_Abort_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
 
 
-/*---------------------TMS570_SYS1GLBSTAT---------------------*/
+/*--------------------TMS570_SYS1_GLBSTAT--------------------*/
 /* field: FBSLIP - PLL over cycle slip detection. */
-#define TMS570_SYS1_GLBSTAT_FBSLIP BSP_FLD32(9)
+#define TMS570_SYS1_GLBSTAT_FBSLIP BSP_BIT32(9)
 
 /* field: RFSLIP - PLL under cycle slip detection. */
-#define TMS570_SYS1_GLBSTAT_RFSLIP BSP_FLD32(8)
+#define TMS570_SYS1_GLBSTAT_RFSLIP BSP_BIT32(8)
 
 /* field: OSCFAIL - Oscillator fail flag bit. */
-#define TMS570_SYS1_GLBSTAT_OSCFAIL BSP_FLD32(0)
+#define TMS570_SYS1_GLBSTAT_OSCFAIL BSP_BIT32(0)
 
 
-/*----------------------TMS570_SYS1DEVID----------------------*/
+/*---------------------TMS570_SYS1_DEVID---------------------*/
 /* field: CP15 - CP15 CPU. This bit indicates whether the CPU has a coprocessor 15 (CP15). */
-#define TMS570_SYS1_DEVID_CP15 BSP_FLD32(31)
+#define TMS570_SYS1_DEVID_CP15 BSP_BIT32(31)
 
 /* field: TECH - These bits define the process technology by which the device was manufactured. */
 #define TMS570_SYS1_DEVID_TECH(val) BSP_FLD32(val,13, 16)
@@ -657,10 +648,10 @@ typedef struct{
 #define TMS570_SYS1_DEVID_TECH_SET(reg,val) BSP_FLD32SET(reg, val,13, 16)
 
 /* field: I_O_VOLTAGE - Input/output voltage. This bit defines the I/O voltage of the device. */
-#define TMS570_SYS1_DEVID_I_O_VOLTAGE BSP_FLD32(12)
+#define TMS570_SYS1_DEVID_I_O_VOLTAGE BSP_BIT32(12)
 
 /* field: PERIPHERAL_PARITY - The peripheral memories have no parity. */
-#define TMS570_SYS1_DEVID_PERIPHERAL_PARITY BSP_FLD32(11)
+#define TMS570_SYS1_DEVID_PERIPHERAL_PARITY BSP_BIT32(11)
 
 /* field: FLASH_ECC - These bits indicate which parity is present for the program memory. */
 #define TMS570_SYS1_DEVID_FLASH_ECC(val) BSP_FLD32(val,9, 10)
@@ -668,7 +659,7 @@ typedef struct{
 #define TMS570_SYS1_DEVID_FLASH_ECC_SET(reg,val) BSP_FLD32SET(reg, val,9, 10)
 
 /* field: RAM_ECC - RAM ECC. This bit indicates whether or not RAM memory ECC is present. */
-#define TMS570_SYS1_DEVID_RAM_ECC BSP_FLD32(8)
+#define TMS570_SYS1_DEVID_RAM_ECC BSP_BIT32(8)
 
 /* field: VERSION - Version. These bits provide the revision of the device. */
 #define TMS570_SYS1_DEVID_VERSION(val) BSP_FLD32(val,3, 7)
@@ -681,7 +672,7 @@ typedef struct{
 #define TMS570_SYS1_DEVID_PLATFORM_ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
 
 
-/*---------------------TMS570_SYS1SSIVEC---------------------*/
+/*---------------------TMS570_SYS1_SSIVEC---------------------*/
 /* field: SSIDATA - System software interrupt data key. */
 #define TMS570_SYS1_SSIVEC_SSIDATA(val) BSP_FLD32(val,8, 15)
 #define TMS570_SYS1_SSIVEC_SSIDATA_GET(reg) BSP_FLD32GET(reg,8, 15)
@@ -693,7 +684,7 @@ typedef struct{
 #define TMS570_SYS1_SSIVEC_SSIVECT_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*----------------------TMS570_SYS1SSIF----------------------*/
+/*----------------------TMS570_SYS1_SSIF----------------------*/
 /* field: SSI_FLAG - System software interrupt flag[4-1]. */
 #define TMS570_SYS1_SSIF_SSI_FLAG(val) BSP_FLD32(val,0, 3)
 #define TMS570_SYS1_SSIF_SSI_FLAG_GET(reg) BSP_FLD32GET(reg,0, 3)
@@ -701,4 +692,4 @@ typedef struct{
 
 
 
-#endif /* LIBBSP_ARM_tms570_SYS1 */
+#endif /* LIBBSP_ARM_TMS570_SYS1 */

c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_sys2.h

@@ -36,8 +36,8 @@
  * of the authors and should not be interpreted as representing official policies,
  * either expressed or implied, of the FreeBSD Project.
 */
-#ifndef LIBBSP_ARM_tms570_SYS2
+#ifndef LIBBSP_ARM_TMS570_SYS2
-#define LIBBSP_ARM_tms570_SYS2
+#define LIBBSP_ARM_TMS570_SYS2
 
 #include <bsp/utility.h>
 
@@ -61,7 +61,7 @@ typedef struct{
 } tms570_sys2_t;
 
 
-/*---------------------TMS570_SYS2PLLCTL3---------------------*/
+/*--------------------TMS570_SYS2_PLLCTL3--------------------*/
 /* field: ODPLL2 - Internal PLL Output Divider */
 #define TMS570_SYS2_PLLCTL3_ODPLL2(val) BSP_FLD32(val,29, 31)
 #define TMS570_SYS2_PLLCTL3_ODPLL2_GET(reg) BSP_FLD32GET(reg,29, 31)
@@ -83,19 +83,19 @@ typedef struct{
 #define TMS570_SYS2_PLLCTL3_PLLMUL2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*--------------------TMS570_SYS2STCCLKDIV--------------------*/
+/*-------------------TMS570_SYS2_STCCLKDIV-------------------*/
 /* field: CLKDIV - Clock divider/prescaler for CPU clock during logic BIST */
 #define TMS570_SYS2_STCCLKDIV_CLKDIV(val) BSP_FLD32(val,24, 26)
 #define TMS570_SYS2_STCCLKDIV_CLKDIV_GET(reg) BSP_FLD32GET(reg,24, 26)
 #define TMS570_SYS2_STCCLKDIV_CLKDIV_SET(reg,val) BSP_FLD32SET(reg, val,24, 26)
 
 
-/*---------------------TMS570_SYS2ECPCNTL---------------------*/
+/*--------------------TMS570_SYS2_ECPCNTL--------------------*/
 /* field: ECPSSEL - This bit allows the selection between VCLK and OSCIN as the clock source for ECLK. */
-#define TMS570_SYS2_ECPCNTL_ECPSSEL BSP_FLD32(24)
+#define TMS570_SYS2_ECPCNTL_ECPSSEL BSP_BIT32(24)
 
 /* field: ECPCOS - ECP continue on suspend. */
-#define TMS570_SYS2_ECPCNTL_ECPCOS BSP_FLD32(23)
+#define TMS570_SYS2_ECPCNTL_ECPCOS BSP_BIT32(23)
 
 /* field: ECPINSEL - Select ECP input clock source. */
 #define TMS570_SYS2_ECPCNTL_ECPINSEL(val) BSP_FLD32(val,6, 17)
@@ -108,21 +108,21 @@ typedef struct{
 #define TMS570_SYS2_ECPCNTL_ECPDIV_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*--------------------TMS570_SYS2CLK2CNTRL--------------------*/
+/*-------------------TMS570_SYS2_CLK2CNTRL-------------------*/
 /* field: VCLK3R - VBUS clock3 ratio. */
 #define TMS570_SYS2_CLK2CNTRL_VCLK3R(val) BSP_FLD32(val,0, 3)
 #define TMS570_SYS2_CLK2CNTRL_VCLK3R_GET(reg) BSP_FLD32GET(reg,0, 3)
 #define TMS570_SYS2_CLK2CNTRL_VCLK3R_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*--------------------TMS570_SYS2VCLKACON1--------------------*/
+/*-------------------TMS570_SYS2_VCLKACON1-------------------*/
 /* field: VCLKA4R - Clock divider for the VCLKA4 source. Output will be present on VCLKA4_DIVR. */
 #define TMS570_SYS2_VCLKACON1_VCLKA4R(val) BSP_FLD32(val,24, 26)
 #define TMS570_SYS2_VCLKACON1_VCLKA4R_GET(reg) BSP_FLD32GET(reg,24, 26)
 #define TMS570_SYS2_VCLKACON1_VCLKA4R_SET(reg,val) BSP_FLD32SET(reg, val,24, 26)
 
 /* field: VCLKA4_DIV_CDDIS - Disable the VCLKA4 divider output. */
-#define TMS570_SYS2_VCLKACON1_VCLKA4_DIV_CDDIS BSP_FLD32(20)
+#define TMS570_SYS2_VCLKACON1_VCLKA4_DIV_CDDIS BSP_BIT32(20)
 
 /* field: VCLKA4S - Peripheral asynchronous clock4 source. */
 #define TMS570_SYS2_VCLKACON1_VCLKA4S(val) BSP_FLD32(val,16, 19)
@@ -135,7 +135,7 @@ typedef struct{
 #define TMS570_SYS2_VCLKACON1_VCLKA3R_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
 
 /* field: VCLKA3_DIV_CDDIS - Disable the VCLKA3 divider output. */
-#define TMS570_SYS2_VCLKACON1_VCLKA3_DIV_CDDIS BSP_FLD32(4)
+#define TMS570_SYS2_VCLKACON1_VCLKA3_DIV_CDDIS BSP_BIT32(4)
 
 /* field: VCLKA3S - Peripheral asynchronous clock3 source. */
 #define TMS570_SYS2_VCLKACON1_VCLKA3S(val) BSP_FLD32(val,0, 3)
@@ -143,7 +143,7 @@ typedef struct{
 #define TMS570_SYS2_VCLKACON1_VCLKA3S_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*---------------------TMS570_SYS2CLKSLIP---------------------*/
+/*--------------------TMS570_SYS2_CLKSLIP--------------------*/
 /* field: PLL1_SLIP_FILTER_COUNT - Configure the count for the filtered PLL slip. Count is on 10M clock. */
 #define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_COUNT(val) BSP_FLD32(val,8, 13)
 #define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_COUNT_GET(reg) BSP_FLD32GET(reg,8, 13)
@@ -155,19 +155,16 @@ typedef struct{
 #define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*-------------------TMS570_SYS2EFC_CTLREG-------------------*/
+/*-------------------TMS570_SYS2_EFC_CTLREG-------------------*/
 /* field: EFC_INSTR_WEN - Enable user write of 4 EFUSE controller instructions. */
 #define TMS570_SYS2_EFC_CTLREG_EFC_INSTR_WEN(val) BSP_FLD32(val,0, 3)
 #define TMS570_SYS2_EFC_CTLREG_EFC_INSTR_WEN_GET(reg) BSP_FLD32GET(reg,0, 3)
 #define TMS570_SYS2_EFC_CTLREG_EFC_INSTR_WEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*-------------------TMS570_SYS2DIEDL_REG0-------------------*/
+/*-----------------------TMS570_SYS2_x-----------------------*/
 /* field: DIE - This read-only register contains the lower/upper word (31:0) of the die ID information. */
-#define TMS570_SYS2_DIEDL_REG0_DIE(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_SYS2_DIEDL_REG0_DIE_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_SYS2_DIEDL_REG0_DIE_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
 
-
+#endif /* LIBBSP_ARM_TMS570_SYS2 */
-#endif /* LIBBSP_ARM_tms570_SYS2 */

c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_tcr.h

@@ -36,8 +36,8 @@
  * of the authors and should not be interpreted as representing official policies,
  * either expressed or implied, of the FreeBSD Project.
 */
-#ifndef LIBBSP_ARM_tms570_TCR
+#ifndef LIBBSP_ARM_TMS570_TCR
-#define LIBBSP_ARM_tms570_TCR
+#define LIBBSP_ARM_TMS570_TCR
 
 #include <bsp/utility.h>
 
@@ -47,21 +47,21 @@ typedef struct{
 } tms570_tcr_t;
 
 
-/*-----------------------TMS570_TCRTCR-----------------------*/
+/*-----------------------TMS570_TCR_TCR-----------------------*/
 /* field: STXR - Set Transmit Request. */
-#define TMS570_TCR_TCR_STXR BSP_FLD32(18)
+#define TMS570_TCR_TCR_STXR BSP_BIT32(18)
 
 /* field: THTSM - Transfer Header to System Memory. */
-#define TMS570_TCR_TCR_THTSM BSP_FLD32(17)
+#define TMS570_TCR_TCR_THTSM BSP_BIT32(17)
 
 /* field: TPTSM - Transfer Payload to System Memory. */
-#define TMS570_TCR_TCR_TPTSM BSP_FLD32(16)
+#define TMS570_TCR_TCR_TPTSM BSP_BIT32(16)
 
 /* field: THTCC - Transfer Header to Communication Controller. */
-#define TMS570_TCR_TCR_THTCC BSP_FLD32(15)
+#define TMS570_TCR_TCR_THTCC BSP_BIT32(15)
 
 /* field: TPTCC - Transfer Payload to Communication Controller. */
-#define TMS570_TCR_TCR_TPTCC BSP_FLD32(14)
+#define TMS570_TCR_TCR_TPTCC BSP_BIT32(14)
 
 /* field: TSO - Transfer Start Offset. */
 #define TMS570_TCR_TCR_TSO(val) BSP_FLD32(val,0, 13)
@@ -69,16 +69,16 @@ typedef struct{
 #define TMS570_TCR_TCR_TSO_SET(reg,val) BSP_FLD32SET(reg, val,0, 13)
 
 
-/*--------------------TMS570_TCRTCR_Parity--------------------*/
+/*-------------------TMS570_TCR_TCR_Parity-------------------*/
 /* field: PAB2 - Parity Bit for TCRx Byte 2. Parity information for byte 2 of TCRx(18-16). */
-#define TMS570_TCR_TCR_Parity_PAB2 BSP_FLD32(16)
+#define TMS570_TCR_TCR_Parity_PAB2 BSP_BIT32(16)
 
 /* field: PAB1 - Parity Bit for TCRx Byte 1. Parity information for byte 1 of TCRx(15:8). */
-#define TMS570_TCR_TCR_Parity_PAB1 BSP_FLD32(8)
+#define TMS570_TCR_TCR_Parity_PAB1 BSP_BIT32(8)
 
 /* field: PAB0 - Parity Bit for Byte 0. */
-#define TMS570_TCR_TCR_Parity_PAB0 BSP_FLD32(0)
+#define TMS570_TCR_TCR_Parity_PAB0 BSP_BIT32(0)
 
 
 
-#endif /* LIBBSP_ARM_tms570_TCR */
+#endif /* LIBBSP_ARM_TMS570_TCR */

c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_tcram.h

@@ -36,8 +36,8 @@
  * of the authors and should not be interpreted as representing official policies,
  * either expressed or implied, of the FreeBSD Project.
 */
-#ifndef LIBBSP_ARM_tms570_TCRAM
+#ifndef LIBBSP_ARM_TMS570_TCRAM
-#define LIBBSP_ARM_tms570_TCRAM
+#define LIBBSP_ARM_TMS570_TCRAM
 
 #include <bsp/utility.h>
 
@@ -58,9 +58,9 @@ typedef struct{
 } tms570_tcram_t;
 
 
-/*--------------------TMS570_TCRAMRAMCTRL--------------------*/
+/*--------------------TMS570_TCRAM_RAMCTRL--------------------*/
 /* field: EMU_TRACE_DIS - Emulation Mode Trace Disable. */
-#define TMS570_TCRAM_RAMCTRL_EMU_TRACE_DIS BSP_FLD32(30)
+#define TMS570_TCRAM_RAMCTRL_EMU_TRACE_DIS BSP_BIT32(30)
 
 /* field: ADDR_PARITY_OVERRIDE - Address Parity Override. */
 #define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_OVERRIDE(val) BSP_FLD32(val,24, 27)
@@ -73,7 +73,7 @@ typedef struct{
 #define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_DISABLE_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
 
 /* field: ECC_WR_EN - ECC Memory Write Enable. */
-#define TMS570_TCRAM_RAMCTRL_ECC_WR_EN BSP_FLD32(8)
+#define TMS570_TCRAM_RAMCTRL_ECC_WR_EN BSP_BIT32(8)
 
 /* field: ECC_DETECT_EN - ECC Detect Enable. */
 #define TMS570_TCRAM_RAMCTRL_ECC_DETECT_EN(val) BSP_FLD32(val,0, 3)
@@ -81,62 +81,62 @@ typedef struct{
 #define TMS570_TCRAM_RAMCTRL_ECC_DETECT_EN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*------------------TMS570_TCRAMRAMTHRESHOLD------------------*/
+/*-----------------TMS570_TCRAM_RAMTHRESHOLD-----------------*/
 /* field: THRESHOLD - Single-bit Error Threshold Count. */
 #define TMS570_TCRAM_RAMTHRESHOLD_THRESHOLD(val) BSP_FLD32(val,0, 15)
 #define TMS570_TCRAM_RAMTHRESHOLD_THRESHOLD_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_TCRAM_RAMTHRESHOLD_THRESHOLD_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*--------------------TMS570_TCRAMRAMOCCUR--------------------*/
+/*-------------------TMS570_TCRAM_RAMOCCUR-------------------*/
 /* field: SINGLE_ERROR - Single-bit Error Correction Occurrences. */
 #define TMS570_TCRAM_RAMOCCUR_SINGLE_ERROR(val) BSP_FLD32(val,0, 15)
 #define TMS570_TCRAM_RAMOCCUR_SINGLE_ERROR_GET(reg) BSP_FLD32GET(reg,0, 15)
 #define TMS570_TCRAM_RAMOCCUR_SINGLE_ERROR_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*-------------------TMS570_TCRAMRAMINTCTRL-------------------*/
+/*------------------TMS570_TCRAM_RAMINTCTRL------------------*/
 /* field: SERR_EN - Single-bit Error Correction Interrupt Enable. */
-#define TMS570_TCRAM_RAMINTCTRL_SERR_EN BSP_FLD32(0)
+#define TMS570_TCRAM_RAMINTCTRL_SERR_EN BSP_BIT32(0)
 
 
-/*------------------TMS570_TCRAMRAMERRSTATUS------------------*/
+/*-----------------TMS570_TCRAM_RAMERRSTATUS-----------------*/
 /* field: WADDR_PAR_FAIL - This bit indicates a Write Address Parity Failure. */
-#define TMS570_TCRAM_RAMERRSTATUS_WADDR_PAR_FAIL BSP_FLD32(9)
+#define TMS570_TCRAM_RAMERRSTATUS_WADDR_PAR_FAIL BSP_BIT32(9)
 
 /* field: RADDR_PAR_FAIL - This bit indicates a Read Address Parity Failure. */
-#define TMS570_TCRAM_RAMERRSTATUS_RADDR_PAR_FAIL BSP_FLD32(8)
+#define TMS570_TCRAM_RAMERRSTATUS_RADDR_PAR_FAIL BSP_BIT32(8)
 
 /* field: DERR - This bit indicates a multi-bit error detected by the Cortex-R4F SECDED logic. */
-#define TMS570_TCRAM_RAMERRSTATUS_DERR BSP_FLD32(5)
+#define TMS570_TCRAM_RAMERRSTATUS_DERR BSP_BIT32(5)
 
 /* field: ADDR_COMP_LOGIC_FAIL - Address decode logic element failed. */
-#define TMS570_TCRAM_RAMERRSTATUS_ADDR_COMP_LOGIC_FAIL BSP_FLD32(4)
+#define TMS570_TCRAM_RAMERRSTATUS_ADDR_COMP_LOGIC_FAIL BSP_BIT32(4)
 
 /* field: ADDR_DEC_FAIL - Address decode failed. */
-#define TMS570_TCRAM_RAMERRSTATUS_ADDR_DEC_FAIL BSP_FLD32(2)
+#define TMS570_TCRAM_RAMERRSTATUS_ADDR_DEC_FAIL BSP_BIT32(2)
 
 /* field: SERR - Single Error Status. */
-#define TMS570_TCRAM_RAMERRSTATUS_SERR BSP_FLD32(0)
+#define TMS570_TCRAM_RAMERRSTATUS_SERR BSP_BIT32(0)
 
 
-/*------------------TMS570_TCRAMRAMSERRADDR------------------*/
+/*------------------TMS570_TCRAM_RAMSERRADDR------------------*/
 /* field: SINGLE_ERROR_ADDRESS - This register captures the bits 17-3 of the address for which the Cortex-R4F CPU */
 #define TMS570_TCRAM_RAMSERRADDR_SINGLE_ERROR_ADDRESS(val) BSP_FLD32(val,3, 17)
 #define TMS570_TCRAM_RAMSERRADDR_SINGLE_ERROR_ADDRESS_GET(reg) BSP_FLD32GET(reg,3, 17)
 #define TMS570_TCRAM_RAMSERRADDR_SINGLE_ERROR_ADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,3, 17)
 
 
-/*------------------TMS570_TCRAMRAMUERRADDR------------------*/
+/*------------------TMS570_TCRAM_RAMUERRADDR------------------*/
 /* field: UNCORRECTABLE - address parity error. */
 #define TMS570_TCRAM_RAMUERRADDR_UNCORRECTABLE(val) BSP_FLD32(val,3, 22)
 #define TMS570_TCRAM_RAMUERRADDR_UNCORRECTABLE_GET(reg) BSP_FLD32GET(reg,3, 22)
 #define TMS570_TCRAM_RAMUERRADDR_UNCORRECTABLE_SET(reg,val) BSP_FLD32SET(reg, val,3, 22)
 
 
-/*--------------------TMS570_TCRAMRAMTEST--------------------*/
+/*--------------------TMS570_TCRAM_RAMTEST--------------------*/
 /* field: TRIGGER - Test Trigger. */
-#define TMS570_TCRAM_RAMTEST_TRIGGER BSP_FLD32(8)
+#define TMS570_TCRAM_RAMTEST_TRIGGER BSP_BIT32(8)
 
 /* field: TEST_MODE - Test Mode. This field selects either equality of inequality testing schemes. */
 #define TMS570_TCRAM_RAMTEST_TEST_MODE(val) BSP_FLD32(val,6, 7)
@@ -149,9 +149,9 @@ typedef struct{
 #define TMS570_TCRAM_RAMTEST_TEST_ENABLE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*-----------------TMS570_TCRAMRAMADDRDECVECT-----------------*/
+/*----------------TMS570_TCRAM_RAMADDRDECVECT----------------*/
 /* field: ECC_SELECT - ECC Select. */
-#define TMS570_TCRAM_RAMADDRDECVECT_ECC_SELECT BSP_FLD32(26)
+#define TMS570_TCRAM_RAMADDRDECVECT_ECC_SELECT BSP_BIT32(26)
 
 /* field: RAM_CHIP_SELECT - RAM Chip Select. */
 #define TMS570_TCRAM_RAMADDRDECVECT_RAM_CHIP_SELECT(val) BSP_FLD32(val,0, 15)
@@ -159,7 +159,7 @@ typedef struct{
 #define TMS570_TCRAM_RAMADDRDECVECT_RAM_CHIP_SELECT_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
 
 
-/*-------------------TMS570_TCRAMRAMPERADDR-------------------*/
+/*------------------TMS570_TCRAM_RAMPERADDR------------------*/
 /* field: ADDRESS_PARITY - Parity Error Address. */
 #define TMS570_TCRAM_RAMPERADDR_ADDRESS_PARITY(val) BSP_FLD32(val,3, 22)
 #define TMS570_TCRAM_RAMPERADDR_ADDRESS_PARITY_GET(reg) BSP_FLD32GET(reg,3, 22)
@@ -167,4 +167,4 @@ typedef struct{
 
 
 
-#endif /* LIBBSP_ARM_tms570_TCRAM */
+#endif /* LIBBSP_ARM_TMS570_TCRAM */

c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_vim.h

@@ -36,8 +36,8 @@
  * of the authors and should not be interpreted as representing official policies,
  * either expressed or implied, of the FreeBSD Project.
 */
-#ifndef LIBBSP_ARM_tms570_VIM
+#ifndef LIBBSP_ARM_TMS570_VIM
-#define LIBBSP_ARM_tms570_VIM
+#define LIBBSP_ARM_TMS570_VIM
 
 #include <bsp/utility.h>
 
@@ -70,14 +70,14 @@ typedef struct{
 } tms570_vim_t;
 
 
-/*----------------------TMS570_VIMPARFLG----------------------*/
+/*---------------------TMS570_VIM_PARFLG---------------------*/
 /* field: PARFLG - The PARFLG indicates that a parity error has been found and that theInterrupt Vector Table is */
-#define TMS570_VIM_PARFLG_PARFLG BSP_FLD32(0)
+#define TMS570_VIM_PARFLG_PARFLG BSP_BIT32(0)
 
 
-/*----------------------TMS570_VIMPARCTL----------------------*/
+/*---------------------TMS570_VIM_PARCTL---------------------*/
 /* field: TEST - This bit maps the parity bits into the Interrupt Vector Table frame to make them accessible by the */
-#define TMS570_VIM_PARCTL_TEST BSP_FLD32(8)
+#define TMS570_VIM_PARCTL_TEST BSP_BIT32(8)
 
 /* field: PARENA - VIM parity enable. */
 #define TMS570_VIM_PARCTL_PARENA(val) BSP_FLD32(val,0, 3)
@@ -85,7 +85,7 @@ typedef struct{
 #define TMS570_VIM_PARCTL_PARENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
 
 
-/*----------------------TMS570_VIMADDERR----------------------*/
+/*---------------------TMS570_VIM_ADDERR---------------------*/
 /* field: Interrupt_Vector_Table - Interrupt Vector Table offset. */
 #define TMS570_VIM_ADDERR_Interrupt_Vector_Table(val) BSP_FLD32(val,9, 31)
 #define TMS570_VIM_ADDERR_Interrupt_Vector_Table_GET(reg) BSP_FLD32GET(reg,9, 31)
@@ -102,84 +102,57 @@ typedef struct{
 #define TMS570_VIM_ADDERR_Word_offset_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
 
 
-/*---------------------TMS570_VIMFBPARERR---------------------*/
+/*--------------------TMS570_VIM_FBPARERR--------------------*/
 /* field: FBPARERR - Fall back address parity error. */
-#define TMS570_VIM_FBPARERR_FBPARERR(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_VIM_FBPARERR_FBPARERR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_VIM_FBPARERR_FBPARERR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*--------------------TMS570_VIM_IRQINDEX--------------------*/
-/*---------------------TMS570_VIMIRQINDEX---------------------*/
 /* field: IRQINDEX - IRQ index vector. */
 #define TMS570_VIM_IRQINDEX_IRQINDEX(val) BSP_FLD32(val,0, 7)
 #define TMS570_VIM_IRQINDEX_IRQINDEX_GET(reg) BSP_FLD32GET(reg,0, 7)
 #define TMS570_VIM_IRQINDEX_IRQINDEX_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*---------------------TMS570_VIMFIQINDEX---------------------*/
+/*--------------------TMS570_VIM_FIQINDEX--------------------*/
 /* field: FIQINDEX - FIQ index offset vector. */
 #define TMS570_VIM_FIQINDEX_FIQINDEX(val) BSP_FLD32(val,0, 7)
 #define TMS570_VIM_FIQINDEX_FIQINDEX_GET(reg) BSP_FLD32GET(reg,0, 7)
 #define TMS570_VIM_FIQINDEX_FIQINDEX_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
 
 
-/*----------------------TMS570_VIMFIRQPR----------------------*/
+/*---------------------TMS570_VIM_FIRQPR---------------------*/
 /* field: FIRQPRx - FIQ/IRQ program control bits. 96 bit register. 0-1 bits reserved. */
-#define TMS570_VIM_FIRQPR_FIRQPRx(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_VIM_FIRQPR_FIRQPRx_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_VIM_FIRQPR_FIRQPRx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*---------------------TMS570_VIM_INTREQ---------------------*/
-/*----------------------TMS570_VIMINTREQ----------------------*/
 /* field: INTREQx - Pending interrupt bits. 96 bit register. */
-#define TMS570_VIM_INTREQ_INTREQx(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_VIM_INTREQ_INTREQx_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_VIM_INTREQ_INTREQx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*--------------------TMS570_VIM_REQENASET--------------------*/
-/*--------------------TMS570_VIMREQENASET--------------------*/
 /* field: REQENASETx - Request enable set bits. 96 bit register. 0-1 bits reserved. */
-#define TMS570_VIM_REQENASET_REQENASETx(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_VIM_REQENASET_REQENASETx_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_VIM_REQENASET_REQENASETx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*--------------------TMS570_VIM_REQENACLR--------------------*/
-/*--------------------TMS570_VIMREQENACLR--------------------*/
 /* field: REQENACLRx - Request enable clear bits. 96 bit register. 0-1 bits reserved. */
-#define TMS570_VIM_REQENACLR_REQENACLRx(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_VIM_REQENACLR_REQENACLRx_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_VIM_REQENACLR_REQENACLRx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_VIM_WAKEENASET-------------------*/
-/*--------------------TMS570_VIMWAKEENASET--------------------*/
 /* field: WAKEENASETx - Wake-up enable set bits. This vector determines whether the wake-up interrupt line is enabled. */
-#define TMS570_VIM_WAKEENASET_WAKEENASETx(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_VIM_WAKEENASET_WAKEENASETx_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_VIM_WAKEENASET_WAKEENASETx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*-------------------TMS570_VIM_WAKEENACLR-------------------*/
-/*--------------------TMS570_VIMWAKEENACLR--------------------*/
 /* field: WAKEENACLRx - Wake-up enable clear bits. This vector determines whether the wake-up interrupt line is enabled. */
-#define TMS570_VIM_WAKEENACLR_WAKEENACLRx(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_VIM_WAKEENACLR_WAKEENACLRx_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_VIM_WAKEENACLR_WAKEENACLRx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*--------------------TMS570_VIM_IRQVECREG--------------------*/
-/*--------------------TMS570_VIMIRQVECREG--------------------*/
 /* field: IRQVECREG - IRQ interrupt vector register. */
-#define TMS570_VIM_IRQVECREG_IRQVECREG(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_VIM_IRQVECREG_IRQVECREG_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_VIM_IRQVECREG_IRQVECREG_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*--------------------TMS570_VIM_FIQVECREG--------------------*/
-/*--------------------TMS570_VIMFIQVECREG--------------------*/
 /* field: FIQVECREG - FIQ interrupt vector register. */
-#define TMS570_VIM_FIQVECREG_FIQVECREG(val) BSP_FLD32(val,0, 31)
+/* Whole 32 bits */
-#define TMS570_VIM_FIQVECREG_FIQVECREG_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_VIM_FIQVECREG_FIQVECREG_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
 
-
+/*---------------------TMS570_VIM_CAPEVT---------------------*/
-/*----------------------TMS570_VIMCAPEVT----------------------*/
 /* field: CAPEVTSRC1 - Capture event source 1 mapping control. */
 #define TMS570_VIM_CAPEVT_CAPEVTSRC1(val) BSP_FLD32(val,16, 22)
 #define TMS570_VIM_CAPEVT_CAPEVTSRC1_GET(reg) BSP_FLD32GET(reg,16, 22)
@@ -191,7 +164,7 @@ typedef struct{
 #define TMS570_VIM_CAPEVT_CAPEVTSRC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 6)
 
 
-/*---------------------TMS570_VIMCHANCTRL---------------------*/
+/*--------------------TMS570_VIM_CHANCTRL--------------------*/
 /* field: CHANMAPx0 - CHANMAPx 0(6-0). Interrupt CHANx 0 mapping control. */
 #define TMS570_VIM_CHANCTRL_CHANMAPx0(val) BSP_FLD32(val,24, 30)
 #define TMS570_VIM_CHANCTRL_CHANMAPx0_GET(reg) BSP_FLD32GET(reg,24, 30)
@@ -214,4 +187,4 @@ typedef struct{
 
 
 
-#endif /* LIBBSP_ARM_tms570_VIM */
+#endif /* LIBBSP_ARM_TMS570_VIM */

c/src/lib/libbsp/arm/tms570/include/tms570-pinmux.h

@@ -0,0 +1,137 @@
+/**
+ * @file tms570-pinmux.h
+ *
+ * @ingroup tms570
+ *
+ * @brief I/O Multiplexing Module (IOMM) basic support
+ */
+
+/*
+ * Copyright (c) 2015 Premysl Houdek <kom541000@gmail.com>
+ *
+ * Google Summer of Code 2014 at
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_TMS570_PINMUX_H
+#define LIBBSP_ARM_TMS570_PINMUX_H
+
+#ifndef ASM
+#include <bsp/tms570.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+#define TMS570_PIN_NUM_SHIFT    0
+#define TMS570_PIN_NUM_MASK     0x000007ff
+
+/*
+ * Request clear of interconnection in setup
+ * to ensure that previous peripheral to pin
+ * connection is not enabled in parallel to other one.
+ * Mask is ored with pin number in such list.
+ */
+#define TMS570_PIN_CLEAR_RQ_MASK 0x00000800
+
+#define TMS570_PIN_FNC_SHIFT    12
+#define TMS570_PIN_FNC_MASK     0x0000f000
+
+#define TMS570_PIN_NUM_FNC_MASK 0x0000ffff
+
+#define TMS570_PIN_IN_ALT_SHIFT 16
+#define TMS570_PIN_IN_ALT_MASK  0xffff0000
+
+#define TMS570_PIN_FNC_AUTO  (-1)
+
+#define TMS570_PIN_AND_FNC(pin, fnc) \
+  ((pin) | ((fnc) << TMS570_PIN_FNC_SHIFT))
+
+#define TMS570_PIN_WITH_IN_ALT(pin_num_and_fnc, pin_in_alt_num_and_fnc) \
+  ((pin_num_and_fnc) | ((pin_in_alt_num_and_fnc) << TMS570_PIN_IN_ALT_SHIFT))
+
+#define TMS570_BALL_WITH_MMR(mmrx, pos) \
+  ((pos) | ((mmrx) << 2))
+
+/* Generic functions select pin to peripheral connection */
+
+void tms570_bsp_pin_set_function(int pin_num, int pin_fnc);
+
+void tms570_bsp_pin_clear_function(int pin_num, int pin_fnc);
+
+void tms570_bsp_pin_config_one(uint32_t pin_num_and_fnc);
+
+void tms570_bsp_pinmmr_config(const uint32_t *pinmmr_values, int reg_start, int reg_count);
+
+static inline void
+tms570_bsp_pin_to_pinmmrx(volatile uint32_t **pinmmrx, unsigned int *pin_shift,
+                          int pin_num)
+{
+  pin_num = (pin_num & TMS570_PIN_NUM_MASK) >> TMS570_PIN_NUM_SHIFT;
+  *pinmmrx = &TMS570_IOMM.PINMUX.PINMMR0 + (pin_num >> 2);
+  *pin_shift = (pin_num & 0x3)*8;
+}
+
+#define TMS570_PINMMR_REG_SINGLE_VAL_ACTION(reg, pin) \
+  (((((pin) & TMS570_PIN_NUM_MASK) >> 2 != (reg)) || ((pin) & TMS570_PIN_CLEAR_RQ_MASK))? 0: \
+   1 << ((((pin) & TMS570_PIN_FNC_MASK) >> TMS570_PIN_FNC_SHIFT) + \
+   ((pin) & 3) * 8) \
+  )
+
+#define TMS570_PINMMR_REG_VAL_ACTION(reg, pin) \
+  TMS570_PINMMR_REG_SINGLE_VAL_ACTION(reg, pin) | \
+  ((pin) & TMS570_PIN_IN_ALT_MASK? \
+  TMS570_PINMMR_REG_SINGLE_VAL_ACTION(reg, (pin) >> TMS570_PIN_IN_ALT_SHIFT ): \
+  0) |
+
+/**
+ * Macro which computes value for PINMMRx register from pin list
+ * which is defined as macro calling action macro for each pin
+ *
+ * @param reg      PINMMR register number (0 .. 30 for TMS570LS3137)
+ * @param pin_list declared as macro with parameters
+ *                 \c per_pin_action and \c common_arg which expands
+ *                 to list of \c per_pin_action(\c common_arg, \c TMS570_BALL_xx_function)
+ *
+ * @retval number which represents connections which should be enabled
+ *                in given PINMMR register. Pin setup for other registers than specified
+ *                are ignored
+ */
+#define TMS570_PINMMR_REG_VAL(reg, pin_list) \
+  pin_list(TMS570_PINMMR_REG_VAL_ACTION, reg) 0
+
+#define TMS570_PINMMR_COMA_LIST_ACTION(reg, pin) \
+  (pin),
+
+/**
+ * Macro which generates list of pin and function specification from
+ * from pin list which is defined as macro calling action macro for each pin
+ *
+ * @param pin_list declared as macro with parameters
+ *                 \c per_pin_action and \c common_arg which expands
+ *                 to list of \c per_pin_action(\c common_arg, \c TMS570_BALL_xx_function)
+ *
+ * @retval list of coma separated pin+function combined values which is terminated by coma
+ *              at the end
+ */
+#define TMS570_PINMMR_COMA_LIST(pin_list) \
+  pin_list(TMS570_PINMMR_COMA_LIST_ACTION, 0)
+
+
+#endif
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_TMS570_IRQ_H */

c/src/lib/libbsp/arm/tms570/include/tms570-pins.h

@@ -0,0 +1,10 @@
+/**
+ * @file tms570-pins.h
+ *
+ * @ingroup tms570
+ *
+ * @brief Select pin mapping according to selected chip.
+ *        Defaults to TMS570LS3137ZWT for now.
+ */
+
+#include <bsp/tms570ls3137zwt-pins.h>

c/src/lib/libbsp/arm/tms570/include/tms570-pom.h

@@ -48,8 +48,7 @@ extern "C" {
 
 #define TMS570_POM_REGADDRMASK    ((1<<23)-1)
 
-
+void tms570_initialize_and_clear(void);
-int mem_dump(void *buf, unsigned long start, unsigned long len, int blen);
 void tms570_pom_remap(void);
 
 /** @} */

c/src/lib/libbsp/arm/tms570/include/tms570.h

@@ -38,6 +38,9 @@
 */
 #ifndef LIBBSP_ARM_TMS570
 #define LIBBSP_ARM_TMS570
+
+#include <bsp/tms570-pins.h>
+
 #include <bsp/ti_herc/reg_adc.h>
 #include <bsp/ti_herc/reg_ccmsr.h>
 #include <bsp/ti_herc/reg_crc.h>
@@ -46,7 +49,7 @@
 #include <bsp/ti_herc/reg_dma.h>
 #include <bsp/ti_herc/reg_dmm.h>
 #include <bsp/ti_herc/reg_efuse.h>
-#include <bsp/ti_herc/reg_emac.h>
+#include <bsp/ti_herc/reg_emacc.h>
 #include <bsp/ti_herc/reg_emacm.h>
 #include <bsp/ti_herc/reg_emif.h>
 #include <bsp/ti_herc/reg_esm.h>
@@ -87,7 +90,7 @@
 #define TMS570_DMA (*(volatile tms570_dma_t*)0xFFFFF000)
 #define TMS570_DMM (*(volatile tms570_dmm_t*)0xFFFFF700)
 #define TMS570_EFUSE (*(volatile tms570_efuse_t*)0XFFF8C01C)
-#define TMS570_EMAC (*(volatile tms570_emac_t*)0xFCF78900)
+#define TMS570_EMACC (*(volatile tms570_emacc_t*)0xFCF78800)
 #define TMS570_EMACM (*(volatile tms570_emacm_t*)0xFCF78000)
 #define TMS570_EMIF (*(volatile tms570_emif_t*)0xFCFFE800)
 #define TMS570_ESM (*(volatile tms570_esm_t*)0XFFFFF500)
@@ -122,7 +125,11 @@
 #define TMS570_TCRAM2 (*(volatile tms570_tcram_t*)0xFFFFF900)
 #define TMS570_VIM (*(volatile tms570_vim_t*)0XFFFFFDEC)
 #define TMS570_POM (*(volatile tms570_pom_t*)0XFFA04000)
-#define TMS570_SPI (*(volatile tms570_spi_t*)0xFFF7F400)
+#define TMS570_SPI1 (*(volatile tms570_spi_t*)0xFFF7F400)
+#define TMS570_SPI2 (*(volatile tms570_spi_t*)0xFFF7F600)
+#define TMS570_SPI3 (*(volatile tms570_spi_t*)0xFFF7F800)
+#define TMS570_SPI4 (*(volatile tms570_spi_t*)0xFFF7FA00)
+#define TMS570_SPI5 (*(volatile tms570_spi_t*)0xFFF7FC00)
 #define TMS570_STC (*(volatile tms570_stc_t*)0xFFFFE600)
 #define TMS570_SYS1 (*(volatile tms570_sys1_t*)0xFFFFFF00)
 #define TMS570_SYS2 (*(volatile tms570_sys2_t*)0xFFFFE100)