Remove forced overwrite which leads to file data corruption. The logic
to determine a forced overwrite was fundamentally broken. For simplity,
disable this feature.
Close#2622.
It is all right in case the result uses the full destination buffer.
Without this fix the handling of a maximum 8.3 short file name is
broken.
Close#2928.
In canonical mode, the raw input buffer or the canonical buffer may
overflow without an end of line. Avoid an infinite loop in this case.
Update #2915.
The second FAT entry contains a bit to indicate if the FAT32 filesystem
is not dirty and a bit to indicate if there was no IO error. Set both
bits for a fresh filesystem. This prevents a warning if mounted on
Windows.
Update #2913.
The CPU_CACHE_LINE_BYTES has been introduced after 4.11 branch
fork and is not available for all architectures on RTEMS 4.11.
Use of rtems_cache_get_maximal_line_size() is more descriptive
choice. The min/max data/instruction cache line size is not critical
there, value is used for optimization only to use single operation
for decently following sections.
The configuration is specific for TMS570LS3137 based HDK.
Pins configuration can be easily changed in
rtems/c/src/lib/libbsp/arm/tms570/hwinit/init_pinmux.c
file.
The list tms570_selftest_par_list in the file
rtems/c/src/lib/libbsp/arm/tms570/hwinit/bspstarthooks-hwinit.c
specifies peripherals which health status is examined
by parity self-test at BSP start-up. It can be easily
modified for other TMS570 family members variants same
as the selection of other tests in bspstarthooks-hwinit.c.
Generated header file ti_herc/reg_spi.h contains complete registers
and fields set for Ti MibSPI peripheral.
Care has to be taken that only TMS570_SPI1, TMS570_SPI3 and TMS570_SPI5
are of this complete multibuffer type. TMS570_SPI2 and TMS570_SPI4
have substantial part of registers removed but else they are compatible.
The rtems_monitor_task() setups/updates termios attributes
of the opened TTY and if there is ongoing some other output
it leads to the stuck.
It would be better to use some termios API function which
would call drainOutput() in rtems/cpukit/libcsupport/src/termios.c.
But functionality is not accessible outside of core termios
implementation.
The loop waiting for last character to be sent has to be there anyway
because hardware does not provide Tx machine/shift register empty
interrupt.
Closes#2794
The symbol can be used by bsp_start_hook_0 when complete
RAM memory is initialization and overwritten during BSP
self-test. The test overwrites even memory used to store
return address / link register and regular resturn from
bsp_start_hook_0 is not possible then.
This is minimized version of mainline patch
arm/raspberrypi: move MMU in front of application image to respect variable memory size.
plus correction which has been part of other mainline patches.
This is end of series which allows 4.11 to boot on Raspberry Pi.
Closes#2782Closes#2783
Using conditional branches to find bits is extremely inefficient
and for asynchronous delivery of different interrupt sources
lead to total confusion of branch prediction unit.
Updates #2783
Exception table setup is processed by common CPU architecture support.
For ARM architecture, it can be found in the file
rtems/c/src/lib/libbsp/arm/shared/start/start.S
and ends by bsp_vector_table_copy_done label.
The actual tabel content can be found at
bsp_start_vector_table_begin
For ARMv7-A and even other variant with hypervisor mode support,
it is even not necessary to copy table to address 0 at all
because CP15 register can be used to specify alternative
table start address
arm_cp15_set_vector_base_address(&)bsp_start_vector_table_begin;
ARMv7-M have register to set exception table base as well.
Updates #2783
If the raspberrypi.h has been included without preceding inclussion
of bsp.h then BSP_IS_RPI2 has not been set for Raspberry Pi 2
BSP variant and bad things happen later.
The patch includes bspopts.h by raspberrypi.h and even includes
bsp.h in critical peripherals support.
Updates #2783
Enable even the first megabyte of SDRAM to be cache-able after
problems with stale cache content has been resolved by previous commit.
Because major part of application usually fits to the first
megabyte this speedups test dhrystone application by factor 40.
Updates #2783
When HYP mode is detected at startup then setup HYP mode
vectors table (for future extensions) clean exceptions
switching to HYP mode and switch CPU to ARM SVC mode.
BSPs which want to use this support need to include next option
in their configure.ac
RTEMS_BSPOPTS_SET([BSP_START_IN_HYP_SUPPORT],[*],[1])
RTEMS_BSPOPTS_HELP([BSP_START_IN_HYP_SUPPORT], [Support start of BSP in ARM HYP mode])
AM_CONDITIONAL(BSP_START_IN_HYP_SUPPORT,test "$BSP_START_IN_HYP_SUPPORT" = "1")
and need to include next lines in corresponding Makefile.am
if BSP_START_IN_HYP_SUPPORT
libbsp_a_SOURCES += ../shared/startup/bsp-start-in-hyp-support.S
endif
Updates #2783
New function arm_cp15_cache_invalidate_level and arm_cp15_cache_clean_level
can be used to maintain single cache level (instruction or data).
Updates #2782
Updates #2783
Protection by rtems_interrupt_disable() is incompatible with SMP build.
Actual page table entries manipulation function does not need locking
and disabling cache and can be run concurrently even on multiple
CPUs as long as changes do not modify same region. If the function
is called from more threads/CPUs to modify same region with different
mapping options concurrently then there is problem at another level
of virtual address space management and has to be solved by mutex
or other locking at that level.
Updates #2782
Updates #2783
The change documents meaning of codes and opens
well defined way to use cache type format for cache
examination/debugging outside of arm-cp15.h file.
Updates #2782
Updates #2783
This fix strange behavior where some stale content has been
stored in level 2 cache before RTEMS has been start from U-boot
which has reappeared after MMU enable and shadow vector
table at start of SDRAM.
Updates #2782
Updates #2783
Next cache operations should work on most of cores now
rtems_cache_flush_entire_data()
rtems_cache_invalidate_entire_data()
rtems_cache_invalidate_entire_instruction()
Instruction cache invalidate works on the first level for now only.
Data cacache operations are extended to ensure flush/invalidate
on all cache levels.
The CP15 arm_cp15_data_cache_clean_all_levels() function extended
to continue through unified levels too (ctype = 4).
Updates #2782
Updates #2783
