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Author SHA1 Message Date
Sebastian Huber
4e686261d8 bsps/irq: Fix interrupt server init (SMP) 2019-02-07 11:13:59 +01:00
Sebastian Huber
fbd08066af score: Fix plain priority thread queues (SMP) 
We must add/remove the priority queue to the FIFO of priority queues.
 2019-02-07 08:48:18 +01:00
Sebastian Huber
0fb52cede1 bsps/arm: Fix generic timer frequency 
Update #3456.
 2019-02-07 08:48:18 +01:00
Sebastian Huber
03fcbb15d2 fs: Add struct dirent::d_type support 2019-02-05 10:17:04 +01:00
Sebastian Huber
9399473cb8 riscv: Fix misaligned access in context validate 2019-02-02 11:03:13 +01:00
Sebastian Huber
b015c01443 build: Do not install test programs 2019-01-30 09:46:35 +01:00
Sebastian Huber
03cdd5eab8 record: Add enum value for each event 
Update #3665.
 2019-01-30 09:46:35 +01:00
Sebastian Huber
dca618404e Add low level event recording support 
Add low level event recording infrastructure for system and user
defined events.  The infrastructure is able to record high frequency
events such as

 * SMP lock acquire/release,
 * interrupt entry/exit,
 * thread switches,
 * UMA zone allocate/free, and
 * Ethernet packet input/output, etc.

It allows post-mortem analysis in fatal error handlers, e.g. the last
events are in the record buffer, the newest event overwrites the oldest
event.  It is possible to detect record buffer overflows for consumers
that expect a continuous stream of events, e.g. to display the system
state in real-time.

The implementation supports high-end SMP machines (more than 1GHz
processor frequency, more than four processors).

Add a new API instead. The implementation uses per-processor data
structures and no atomic read-modify-write operations.  It is uses
per-processor ring buffers to record the events.

The CPU counter is used to get the time of events. It is combined with
periodic uptime events to synchronize it with CLOCK_REALTIME.

The existing capture engine tries to solve this problem also, but its
performance is not good enough for high-end production systems.  The
main issues are the variable-size buffers and the use of SMP locks for
synchronization.  To fix this, the API would change significantly.

Update #3665.
 2019-01-29 13:51:33 +01:00
Sebastian Huber
f0ae613ba7 m68k: Avoid _Addresses_Add_offset() 
This prevents a cyclic dependency between <rtems/score/cpu.h> and
<rtems/score/address.h>.
 2019-01-29 13:27:01 +01:00
Sebastian Huber
e74a3fd13d samples/pppd: Use less memory hungry configuration 
This avoids link-time failures on some low memory BSPs.
 2019-01-29 13:27:01 +01:00
Sebastian Huber
4f3a2532a3 psxtmtests: Fix format warnings 
Update #3384.
 2019-01-28 14:17:39 +01:00
Sebastian Huber
b1381ae7c3 bsps/powerpc: Fix warnings 2019-01-25 15:50:40 +01:00
Sebastian Huber
81aec18146 bsps/powerpc: Fix 64-bit issues in assembler files 
We have to be careful with instructions which operate explicitly on
words or doublewords.

Update #3082.
 2019-01-25 15:40:11 +01:00
Maksim E. Kozlov
afd50b3a62 libmisc: Fix swapped parameters and enable floating point usage. 2019-01-23 10:32:55 -06:00
Jiri Gaisler
d3d4e77c42 riscv: add griscv bsp 
Update #3678.
 2019-01-22 12:50:09 +01:00
Jiri Gaisler
c1dcd6af56 grlib: make memory coherency cpu-independent 
Update #3678.
 2019-01-22 12:50:09 +01:00
Jiri Gaisler
9b2b389e8d grlib: use cpu-independent routines for uncached access 
Update #3678.
 2019-01-22 12:50:08 +01:00
Jiri Gaisler
5981c8ca9f grlib: use rtems_interrupt_handler_install() 
Update #3678.
 2019-01-22 12:49:58 +01:00
Jiri Gaisler
411c29735d grlib: make apbuart driver independent of bsp 
Update #3678.
 2019-01-22 12:48:19 +01:00
Sebastian Huber
7eb606d393 grlib: Move source files 
Update #3678.
 2019-01-22 12:46:33 +01:00
Sebastian Huber
3172092576 grlib: Move header files 
Update #3678.
 2019-01-22 12:46:28 +01:00
Sebastian Huber
95c19211d1 bsps/arm: Remove unused bsp_stack_irq_size 
Update #3459.
 2019-01-21 09:17:51 +01:00
Sebastian Huber
926ed2b020 score: Remove unused _ISR_lock_Flash() 2019-01-18 13:33:18 +01:00
Sebastian Huber
41310c026c score: Improve debug support for ISR locks 
Ensure that interrupts are disabled while acquiring an ISR lock.
 2019-01-18 13:33:18 +01:00
Sebastian Huber
b5bdecfe00 score: Avoid internal API and use ISR lock 2019-01-18 13:33:18 +01:00
Sebastian Huber
93e3b34161 score: Simplify _Addresses_Is_aligned() 
The CPU_ALIGNMENT must not be zero, this is also checked via a static
assertion.  Fix formatting.
 2019-01-18 11:49:09 +01:00
Joel Sherrill
12dfe5dcb1 bsps/i386/shared/cache/cache.c: Make compile 2019-01-16 15:42:18 -06:00
Joel Sherrill
4596127889 m68k/include/rtems/score/cpu.h: Add include of address.h 2019-01-14 09:15:49 -06:00
Sebastian Huber
47d5aee5d2 build: Add missing $(LDADD) for dependencies 2019-01-14 09:38:13 +01:00
Sebastian Huber
d1fff86c95 build: Remove bogus spqreslib_LDADD 2019-01-14 09:09:39 +01:00
Sebastian Huber
dc0285fd09 build: Add missing $(LDADD) for dependencies 2019-01-14 09:09:39 +01:00
Sebastian Huber
8eaf136de9 memalign: Add missing attributes to fix warning 
Update #3666.
 2019-01-10 11:35:38 +01:00
Sebastian Huber
7bde91bd5f Fix format warnings due to ino_t changes 2019-01-10 09:06:56 +01:00
Sebastian Huber
3a5c71dea4 psxconfig01: Fix pre-processor conditions 
Do not rely on compiler optimizations to throw away empty loops.

Close #3673.
 2019-01-10 08:12:16 +01:00
Sebastian Huber
e7d623e7e2 bsps/arm: Conditional ARMv7-AR data cache disable 
Update #3667.
Close #3674.
 2019-01-10 08:12:16 +01:00
Thomas Dörfler
0abe47f142 bsps/arm: Fix typo in disable cache for ARMv7-AR 
Update #3667.
 2019-01-10 08:12:16 +01:00
Sebastian Huber
b9ffc41c96 riscv: Enable robust thread dispatch 
It must be enabled, since the context switch code does not save/restore
the interrupt status.

Update #3433.
 2019-01-09 10:36:02 +01:00
Sebastian Huber
3bd3999936 Adjust interrupt mode tests for some CPU ports 
In case the robust thread dispatch is enabled by the CPU port, then the
interrupt level must not be changed through the task mode.

Update #3000.
 2019-01-09 10:35:33 +01:00
Sebastian Huber
1f28518675 rtems: Allow to set ISR level 0 in SMP config 
Update #3000.
 2019-01-09 10:35:31 +01:00
Sebastian Huber
38cb59ee0b Separate task mode checks 
Update #3000.
 2019-01-09 10:35:24 +01:00
Sebastian Huber
feddcde09a tests: Remove bogus RTEMS_INTERRUPT_LEVEL(31) 
It is unnecessary to run these test cases with interrupts disabled.
 2019-01-09 10:32:57 +01:00
Sebastian Huber
fe48400d5b libtests/stackchk: Fix for 64-bit targets 2019-01-09 10:05:03 +01:00
Jacob Shin
e4a19f5b66 psxhdrs: Add POSIX API Signature Compliance Tests for errno.h 2019-01-08 09:48:29 -06:00
Sebastian Huber
9aee88aa54 bsp/riscv: Clear boot command line 2019-01-08 14:44:08 +01:00
Sebastian Huber
07fb7667de build: Call rtems-ld with the $(CC) of the build 
This enables support for non-standard compiler names, e.g.
sparc-rtems6-gcc.
 2019-01-08 09:57:44 +01:00
Sebastian Huber
7802bb9a4d build: Call rtems-syms with the $(CC) of the build 
This enables support for non-standard compiler names, e.g.
sparc-rtems6-gcc.
 2019-01-08 09:57:44 +01:00
Jiri Gaisler
5b951175d0 psxfile01: Fix one second sleep 
Checking of atime in psxfile01 (line 713) can fail since a delay for
rtems_clock_get_ticks_per_second (line 699) gives a delay of less than
one second, depending on when the last tick occurred. atime is measured
in whole seconds, and a fast processor might read the file before a new
second occurs. Add one tick to the delay will solve the problem.
 2019-01-07 14:23:50 +01:00
Sebastian Huber
9c12bcfdc5 Fix format warnings 2019-01-07 09:49:16 +01:00
Sebastian Huber
956d76ccaf score: Remove superfluous include from chainimpl.h 2019-01-07 09:36:47 +01:00
Sebastian Huber
a7e89962df drvmgr: Improve LP64 compatibility 2018-12-27 09:00:59 +01:00