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bsps: Fix GICv3 support for AArch32

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The GICv3 support is shared between AArch32 and AArch64.  For AArch32,
the new AARCH64_IS_NONSECURE is never defined.  Use ARM_MULTILIB_ARCH_V4
instead.

This issue was introduced by 76c6caad52.

There is still a change in bsp_interrupt_vector_enable() for AArch32
compared to the version before 76c6caad52.
This commit is contained in:
Sebastian Huber
2021-06-30 15:22:57 +02:00
parent c18b041b77
commit f2b0877642
1 changed files with 3 additions and 3 deletions
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6
bsps/shared/dev/irq/arm-gicv3.c
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@@ -176,7 +176,7 @@ void bsp_interrupt_vector_enable(rtems_vector_number vector)
volatile gic_sgi_ppi *sgi_ppi =
gicv3_get_sgi_ppi(_SMP_Get_current_processor());
/* Set interrupt group to 1 in the current security mode */
#if defined(AARCH64_IS_NONSECURE)
#if defined(ARM_MULTILIB_ARCH_V4) || defined(AARCH64_IS_NONSECURE)
sgi_ppi->icspigrpr[0] |= 1 << (vector % 32);
sgi_ppi->icspigrpmodr[0] &= ~(1 << (vector % 32));
#else
@@ -228,7 +228,7 @@ static void gicv3_init_cpu_interface(void)
volatile gic_sgi_ppi *sgi_ppi = gicv3_get_sgi_ppi(cpu_index);
/* Set interrupt group to 1 in the current security mode */
#if defined(AARCH64_IS_NONSECURE)
#if defined(ARM_MULTILIB_ARCH_V4) || defined(AARCH64_IS_NONSECURE)
sgi_ppi->icspigrpr[0] = 0xffffffff;
sgi_ppi->icspigrpmodr[0] = 0;
#else
@@ -262,7 +262,7 @@ rtems_status_code bsp_interrupt_facility_initialize(void)
dist->icdicer[id / 32] = 0xffffffff;
/* Set interrupt group to 1 in the current security mode */
#if defined(AARCH64_IS_NONSECURE)
#if defined(ARM_MULTILIB_ARCH_V4) || defined(AARCH64_IS_NONSECURE)
dist->icdigr[id / 32] = 0xffffffff;
dist->icdigmr[id / 32] = 0;
#else