mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
synced 2025-12-24 21:37:11 +00:00
committed by
Amar Takhar
parent
f67f1c8718
commit
ef570cf157
12
bsps/arm/shared/cache/cache-cp15.c
vendored
12
bsps/arm/shared/cache/cache-cp15.c
vendored
@@ -54,6 +54,10 @@
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#define CPU_CACHE_SUPPORT_PROVIDES_DISABLE_DATA
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#endif
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#if __ARM_ARCH == 7 && __ARM_ARCH_PROFILE == 'R'
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#define CACHE_CP15_IS_CORTEX_R5
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#endif
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static inline void _CPU_cache_flush_1_data_line(const void *d_addr)
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{
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arm_cache_l1_flush_1_data_line(d_addr);
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@@ -128,7 +132,9 @@ static inline void _CPU_cache_unfreeze_instruction(void)
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static inline void _CPU_cache_flush_entire_data(void)
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{
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_ARM_Data_synchronization_barrier();
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#if __ARM_ARCH >= 7
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#if defined(CACHE_CP15_IS_CORTEX_R5)
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arm_cp15_data_cache_clean_level(0);
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#elif __ARM_ARCH >= 7
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arm_cp15_data_cache_clean_all_levels();
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#else
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arm_cp15_data_cache_clean_and_invalidate();
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@@ -139,7 +145,9 @@ static inline void _CPU_cache_flush_entire_data(void)
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static inline void _CPU_cache_invalidate_entire_data(void)
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{
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#if __ARM_ARCH >= 7
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#if defined(CACHE_CP15_IS_CORTEX_R5)
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arm_cp15_data_cache_all_invalidate();
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#elif __ARM_ARCH >= 7
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arm_cp15_data_cache_invalidate_all_levels();
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#else
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arm_cp15_data_cache_invalidate();
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