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removing unneeded files
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Thomas Doerfler
@@ -1 +0,0 @@
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Makefile.in
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@@ -1,21 +0,0 @@
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2007-12-11 Joel Sherrill <joel.sherrill@OARcorp.com>
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* thumb_isr.c: Style.
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2007-11-26 Ray Xu <rayx.cn@gmail.com>
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* thumb_isr.c: Remove extra debug information, Change function
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definition.
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2007-11-06 Joel Sherrill <joel.sherrill@OARcorp.com>
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* thumb_isr.c: Fix headers.
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2007-11-06 Joel Sherrill <joel.sherrill@OARcorp.com>
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* .cvsignore, ChangeLog, Makefile.am, thumb_isr.c: New files.
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2007-11-03 Ray Xu <rayx.cn@gmail.com>
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* Makefile.am, thumb_isr.c : add support for ARM<->THUMB veneer
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thumb_isr.c control CPSR/SPRS in thumb mode
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@@ -1,177 +0,0 @@
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/*
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* Thumb mode does not support multi-level ISR, only disable and enable.
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.com/license/LICENSE.
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*
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* $Id$
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*/
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#include <rtems/system.h>
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#if (defined(__THUMB_INTERWORK__) || defined(__thumb__))
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/*
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*
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* _CPU_ISR_Get_level_Thumb - returns the current interrupt level
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*/
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uint32_t _CPU_ISR_Get_level_Thumb(void) __attribute__ ((naked));
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uint32_t _CPU_ISR_Disable_Thumb(void ) __attribute__ ((naked));
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void _CPU_ISR_Enable_Thumb(int _level ) __attribute__ ((naked));
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void _CPU_ISR_Flash_Thumb(int _level ) __attribute__ ((naked));
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void _CPU_ISR_Set_level_Thumb(int new_level ) __attribute__ ((naked));
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/*
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* prevent multipule enable/disable ISR
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* 0: ISR enabled, >1 ISR disabled
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*/
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/*
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* Set the CPSR bit 6,7 to 1 disables FIQ and IRQ
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* Set the CPSR bit 6,7 to 0 enables FIQ and IRQ
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*/
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#define str(x) #x
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#define xstr(x) str(x)
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#define L(x) #x "_" xstr(__LINE__)
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/*
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* Switch to ARM mode Veneer,ugly but safe
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*/
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#define TO_ARM_MODE(x) \
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asm volatile ( \
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".code 16 \n" \
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L(x) "_thumb: \n" \
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".align 2 \n" \
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"push {lr} \n" \
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"adr %0, "L(x) "_arm \n" \
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"bl " L(x)" \n" \
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"pop {pc} \n" \
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".balign 4 \n" \
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L(x) ": \n" \
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"bx %0 \n" \
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"nop \n" \
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".pool \n" \
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".code 32 \n" \
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L(x) "_arm: \n" \
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: "=&r" (reg))
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/*
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* Disable all interrupts for an RTEMS critical section. The previous
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* level is returned in _level.
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*/
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uint32_t _CPU_ISR_Disable_Thumb(void )
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{
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int reg=0;
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TO_ARM_MODE(disable);
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asm volatile(
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".code 32 \n"
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"STMDB sp!, {r1} \n"
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"MRS r0, CPSR \n"
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"DISABLE_ARM: \n"
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"ORR r1, r0, #0xc0 \n"
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"MSR CPSR, r1 \n"
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"pop {r1} \n"
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"BX LR \n"
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".code 16 \n"
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);
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}
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/*
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* Enable interrupts to the previous level (returned by
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* _CPU_ISR_Disable_Thumb).
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* This indicates the end of an RTEMS critical section. The parameter
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* _level is not modified. I do not think _level is useful in this
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*/
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void _CPU_ISR_Enable_Thumb(int _level )
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{
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int reg=0;
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TO_ARM_MODE(enable);
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asm volatile(
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".code 32 \n"
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"ENABLE_ARM: \n"
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"MSR CPSR, %0 \n"
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/* Return back to thumb.*/
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"BX R14 \n"
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".code 16 \n"
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: : "r"(_level)
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);
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}
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/*
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* This temporarily restores the interrupt to _level before immediately
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* disabling them again. This is used to divide long RTEMS critical
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* sections into two or more parts. The parameter _level is not
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* modified.
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*/
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void _CPU_ISR_Flash_Thumb(int _level )
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{
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int reg=0;
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TO_ARM_MODE(flash);
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asm volatile(
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".code 32 \n"
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"FLASH_ARM: \n"
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"MRS %0, CPSR \n"
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"BIC %0, %0, #0xC0 \n"
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/* enable the irq*/
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"MSR CPSR_c, %0 \n"
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"ORR %0, %0, #0xc0 \n"
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"MSR CPSR_c, %0 \n"
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"BX R14 \n"
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".code 16 \n"
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:"=&r"(reg) : "r" (_level)
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);
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}
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/*
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* Map interrupt level in task mode onto the hardware that the CPU
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* actually provides. Currently, interrupt levels which do not
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* map onto the CPU in a generic fashion are undefined. Someday,
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* it would be nice if these were "mapped" by the application
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* via a callout. For example, m68k has 8 levels 0 - 7, levels
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* 8 - 255 would be available for bsp/application specific meaning.
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* This could be used to manage a programmable interrupt controller
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* via the rtems_task_mode directive.
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*
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* The get routine usually must be implemented as a subroutine.
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* ARM/Thumb dont distinguishd the interrupt levels
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*/
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void _CPU_ISR_Set_level_Thumb(int new_level)
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{
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int reg = 0; /* to avoid warning */
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TO_ARM_MODE(SetISR);
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asm volatile (\
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".code 32 \n" \
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"SET_LEVEL_ARM: \n" \
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"MRS %0, CPSR \n" \
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"BIC %0, %0, #0xC0 \n" \
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"MSR CPSR_c, %0 \n" \
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"BX lr \n" \
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".code 16 \n" \
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: "=r" (reg) \
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: "0" (reg));
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}
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uint32_t _CPU_ISR_Get_level_Thumb( void )
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{
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uint32_t reg = 0; /* to avoid warning */
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TO_ARM_MODE(GetISR); \
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asm volatile (\
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".code 32 \n" \
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"GET_ISR_ARM: \n" \
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"MRS r0, cpsr \n" \
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"AND r0, r0, #0xC0 \n" \
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"EOR r0, r0, #0xC0 \n" \
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"BX LR \n" \
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".code 16 \n" \
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".thumb_func \n" );
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}
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#endif
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