build: Merge default-by-family into by-variant

Prefix the BSP family name with "bsps/" to make it distinct to the BSP
variant names.

Update #4468.
This commit is contained in:
Sebastian Huber
2021-07-23 08:45:07 +02:00
parent 75af5be6a8
commit ebdfa24bff
762 changed files with 7 additions and 768 deletions

View File

@@ -8,7 +8,6 @@ copyrights:
- Copyright (C) 2020 On-Line Applications Research (OAR)
default:
- -mcpu=cortex-a53
default-by-family: []
default-by-variant:
- value:
- -mcpu=cortex-a53

View File

@@ -8,7 +8,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 On-Line Applications Research (OAR)
default: 32768
default-by-family: []
default-by-variant: []
description: |
offset of RAM region from memory area base

View File

@@ -8,7 +8,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 On-Line Applications Research (OAR)
default: 1048576
default-by-family: []
default-by-variant: []
description: |
length of nocache RAM region

View File

@@ -8,7 +8,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 On-Line Applications Research (OAR)
default: 0x8000000
default-by-family: []
default-by-variant: []
description: |
length of memory area available to the BSP

View File

@@ -8,7 +8,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 On-Line Applications Research (OAR)
default: 1073741824
default-by-family: []
default-by-variant: []
description: |
base address of memory area available to the BSP

View File

@@ -34,7 +34,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 On-Line Applications Research (OAR)
default: null
default-by-family: []
default-by-variant: []
description: ''
enabled-by: true

View File

@@ -8,7 +8,6 @@ copyrights:
- Copyright (C) 2020 On-Line Applications Research (OAR)
default:
- -mcpu=cortex-a72
default-by-family: []
default-by-variant:
- value:
- -mcpu=cortex-a72

View File

@@ -8,7 +8,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 On-Line Applications Research (OAR)
default: 32768
default-by-family: []
default-by-variant: []
description: |
offset of RAM region from memory area base

View File

@@ -8,7 +8,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 On-Line Applications Research (OAR)
default: 1048576
default-by-family: []
default-by-variant: []
description: |
length of nocache RAM region

View File

@@ -8,7 +8,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 On-Line Applications Research (OAR)
default: 0x8000000
default-by-family: []
default-by-variant: []
description: |
length of memory area available to the BSP

View File

@@ -8,7 +8,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 On-Line Applications Research (OAR)
default: 1073741824
default-by-family: []
default-by-variant: []
description: |
base address of memory area available to the BSP

View File

@@ -34,7 +34,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 On-Line Applications Research (OAR)
default: null
default-by-family: []
default-by-variant: []
description: ''
enabled-by: true

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2021 Gedare Bloom <gedare@rtems.org>
default: false
default-by-family: []
default-by-variant: []
description: |
If set to true, and AARCH64_GENERIC_TIMER_USE_VIRTUAL is false, then

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2021 Gedare Bloom <gedare@rtems.org>
default: false
default-by-family: []
default-by-variant: []
description: |
If set to true, then the clock driver uses the Virtual Timer of the AARCH64

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2021 Gedare Bloom <gedare@rtems.org>
default: true
default-by-family: []
default-by-variant:
- value: false
variants:

View File

@@ -9,7 +9,6 @@ build-type: option
copyrights:
- Copyright (C) 2021 On-Line Applications Research (OAR)
default: 0x40
default-by-family: []
default-by-variant: []
description: |
Defines the number of MMU translation table pages to provide.

View File

@@ -8,7 +8,6 @@ copyrights:
- Copyright (C) 2021 Gedare Bloom
default:
- -mcpu=cortex-a72
default-by-family: []
default-by-variant:
- value:
- -mcpu=cortex-a72

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2021 Gedare Bloom <gedare@rtems.org>
default: 24000000
default-by-family: []
default-by-variant:
- value: 100000000
variants:

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: 0
default-by-family: []
default-by-variant: []
description: |
minor number of console device

View File

@@ -8,7 +8,6 @@ build-type: option
copyrights:
- Copyright (C) 2021 Gedare Bloom <gedare@rtems.org>
default: 32768
default-by-family: []
default-by-variant:
- value: 0x0
variants:

View File

@@ -8,7 +8,6 @@ build-type: option
copyrights:
- Copyright (C) 2021 Gedare Bloom <gedare@rtems.org>
default: 0x100000
default-by-family: []
default-by-variant: []
description: |
length of nocache RAM region

View File

@@ -8,7 +8,6 @@ build-type: option
copyrights:
- Copyright (C) 2021 Gedare Bloom <gedare@rtems.org>
default: 0x10000000
default-by-family: []
default-by-variant: []
description: |
length of memory area available to the BSP

View File

@@ -8,7 +8,6 @@ build-type: option
copyrights:
- Copyright (C) 2021 Gedare Bloom <gedare@rtems.org>
default: 0x20000000
default-by-family: []
default-by-variant:
- value: 0x10000000
variants:

View File

@@ -12,7 +12,6 @@ build-type: option
copyrights:
- Copyright (C) 2021 Gedare Bloom <gedare@rtems.org>
default: null
default-by-family: []
default-by-variant: []
description: ''
enabled-by: true

View File

@@ -12,7 +12,6 @@ build-type: option
copyrights:
- Copyright (C) 2021 Gedare Bloom <gedare@rtems.org>
default: null
default-by-family: []
default-by-variant: []
description: ''
enabled-by: true

View File

@@ -8,7 +8,6 @@ copyrights:
- Copyright (C) 2020 On-Line Applications Research (OAR)
default:
- -mcpu=cortex-a53
default-by-family: []
default-by-variant:
- value:
- -mcpu=cortex-a53

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 On-Line Applications Research (OAR)
default: 100000000
default-by-family: []
default-by-variant:
- value: 100000000
variants:

View File

@@ -8,7 +8,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 On-Line Applications Research (OAR)
default: 32768
default-by-family: []
default-by-variant:
- value: 0x0
variants:

View File

@@ -8,7 +8,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 On-Line Applications Research (OAR)
default: 0x100000
default-by-family: []
default-by-variant: []
description: |
length of nocache RAM region

View File

@@ -8,7 +8,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 On-Line Applications Research (OAR)
default: 0x10000000
default-by-family: []
default-by-variant: []
description: |
length of memory area available to the BSP

View File

@@ -8,7 +8,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 On-Line Applications Research (OAR)
default: 0x40018000
default-by-family: []
default-by-variant:
- value: 0x10000000
variants:

View File

@@ -34,7 +34,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 On-Line Applications Research (OAR)
default: null
default-by-family: []
default-by-variant: []
description: ''
enabled-by: true

View File

@@ -11,7 +11,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 On-Line Applications Research (OAR)
default: null
default-by-family: []
default-by-variant: []
description: ''
enabled-by: true

View File

@@ -12,7 +12,6 @@ default:
- -mfpu=neon
- -mfloat-abi=hard
- -mtune=cortex-a9
default-by-family: []
default-by-variant: []
description: |
ABI flags

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: false
default-by-family: []
default-by-variant: []
description: |
define to set ARM Cortex-A9 MPCore PERIPHCLK clock frequency in Hz, otherwise alt_clk_freq_get() is used

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: true
default-by-family: []
default-by-variant: []
description: |
enable data cache

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: true
default-by-family: []
default-by-variant: []
description: |
enable instruction cache

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: false
default-by-family: []
default-by-variant:
- value: true
variants:

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: true
default-by-family: []
default-by-variant: []
description: |
configuration for console (UART 0)

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: true
default-by-family: []
default-by-variant: []
description: |
configuration for UART 1

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: true
default-by-family: []
default-by-variant: []
description: |
define if FDT is supported

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: 100000
default-by-family: []
default-by-variant: []
description: |
speed for I2C0 in HZ

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: true
default-by-family: []
default-by-variant: []
description: |
Number of configured I2C buses. Note that each bus has to be configured in an apropriate i2cdrv_config array.

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: false
default-by-family: []
default-by-variant: []
description: |
reset vector address for BSP start

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: 115200
default-by-family: []
default-by-variant: []
description: |
baud for UARTs

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: true
default-by-family: []
default-by-variant: []
description: |
enable usage of interrupts for the UART modules

View File

@@ -11,7 +11,6 @@ default:
- -mcpu=cortex-m7
- -mfpu=fpv5-d16
- -mfloat-abi=hard
default-by-family: []
default-by-variant: []
description: |
ABI flags

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: false
default-by-family: []
default-by-variant: []
description: |
Move the functions that set up the clock into the SRAM. This allows to change the clock frequency even if the application is started from SDRAM. Requires a TCM_SIZE > 0.

View File

@@ -44,7 +44,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: samv71q21
default-by-family: []
default-by-variant: []
description: |
Chip variant

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: 115200
default-by-family: []
default-by-variant: []
description: |
initial baud for console devices (default 115200)

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: true
default-by-family: []
default-by-variant: []
description: |
device index for /dev/console (default 1, e.g. USART1)

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: true
default-by-family: []
default-by-variant: []
description: |
use interrupt driven mode for console devices (used by default)

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: false
default-by-family: []
default-by-variant: []
description: |
device type for /dev/console, use 0 for USART and 1 for UART (default USART)

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: 123000000
default-by-family: []
default-by-variant: []
description: |
Frequency of the MCK in Hz. Set to 0 to force application defined speed. See start/pmc-config.c for available clock configurations.

View File

@@ -7,7 +7,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: 4096
default-by-family: []
default-by-variant: []
description: |
size of NOCACHE section in bytes

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: 12000000
default-by-family: []
default-by-variant: []
description: |
Main oscillator frequency in Hz (default 12MHz)

View File

@@ -7,7 +7,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: 2097152
default-by-family: []
default-by-variant: []
description: |
size of QSPI flash in bytes

View File

@@ -19,7 +19,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: is42s16100e-7bli
default-by-family: []
default-by-variant: []
description: |
SDRAM variant

View File

@@ -7,7 +7,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: 0
default-by-family: []
default-by-variant: []
description: |
size of tightly coupled memories (TCM) in bytes

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: true
default-by-family: []
default-by-variant: []
description: |
Use the external crystal as source for the slow clock instead of the internal RC oscillator. Note that on the ATSAM the NRST pin seems to depend on the slow clock as well as all watchdogs. If ATSAM_SLOWCLOCK_USE_XTAL is set to 1 without a external crystal connected, the controller might hang in the switching process without a working NRST pin.

View File

@@ -28,7 +28,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: null
default-by-family: []
default-by-variant: []
description: ''
enabled-by: true

View File

@@ -8,7 +8,6 @@ copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default:
- -mcpu=cortex-a8
default-by-family: []
default-by-variant: []
description: |
ABI flags

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: false
default-by-family: []
default-by-variant:
- value: true
variants:

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: 115200
default-by-family: []
default-by-variant: []
description: |
initial baud for console UART

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: false
default-by-family: []
default-by-variant: []
description: |
polled console i/o (e.g. to run testsuite)

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: false
default-by-family: []
default-by-variant:
- value: false
variants:

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: false
default-by-family: []
default-by-variant:
- value: true
variants:

View File

@@ -8,7 +8,6 @@ copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default:
- -mcpu=arm920
default-by-family: []
default-by-variant: []
description: |
ABI flags

View File

@@ -8,7 +8,6 @@ copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default:
- -mcpu=arm920
default-by-family: []
default-by-variant: []
description: |
ABI flags

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: false
default-by-family: []
default-by-variant:
- value: true
variants:

View File

@@ -7,7 +7,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: false
default-by-family: []
default-by-variant:
- value: false
variants:

View File

@@ -7,7 +7,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: true
default-by-family: []
default-by-variant: []
description: |
If defined, enable use of the uMon console.

View File

@@ -7,7 +7,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: true
default-by-family: []
default-by-variant: []
description: |
If defined, enable use of the MicroMonitor console device.

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: true
default-by-family: []
default-by-variant: []
description: |
If defined, enable use of the USART 0.

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: true
default-by-family: []
default-by-variant: []
description: |
If defined, enable use of the USART 1.

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: true
default-by-family: []
default-by-variant: []
description: |
If defined, enable use of the USART 2.

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: true
default-by-family: []
default-by-variant: []
description: |
If defined, enable use of the USART 3.

View File

@@ -8,7 +8,6 @@ copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default:
- -mcpu=arm7tdmi
default-by-family: []
default-by-variant: []
description: |
ABI flags

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: false
default-by-family: []
default-by-variant: []
description: |
If defined, enable options which optimize executingon the Skyeye simulator. Speed up the clock ticks while the idle task is running so time spent in the idle task is minimized. This significantly reduces the wall time required to execute the RTEMS test suites.

View File

@@ -11,7 +11,6 @@ default:
- -mthumb
- -mfloat-abi=hard
- -mfpu=auto
default-by-family: []
default-by-variant: []
description: |
ABI flags

View File

@@ -9,7 +9,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: 436207616
default-by-family: []
default-by-variant:
- value: 2583691264
variants:

View File

@@ -8,7 +8,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: 354418688
default-by-family: []
default-by-variant: []
description: |
Defines the size in bytes of the device area.

View File

@@ -8,7 +8,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: 2147483648
default-by-family: []
default-by-variant:
- value: 1024
variants:

View File

@@ -8,7 +8,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: 33554432
default-by-family: []
default-by-variant:
- value: 33553408
variants:

View File

@@ -8,7 +8,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: 1048576
default-by-family: []
default-by-variant:
- value: 1024
variants:

View File

@@ -8,7 +8,6 @@ copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default:
- -mcpu=xscale
default-by-family: []
default-by-variant: []
description: |
ABI flags

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: false
default-by-family: []
default-by-variant: []
description: |
If defined, enable options which optimize executingon the Skyeye simulator. Speed up the clock ticks while the idle task is running so time spent in the idle task is minimized. This significantly reduces the wall time required to execute the RTEMS test suites.

View File

@@ -12,7 +12,6 @@ default:
- -mfpu=neon
- -mfloat-abi=hard
- -mtune=cortex-a7
default-by-family: []
default-by-variant: []
description: |
ABI flags

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: true
default-by-family: []
default-by-variant:
- value: false
variants:

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: true
default-by-family: []
default-by-variant:
- value: false
variants:

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: 135000000
default-by-family: []
default-by-variant: []
description: |
AHB clock frequency in Hz

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: 67500000
default-by-family: []
default-by-variant: []
description: |
ECSPI clock frequency in Hz

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: 67500000
default-by-family: []
default-by-variant: []
description: |
IPG clock frequency in Hz

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: 196363000
default-by-family: []
default-by-variant: []
description: |
SDHCI clock frequency in Hz

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: 24000000
default-by-family: []
default-by-variant: []
description: |
UART clock frequency in Hz

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: 1
default-by-family: []
default-by-variant: []
description: |
use interrupt driven mode for console devices (used by default)

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: false
default-by-family: []
default-by-variant: []
description: |
reset vector address for BSP start

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@@ -11,7 +11,6 @@ default:
- -mcpu=cortex-m7
- -mfpu=fpv5-d16
- -mfloat-abi=hard
default-by-family: []
default-by-variant: []
description: |
ABI flags

View File

@@ -6,7 +6,6 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: true
default-by-family: []
default-by-variant: []
description: |
Enable the minor loop mapping of the Freescale EDMA.

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@@ -3,7 +3,6 @@ actions:
- env-assign: null
build-type: option
default: linkcmds.flexspi
default-by-family: []
default-by-variant: []
enabled-by: true
format: '{}'

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