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arm: Simplify default exception handling
Writes to the execution state bits of the CPSR through MRS instructions are ignored.
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@@ -103,7 +103,6 @@ save_more_context:
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mrs r3, spsr
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mrs r7, cpsr
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orr r5, r5, r3
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bic r5, #ARM_PSR_T
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msr cpsr, r5
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mov r0, sp
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mov r1, lr
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