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bsps/uC5282: Convert tabs to spaces

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Most of these files were mixed spaces/tabs, this normalizes it
This commit is contained in:
Jeremy Lorelli
2025-07-16 16:03:34 -07:00
committed by Kinsey Moore
parent 272d355c42
commit d8c5b7fa85
4 changed files with 500 additions and 495 deletions
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22
bsps/m68k/uC5282/clock/clock.c
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@@ -101,17 +101,17 @@ static void uC5282_tc_tick(void)
unsigned long long N; \
int level; \
int preScaleCode = 0; \
N = bsp_get_CPU_clock_speed(); \
N *= rtems_configuration_get_microseconds_per_tick(); \
N /= 2*1000000; /* min_prescale * us_per_s */ \
while ( N > 0x10000 ) { \
preScaleCode++; \
N >>= 1; \
} \
PITC_PER_TICK = N; \
N = 2000000000ULL << preScaleCode; \
N /= bsp_get_CPU_clock_speed(); \
NSEC_PER_PITC = N; \
N = bsp_get_CPU_clock_speed(); \
N *= rtems_configuration_get_microseconds_per_tick(); \
N /= 2*1000000; /* min_prescale * us_per_s */ \
while ( N > 0x10000 ) { \
preScaleCode++; \
N >>= 1; \
} \
PITC_PER_TICK = N; \
N = 2000000000ULL << preScaleCode; \
N /= bsp_get_CPU_clock_speed(); \
NSEC_PER_PITC = N; \
IDLE_COUNTER = 0; \
FILTERED_IDLE = 0; \
MAX_IDLE_COUNT = 0; \

850
bsps/m68k/uC5282/console/console.c
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File diff suppressed because it is too large Load Diff

16
bsps/m68k/uC5282/include/bsp.h
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@@ -166,14 +166,14 @@ typedef struct mcf5282BufferDescriptor_ {
} mcf5282BufferDescriptor_t;
extern struct {
uint32_t idle_counter;
uint32_t filtered_idle;
uint32_t max_idle_count;
uint32_t pitc_per_tick;
uint32_t nsec_per_pitc;
uint32_t pad[3]; /* align to 16-bytes for descriptors */
mcf5282BufferDescriptor_t fec_descriptors[];
/* buffer descriptors are allocated from here */
uint32_t idle_counter;
uint32_t filtered_idle;
uint32_t max_idle_count;
uint32_t pitc_per_tick;
uint32_t nsec_per_pitc;
uint32_t pad[3]; /* align to 16-bytes for descriptors */
mcf5282BufferDescriptor_t fec_descriptors[];
/* buffer descriptors are allocated from here */
/* initial stack is at top of SRAM (start.S) */
} __SRAMBASE;

107
bsps/m68k/uC5282/start/bspstart.c
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@@ -255,67 +255,70 @@ void bsp_start( void )
printk("Checking ENV variable SYS_CLOCK_SPEED:\n");
if ( (clk_speed_str = bsp_getbenv("SYS_CLOCK_SPEED")) ) {
printk("Found: %s\n", clk_speed_str);
for ( clk_speed = 0, i=0;
clk_speed_str[i] >= '0' && clk_speed_str[i] <= '9';
i++ ) {
clk_speed = 10*clk_speed + clk_speed_str[i] - '0';
}
if ( 0 != clk_speed_str[i] ) {
printk("Not a decimal number; I'm not using this setting\n");
clk_speed = 0;
}
for ( clk_speed = 0, i=0;
clk_speed_str[i] >= '0' && clk_speed_str[i] <= '9';
i++ ) {
clk_speed = 10*clk_speed + clk_speed_str[i] - '0';
}
if ( 0 != clk_speed_str[i] ) {
printk("Not a decimal number; I'm not using this setting\n");
clk_speed = 0;
}
} else {
printk("Not set.\n");
}
if ( 0 == clk_speed )
clk_speed = BSP_sys_clk_speed;
if ( 0 == clk_speed ) {
printk("Using some heuristics to determine clock speed...\n");
byte = MCF5282_CLOCK_SYNSR;
if ( 0 == byte ) {
printk("SYNSR == 0; assuming QEMU at 66MHz\n");
BSP_pll_ref_clock = 8250000;
mfd = ( 0 << 8 ) | ( 2 << 12 );
} else {
if ( 0xf8 != byte ) {
printk(
"FATAL ERROR: Unexpected SYNSR contents "
"(0x%02x), can't proceed\n", byte);
bsp_sysReset(0);
}
mfd = MCF5282_CLOCK_SYNCR;
}
printk("Assuming %" PRIu32 "Hz PLL ref. clock\n", BSP_pll_ref_clock);
rfd = (mfd >> 8) & 7;
mfd = (mfd >> 12) & 7;
/* Check against 'known' cases */
if ( 0 != rfd || (2 != mfd && 3 != mfd) ) {
printk("WARNING: Pll divisor/multiplier has unknown value; \n");
printk(" either your board is not 64MHz or 80Mhz or\n");
printk(" it uses a PLL reference other than 8MHz.\n");
printk(" I'll proceed anyways but you might have to\n");
printk(" reset the board and set uCbootloader ENV\n");
printk(" variable \"SYS_CLOCK_SPEED\".\n");
}
mfd = 2 * (mfd + 2);
/* sysclk = pll_ref * 2 * (MFD + 2) / 2^(rfd) */
printk(
"PLL multiplier: %" PRIu32", output divisor: %" PRIu32 "\n",
mfd,
rfd
);
clk_speed = (BSP_pll_ref_clock * mfd) >> rfd;
clk_speed = BSP_sys_clk_speed;
}
if ( 0 == clk_speed ) {
printk("FATAL ERROR: Unable to determine system clock speed\n");
bsp_sysReset(0);
printk("Using some heuristics to determine clock speed...\n");
byte = MCF5282_CLOCK_SYNSR;
if ( 0 == byte ) {
printk("SYNSR == 0; assuming QEMU at 66MHz\n");
BSP_pll_ref_clock = 8250000;
mfd = ( 0 << 8 ) | ( 2 << 12 );
} else {
if ( 0xf8 != byte ) {
printk(
"FATAL ERROR: Unexpected SYNSR contents "
"(0x%02x), can't proceed\n", byte
);
bsp_sysReset(0);
}
mfd = MCF5282_CLOCK_SYNCR;
}
printk("Assuming %" PRIu32 "Hz PLL ref. clock\n", BSP_pll_ref_clock);
rfd = (mfd >> 8) & 7;
mfd = (mfd >> 12) & 7;
/* Check against 'known' cases */
if ( 0 != rfd || (2 != mfd && 3 != mfd) ) {
printk("WARNING: Pll divisor/multiplier has unknown value; \n");
printk(" either your board is not 64MHz or 80Mhz or\n");
printk(" it uses a PLL reference other than 8MHz.\n");
printk(" I'll proceed anyways but you might have to\n");
printk(" reset the board and set uCbootloader ENV\n");
printk(" variable \"SYS_CLOCK_SPEED\".\n");
}
mfd = 2 * (mfd + 2);
/* sysclk = pll_ref * 2 * (MFD + 2) / 2^(rfd) */
printk(
"PLL multiplier: %" PRIu32", output divisor: %" PRIu32 "\n",
mfd,
rfd
);
clk_speed = (BSP_pll_ref_clock * mfd) >> rfd;
}
if ( 0 == clk_speed ) {
printk("FATAL ERROR: Unable to determine system clock speed\n");
bsp_sysReset(0);
} else {
BSP_sys_clk_speed = clk_speed;
printk(
"System clock speed: %" PRIu32 "Hz\n", bsp_get_CPU_clock_speed());
BSP_sys_clk_speed = clk_speed;
printk(
"System clock speed: %" PRIu32 "Hz\n", bsp_get_CPU_clock_speed()
);
}
}