bsps/stm32u5-grisp-nano: New BSP

This BSP supports a custom STM32U5 based board. It uses a similar structure like the existing STM32H7 BSP and therefore should be well adaptable to other boards. Co-authored-by: Christian Mauderer <christian.mauderer@embedded-brains.de>
2025-11-16 12:34:45 +00:00 · 2024-06-25 16:22:49 +02:00
parent 03aedc0539
commit d735d4459c
50 changed files with 2921 additions and 1 deletions
--- a/spec/build/bsps/arm/grp.yml
+++ b/spec/build/bsps/arm/grp.yml
@@ -14,9 +14,11 @@ install:
  - bsps/arm/include/cmsis_compiler.h
  - bsps/arm/include/cmsis_gcc.h
  - bsps/arm/include/cmsis_version.h
-  - bsps/arm/include/core_cm7.h
+  - bsps/arm/include/core_cm33.h
  - bsps/arm/include/core_cm4.h
+  - bsps/arm/include/core_cm7.h
  - bsps/arm/include/mpu_armv7.h
+  - bsps/arm/include/mpu_armv8.h
 - destination: ${BSP_INCLUDEDIR}/bsp
  source:
  - bsps/arm/include/bsp/arm-a9mpcore-clock.h
--- a/spec/build/bsps/arm/stm32u5/abi.yml
+++ b/spec/build/bsps/arm/stm32u5/abi.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-string: null
+- split: null
+- env-append: null
+build-type: option
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+default:
+- enabled-by: true
+  value:
+  - -mthumb
+  - -mcpu=cortex-m33
+description: |
+  ABI flags
+enabled-by: true
+links: []
+name: ABI_FLAGS
+type: build
--- a/spec/build/bsps/arm/stm32u5/bspstm32u5-grisp-nano.yml
+++ b/spec/build/bsps/arm/stm32u5/bspstm32u5-grisp-nano.yml
@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: arm
+bsp: stm32u5-grisp-nano
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+cppflags: []
+enabled-by: true
+family: stm32u5
+includes: []
+install: []
+links:
+- role: build-dependency
+  uid: grp
+source: []
+type: build
--- a/spec/build/bsps/arm/stm32u5/grp.yml
+++ b/spec/build/bsps/arm/stm32u5/grp.yml
@@ -0,0 +1,69 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: group
+cflags: []
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+cppflags: []
+cxxflags: []
+enabled-by: true
+includes: []
+install: []
+ldflags: []
+links:
+- role: build-dependency
+  uid: ../../obj
+- role: build-dependency
+  uid: ../../objirq
+- role: build-dependency
+  uid: ../../opto2
+- role: build-dependency
+  uid: abi
+- role: build-dependency
+  uid: obj
+- role: build-dependency
+  uid: optmemflashsz
+- role: build-dependency
+  uid: optmemnullsz
+- role: build-dependency
+  uid: optmemintsramsz
+- role: build-dependency
+  uid: optmemintsramlpbamsz
+- role: build-dependency
+  uid: optmemoctospi1sz
+- role: build-dependency
+  uid: optmemoctospi2sz
+- role: build-dependency
+  uid: optprintkinstance
+- role: build-dependency
+  uid: optusart1gpiopins
+- role: build-dependency
+  uid: optusart2gpiopins
+- role: build-dependency
+  uid: optusart3gpiopins
+- role: build-dependency
+  uid: optenusart1
+- role: build-dependency
+  uid: optenusart2
+- role: build-dependency
+  uid: optenusart3
+- role: build-dependency
+  uid: optlinkcmds
+- role: build-dependency
+  uid: ../../objmem
+- role: build-dependency
+  uid: ../grp
+- role: build-dependency
+  uid: ../start
+- role: build-dependency
+  uid: linkcmds
+- role: build-dependency
+  uid: linkcmdsmemory
+- role: build-dependency
+  uid: ../../bspopts
+- role: build-dependency
+  uid: ../../optconsolebaud
+- role: build-dependency
+  uid: ../../optconsoleirq
+type: build
+use-after: []
+use-before: []
--- a/spec/build/bsps/arm/stm32u5/linkcmds.yml
+++ b/spec/build/bsps/arm/stm32u5/linkcmds.yml
@@ -0,0 +1,11 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: config-file
+content: |
+  INCLUDE ${STM32U5_DEFAULT_LINKCMDS}
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+enabled-by: true
+install-path: ${BSP_LIBDIR}
+links: []
+target: linkcmds
+type: build
--- a/spec/build/bsps/arm/stm32u5/linkcmdsmemory.yml
+++ b/spec/build/bsps/arm/stm32u5/linkcmdsmemory.yml
@@ -0,0 +1,42 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: config-file
+content: |
+  MEMORY {
+    NULL           : ORIGIN = 0x00000000, LENGTH = ${STM32U5_MEMORY_NULL_SIZE:#010x}
+    FLASH          : ORIGIN = 0x08000000, LENGTH = ${STM32U5_MEMORY_FLASH_SIZE:#010x}
+    INT_SRAM       : ORIGIN = 0x20000000, LENGTH = ${STM32U5_MEMORY_INT_SRAM_SIZE:#010x}
+    INT_SRAM_LPBAM : ORIGIN = 0x28000000, LENGTH = ${STM32U5_MEMORY_INT_SRAM_LPBAM_SIZE:#010x}
+    OCTOSPI_2      : ORIGIN = 0x70000000, LENGTH = ${STM32U5_MEMORY_OCTOSPI_2_SIZE:#010x}
+    OCTOSPI_1      : ORIGIN = 0x90000000, LENGTH = ${STM32U5_MEMORY_OCTOSPI_1_SIZE:#010x}
+  }
+
+  stm32u5_memory_null_begin = ORIGIN (NULL);
+  stm32u5_memory_null_end = ORIGIN (NULL) + LENGTH (NULL);
+  stm32u5_memory_null_size = LENGTH (NULL);
+
+  stm32u5_memory_flash_begin = ORIGIN (FLASH);
+  stm32u5_memory_flash_end = ORIGIN (FLASH) + LENGTH (FLASH);
+  stm32u5_memory_flash_size = LENGTH (FLASH);
+
+  stm32u5_memory_int_sram_begin = ORIGIN (INT_SRAM);
+  stm32u5_memory_int_sram_end = ORIGIN (INT_SRAM) + LENGTH (INT_SRAM);
+  stm32u5_memory_int_sram_size = LENGTH (INT_SRAM);
+
+  stm32u5_memory_int_sram_lpbam_begin = ORIGIN (INT_SRAM_LPBAM);
+  stm32u5_memory_int_sram_lpbam_end = ORIGIN (INT_SRAM_LPBAM) + LENGTH (INT_SRAM_LPBAM);
+  stm32u5_memory_int_sram_lpbam_size = LENGTH (INT_SRAM_LPBAM);
+
+  stm32u5_memory_octospi_1_begin = ORIGIN (OCTOSPI_1);
+  stm32u5_memory_octospi_1_end = ORIGIN (OCTOSPI_1) + LENGTH (OCTOSPI_1);
+  stm32u5_memory_octospi_1_size = LENGTH (OCTOSPI_1);
+
+  stm32u5_memory_octospi_2_begin = ORIGIN (OCTOSPI_2);
+  stm32u5_memory_octospi_2_end = ORIGIN (OCTOSPI_2) + LENGTH (OCTOSPI_2);
+  stm32u5_memory_octospi_2_size = LENGTH (OCTOSPI_2);
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+enabled-by: true
+install-path: ${BSP_LIBDIR}
+links: []
+target: linkcmds.memory
+type: build
--- a/spec/build/bsps/arm/stm32u5/obj.yml
+++ b/spec/build/bsps/arm/stm32u5/obj.yml
@@ -0,0 +1,312 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: objects
+cflags: []
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+cppflags: []
+cxxflags: []
+enabled-by: true
+includes: []
+install:
+- destination: ${BSP_INCLUDEDIR}
+  source:
+  - bsps/arm/stm32u5/include/bsp.h
+  - bsps/arm/stm32u5/include/chip.h
+  - bsps/arm/stm32u5/include/tm27.h
+  - bsps/arm/stm32u5/include/stm32u5xx.h
+  - bsps/arm/stm32u5/include/stm32u5g9xx.h
+  - bsps/arm/stm32u5/include/system_stm32u5xx.h
+  - bsps/arm/stm32u5/include/stm32u5xx_ll_cortex.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_smbus.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_flash.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_exti.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_otfdec.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_adc_ex.h
+  - bsps/arm/stm32u5/include/stm32u5xx_ll_iwdg.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_hcd.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_sd_ex.h
+  - bsps/arm/stm32u5/include/stm32u5xx_ll_fmc.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_spi.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_dsi.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_xspi.h
+  - bsps/arm/stm32u5/include/stm32u5xx_ll_dma2d.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_tim_ex.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_mdf.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_dma_ex.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_mmc.h
+  - bsps/arm/stm32u5/include/stm32u5xx_ll_crc.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_def.h
+  - bsps/arm/stm32u5/include/stm32u5xx_ll_rtc.h
+  - bsps/arm/stm32u5/include/stm32u5xx_ll_sdmmc.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_gtzc.h
+  - bsps/arm/stm32u5/include/stm32u5xx_ll_rng.h
+  - bsps/arm/stm32u5/include/stm32u5xx_ll_dma.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_rng.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_gpu2d.h
+  - bsps/arm/stm32u5/include/stm32_assert.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_nand.h
+  - bsps/arm/stm32u5/include/stm32u5xx_ll_tim.h
+  - bsps/arm/stm32u5/include/stm32u5xx_ll_ucpd.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_wwdg.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_dcache.h
+  - bsps/arm/stm32u5/include/stm32u5xx_ll_lpuart.h
+  - bsps/arm/stm32u5/include/stm32u5xx_ll_spi.h
+  - bsps/arm/stm32u5/include/stm32u5xx_ll_comp.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_fdcan.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_cryp_ex.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_rng_ex.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_rtc.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_adc.h
+  - bsps/arm/stm32u5/include/stm32u5xx_ll_pwr.h
+  - bsps/arm/stm32u5/include/stm32u5xx_ll_fmac.h
+  - bsps/arm/stm32u5/include/stm32u5xx_ll_lptim.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_dma.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_sai.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_gfxtim.h
+  - bsps/arm/stm32u5/include/stm32u5xx_ll_dac.h
+  - bsps/arm/stm32u5/include/stm32u5xx_ll_dcache.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_crc.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_crc_ex.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_pwr_ex.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_usart.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_rtc_ex.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_opamp_ex.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_sai_ex.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_ospi.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_rcc.h
+  - bsps/arm/stm32u5/include/stm32u5xx_ll_system.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_usart_ex.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_i2c_ex.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_tsc.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_smartcard.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_irda_ex.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_pcd_ex.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_jpeg.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_cortex.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_tim.h
+  - bsps/arm/stm32u5/include/stm32u5xx_ll_pka.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_cordic.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_pwr.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_gpio_ex.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_gpio.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_dac.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_smbus_ex.h
+  - bsps/arm/stm32u5/include/stm32u5xx_ll_icache.h
+  - bsps/arm/stm32u5/include/stm32u5xx_ll_opamp.h
+  - bsps/arm/stm32u5/include/stm32u5xx_ll_bus.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_nor.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_pssi.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_dac_ex.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_spi_ex.h
+  - bsps/arm/stm32u5/include/stm32u5xx_ll_crs.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_sd.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_ramcfg.h
+  - bsps/arm/stm32u5/include/stm32u5xx_ll_wwdg.h
+  - bsps/arm/stm32u5/include/stm32u5xx_ll_usart.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_i2c.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_uart_ex.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_sram.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_opamp.h
+  - bsps/arm/stm32u5/include/stm32u5xx_ll_exti.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_smartcard_ex.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_iwdg.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_dma2d.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_ltdc_ex.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_pka.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_mmc_ex.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_cryp.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_pcd.h
+  - bsps/arm/stm32u5/include/stm32u5xx_ll_adc.h
+  - bsps/arm/stm32u5/include/stm32u5xx_ll_gpio.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_comp.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_gfxmmu.h
+  - bsps/arm/stm32u5/include/stm32u5xx_ll_dlyb.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_uart.h
+  - bsps/arm/stm32u5/include/stm32u5xx_ll_cordic.h
+  - bsps/arm/stm32u5/include/stm32u5xx_ll_i2c.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_hash.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_rcc_ex.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_dcmi.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_flash_ex.h
+  - bsps/arm/stm32u5/include/stm32u5xx_ll_usb.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_fmac.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_lptim.h
+  - bsps/arm/stm32u5/include/stm32u5xx_ll_utils.h
+  - bsps/arm/stm32u5/include/stm32u5xx_ll_lpgpio.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_irda.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_icache.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_ltdc.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_hash_ex.h
+  - bsps/arm/stm32u5/include/stm32u5xx_ll_rcc.h
+  - bsps/arm/stm32u5/include/stm32u5xx_hal_conf.h
+- destination: ${BSP_INCLUDEDIR}/Legacy
+  source:
+  - bsps/arm/stm32u5/include/Legacy/stm32_hal_legacy.h
+- destination: ${BSP_INCLUDEDIR}/bsp
+  source:
+  - bsps/arm/stm32u5/include/bsp/irq.h
+- destination: ${BSP_INCLUDEDIR}/stm32u5
+  source:
+  - bsps/arm/stm32u5/include/stm32u5/hal.h
+- destination: ${BSP_LIBDIR}
+  source:
+  - bsps/arm/stm32u5/start/linkcmds.flash
+  - bsps/arm/stm32u5/start/linkcmds.flash+ospi
+  - bsps/arm/stm32u5/start/linkcmds.sram
+  - bsps/arm/stm32u5/start/linkcmds.ospi
+links: []
+source:
+- bsps/arm/shared/clock/clock-armv7m.c
+- bsps/arm/shared/cpucounter/cpucounter-armv7m.c
+- bsps/arm/shared/irq/irq-armv7m.c
+- bsps/arm/shared/irq/irq-dispatch-armv7m.c
+- bsps/arm/shared/start/bsp-start-memcpy.S
+- bsps/arm/shared/start/bspreset-armv7m.c
+- bsps/shared/dev/btimer/btimer-cpucounter.c
+- bsps/shared/dev/rtc/rtc-support.c
+- bsps/shared/dev/serial/console-termios.c
+- bsps/shared/irq/irq-default-handler.c
+- bsps/shared/start/bspfatal-default.c
+- bsps/shared/start/gettargethash-default.c
+- bsps/shared/start/sbrk.c
+- bsps/shared/start/stackalloc.c
+- bsps/arm/shared/cache/cache-v7m.c
+- bsps/arm/stm32u5/console/console.c
+- bsps/arm/stm32u5/console/printk-support.c
+- bsps/arm/stm32u5/console/console-usart1.c
+- bsps/arm/stm32u5/console/console-usart1-cfg.c
+- bsps/arm/stm32u5/console/console-usart2.c
+- bsps/arm/stm32u5/console/console-usart2-cfg.c
+- bsps/arm/stm32u5/console/console-usart3.c
+- bsps/arm/stm32u5/console/console-usart3-cfg.c
+- bsps/arm/stm32u5/start/bspstart.c
+- bsps/arm/stm32u5/start/bspstarthooks.c
+- bsps/arm/stm32u5/start/getentropy-rng.c
+- bsps/arm/stm32u5/start/stm32u5-hal.c
+- bsps/arm/stm32u5/start/stm32u5-config-clk.c
+- bsps/arm/stm32u5/start/stm32u5-config-osc.c
+- bsps/arm/stm32u5/start/stm32u5-config-per.c
+- bsps/arm/stm32u5/start/stm32u5-hal-uart.c
+- bsps/arm/stm32u5/start/stm32u5-hal-sdmmc.c
+- bsps/arm/stm32u5/start/stm32u5-init-octospi.c
+- bsps/arm/stm32u5/start/stm32u5-config-rtc.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_rtc.c
+- bsps/arm/stm32u5/hal/system_stm32u5xx.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_dac_ex.c
+- bsps/arm/stm32u5/hal/stm32u5xx_ll_spi.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_opamp_ex.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_nand.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_lptim.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_usart_ex.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_gpio.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_uart_ex.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_rng.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_timebase_rtc_alarm.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_comp.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_sai.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_dcmi.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_wwdg.c
+- bsps/arm/stm32u5/hal/stm32u5xx_ll_usart.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_tsc.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_ospi.c
+- bsps/arm/stm32u5/hal/stm32u5xx_ll_crc.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_dac.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_pcd.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_xspi.c
+- bsps/arm/stm32u5/hal/stm32u5xx_ll_adc.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_dma_ex.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_dma2d.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_irda.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_rcc.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_nor.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_pwr.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_adc.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_usart.c
+- bsps/arm/stm32u5/hal/stm32u5xx_ll_rcc.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_otfdec.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_i2c_ex.c
+- bsps/arm/stm32u5/hal/stm32u5xx_ll_lpgpio.c
+- bsps/arm/stm32u5/hal/stm32u5xx_ll_crs.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_sai_ex.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_mmc.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_mmc_ex.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_sram.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_spi.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_timebase_tim.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_cordic.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_msp.c
+- bsps/arm/stm32u5/hal/stm32u5xx_ll_pwr.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_dcache.c
+- bsps/arm/stm32u5/hal/stm32u5xx_ll_ucpd.c
+- bsps/arm/stm32u5/hal/stm32u5xx_ll_icache.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_hash_ex.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_pka.c
+- bsps/arm/stm32u5/hal/stm32u5xx_ll_fmac.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_opamp.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_ltdc.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_pssi.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_jpeg.c
+- bsps/arm/stm32u5/hal/stm32u5xx_ll_cordic.c
+- bsps/arm/stm32u5/hal/stm32u5xx_ll_exti.c
+- bsps/arm/stm32u5/hal/stm32u5xx_ll_pka.c
+- bsps/arm/stm32u5/hal/stm32u5xx_ll_utils.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_cryp_ex.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_fmac.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_rcc_ex.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_icache.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_hcd.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_timebase_rtc_wakeup.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_uart.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_flash.c
+- bsps/arm/stm32u5/hal/stm32u5xx_ll_gpio.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_rtc_ex.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_smbus_ex.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_smbus.c
+- bsps/arm/stm32u5/hal/stm32u5xx_ll_dac.c
+- bsps/arm/stm32u5/hal/stm32u5xx_ll_opamp.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_dsi.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_pwr_ex.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_gfxmmu.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_cortex.c
+- bsps/arm/stm32u5/hal/stm32u5xx_ll_sdmmc.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_fdcan.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_adc_ex.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_tim.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_smartcard_ex.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_smartcard.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_gfxtim.c
+- bsps/arm/stm32u5/hal/stm32u5xx_ll_lptim.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_exti.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_tim_ex.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_pcd_ex.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_sd.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_flash_ex.c
+- bsps/arm/stm32u5/hal/stm32u5xx_ll_rng.c
+- bsps/arm/stm32u5/hal/stm32u5xx_ll_lpuart.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_ramcfg.c
+- bsps/arm/stm32u5/hal/stm32u5xx_ll_dlyb.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_sd_ex.c
+- bsps/arm/stm32u5/hal/stm32u5xx_ll_fmc.c
+- bsps/arm/stm32u5/hal/stm32u5xx_ll_tim.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_cryp.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_dma.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal.c
+- bsps/arm/stm32u5/hal/stm32u5xx_ll_dma.c
+- bsps/arm/stm32u5/hal/stm32u5xx_ll_i2c.c
+- bsps/arm/stm32u5/hal/stm32u5xx_ll_rtc.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_spi_ex.c
+- bsps/arm/stm32u5/hal/stm32u5xx_ll_usb.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_crc_ex.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_crc.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_i2c.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_gpu2d.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_ltdc_ex.c
+- bsps/arm/stm32u5/hal/stm32u5xx_ll_comp.c
+- bsps/arm/stm32u5/hal/stm32u5xx_ll_dma2d.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_iwdg.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_hash.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_mdf.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_gtzc.c
+- bsps/arm/stm32u5/hal/stm32u5xx_hal_rng_ex.c
+type: build
--- a/spec/build/bsps/arm/stm32u5/optenusart1.yml
+++ b/spec/build/bsps/arm/stm32u5/optenusart1.yml
@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-boolean: null
+- define-condition: null
+build-type: option
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+default:
+- enabled-by: true
+  value: false
+description: |
+  Enable USART1 device in console driver.
+enabled-by: true
+format: '{}'
+links: []
+name: STM32U5_CONSOLE_ENABLE_USART1
+type: build
--- a/spec/build/bsps/arm/stm32u5/optenusart2.yml
+++ b/spec/build/bsps/arm/stm32u5/optenusart2.yml
@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-boolean: null
+- define-condition: null
+build-type: option
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+default:
+- enabled-by: true
+  value: true
+description: |
+  Enable USART2 device in console driver.
+enabled-by: true
+format: '{}'
+links: []
+name: STM32U5_CONSOLE_ENABLE_USART2
+type: build
--- a/spec/build/bsps/arm/stm32u5/optenusart3.yml
+++ b/spec/build/bsps/arm/stm32u5/optenusart3.yml
@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-boolean: null
+- define-condition: null
+build-type: option
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+default:
+- enabled-by: true
+  value: false
+description: |
+  Enable USART3 device in console driver.
+enabled-by: true
+format: '{}'
+links: []
+name: STM32U5_CONSOLE_ENABLE_USART3
+type: build
--- a/spec/build/bsps/arm/stm32u5/optlinkcmds.yml
+++ b/spec/build/bsps/arm/stm32u5/optlinkcmds.yml
@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-string: null
+- env-assign: null
+build-type: option
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+default:
+- enabled-by: true
+  value: linkcmds.flash
+description: |
+  The default linker command file
+enabled-by: true
+format: '{}'
+links: []
+name: STM32U5_DEFAULT_LINKCMDS
+type: build
--- a/spec/build/bsps/arm/stm32u5/optmemflashsz.yml
+++ b/spec/build/bsps/arm/stm32u5/optmemflashsz.yml
@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- env-assign: null
+build-type: option
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+default:
+- enabled-by: true
+  value: 0x00400000
+description: |
+  Size of the FLASH memory area in bytes.
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: STM32U5_MEMORY_FLASH_SIZE
+type: build
--- a/spec/build/bsps/arm/stm32u5/optmemintsramlpbamsz.yml
+++ b/spec/build/bsps/arm/stm32u5/optmemintsramlpbamsz.yml
@@ -0,0 +1,18 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- env-assign: null
+build-type: option
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+default:
+- enabled-by: true
+  value: 0x00004000
+description: |
+  Size of the peripheral low-power background autonomous mode (LPBAM / SRAM 4)
+  memory area in bytes.
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: STM32U5_MEMORY_INT_SRAM_LPBAM_SIZE
+type: build
--- a/spec/build/bsps/arm/stm32u5/optmemintsramsz.yml
+++ b/spec/build/bsps/arm/stm32u5/optmemintsramsz.yml
@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- env-assign: null
+build-type: option
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+default:
+- enabled-by: true
+  value: 0x002F0000
+description: |
+  Size of the Internal SRAM memory area in bytes.
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: STM32U5_MEMORY_INT_SRAM_SIZE
+type: build
--- a/spec/build/bsps/arm/stm32u5/optmemnullsz.yml
+++ b/spec/build/bsps/arm/stm32u5/optmemnullsz.yml
@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- env-assign: null
+build-type: option
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+default:
+- enabled-by: true
+  value: 0x00000000
+description: |
+  Size of the NULL pointer protection area in bytes.
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: STM32U5_MEMORY_NULL_SIZE
+type: build
--- a/spec/build/bsps/arm/stm32u5/optmemoctospi1sz.yml
+++ b/spec/build/bsps/arm/stm32u5/optmemoctospi1sz.yml
@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- env-assign: null
+build-type: option
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+default:
+- enabled-by: true
+  value: 0x1000000
+description: |
+  Size of the memory connected to OCTOSPI 1 in bytes.
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: STM32U5_MEMORY_OCTOSPI_1_SIZE
+type: build
--- a/spec/build/bsps/arm/stm32u5/optmemoctospi2sz.yml
+++ b/spec/build/bsps/arm/stm32u5/optmemoctospi2sz.yml
@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- env-assign: null
+build-type: option
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+default:
+- enabled-by: true
+  value: 0x10000000
+description: |
+  Size of the OCTOSPI 2 bank area in bytes.
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: STM32U5_MEMORY_OCTOSPI_2_SIZE
+type: build
--- a/spec/build/bsps/arm/stm32u5/optprintkinstance.yml
+++ b/spec/build/bsps/arm/stm32u5/optprintkinstance.yml
@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-string: null
+- define-unquoted: null
+build-type: option
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+default:
+- enabled-by: true
+  value: stm32u5_usart2_instance
+description: |
+  UART/USART instance used for printk() and getchark().
+enabled-by: true
+format: '{}'
+links: []
+name: STM32U5_PRINTK_INSTANCE
+type: build
--- a/spec/build/bsps/arm/stm32u5/optusart1gpiopins.yml
+++ b/spec/build/bsps/arm/stm32u5/optusart1gpiopins.yml
@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-string: null
+- define-unquoted: null
+build-type: option
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+default:
+- enabled-by: true
+  value: ( GPIO_PIN_9 | GPIO_PIN_10 )
+description: |
+  GPIO pins used for the USART1 pin configuration.
+enabled-by: true
+format: '{}'
+links: []
+name: STM32U5_USART1_GPIO_PINS
+type: build
--- a/spec/build/bsps/arm/stm32u5/optusart2gpiopins.yml
+++ b/spec/build/bsps/arm/stm32u5/optusart2gpiopins.yml
@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-string: null
+- define-unquoted: null
+build-type: option
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+default:
+- enabled-by: true
+  value: ( GPIO_PIN_2 | GPIO_PIN_3 )
+description: |
+  GPIO pins used for the USART2 pin configuration.
+enabled-by: true
+format: '{}'
+links: []
+name: STM32U5_USART2_GPIO_PINS
+type: build
--- a/spec/build/bsps/arm/stm32u5/optusart3gpiopins.yml
+++ b/spec/build/bsps/arm/stm32u5/optusart3gpiopins.yml
@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-string: null
+- define-unquoted: null
+build-type: option
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+default:
+- enabled-by: true
+  value: ( GPIO_PIN_8 | GPIO_PIN_9 )
+description: |
+  GPIO pins used for the USART3 pin configuration.
+enabled-by: true
+format: '{}'
+links: []
+name: STM32U5_USART3_GPIO_PINS
+type: build
--- a/spec/build/cpukit/optlibdebugger.yml
+++ b/spec/build/cpukit/optlibdebugger.yml
@@ -18,6 +18,7 @@ enabled-by:
  - not: bsps/arm/lpc24xx
  - not: bsps/arm/stm32h7
  - not: bsps/arm/stm32f4
+  - not: bsps/arm/stm32u5
 - i386
 - microblaze
 - and: