From d735d4459c126c17e1f0f1eb6ae441a6047664b0 Mon Sep 17 00:00:00 2001 From: Matt Joyce Date: Tue, 25 Jun 2024 16:22:49 +0200 Subject: [PATCH] bsps/stm32u5-grisp-nano: New BSP This BSP supports a custom STM32U5 based board. It uses a similar structure like the existing STM32H7 BSP and therefore should be well adaptable to other boards. Co-authored-by: Christian Mauderer --- bsps/arm/stm32u5/console/console-usart1-cfg.c | 55 +++ bsps/arm/stm32u5/console/console-usart1.c | 56 ++++ bsps/arm/stm32u5/console/console-usart2-cfg.c | 55 +++ bsps/arm/stm32u5/console/console-usart2.c | 56 ++++ bsps/arm/stm32u5/console/console-usart3-cfg.c | 55 +++ bsps/arm/stm32u5/console/console-usart3.c | 56 ++++ bsps/arm/stm32u5/console/console.c | 304 +++++++++++++++++ bsps/arm/stm32u5/console/printk-support.c | 99 ++++++ bsps/arm/stm32u5/include/bsp.h | 107 ++++++ bsps/arm/stm32u5/include/bsp/irq.h | 49 +++ bsps/arm/stm32u5/include/chip.h | 42 +++ bsps/arm/stm32u5/include/tm27.h | 11 + bsps/arm/stm32u5/start/bspstart.c | 50 +++ bsps/arm/stm32u5/start/bspstarthooks.c | 159 +++++++++ bsps/arm/stm32u5/start/getentropy-rng.c | 88 +++++ bsps/arm/stm32u5/start/linkcmds.flash | 23 ++ bsps/arm/stm32u5/start/linkcmds.flash+ospi | 23 ++ bsps/arm/stm32u5/start/linkcmds.ospi | 23 ++ bsps/arm/stm32u5/start/linkcmds.sram | 23 ++ bsps/arm/stm32u5/start/stm32u5-config-clk.c | 50 +++ bsps/arm/stm32u5/start/stm32u5-config-osc.c | 65 ++++ bsps/arm/stm32u5/start/stm32u5-config-per.c | 53 +++ bsps/arm/stm32u5/start/stm32u5-config-rtc.c | 143 ++++++++ bsps/arm/stm32u5/start/stm32u5-hal-sdmmc.c | 94 ++++++ bsps/arm/stm32u5/start/stm32u5-hal-uart.c | 53 +++ bsps/arm/stm32u5/start/stm32u5-hal.c | 187 +++++++++++ bsps/arm/stm32u5/start/stm32u5-init-octospi.c | 221 +++++++++++++ bsps/include/bsp/fatal.h | 8 + spec/build/bsps/arm/grp.yml | 4 +- spec/build/bsps/arm/stm32u5/abi.yml | 19 ++ .../arm/stm32u5/bspstm32u5-grisp-nano.yml | 17 + spec/build/bsps/arm/stm32u5/grp.yml | 69 ++++ spec/build/bsps/arm/stm32u5/linkcmds.yml | 11 + .../build/bsps/arm/stm32u5/linkcmdsmemory.yml | 42 +++ spec/build/bsps/arm/stm32u5/obj.yml | 312 ++++++++++++++++++ spec/build/bsps/arm/stm32u5/optenusart1.yml | 17 + spec/build/bsps/arm/stm32u5/optenusart2.yml | 17 + spec/build/bsps/arm/stm32u5/optenusart3.yml | 17 + spec/build/bsps/arm/stm32u5/optlinkcmds.yml | 17 + spec/build/bsps/arm/stm32u5/optmemflashsz.yml | 17 + .../bsps/arm/stm32u5/optmemintsramlpbamsz.yml | 18 + .../bsps/arm/stm32u5/optmemintsramsz.yml | 17 + spec/build/bsps/arm/stm32u5/optmemnullsz.yml | 17 + .../bsps/arm/stm32u5/optmemoctospi1sz.yml | 17 + .../bsps/arm/stm32u5/optmemoctospi2sz.yml | 17 + .../bsps/arm/stm32u5/optprintkinstance.yml | 17 + .../bsps/arm/stm32u5/optusart1gpiopins.yml | 17 + .../bsps/arm/stm32u5/optusart2gpiopins.yml | 17 + .../bsps/arm/stm32u5/optusart3gpiopins.yml | 17 + spec/build/cpukit/optlibdebugger.yml | 1 + 50 files changed, 2921 insertions(+), 1 deletion(-) create mode 100644 bsps/arm/stm32u5/console/console-usart1-cfg.c create mode 100644 bsps/arm/stm32u5/console/console-usart1.c create mode 100644 bsps/arm/stm32u5/console/console-usart2-cfg.c create mode 100644 bsps/arm/stm32u5/console/console-usart2.c create mode 100644 bsps/arm/stm32u5/console/console-usart3-cfg.c create mode 100644 bsps/arm/stm32u5/console/console-usart3.c create mode 100644 bsps/arm/stm32u5/console/console.c create mode 100644 bsps/arm/stm32u5/console/printk-support.c create mode 100644 bsps/arm/stm32u5/include/bsp.h create mode 100644 bsps/arm/stm32u5/include/bsp/irq.h create mode 100644 bsps/arm/stm32u5/include/chip.h create mode 100644 bsps/arm/stm32u5/include/tm27.h create mode 100644 bsps/arm/stm32u5/start/bspstart.c create mode 100644 bsps/arm/stm32u5/start/bspstarthooks.c create mode 100644 bsps/arm/stm32u5/start/getentropy-rng.c create mode 100644 bsps/arm/stm32u5/start/linkcmds.flash create mode 100644 bsps/arm/stm32u5/start/linkcmds.flash+ospi create mode 100644 bsps/arm/stm32u5/start/linkcmds.ospi create mode 100644 bsps/arm/stm32u5/start/linkcmds.sram create mode 100644 bsps/arm/stm32u5/start/stm32u5-config-clk.c create mode 100644 bsps/arm/stm32u5/start/stm32u5-config-osc.c create mode 100644 bsps/arm/stm32u5/start/stm32u5-config-per.c create mode 100644 bsps/arm/stm32u5/start/stm32u5-config-rtc.c create mode 100644 bsps/arm/stm32u5/start/stm32u5-hal-sdmmc.c create mode 100644 bsps/arm/stm32u5/start/stm32u5-hal-uart.c create mode 100644 bsps/arm/stm32u5/start/stm32u5-hal.c create mode 100644 bsps/arm/stm32u5/start/stm32u5-init-octospi.c create mode 100644 spec/build/bsps/arm/stm32u5/abi.yml create mode 100644 spec/build/bsps/arm/stm32u5/bspstm32u5-grisp-nano.yml create mode 100644 spec/build/bsps/arm/stm32u5/grp.yml create mode 100644 spec/build/bsps/arm/stm32u5/linkcmds.yml create mode 100644 spec/build/bsps/arm/stm32u5/linkcmdsmemory.yml create mode 100644 spec/build/bsps/arm/stm32u5/obj.yml create mode 100644 spec/build/bsps/arm/stm32u5/optenusart1.yml create mode 100644 spec/build/bsps/arm/stm32u5/optenusart2.yml create mode 100644 spec/build/bsps/arm/stm32u5/optenusart3.yml create mode 100644 spec/build/bsps/arm/stm32u5/optlinkcmds.yml create mode 100644 spec/build/bsps/arm/stm32u5/optmemflashsz.yml create mode 100644 spec/build/bsps/arm/stm32u5/optmemintsramlpbamsz.yml create mode 100644 spec/build/bsps/arm/stm32u5/optmemintsramsz.yml create mode 100644 spec/build/bsps/arm/stm32u5/optmemnullsz.yml create mode 100644 spec/build/bsps/arm/stm32u5/optmemoctospi1sz.yml create mode 100644 spec/build/bsps/arm/stm32u5/optmemoctospi2sz.yml create mode 100644 spec/build/bsps/arm/stm32u5/optprintkinstance.yml create mode 100644 spec/build/bsps/arm/stm32u5/optusart1gpiopins.yml create mode 100644 spec/build/bsps/arm/stm32u5/optusart2gpiopins.yml create mode 100644 spec/build/bsps/arm/stm32u5/optusart3gpiopins.yml diff --git a/bsps/arm/stm32u5/console/console-usart1-cfg.c b/bsps/arm/stm32u5/console/console-usart1-cfg.c new file mode 100644 index 0000000000..16937d40e2 --- /dev/null +++ b/bsps/arm/stm32u5/console/console-usart1-cfg.c @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMSTM32U5 + * + * @brief STM32 USART1 Configuration + */ + +/* + * Copyright (C) 2024 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include + +#include + +const stm32u5_uart_config stm32u5_usart1_config = { + .gpio = + { .regs = GPIOA, + .config = + { .Pin = STM32U5_USART1_GPIO_PINS, + .Mode = GPIO_MODE_AF_PP, + .Pull = GPIO_NOPULL, + .Speed = GPIO_SPEED_FREQ_LOW, + .Alternate = GPIO_AF7_USART1 } }, + .irq = USART1_IRQn, + .device_index = 0 +}; diff --git a/bsps/arm/stm32u5/console/console-usart1.c b/bsps/arm/stm32u5/console/console-usart1.c new file mode 100644 index 0000000000..3fd47124c8 --- /dev/null +++ b/bsps/arm/stm32u5/console/console-usart1.c @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMSTM32U5 + * + * @brief STM32U5 USART1 instance. + */ + +/* + * Copyright (C) 2024 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include + +stm32u5_uart_context stm32u5_usart1_instance = { + .uart = + { .Instance = USART1, + .Init.BaudRate = BSP_CONSOLE_BAUD, + .Init.WordLength = UART_WORDLENGTH_8B, + .Init.StopBits = UART_STOPBITS_1, + .Init.Parity = UART_PARITY_NONE, + .Init.Mode = UART_MODE_TX_RX, + .Init.HwFlowCtl = UART_HWCONTROL_NONE, + .Init.OverSampling = UART_OVERSAMPLING_16, + .Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE, + .Init.ClockPrescaler = UART_PRESCALER_DIV1, + .AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT }, + .config = &stm32u5_usart1_config +}; diff --git a/bsps/arm/stm32u5/console/console-usart2-cfg.c b/bsps/arm/stm32u5/console/console-usart2-cfg.c new file mode 100644 index 0000000000..8fd337bda5 --- /dev/null +++ b/bsps/arm/stm32u5/console/console-usart2-cfg.c @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMSTM32U5 + * + * @brief STM32 USART2 Configuration + */ + +/* + * Copyright (C) 2024 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include + +#include + +const stm32u5_uart_config stm32u5_usart2_config = { + .gpio = + { .regs = GPIOA, + .config = + { .Pin = STM32U5_USART2_GPIO_PINS, + .Mode = GPIO_MODE_AF_PP, + .Pull = GPIO_NOPULL, + .Speed = GPIO_SPEED_FREQ_LOW, + .Alternate = GPIO_AF7_USART2 } }, + .irq = USART2_IRQn, + .device_index = 1 +}; diff --git a/bsps/arm/stm32u5/console/console-usart2.c b/bsps/arm/stm32u5/console/console-usart2.c new file mode 100644 index 0000000000..561a4c35a3 --- /dev/null +++ b/bsps/arm/stm32u5/console/console-usart2.c @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMSTM32U5 + * + * @brief STM32U5 USART2 instance. + */ + +/* + * Copyright (C) 2024 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include + +stm32u5_uart_context stm32u5_usart2_instance = { + .uart = + { .Instance = USART2, + .Init.BaudRate = BSP_CONSOLE_BAUD, + .Init.WordLength = UART_WORDLENGTH_8B, + .Init.StopBits = UART_STOPBITS_1, + .Init.Parity = UART_PARITY_NONE, + .Init.Mode = UART_MODE_TX_RX, + .Init.HwFlowCtl = UART_HWCONTROL_NONE, + .Init.OverSampling = UART_OVERSAMPLING_16, + .Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE, + .Init.ClockPrescaler = UART_PRESCALER_DIV1, + .AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT }, + .config = &stm32u5_usart2_config +}; diff --git a/bsps/arm/stm32u5/console/console-usart3-cfg.c b/bsps/arm/stm32u5/console/console-usart3-cfg.c new file mode 100644 index 0000000000..f0d50345f5 --- /dev/null +++ b/bsps/arm/stm32u5/console/console-usart3-cfg.c @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMSTM32U5 + * + * @brief STM32 USART3 Configuration + */ + +/* + * Copyright (C) 2024 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include + +#include + +const stm32u5_uart_config stm32u5_usart3_config = { + .gpio = + { .regs = GPIOD, + .config = + { .Pin = STM32U5_USART3_GPIO_PINS, + .Mode = GPIO_MODE_AF_PP, + .Pull = GPIO_NOPULL, + .Speed = GPIO_SPEED_FREQ_LOW, + .Alternate = GPIO_AF7_USART3 } }, + .irq = USART3_IRQn, + .device_index = 2 +}; diff --git a/bsps/arm/stm32u5/console/console-usart3.c b/bsps/arm/stm32u5/console/console-usart3.c new file mode 100644 index 0000000000..291f45d702 --- /dev/null +++ b/bsps/arm/stm32u5/console/console-usart3.c @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMSTM32U5 + * + * @brief STM32U5 USART3 instance. + */ + +/* + * Copyright (C) 2024 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include + +stm32u5_uart_context stm32u5_usart3_instance = { + .uart = + { .Instance = USART3, + .Init.BaudRate = BSP_CONSOLE_BAUD, + .Init.WordLength = UART_WORDLENGTH_8B, + .Init.StopBits = UART_STOPBITS_1, + .Init.Parity = UART_PARITY_NONE, + .Init.Mode = UART_MODE_TX_RX, + .Init.HwFlowCtl = UART_HWCONTROL_RTS_CTS, + .Init.OverSampling = UART_OVERSAMPLING_16, + .Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE, + .Init.ClockPrescaler = UART_PRESCALER_DIV1, + .AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT }, + .config = &stm32u5_usart3_config +}; diff --git a/bsps/arm/stm32u5/console/console.c b/bsps/arm/stm32u5/console/console.c new file mode 100644 index 0000000000..791ceba76a --- /dev/null +++ b/bsps/arm/stm32u5/console/console.c @@ -0,0 +1,304 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMSTM32U5 + * + * @brief Console driver for STM32U5 + * + * Implementation of the STM32U5 console driver. + */ + +/* + * Copyright (C) 2024 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include + +#include +#include +#include +#include + +#include +#include +#include + +static stm32u5_uart_context *const stm32u5_uart_instances[] = { +#ifdef STM32U5_CONSOLE_ENABLE_USART1 + &stm32u5_usart1_instance, +#endif +#ifdef STM32U5_CONSOLE_ENABLE_USART2 + &stm32u5_usart2_instance, +#endif +#ifdef STM32U5_CONSOLE_ENABLE_USART3 + &stm32u5_usart3_instance, +#endif +#ifdef STM32U5_CONSOLE_ENABLE_UART4 + &stm32u5_uart4_instance, +#endif +#ifdef STM32U5_CONSOLE_ENABLE_UART5 + &stm32u5_uart5_instance, +#endif +#ifdef STM32U5_CONSOLE_ENABLE_USART6 + &stm32u5_usart6_instance, +#endif +}; + +static bool stm32u5_uart_set_attributes( + rtems_termios_device_context *base, + const struct termios *term +) +{ + stm32u5_uart_context *ctx; + uint32_t previous_baud; + uint32_t previous_stop_bits; + uint32_t previous_parity; + uint32_t previous_mode; + HAL_StatusTypeDef status; + + if ( ( term->c_cflag & CSIZE ) != CS8 ) { + return false; + } + + ctx = stm32u5_uart_get_context( base ); + + previous_baud = ctx->uart.Init.BaudRate; + ctx->uart.Init.BaudRate = rtems_termios_baud_to_number( term->c_ospeed ); + + previous_stop_bits = ctx->uart.Init.StopBits; + if ( ( term->c_cflag & CSTOPB ) != 0 ) { + ctx->uart.Init.StopBits = UART_STOPBITS_2; + } else { + ctx->uart.Init.StopBits = UART_STOPBITS_1; + } + + previous_parity = ctx->uart.Init.Parity; + if ( ( term->c_cflag & PARENB ) != 0 ) { + if ( ( term->c_cflag & PARODD ) != 0 ) { + ctx->uart.Init.Parity = UART_PARITY_ODD; + } else { + ctx->uart.Init.Parity = UART_PARITY_EVEN; + } + } else { + ctx->uart.Init.Parity = UART_PARITY_NONE; + } + + previous_mode = ctx->uart.Init.Mode; + if ( ( term->c_cflag & CREAD ) != 0 ) { + ctx->uart.Init.Mode = UART_MODE_TX_RX; + } else { + ctx->uart.Init.Mode = UART_MODE_RX; + } + + status = UART_SetConfig( &ctx->uart ); + if ( status != HAL_OK ) { + ctx->uart.Init.BaudRate = previous_baud; + ctx->uart.Init.StopBits = previous_stop_bits; + ctx->uart.Init.Parity = previous_parity; + ctx->uart.Init.Mode = previous_mode; + return false; + } + + return true; +} + +#ifdef BSP_CONSOLE_USE_INTERRUPTS +static void stm32u5_uart_interrupt( void *arg ) +{ + rtems_termios_tty *tty; + rtems_termios_device_context *base; + stm32u5_uart_context *ctx; + USART_TypeDef *regs; + uint32_t isr; + + tty = arg; + base = rtems_termios_get_device_context( tty ); + ctx = stm32u5_uart_get_context( base ); + regs = ctx->uart.Instance; + isr = regs->ISR; + + while ( ( isr & USART_ISR_RXNE_RXFNE ) != 0 ) { + char c; + + c = (uint8_t) regs->RDR; + rtems_termios_enqueue_raw_characters( tty, &c, 1 ); + + isr = regs->ISR; + } + + if ( ctx->transmitting && ( isr & USART_ISR_TXE_TXFNF ) != 0 ) { + rtems_termios_dequeue_characters( tty, 1 ); + } + + regs->ICR = USART_ICR_ORECF; +} +#endif + +static bool stm32u5_uart_first_open( + rtems_termios_tty *tty, + rtems_termios_device_context *base, + struct termios *term, + rtems_libio_open_close_args_t *args +) +{ + stm32u5_uart_context *ctx; + UART_HandleTypeDef *uart; +#ifdef BSP_CONSOLE_USE_INTERRUPTS + rtems_status_code sc; +#endif + + ctx = stm32u5_uart_get_context( base ); + uart = &ctx->uart; + + rtems_termios_set_initial_baud( tty, BSP_CONSOLE_BAUD ); + + (void) HAL_UART_Init( uart ); + (void) HAL_UARTEx_SetTxFifoThreshold( uart, UART_TXFIFO_THRESHOLD_1_8 ); + (void) HAL_UARTEx_SetRxFifoThreshold( uart, UART_RXFIFO_THRESHOLD_1_8 ); + (void) HAL_UARTEx_EnableFifoMode( uart ); + +#ifdef BSP_CONSOLE_USE_INTERRUPTS + sc = rtems_interrupt_handler_install( + ctx->config->irq, + "UART", + RTEMS_INTERRUPT_SHARED, + stm32u5_uart_interrupt, + tty + ); + if ( sc != RTEMS_SUCCESSFUL ) { + return false; + } + + ctx->uart.Instance->CR1 |= USART_CR1_RXNEIE_RXFNEIE; +#endif + + stm32u5_uart_set_attributes( base, term ); + + return true; +} + +static void stm32u5_uart_last_close( + rtems_termios_tty *tty, + rtems_termios_device_context *base, + rtems_libio_open_close_args_t *args +) +{ +#ifdef BSP_CONSOLE_USE_INTERRUPTS + stm32u5_uart_context *ctx; + + ctx = stm32u5_uart_get_context( base ); + + (void) rtems_interrupt_handler_remove( + ctx->config->irq, + stm32u5_uart_interrupt, + tty + ); +#endif +} + +static void stm32u5_uart_write( + rtems_termios_device_context *base, + const char *buf, + size_t len +) +{ +#ifdef BSP_CONSOLE_USE_INTERRUPTS + stm32u5_uart_context *ctx; + USART_TypeDef *regs; + + ctx = stm32u5_uart_get_context( base ); + regs = ctx->uart.Instance; + + if ( len > 0 ) { + ctx->transmitting = true; + regs->TDR = (uint8_t) buf[ 0 ]; + regs->CR1 |= USART_CR1_TXEIE_TXFNFIE; + } else { + ctx->transmitting = false; + regs->CR1 &= ~USART_CR1_TXEIE_TXFNFIE; + } +#else + size_t i; + + for ( i = 0; i < len; ++i ) { + stm32u5_uart_polled_write( base, buf[ i ] ); + } +#endif +} + +static const rtems_termios_device_handler stm32u5_uart_handler = { + .first_open = stm32u5_uart_first_open, + .last_close = stm32u5_uart_last_close, + .write = stm32u5_uart_write, + .set_attributes = stm32u5_uart_set_attributes, +#ifdef BSP_CONSOLE_USE_INTERRUPTS + .mode = TERMIOS_IRQ_DRIVEN +#else + .poll_read = stm32u5_uart_polled_read, + .mode = TERMIOS_POLLED +#endif +}; + +rtems_status_code console_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +) +{ + size_t i; + + rtems_termios_initialize(); + + for ( i = 0; i < RTEMS_ARRAY_SIZE( stm32u5_uart_instances ); ++i ) { + stm32u5_uart_context *ctx; + char path[ sizeof( "/dev/ttyACMXXX" ) ]; + + ctx = stm32u5_uart_instances[ i ]; + snprintf( + path, + sizeof( path ), + "/dev/ttyACM%" PRIu8, + ctx->config->device_index + ); + + rtems_termios_device_install( + path, + &stm32u5_uart_handler, + NULL, + &ctx->device + ); + + if ( ctx == &STM32U5_PRINTK_INSTANCE ) { + link( path, CONSOLE_DEVICE_NAME ); + } + } + + return RTEMS_SUCCESSFUL; +} diff --git a/bsps/arm/stm32u5/console/printk-support.c b/bsps/arm/stm32u5/console/printk-support.c new file mode 100644 index 0000000000..1fc286fae8 --- /dev/null +++ b/bsps/arm/stm32u5/console/printk-support.c @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMSTM32U5 + * + * @brief Support for polled prints on STM32U5. + * + * Implementation of the STM32U5 printk (polled) output. + */ + +/* + * Copyright (C) 2024 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include +#include +#include +#include + +#include + +static void stm32u5_output_char( char c ) +{ + stm32u5_uart_polled_write( &STM32U5_PRINTK_INSTANCE.device, c ); +} + +static void stm32u5_output_char_init( void ) +{ + UART_HandleTypeDef *uart; + HAL_StatusTypeDef status; + + uart = &STM32U5_PRINTK_INSTANCE.uart; + status = HAL_UART_Init( uart ); + if ( status != HAL_OK ) { + bsp_fatal( BSP_FATAL_CONSOLE_INSTALL_0 ); + } + status = HAL_UARTEx_SetTxFifoThreshold( uart, UART_TXFIFO_THRESHOLD_1_8 ); + if ( status != HAL_OK ) { + bsp_fatal( BSP_FATAL_CONSOLE_INSTALL_0 ); + } + status = HAL_UARTEx_SetRxFifoThreshold( uart, UART_RXFIFO_THRESHOLD_1_8 ); + if ( status != HAL_OK ) { + bsp_fatal( BSP_FATAL_CONSOLE_INSTALL_0 ); + } + status = HAL_UARTEx_EnableFifoMode( uart ); + if ( status != HAL_OK ) { + bsp_fatal( BSP_FATAL_CONSOLE_INSTALL_0 ); + } + + BSP_output_char = stm32u5_output_char; +} + +static void stm32u5_output_char_init_early( char c ) +{ + stm32u5_output_char_init(); + stm32u5_output_char( c ); +} + +static int stm32u5_poll_char( void ) +{ + return stm32u5_uart_polled_read( &STM32U5_PRINTK_INSTANCE.device ); +} + +BSP_output_char_function_type BSP_output_char = stm32u5_output_char_init_early; + +BSP_polling_getchar_function_type BSP_poll_char = stm32u5_poll_char; + +RTEMS_SYSINIT_ITEM( + stm32u5_output_char_init, + RTEMS_SYSINIT_BSP_START, + RTEMS_SYSINIT_ORDER_LAST_BUT_5 +); diff --git a/bsps/arm/stm32u5/include/bsp.h b/bsps/arm/stm32u5/include/bsp.h new file mode 100644 index 0000000000..b5c082e770 --- /dev/null +++ b/bsps/arm/stm32u5/include/bsp.h @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMSTM32U5 + * + * @brief Global BSP definitions for STM32U5 + */ + +/* + * Copyright (C) 2024 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_ARM_STM32U5_BSP_H +#define LIBBSP_ARM_STM32U5_BSP_H + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup RTEMSBSPsARMSTM32U5 STM32U5 + * + * @ingroup RTEMSBSPsARM + * + * @brief STM32U5 Board Support Package. + * + * @{ + */ + +#define BSP_FEATURE_IRQ_EXTENSION + +#define BSP_ARMV7M_IRQ_PRIORITY_DEFAULT ( 13 << 4 ) + +#define BSP_ARMV7M_SYSTICK_PRIORITY ( 14 << 4 ) + +#define BSP_ARMV7M_SYSTICK_FREQUENCY stm32u5_systick_frequency() + +uint32_t stm32u5_systick_frequency( void ); + +/* default functions */ +void stm32u5_init_oscillator( void ); +void stm32u5_init_clocks( void ); +void stm32u5_init_power( void ); +void stm32u5_init_peripheral_clocks( void ); +void stm32u5_rcc_power_clock_enable( void ); +void stm32u5_init_octospi( void ); + +/* Linker symbols */ +extern char stm32u5_memory_null_begin[]; +extern char stm32u5_memory_null_end[]; +extern char stm32u5_memory_null_size[]; + +extern char stm32u5_memory_flash_begin[]; +extern char stm32u5_memory_flash_end[]; +extern char stm32u5_memory_flash_size[]; + +extern char stm32u5_memory_int_sram_begin[]; +extern char stm32u5_memory_int_sram_end[]; +extern char stm32u5_memory_int_sram_size[]; + +extern char stm32u5_memory_int_sram_lpbam_begin[]; +extern char stm32u5_memory_int_sram_lpbam_end[]; +extern char stm32u5_memory_int_sram_lpbam_size[]; + +extern char stm32u5_memory_octospi_1_begin[]; +extern char stm32u5_memory_octospi_1_end[]; +extern char stm32u5_memory_octospi_1_size[]; + +extern char stm32u5_memory_octospi_2_begin[]; +extern char stm32u5_memory_octospi_2_end[]; +extern char stm32u5_memory_octospi_2_size[]; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* LIBBSP_ARM_STM32U5_BSP_H */ diff --git a/bsps/arm/stm32u5/include/bsp/irq.h b/bsps/arm/stm32u5/include/bsp/irq.h new file mode 100644 index 0000000000..bfafd69c5b --- /dev/null +++ b/bsps/arm/stm32u5/include/bsp/irq.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMSTM32U5 + * + * @brief Interrupt definitions for STM32U5 + */ + +/* + * Copyright (C) 2024 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_ARM_STM32U5_IRQ_H +#define LIBBSP_ARM_STM32U5_IRQ_H + +#ifndef ASM + +#include +#include +#include + +#endif /* ASM */ + +#define BSP_INTERRUPT_VECTOR_COUNT 480 + +#endif /* LIBBSP_ARM_STM32U5_IRQ_H */ diff --git a/bsps/arm/stm32u5/include/chip.h b/bsps/arm/stm32u5/include/chip.h new file mode 100644 index 0000000000..2d19509978 --- /dev/null +++ b/bsps/arm/stm32u5/include/chip.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMSTM32U5 + * + * @brief Chip definitions for STM32U5 + */ + +/* + * Copyright (C) 2024 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_ARM_STM32U5_CHIP_H +#define LIBBSP_ARM_STM32U5_CHIP_H + +#include +#include + +#endif /* LIBBSP_ARM_STM32U5_CHIP_H */ diff --git a/bsps/arm/stm32u5/include/tm27.h b/bsps/arm/stm32u5/include/tm27.h new file mode 100644 index 0000000000..dfd4c1c2c3 --- /dev/null +++ b/bsps/arm/stm32u5/include/tm27.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMSTM32U5 + * + * @brief Implementations of interrupt mechanisms for Time Test 27. + */ + +#include diff --git a/bsps/arm/stm32u5/start/bspstart.c b/bsps/arm/stm32u5/start/bspstart.c new file mode 100644 index 0000000000..df376d42fc --- /dev/null +++ b/bsps/arm/stm32u5/start/bspstart.c @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMSTM32U5 + * + * @brief Implementation of basic startup functions. + */ + +/* + * Copyright (C) 2024 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +uint32_t stm32u5_systick_frequency( void ) +{ + return SystemCoreClock; +} + +void bsp_start( void ) +{ + bsp_interrupt_initialize(); +} diff --git a/bsps/arm/stm32u5/start/bspstarthooks.c b/bsps/arm/stm32u5/start/bspstarthooks.c new file mode 100644 index 0000000000..50fdc61655 --- /dev/null +++ b/bsps/arm/stm32u5/start/bspstarthooks.c @@ -0,0 +1,159 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMSTM32U5 + * + * @brief Implementation of the STM32U5 early start hooks. + */ + +/* + * Copyright (c) 2024 embedded brains GmbH. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + +/* + * We use some HAL stuff before the system tick is initialized. As a + * workarround, a function is used that just counts calls. + * + * Usually HAL_GetTick would provide something in a millisecond scale. We run at + * 160MHz. So we need 160000 CPU instructions per millisecond. Let's guess that + * the HAL_GetTick is used for timeouts in loops reading a few registers in the + * HAL. So maybe 10 instructions. So just return (calls / 2**14) as an estimate. + */ +uint32_t BSP_FAST_DATA_SECTION startup_delay_call_counter; +uint32_t BSP_FAST_DATA_SECTION ( *HAL_GetTick_ptr )( void ); + +static uint32_t BSP_START_TEXT_SECTION Startup_HAL_GetTick( void ) +{ + ++startup_delay_call_counter; + return startup_delay_call_counter >> 14; +} + +static uint32_t BSP_START_TEXT_SECTION Booted_HAL_GetTick( void ) +{ + return rtems_clock_get_ticks_since_boot() * + rtems_configuration_get_milliseconds_per_tick(); +} + +/* Get number of milliseconds elapsed since startup */ +uint32_t BSP_START_TEXT_SECTION HAL_GetTick( void ) +{ + return HAL_GetTick_ptr(); +} + +void BSP_START_TEXT_SECTION stm32u5_rcc_power_clock_enable( void ) +{ + __HAL_RCC_PWR_CLK_ENABLE(); + HAL_PWREx_EnableVddA(); +} + +void BSP_START_TEXT_SECTION stm32u5_init_power( void ) +{ + HAL_PWREx_DisableUCPDDeadBattery(); + + if ( HAL_PWREx_ConfigSupply( PWR_SMPS_SUPPLY ) != HAL_OK ) { + bsp_fatal( STM32U5_FATAL_INIT_POWER ); + } +} + +void BSP_START_TEXT_SECTION stm32u5_init_oscillator( void ) +{ + HAL_StatusTypeDef status; + + /* + * Voltage scaling range 1 is used when CPU Clock frequency is up to + * 160 MHz. See STM32U5 Reference Manual (RM0456) section 10.5.4. + */ + if ( HAL_PWREx_ControlVoltageScaling( PWR_REGULATOR_VOLTAGE_SCALE1 ) != + HAL_OK ) { + bsp_fatal( STM32U5_FATAL_INIT_CLOCKS ); + } + + status = HAL_RCC_OscConfig( &stm32u5_config_oscillator ); + if ( status != HAL_OK ) { + bsp_fatal( STM32U5_FATAL_INIT_CLOCKS ); + } +} + +void BSP_START_TEXT_SECTION stm32u5_init_clocks( void ) +{ + HAL_StatusTypeDef status; + + /* + * Flash latency must be configured according to the frequency of the CPU + * Clock (HCLK). In high-performance range (voltage scaling range 1), with + * a CPU clock of 160 MHz, 4 wait states are required (FLASH_LATENCY_4). + * See STM32U5 Reference Manual (RM0456) section 7.3.3. + */ + status = HAL_RCC_ClockConfig( &stm32u5_config_clocks, FLASH_LATENCY_4 ); + if ( status != HAL_OK ) { + bsp_fatal( STM32U5_FATAL_INIT_CLOCKS ); + } +} + +void BSP_START_TEXT_SECTION stm32u5_init_peripheral_clocks( void ) +{ + HAL_StatusTypeDef status; + + status = HAL_RCCEx_PeriphCLKConfig( &stm32u5_config_peripheral_clocks ); + if ( status != HAL_OK ) { + bsp_fatal( STM32U5_FATAL_INIT_CLOCKS ); + } +} + +void BSP_START_TEXT_SECTION bsp_start_hook_0( void ) +{ + HAL_GetTick_ptr = Startup_HAL_GetTick; + startup_delay_call_counter = 0; + + SystemInit(); + SystemCoreClockUpdate(); + stm32u5_rcc_power_clock_enable(); + stm32u5_init_oscillator(); + stm32u5_init_clocks(); + stm32u5_init_power(); + stm32u5_init_peripheral_clocks(); + HAL_Init(); +} + +void BSP_START_TEXT_SECTION bsp_start_hook_1( void ) +{ + /* Init OctoSPI only if we are not running from it */ + if ( stm32u5_init_octospi < stm32u5_memory_octospi_1_begin || + stm32u5_init_octospi > stm32u5_memory_octospi_1_end ) { + stm32u5_init_octospi(); + } + bsp_start_copy_sections(); + bsp_start_clear_bss(); + + HAL_GetTick_ptr = Booted_HAL_GetTick; +} diff --git a/bsps/arm/stm32u5/start/getentropy-rng.c b/bsps/arm/stm32u5/start/getentropy-rng.c new file mode 100644 index 0000000000..f58d8c28c1 --- /dev/null +++ b/bsps/arm/stm32u5/start/getentropy-rng.c @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMSTM32U5 + * + * @brief Implementation of an entropy source for STM32U5. + */ + +/* + * Copyright (C) 2024 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include +#include + +#include +#include +#include + +static RNG_HandleTypeDef stm32u5_rng_instance = { + .Instance = RNG, + .Init.ClockErrorDetection = RNG_CED_DISABLE +}; + +static void stm32u5_rng_enable( void ) +{ + stm32u5_clk_enable( STM32U5_MODULE_RNG ); + HAL_RNG_Init( &stm32u5_rng_instance ); +} + +int getentropy( void *ptr, size_t n ) +{ + while ( n > 0 ) { + rtems_interrupt_level level; + uint32_t random; + bool ok; + size_t copy; + + do { + rtems_interrupt_disable( level ); + + ok = ( RNG->SR & RNG_FLAG_DRDY ) != 0; + if ( ok ) { + random = RNG->DR; + } + + rtems_interrupt_enable( level ); + } while ( !ok ); + + copy = MIN( sizeof( random ), n ); + ptr = memcpy( ptr, &random, copy ); + n -= copy; + ptr += copy; + } + + return 0; +} + +RTEMS_SYSINIT_ITEM( + stm32u5_rng_enable, + RTEMS_SYSINIT_DEVICE_DRIVERS, + RTEMS_SYSINIT_ORDER_LAST_BUT_5 +); diff --git a/bsps/arm/stm32u5/start/linkcmds.flash b/bsps/arm/stm32u5/start/linkcmds.flash new file mode 100644 index 0000000000..42c3aefb7c --- /dev/null +++ b/bsps/arm/stm32u5/start/linkcmds.flash @@ -0,0 +1,23 @@ +INCLUDE linkcmds.memory + +REGION_ALIAS ("REGION_START", FLASH); +REGION_ALIAS ("REGION_VECTOR", FLASH); +REGION_ALIAS ("REGION_TEXT", FLASH); +REGION_ALIAS ("REGION_TEXT_LOAD", FLASH); +REGION_ALIAS ("REGION_RODATA", FLASH); +REGION_ALIAS ("REGION_RODATA_LOAD", FLASH); +REGION_ALIAS ("REGION_DATA", INT_SRAM); +REGION_ALIAS ("REGION_DATA_LOAD", FLASH); +REGION_ALIAS ("REGION_FAST_TEXT", FLASH); +REGION_ALIAS ("REGION_FAST_TEXT_LOAD", FLASH); +REGION_ALIAS ("REGION_FAST_DATA", INT_SRAM); +REGION_ALIAS ("REGION_FAST_DATA_LOAD", FLASH); +REGION_ALIAS ("REGION_BSS", INT_SRAM); +REGION_ALIAS ("REGION_WORK", INT_SRAM); +REGION_ALIAS ("REGION_STACK", INT_SRAM); +REGION_ALIAS ("REGION_NOCACHE", INT_SRAM); +REGION_ALIAS ("REGION_NOCACHE_LOAD", FLASH); + +bsp_vector_table_in_start_section = 1; + +INCLUDE linkcmds.armv7m diff --git a/bsps/arm/stm32u5/start/linkcmds.flash+ospi b/bsps/arm/stm32u5/start/linkcmds.flash+ospi new file mode 100644 index 0000000000..fe0d852e7f --- /dev/null +++ b/bsps/arm/stm32u5/start/linkcmds.flash+ospi @@ -0,0 +1,23 @@ +INCLUDE linkcmds.memory + +REGION_ALIAS ("REGION_START", FLASH); +REGION_ALIAS ("REGION_VECTOR", FLASH); +REGION_ALIAS ("REGION_TEXT", FLASH); +REGION_ALIAS ("REGION_TEXT_LOAD", FLASH); +REGION_ALIAS ("REGION_RODATA", FLASH); +REGION_ALIAS ("REGION_RODATA_LOAD", FLASH); +REGION_ALIAS ("REGION_DATA", OCTOSPI_1); +REGION_ALIAS ("REGION_DATA_LOAD", FLASH); +REGION_ALIAS ("REGION_FAST_TEXT", FLASH); +REGION_ALIAS ("REGION_FAST_TEXT_LOAD", FLASH); +REGION_ALIAS ("REGION_FAST_DATA", INT_SRAM); +REGION_ALIAS ("REGION_FAST_DATA_LOAD", FLASH); +REGION_ALIAS ("REGION_BSS", OCTOSPI_1); +REGION_ALIAS ("REGION_WORK", OCTOSPI_1); +REGION_ALIAS ("REGION_STACK", INT_SRAM); +REGION_ALIAS ("REGION_NOCACHE", INT_SRAM); +REGION_ALIAS ("REGION_NOCACHE_LOAD", FLASH); + +bsp_vector_table_in_start_section = 1; + +INCLUDE linkcmds.armv7m diff --git a/bsps/arm/stm32u5/start/linkcmds.ospi b/bsps/arm/stm32u5/start/linkcmds.ospi new file mode 100644 index 0000000000..f8757a31fc --- /dev/null +++ b/bsps/arm/stm32u5/start/linkcmds.ospi @@ -0,0 +1,23 @@ +INCLUDE linkcmds.memory + +REGION_ALIAS ("REGION_START", OCTOSPI_1); +REGION_ALIAS ("REGION_VECTOR", OCTOSPI_1); +REGION_ALIAS ("REGION_TEXT", OCTOSPI_1); +REGION_ALIAS ("REGION_TEXT_LOAD", OCTOSPI_1); +REGION_ALIAS ("REGION_RODATA", OCTOSPI_1); +REGION_ALIAS ("REGION_RODATA_LOAD", OCTOSPI_1); +REGION_ALIAS ("REGION_DATA", OCTOSPI_1); +REGION_ALIAS ("REGION_DATA_LOAD", OCTOSPI_1); +REGION_ALIAS ("REGION_FAST_TEXT", OCTOSPI_1); +REGION_ALIAS ("REGION_FAST_TEXT_LOAD", OCTOSPI_1); +REGION_ALIAS ("REGION_FAST_DATA", OCTOSPI_1); +REGION_ALIAS ("REGION_FAST_DATA_LOAD", OCTOSPI_1); +REGION_ALIAS ("REGION_BSS", OCTOSPI_1); +REGION_ALIAS ("REGION_WORK", OCTOSPI_1); +REGION_ALIAS ("REGION_STACK", OCTOSPI_1); +REGION_ALIAS ("REGION_NOCACHE", OCTOSPI_1); +REGION_ALIAS ("REGION_NOCACHE_LOAD", OCTOSPI_1); + +bsp_vector_table_in_start_section = 1; + +INCLUDE linkcmds.armv7m diff --git a/bsps/arm/stm32u5/start/linkcmds.sram b/bsps/arm/stm32u5/start/linkcmds.sram new file mode 100644 index 0000000000..a6281e514d --- /dev/null +++ b/bsps/arm/stm32u5/start/linkcmds.sram @@ -0,0 +1,23 @@ +INCLUDE linkcmds.memory + +REGION_ALIAS ("REGION_START", INT_SRAM); +REGION_ALIAS ("REGION_VECTOR", INT_SRAM); +REGION_ALIAS ("REGION_TEXT", INT_SRAM); +REGION_ALIAS ("REGION_TEXT_LOAD", INT_SRAM); +REGION_ALIAS ("REGION_RODATA", INT_SRAM); +REGION_ALIAS ("REGION_RODATA_LOAD", INT_SRAM); +REGION_ALIAS ("REGION_DATA", INT_SRAM); +REGION_ALIAS ("REGION_DATA_LOAD", INT_SRAM); +REGION_ALIAS ("REGION_FAST_TEXT", INT_SRAM); +REGION_ALIAS ("REGION_FAST_TEXT_LOAD", INT_SRAM); +REGION_ALIAS ("REGION_FAST_DATA", INT_SRAM); +REGION_ALIAS ("REGION_FAST_DATA_LOAD", INT_SRAM); +REGION_ALIAS ("REGION_BSS", INT_SRAM); +REGION_ALIAS ("REGION_WORK", INT_SRAM); +REGION_ALIAS ("REGION_STACK", INT_SRAM); +REGION_ALIAS ("REGION_NOCACHE", INT_SRAM); +REGION_ALIAS ("REGION_NOCACHE_LOAD", INT_SRAM); + +bsp_vector_table_in_start_section = 1; + +INCLUDE linkcmds.armv7m diff --git a/bsps/arm/stm32u5/start/stm32u5-config-clk.c b/bsps/arm/stm32u5/start/stm32u5-config-clk.c new file mode 100644 index 0000000000..8ef25d954f --- /dev/null +++ b/bsps/arm/stm32u5/start/stm32u5-config-clk.c @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMSTM32U5 + * + * @brief Basic clock configuration for the STM32U5 + */ + +/* + * Copyright (C) 2024 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include + +const RCC_ClkInitTypeDef stm32u5_config_clocks = { + .ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | + RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3, + .SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK, + .AHBCLKDivider = RCC_SYSCLK_DIV1, + .APB1CLKDivider = RCC_HCLK_DIV1, + .APB2CLKDivider = RCC_HCLK_DIV1, + .APB3CLKDivider = RCC_HCLK_DIV1 +}; diff --git a/bsps/arm/stm32u5/start/stm32u5-config-osc.c b/bsps/arm/stm32u5/start/stm32u5-config-osc.c new file mode 100644 index 0000000000..a6076a9754 --- /dev/null +++ b/bsps/arm/stm32u5/start/stm32u5-config-osc.c @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMSTM32U5 + * + * @brief Oscillator configuration for the STM32U5 + */ + +/* + * Copyright (C) 2024 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include + +const RCC_OscInitTypeDef stm32u5_config_oscillator = { + .OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSI | + RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_MSI | + RCC_OSCILLATORTYPE_LSE, + .HSEState = RCC_HSE_ON, + .HSIState = RCC_HSI_ON, + .HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT, + .LSIState = RCC_LSI_ON, + .MSIState = RCC_MSI_ON, + .LSEState = RCC_LSE_ON_RTC_ONLY, + .MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT, + .MSIClockRange = RCC_MSIRANGE_0, + .LSIDiv = RCC_LSI_DIV1, + .PLL.PLLState = RCC_PLL_ON, + .PLL.PLLSource = RCC_PLLSOURCE_HSE, + .PLL.PLLMBOOST = RCC_PLLMBOOST_DIV1, + .PLL.PLLM = 1, + .PLL.PLLN = 20, + .PLL.PLLP = 5, + .PLL.PLLQ = 2, + .PLL.PLLR = 2, + .PLL.PLLRGE = RCC_PLLVCIRANGE_1, + .PLL.PLLFRACN = 0 +}; diff --git a/bsps/arm/stm32u5/start/stm32u5-config-per.c b/bsps/arm/stm32u5/start/stm32u5-config-per.c new file mode 100644 index 0000000000..8a35b47c5e --- /dev/null +++ b/bsps/arm/stm32u5/start/stm32u5-config-per.c @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMSTM32U5 + * + * @brief Peripheral clock configuration for the STM32U5 + */ + +/* + * Copyright (C) 2024 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include +#include + +BSP_START_TEXT_SECTION const RCC_PeriphCLKInitTypeDef + stm32u5_config_peripheral_clocks = { + .PeriphClockSelection = RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | + RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_RTC | + RCC_PERIPHCLK_SDMMC, + .Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1, + .Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1, + .OspiClockSelection = RCC_OSPICLKSOURCE_PLL1, + .RTCClockSelection = RCC_RTCCLKSOURCE_LSE, + .SdmmcClockSelection = RCC_SDMMCCLKSOURCE_PLL1 +}; diff --git a/bsps/arm/stm32u5/start/stm32u5-config-rtc.c b/bsps/arm/stm32u5/start/stm32u5-config-rtc.c new file mode 100644 index 0000000000..9b63dc517e --- /dev/null +++ b/bsps/arm/stm32u5/start/stm32u5-config-rtc.c @@ -0,0 +1,143 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMSTM32U5 + * + * @brief Implementation of the RTC driver for the STM32U5 + */ + +/* + * Copyright (c) 2024 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include + +RTC_HandleTypeDef hrtc = { 0 }; +RTC_TimeTypeDef sTime = { 0 }; +RTC_DateTypeDef sDate = { 0 }; + +void stm32u5_rtc_get_time( rtems_time_of_day *tod ) +{ + if ( HAL_RTC_GetTime( &hrtc, &sTime, RTC_FORMAT_BIN ) != HAL_OK ) { + bsp_fatal( STM32U5_FATAL_RTC ); + } + + if ( HAL_RTC_GetDate( &hrtc, &sDate, RTC_FORMAT_BIN ) != HAL_OK ) { + bsp_fatal( STM32U5_FATAL_RTC ); + } + + tod->ticks = 0; + tod->second = sTime.Seconds; + tod->minute = sTime.Minutes; + tod->hour = sTime.Hours; + tod->day = sDate.Date; + tod->month = sDate.Month; + tod->year = TOD_BASE_YEAR + sDate.Year; +} + +static void stm32u5_rtc_device_initialize( int minor ) +{ + hrtc.Instance = RTC; + hrtc.Init.HourFormat = RTC_HOURFORMAT_24; + hrtc.Init.AsynchPrediv = 127; + hrtc.Init.SynchPrediv = 255; + hrtc.Init.OutPut = RTC_OUTPUT_DISABLE; + hrtc.Init.OutPutRemap = RTC_OUTPUT_REMAP_NONE; + hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; + hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; + hrtc.Init.OutPutPullUp = RTC_OUTPUT_PULLUP_NONE; + hrtc.Init.BinMode = RTC_BINARY_MIX; + if ( HAL_RTC_Init( &hrtc ) != HAL_OK ) { + bsp_fatal( STM32U5_FATAL_RTC ); + } +} + +static int stm32u5_rtc_device_get_time( int minor, rtems_time_of_day *tod ) +{ + stm32u5_rtc_get_time( tod ); + + return 0; +} + +static int stm32u5_rtc_device_set_time( + int minor, + const rtems_time_of_day *tod +) +{ + sTime.Hours = (uint8_t) tod->hour; + sTime.Minutes = (uint8_t) tod->minute; + sTime.Seconds = (uint8_t) tod->second; + sDate.Date = (uint8_t) tod->day; + sDate.Month = (uint8_t) tod->month; + sDate.Year = (uint8_t) tod->year - TOD_BASE_YEAR; + + if ( HAL_RTC_SetTime( &hrtc, &sTime, RTC_FORMAT_BIN ) != HAL_OK ) { + bsp_fatal( STM32U5_FATAL_RTC ); + } + + if ( HAL_RTC_SetDate( &hrtc, &sDate, RTC_FORMAT_BIN ) != HAL_OK ) { + bsp_fatal( STM32U5_FATAL_RTC ); + } + + return 0; +} + +static bool stm32u5_rtc_device_probe( int minor ) +{ + return true; +} + +const rtc_fns stm32u5_rtc_device_ops = { + .deviceInitialize = stm32u5_rtc_device_initialize, + .deviceGetTime = stm32u5_rtc_device_get_time, + .deviceSetTime = stm32u5_rtc_device_set_time +}; + +rtc_tbl RTC_Table[] = { + { .sDeviceName = "/dev/rtc", + .deviceType = RTC_CUSTOM, + .pDeviceFns = &stm32u5_rtc_device_ops, + .deviceProbe = stm32u5_rtc_device_probe } +}; + +void BSP_START_TEXT_SECTION HAL_RTC_MspInit( RTC_HandleTypeDef *hrtc ) +{ + /* Enable peripheral clocks and battery backup. */ + __HAL_RCC_PWR_CLK_ENABLE(); + HAL_PWR_EnableBkUpAccess(); + __HAL_RCC_RTC_CONFIG( RCC_RTCCLKSOURCE_LSE ); + __HAL_RCC_RTC_ENABLE(); + __HAL_RCC_RTCAPB_CLK_ENABLE(); + __HAL_RCC_RTCAPB_CLKAM_ENABLE(); +} + +size_t RTC_Count = RTEMS_ARRAY_SIZE( RTC_Table ); diff --git a/bsps/arm/stm32u5/start/stm32u5-hal-sdmmc.c b/bsps/arm/stm32u5/start/stm32u5-hal-sdmmc.c new file mode 100644 index 0000000000..5469b34f1b --- /dev/null +++ b/bsps/arm/stm32u5/start/stm32u5-hal-sdmmc.c @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMSTM32U5 + * + * @brief Configuration for the SD card pins + */ + +/* + * Copyright (C) 2024 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include + +static const stm32u5_gpio_config gpioc_af12 = { + .regs = GPIOC, + .config = { + .Pin = GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_12, + .Mode = GPIO_MODE_AF_PP, + .Pull = GPIO_PULLUP, + .Speed = GPIO_SPEED_FREQ_VERY_HIGH, + .Alternate = GPIO_AF12_SDMMC1 + } +}; + +static const stm32u5_gpio_config gpioc_af12_2 = { + .regs = GPIOC, + .config = { + .Pin = GPIO_PIN_11, + .Mode = GPIO_MODE_AF_PP, + .Pull = GPIO_PULLUP, + .Speed = GPIO_SPEED_FREQ_VERY_HIGH, + .Alternate = GPIO_AF12_SDMMC1 + } +}; + +static const stm32u5_gpio_config gpiod_af12 = { + .regs = GPIOD, + .config = { + .Pin = GPIO_PIN_2, + .Mode = GPIO_MODE_AF_PP, + .Pull = GPIO_PULLUP, + .Speed = GPIO_SPEED_FREQ_VERY_HIGH, + .Alternate = GPIO_AF12_SDMMC1 + } +}; + +void HAL_SD_MspInit( SD_HandleTypeDef *hsd ) +{ + /* Set PD7 to LOW to enable power to SD Card. */ + GPIO_InitTypeDef GPIO_InitStruct = { 0 }; + __HAL_RCC_GPIOD_CLK_ENABLE(); + HAL_GPIO_WritePin( GPIOD, GPIO_PIN_7, GPIO_PIN_RESET ); + GPIO_InitStruct.Pin = GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init( GPIOD, &GPIO_InitStruct ); + HAL_GPIO_WritePin( GPIOD, GPIO_PIN_7, GPIO_PIN_RESET ); + sleep( 1 ); + + /* Initializes the clock and gpio pins for SDMMC1 module */ + stm32u5_clk_enable( STM32U5_MODULE_SDMMC1 ); + stm32u5_gpio_init( &gpioc_af12 ); + stm32u5_gpio_init( &gpioc_af12_2 ); + stm32u5_gpio_init( &gpiod_af12 ); +} diff --git a/bsps/arm/stm32u5/start/stm32u5-hal-uart.c b/bsps/arm/stm32u5/start/stm32u5-hal-uart.c new file mode 100644 index 0000000000..d0d1d023c5 --- /dev/null +++ b/bsps/arm/stm32u5/start/stm32u5-hal-uart.c @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMSTM32U5 + * + * @brief UART clock and pin initialization called by HAL + */ + +/* + * Copyright (C) 2024 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include + +void HAL_UART_MspInit( UART_HandleTypeDef *uart ) +{ + stm32u5_uart_context *ctx; + const stm32u5_uart_config *config; + stm32u5_module_index index; + + ctx = (stm32u5_uart_context *) uart; + config = ctx->config; + index = stm32u5_get_module_index( ctx->uart.Instance ); + stm32u5_clk_enable( index ); + stm32u5_gpio_init( &config->gpio ); +} diff --git a/bsps/arm/stm32u5/start/stm32u5-hal.c b/bsps/arm/stm32u5/start/stm32u5-hal.c new file mode 100644 index 0000000000..a481d55d15 --- /dev/null +++ b/bsps/arm/stm32u5/start/stm32u5-hal.c @@ -0,0 +1,187 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMSTM32U5 + * + * @brief Implementation of support functions for the STM32U5 HAL + */ + +/* + * Copyright (C) 2024 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include + +#include + +stm32u5_module_index stm32u5_get_module_index( const void *regs ) +{ + switch ( (uintptr_t) regs ) { + case GPIOA_BASE: + return STM32U5_MODULE_GPIOA; + case GPIOB_BASE: + return STM32U5_MODULE_GPIOB; + case GPIOC_BASE: + return STM32U5_MODULE_GPIOC; + case GPIOD_BASE: + return STM32U5_MODULE_GPIOD; + case GPIOE_BASE: + return STM32U5_MODULE_GPIOE; + case GPIOF_BASE: + return STM32U5_MODULE_GPIOF; + case GPIOG_BASE: + return STM32U5_MODULE_GPIOG; + case GPIOH_BASE: + return STM32U5_MODULE_GPIOH; + case GPIOI_BASE: + return STM32U5_MODULE_GPIOI; + case GPIOJ_BASE: + return STM32U5_MODULE_GPIOJ; + case USART1_BASE: + return STM32U5_MODULE_USART1; + case USART2_BASE: + return STM32U5_MODULE_USART2; + case USART3_BASE: + return STM32U5_MODULE_USART3; + case UART4_BASE: + return STM32U5_MODULE_UART4; + case UART5_BASE: + return STM32U5_MODULE_UART5; + case USART6_BASE: + return STM32U5_MODULE_USART6; + case RNG_BASE: + return STM32U5_MODULE_RNG; + case SDMMC1_BASE: + case DLYB_SDMMC1_BASE: + return STM32U5_MODULE_SDMMC1; + case SDMMC2_BASE: + case DLYB_SDMMC2_BASE: + return STM32U5_MODULE_SDMMC2; + } + + return STM32U5_MODULE_INVALID; +} + +typedef struct { + __IO uint32_t *enr; + uint32_t enable_bit; +} stm32u5_clk_info; + +static const stm32u5_clk_info stm32u5_clk[] = { + [STM32U5_MODULE_INVALID] = { NULL, 0 }, + [STM32U5_MODULE_GPIOA] = { &RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN }, + [STM32U5_MODULE_GPIOB] = { &RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN }, + [STM32U5_MODULE_GPIOC] = { &RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN }, + [STM32U5_MODULE_GPIOD] = { &RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN }, + [STM32U5_MODULE_GPIOE] = { &RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN }, + [STM32U5_MODULE_GPIOF] = { &RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN }, + [STM32U5_MODULE_GPIOG] = { &RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN }, + [STM32U5_MODULE_GPIOH] = { &RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN }, + [STM32U5_MODULE_GPIOI] = { &RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN }, + [STM32U5_MODULE_GPIOJ] = { &RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOJEN }, + [STM32U5_MODULE_USART1] = { &RCC->APB2ENR, RCC_APB2ENR_USART1EN }, + [STM32U5_MODULE_USART2] = { &RCC->APB1ENR1, RCC_APB1ENR1_USART2EN }, + [STM32U5_MODULE_USART3] = { &RCC->APB1ENR1, RCC_APB1ENR1_USART3EN }, + [STM32U5_MODULE_UART4] = { &RCC->APB1ENR1, RCC_APB1ENR1_UART4EN }, + [STM32U5_MODULE_UART5] = { &RCC->APB1ENR1, RCC_APB1ENR1_UART5EN }, + [STM32U5_MODULE_USART6] = { &RCC->APB1ENR1, RCC_APB1ENR1_USART6EN }, + [STM32U5_MODULE_RNG] = { &RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN }, + [STM32U5_MODULE_SDMMC1] = { &RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN }, + [STM32U5_MODULE_SDMMC2] = { &RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN }, +}; + +void stm32u5_clk_enable( stm32u5_module_index index ) +{ + __IO uint32_t *enr; + uint32_t enable_bit; + rtems_interrupt_level level; + + enr = stm32u5_clk[ index ].enr; + enable_bit = stm32u5_clk[ index ].enable_bit; + + rtems_interrupt_disable( level ); + SET_BIT( *enr, enable_bit ); + /* Delay after an RCC peripheral clock enabling */ + *enr; + rtems_interrupt_enable( level ); +} + +void stm32u5_clk_disable( stm32u5_module_index index ) +{ + __IO uint32_t *enr; + uint32_t enable_bit; + rtems_interrupt_level level; + + enr = stm32u5_clk[ index ].enr; + enable_bit = stm32u5_clk[ index ].enable_bit; + + rtems_interrupt_disable( level ); + CLEAR_BIT( *enr, enable_bit ); + rtems_interrupt_enable( level ); +} + +void stm32u5_gpio_init( const stm32u5_gpio_config *config ) +{ + stm32u5_module_index index; + + index = stm32u5_get_module_index( config->regs ); + stm32u5_clk_enable( index ); + HAL_GPIO_Init( config->regs, &config->config ); +} + +void stm32u5_uart_polled_write( rtems_termios_device_context *base, char c ) +{ + stm32u5_uart_context *ctx; + USART_TypeDef *regs; + + ctx = stm32u5_uart_get_context( base ); + regs = ctx->uart.Instance; + + while ( ( regs->ISR & USART_ISR_TXE_TXFNF ) == 0 ) { + /* Wait */ + } + + regs->TDR = (uint8_t) c; +} + +int stm32u5_uart_polled_read( rtems_termios_device_context *base ) +{ + stm32u5_uart_context *ctx; + USART_TypeDef *regs; + + ctx = stm32u5_uart_get_context( base ); + regs = ctx->uart.Instance; + + if ( ( regs->ISR & USART_ISR_RXNE_RXFNE ) == 0 ) { + return -1; + } + + return (uint8_t) regs->RDR; +} diff --git a/bsps/arm/stm32u5/start/stm32u5-init-octospi.c b/bsps/arm/stm32u5/start/stm32u5-init-octospi.c new file mode 100644 index 0000000000..c0a1ed64f2 --- /dev/null +++ b/bsps/arm/stm32u5/start/stm32u5-init-octospi.c @@ -0,0 +1,221 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMSTM32U5 + * + * @brief Implementation of OctoSPI initialization + */ + +/* + * Copyright (C) 2024 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +void BSP_START_TEXT_SECTION stm32u5_init_octospi( void ) +{ + OSPI_HandleTypeDef hospi1 = { + .Instance = OCTOSPI1, + .Init = { + .FifoThreshold = 2, + .DualQuad = HAL_OSPI_DUALQUAD_DISABLE, + .MemoryType = HAL_OSPI_MEMTYPE_HYPERBUS, + .DeviceSize = 24, + .ChipSelectHighTime = 1, /* min 6ns -> 1 works for up to 160MHz */ + .FreeRunningClock = HAL_OSPI_FREERUNCLK_DISABLE, + .ClockMode = HAL_OSPI_CLOCK_MODE_0, + /* + * FIXME: Enable Hybrid burst in CR0 of the RAM and set to a sensible + * WrapSize + */ + .WrapSize = HAL_OSPI_WRAP_NOT_SUPPORTED, + .ClockPrescaler = 2, + /* + * Reference Manual: The firmware must clear SSHIFT when the data phase is + * configured in DTR mode (DDTR = 1). + */ + .SampleShifting = HAL_OSPI_SAMPLE_SHIFTING_NONE, + /* + * Reference Manual: In DTR mode, it is recommended to set DHQC of + * OCTOSPI_TCR, to shift the outputs by a quarter of cycle and avoid + * holding issues on the memory side. + */ + .DelayHoldQuarterCycle = HAL_OSPI_DHQC_ENABLE, + .ChipSelectBoundary = 7, + .DelayBlockBypass = HAL_OSPI_DELAY_BLOCK_USED, + .MaxTran = 0, + .Refresh = 241, /* based on AN5050 */ + }, + }; + + OSPIM_CfgTypeDef sOspiManagerCfg = { + .ClkPort = 1, + .DQSPort = 1, + .NCSPort = 1, + .IOLowPort = HAL_OSPIM_IOPORT_1_LOW, + .IOHighPort = HAL_OSPIM_IOPORT_1_HIGH, + }; + + OSPI_HyperbusCfgTypeDef sHyperBusCfg = { + /* + * S70KL1282 in 166MHz version needs at least 36ns. At 100MHz that's 3.6 + * clock cycles. + */ + .RWRecoveryTime = 4, + /* + * FIXME: That's the Clock latency. We could set the RAM config register to + * 4 clock latencies for 100 MHz. + */ + .AccessTime = 7, + .WriteZeroLatency = HAL_OSPI_LATENCY_ON_WRITE, + /* 128-Mb version of S70KL1282 only supports fixed latency */ + .LatencyMode = HAL_OSPI_FIXED_LATENCY, + }; + + OSPI_HyperbusCmdTypeDef sCommand = { + .AddressSpace = HAL_OSPI_MEMORY_ADDRESS_SPACE, + .AddressSize = HAL_OSPI_ADDRESS_32_BITS, + .DQSMode = HAL_OSPI_DQS_ENABLE, + .Address = 0, + .NbData = 1, + }; + + OSPI_MemoryMappedTypeDef sMemMappedCfg = { + .TimeOutActivation = HAL_OSPI_TIMEOUT_COUNTER_ENABLE, + .TimeOutPeriod = 0x20, + }; + + HAL_OSPI_DLYB_CfgTypeDef HAL_OSPI_DLYB_Cfg_Struct = { 0 }; + + if ( HAL_OSPIM_Config( + &hospi1, + &sOspiManagerCfg, + HAL_OSPI_TIMEOUT_DEFAULT_VALUE + ) != HAL_OK ) { + bsp_fatal( STM32U5_FATAL_OSPI ); + } + + if ( HAL_OSPI_Init( &hospi1 ) != HAL_OK ) { + bsp_fatal( STM32U5_FATAL_OSPI ); + } + + if ( HAL_OSPI_HyperbusCfg( + &hospi1, + &sHyperBusCfg, + HAL_OSPI_TIMEOUT_DEFAULT_VALUE + ) != HAL_OK ) { + bsp_fatal( STM32U5_FATAL_OSPI ); + } + + /* Delay block tuning */ + if ( HAL_OSPI_DLYB_GetClockPeriod( &hospi1, &HAL_OSPI_DLYB_Cfg_Struct ) != + HAL_OK ) { + bsp_fatal( STM32U5_FATAL_OSPI ); + } + /* From ST example: Set at one quarter. */ + HAL_OSPI_DLYB_Cfg_Struct.PhaseSel /= 4; + if ( HAL_OSPI_DLYB_SetConfig( &hospi1, &HAL_OSPI_DLYB_Cfg_Struct ) != + HAL_OK ) { + bsp_fatal( STM32U5_FATAL_OSPI ); + } + + /* Memory-mapped mode configuration */ + if ( HAL_OSPI_HyperbusCmd( + &hospi1, + &sCommand, + HAL_OSPI_TIMEOUT_DEFAULT_VALUE + ) != HAL_OK ) { + bsp_fatal( STM32U5_FATAL_OSPI ); + } + + /* OctoSPI activation of memory-mapped mode */ + if ( HAL_OSPI_MemoryMapped( &hospi1, &sMemMappedCfg ) != HAL_OK ) { + bsp_fatal( STM32U5_FATAL_OSPI ); + } +} + +void BSP_START_TEXT_SECTION HAL_OSPI_MspInit( OSPI_HandleTypeDef *hospi ) +{ + GPIO_InitTypeDef GPIO_InitStruct = { 0 }; + RCC_PeriphCLKInitTypeDef PeriphClkInit = { 0 }; + if ( hospi->Instance == OCTOSPI1 ) { + /* Initializes the peripherals clock */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_OSPI; + PeriphClkInit.OspiClockSelection = RCC_OSPICLKSOURCE_PLL2; + PeriphClkInit.PLL2.PLL2Source = RCC_PLLSOURCE_MSI; + PeriphClkInit.PLL2.PLL2M = 3; + PeriphClkInit.PLL2.PLL2N = 12; + PeriphClkInit.PLL2.PLL2P = 2; + PeriphClkInit.PLL2.PLL2Q = 1; + PeriphClkInit.PLL2.PLL2R = 2; + PeriphClkInit.PLL2.PLL2RGE = RCC_PLLVCIRANGE_1; + PeriphClkInit.PLL2.PLL2FRACN = 4096.0; + PeriphClkInit.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ; + if ( HAL_RCCEx_PeriphCLKConfig( &PeriphClkInit ) != HAL_OK ) { + bsp_fatal( STM32U5_FATAL_OSPI ); + } + + /* Peripheral clock enable */ + __HAL_RCC_OSPIM_CLK_ENABLE(); + __HAL_RCC_OSPI1_CLK_ENABLE(); + + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + + /* OCTOSPI1 GPIO Configuration */ + GPIO_InitStruct.Pin = GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF3_OCTOSPI1; + HAL_GPIO_Init( GPIOE, &GPIO_InitStruct ); + + GPIO_InitStruct.Pin = GPIO_PIN_0; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF3_OCTOSPI1; + HAL_GPIO_Init( GPIOC, &GPIO_InitStruct ); + + GPIO_InitStruct.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_OCTOSPI1; + HAL_GPIO_Init( GPIOC, &GPIO_InitStruct ); + + GPIO_InitStruct.Pin = GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | + GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_OCTOSPI1; + HAL_GPIO_Init( GPIOE, &GPIO_InitStruct ); + } +} diff --git a/bsps/include/bsp/fatal.h b/bsps/include/bsp/fatal.h index 74a9614c82..d3cc499bbc 100644 --- a/bsps/include/bsp/fatal.h +++ b/bsps/include/bsp/fatal.h @@ -226,6 +226,14 @@ typedef enum { /* STM32H7 fatal codes */ STM32H7_FATAL_MMU_CANNOT_REGISTER_SPI = BSP_FATAL_CODE_BLOCK(20), + + /* STM32U5 fatal codes */ + STM32U5_FATAL_INIT_POWER = BSP_FATAL_CODE_BLOCK(21), + STM32U5_FATAL_INIT_CLOCKS, + STM32U5_FATAL_OUTPUT_CHAR, + STM32U5_FATAL_OSPI, + STM32U5_FATAL_RTC, + } bsp_fatal_code; RTEMS_NO_RETURN static inline void diff --git a/spec/build/bsps/arm/grp.yml b/spec/build/bsps/arm/grp.yml index afe11a255d..2cb23665d2 100644 --- a/spec/build/bsps/arm/grp.yml +++ b/spec/build/bsps/arm/grp.yml @@ -14,9 +14,11 @@ install: - bsps/arm/include/cmsis_compiler.h - bsps/arm/include/cmsis_gcc.h - bsps/arm/include/cmsis_version.h - - bsps/arm/include/core_cm7.h + - bsps/arm/include/core_cm33.h - bsps/arm/include/core_cm4.h + - bsps/arm/include/core_cm7.h - bsps/arm/include/mpu_armv7.h + - bsps/arm/include/mpu_armv8.h - destination: ${BSP_INCLUDEDIR}/bsp source: - bsps/arm/include/bsp/arm-a9mpcore-clock.h diff --git a/spec/build/bsps/arm/stm32u5/abi.yml b/spec/build/bsps/arm/stm32u5/abi.yml new file mode 100644 index 0000000000..6f2d581099 --- /dev/null +++ b/spec/build/bsps/arm/stm32u5/abi.yml @@ -0,0 +1,19 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- split: null +- env-append: null +build-type: option +copyrights: +- Copyright (C) 2024 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: + - -mthumb + - -mcpu=cortex-m33 +description: | + ABI flags +enabled-by: true +links: [] +name: ABI_FLAGS +type: build diff --git a/spec/build/bsps/arm/stm32u5/bspstm32u5-grisp-nano.yml b/spec/build/bsps/arm/stm32u5/bspstm32u5-grisp-nano.yml new file mode 100644 index 0000000000..5394e91310 --- /dev/null +++ b/spec/build/bsps/arm/stm32u5/bspstm32u5-grisp-nano.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +arch: arm +bsp: stm32u5-grisp-nano +build-type: bsp +cflags: [] +copyrights: +- Copyright (C) 2024 embedded brains GmbH & Co. KG +cppflags: [] +enabled-by: true +family: stm32u5 +includes: [] +install: [] +links: +- role: build-dependency + uid: grp +source: [] +type: build diff --git a/spec/build/bsps/arm/stm32u5/grp.yml b/spec/build/bsps/arm/stm32u5/grp.yml new file mode 100644 index 0000000000..ec34d95721 --- /dev/null +++ b/spec/build/bsps/arm/stm32u5/grp.yml @@ -0,0 +1,69 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +build-type: group +cflags: [] +copyrights: +- Copyright (C) 2024 embedded brains GmbH & Co. KG +cppflags: [] +cxxflags: [] +enabled-by: true +includes: [] +install: [] +ldflags: [] +links: +- role: build-dependency + uid: ../../obj +- role: build-dependency + uid: ../../objirq +- role: build-dependency + uid: ../../opto2 +- role: build-dependency + uid: abi +- role: build-dependency + uid: obj +- role: build-dependency + uid: optmemflashsz +- role: build-dependency + uid: optmemnullsz +- role: build-dependency + uid: optmemintsramsz +- role: build-dependency + uid: optmemintsramlpbamsz +- role: build-dependency + uid: optmemoctospi1sz +- role: build-dependency + uid: optmemoctospi2sz +- role: build-dependency + uid: optprintkinstance +- role: build-dependency + uid: optusart1gpiopins +- role: build-dependency + uid: optusart2gpiopins +- role: build-dependency + uid: optusart3gpiopins +- role: build-dependency + uid: optenusart1 +- role: build-dependency + uid: optenusart2 +- role: build-dependency + uid: optenusart3 +- role: build-dependency + uid: optlinkcmds +- role: build-dependency + uid: ../../objmem +- role: build-dependency + uid: ../grp +- role: build-dependency + uid: ../start +- role: build-dependency + uid: linkcmds +- role: build-dependency + uid: linkcmdsmemory +- role: build-dependency + uid: ../../bspopts +- role: build-dependency + uid: ../../optconsolebaud +- role: build-dependency + uid: ../../optconsoleirq +type: build +use-after: [] +use-before: [] diff --git a/spec/build/bsps/arm/stm32u5/linkcmds.yml b/spec/build/bsps/arm/stm32u5/linkcmds.yml new file mode 100644 index 0000000000..fdbc3466f6 --- /dev/null +++ b/spec/build/bsps/arm/stm32u5/linkcmds.yml @@ -0,0 +1,11 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +build-type: config-file +content: | + INCLUDE ${STM32U5_DEFAULT_LINKCMDS} +copyrights: +- Copyright (C) 2024 embedded brains GmbH & Co. KG +enabled-by: true +install-path: ${BSP_LIBDIR} +links: [] +target: linkcmds +type: build diff --git a/spec/build/bsps/arm/stm32u5/linkcmdsmemory.yml b/spec/build/bsps/arm/stm32u5/linkcmdsmemory.yml new file mode 100644 index 0000000000..d4b7944b81 --- /dev/null +++ b/spec/build/bsps/arm/stm32u5/linkcmdsmemory.yml @@ -0,0 +1,42 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +build-type: config-file +content: | + MEMORY { + NULL : ORIGIN = 0x00000000, LENGTH = ${STM32U5_MEMORY_NULL_SIZE:#010x} + FLASH : ORIGIN = 0x08000000, LENGTH = ${STM32U5_MEMORY_FLASH_SIZE:#010x} + INT_SRAM : ORIGIN = 0x20000000, LENGTH = ${STM32U5_MEMORY_INT_SRAM_SIZE:#010x} + INT_SRAM_LPBAM : ORIGIN = 0x28000000, LENGTH = ${STM32U5_MEMORY_INT_SRAM_LPBAM_SIZE:#010x} + OCTOSPI_2 : ORIGIN = 0x70000000, LENGTH = ${STM32U5_MEMORY_OCTOSPI_2_SIZE:#010x} + OCTOSPI_1 : ORIGIN = 0x90000000, LENGTH = ${STM32U5_MEMORY_OCTOSPI_1_SIZE:#010x} + } + + stm32u5_memory_null_begin = ORIGIN (NULL); + stm32u5_memory_null_end = ORIGIN (NULL) + LENGTH (NULL); + stm32u5_memory_null_size = LENGTH (NULL); + + stm32u5_memory_flash_begin = ORIGIN (FLASH); + stm32u5_memory_flash_end = ORIGIN (FLASH) + LENGTH (FLASH); + stm32u5_memory_flash_size = LENGTH (FLASH); + + stm32u5_memory_int_sram_begin = ORIGIN (INT_SRAM); + stm32u5_memory_int_sram_end = ORIGIN (INT_SRAM) + LENGTH (INT_SRAM); + stm32u5_memory_int_sram_size = LENGTH (INT_SRAM); + + stm32u5_memory_int_sram_lpbam_begin = ORIGIN (INT_SRAM_LPBAM); + stm32u5_memory_int_sram_lpbam_end = ORIGIN (INT_SRAM_LPBAM) + LENGTH (INT_SRAM_LPBAM); + stm32u5_memory_int_sram_lpbam_size = LENGTH (INT_SRAM_LPBAM); + + stm32u5_memory_octospi_1_begin = ORIGIN (OCTOSPI_1); + stm32u5_memory_octospi_1_end = ORIGIN (OCTOSPI_1) + LENGTH (OCTOSPI_1); + stm32u5_memory_octospi_1_size = LENGTH (OCTOSPI_1); + + stm32u5_memory_octospi_2_begin = ORIGIN (OCTOSPI_2); + stm32u5_memory_octospi_2_end = ORIGIN (OCTOSPI_2) + LENGTH (OCTOSPI_2); + stm32u5_memory_octospi_2_size = LENGTH (OCTOSPI_2); +copyrights: +- Copyright (C) 2024 embedded brains GmbH & Co. KG +enabled-by: true +install-path: ${BSP_LIBDIR} +links: [] +target: linkcmds.memory +type: build diff --git a/spec/build/bsps/arm/stm32u5/obj.yml b/spec/build/bsps/arm/stm32u5/obj.yml new file mode 100644 index 0000000000..a0d84eb31f --- /dev/null +++ b/spec/build/bsps/arm/stm32u5/obj.yml @@ -0,0 +1,312 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +build-type: objects +cflags: [] +copyrights: +- Copyright (C) 2024 embedded brains GmbH & Co. KG +cppflags: [] +cxxflags: [] +enabled-by: true +includes: [] +install: +- destination: ${BSP_INCLUDEDIR} + source: + - bsps/arm/stm32u5/include/bsp.h + - bsps/arm/stm32u5/include/chip.h + - bsps/arm/stm32u5/include/tm27.h + - bsps/arm/stm32u5/include/stm32u5xx.h + - bsps/arm/stm32u5/include/stm32u5g9xx.h + - bsps/arm/stm32u5/include/system_stm32u5xx.h + - bsps/arm/stm32u5/include/stm32u5xx_ll_cortex.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_smbus.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_flash.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_exti.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_otfdec.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_adc_ex.h + - bsps/arm/stm32u5/include/stm32u5xx_ll_iwdg.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_hcd.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_sd_ex.h + - bsps/arm/stm32u5/include/stm32u5xx_ll_fmc.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_spi.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_dsi.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_xspi.h + - bsps/arm/stm32u5/include/stm32u5xx_ll_dma2d.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_tim_ex.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_mdf.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_dma_ex.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_mmc.h + - bsps/arm/stm32u5/include/stm32u5xx_ll_crc.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_def.h + - bsps/arm/stm32u5/include/stm32u5xx_ll_rtc.h + - bsps/arm/stm32u5/include/stm32u5xx_ll_sdmmc.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_gtzc.h + - bsps/arm/stm32u5/include/stm32u5xx_ll_rng.h + - bsps/arm/stm32u5/include/stm32u5xx_ll_dma.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_rng.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_gpu2d.h + - bsps/arm/stm32u5/include/stm32_assert.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_nand.h + - bsps/arm/stm32u5/include/stm32u5xx_ll_tim.h + - bsps/arm/stm32u5/include/stm32u5xx_ll_ucpd.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_wwdg.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_dcache.h + - bsps/arm/stm32u5/include/stm32u5xx_ll_lpuart.h + - bsps/arm/stm32u5/include/stm32u5xx_ll_spi.h + - bsps/arm/stm32u5/include/stm32u5xx_ll_comp.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_fdcan.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_cryp_ex.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_rng_ex.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_rtc.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_adc.h + - bsps/arm/stm32u5/include/stm32u5xx_ll_pwr.h + - bsps/arm/stm32u5/include/stm32u5xx_ll_fmac.h + - bsps/arm/stm32u5/include/stm32u5xx_ll_lptim.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_dma.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_sai.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_gfxtim.h + - bsps/arm/stm32u5/include/stm32u5xx_ll_dac.h + - bsps/arm/stm32u5/include/stm32u5xx_ll_dcache.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_crc.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_crc_ex.h + - bsps/arm/stm32u5/include/stm32u5xx_hal.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_pwr_ex.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_usart.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_rtc_ex.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_opamp_ex.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_sai_ex.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_ospi.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_rcc.h + - bsps/arm/stm32u5/include/stm32u5xx_ll_system.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_usart_ex.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_i2c_ex.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_tsc.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_smartcard.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_irda_ex.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_pcd_ex.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_jpeg.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_cortex.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_tim.h + - bsps/arm/stm32u5/include/stm32u5xx_ll_pka.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_cordic.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_pwr.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_gpio_ex.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_gpio.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_dac.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_smbus_ex.h + - bsps/arm/stm32u5/include/stm32u5xx_ll_icache.h + - bsps/arm/stm32u5/include/stm32u5xx_ll_opamp.h + - bsps/arm/stm32u5/include/stm32u5xx_ll_bus.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_nor.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_pssi.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_dac_ex.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_spi_ex.h + - bsps/arm/stm32u5/include/stm32u5xx_ll_crs.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_sd.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_ramcfg.h + - bsps/arm/stm32u5/include/stm32u5xx_ll_wwdg.h + - bsps/arm/stm32u5/include/stm32u5xx_ll_usart.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_i2c.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_uart_ex.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_sram.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_opamp.h + - bsps/arm/stm32u5/include/stm32u5xx_ll_exti.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_smartcard_ex.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_iwdg.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_dma2d.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_ltdc_ex.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_pka.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_mmc_ex.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_cryp.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_pcd.h + - bsps/arm/stm32u5/include/stm32u5xx_ll_adc.h + - bsps/arm/stm32u5/include/stm32u5xx_ll_gpio.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_comp.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_gfxmmu.h + - bsps/arm/stm32u5/include/stm32u5xx_ll_dlyb.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_uart.h + - bsps/arm/stm32u5/include/stm32u5xx_ll_cordic.h + - bsps/arm/stm32u5/include/stm32u5xx_ll_i2c.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_hash.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_rcc_ex.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_dcmi.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_flash_ex.h + - bsps/arm/stm32u5/include/stm32u5xx_ll_usb.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_fmac.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_lptim.h + - bsps/arm/stm32u5/include/stm32u5xx_ll_utils.h + - bsps/arm/stm32u5/include/stm32u5xx_ll_lpgpio.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_irda.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_icache.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_ltdc.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_hash_ex.h + - bsps/arm/stm32u5/include/stm32u5xx_ll_rcc.h + - bsps/arm/stm32u5/include/stm32u5xx_hal_conf.h +- destination: ${BSP_INCLUDEDIR}/Legacy + source: + - bsps/arm/stm32u5/include/Legacy/stm32_hal_legacy.h +- destination: ${BSP_INCLUDEDIR}/bsp + source: + - bsps/arm/stm32u5/include/bsp/irq.h +- destination: ${BSP_INCLUDEDIR}/stm32u5 + source: + - bsps/arm/stm32u5/include/stm32u5/hal.h +- destination: ${BSP_LIBDIR} + source: + - bsps/arm/stm32u5/start/linkcmds.flash + - bsps/arm/stm32u5/start/linkcmds.flash+ospi + - bsps/arm/stm32u5/start/linkcmds.sram + - bsps/arm/stm32u5/start/linkcmds.ospi +links: [] +source: +- bsps/arm/shared/clock/clock-armv7m.c +- bsps/arm/shared/cpucounter/cpucounter-armv7m.c +- bsps/arm/shared/irq/irq-armv7m.c +- bsps/arm/shared/irq/irq-dispatch-armv7m.c +- bsps/arm/shared/start/bsp-start-memcpy.S +- bsps/arm/shared/start/bspreset-armv7m.c +- bsps/shared/dev/btimer/btimer-cpucounter.c +- bsps/shared/dev/rtc/rtc-support.c +- bsps/shared/dev/serial/console-termios.c +- bsps/shared/irq/irq-default-handler.c +- bsps/shared/start/bspfatal-default.c +- bsps/shared/start/gettargethash-default.c +- bsps/shared/start/sbrk.c +- bsps/shared/start/stackalloc.c +- bsps/arm/shared/cache/cache-v7m.c +- bsps/arm/stm32u5/console/console.c +- bsps/arm/stm32u5/console/printk-support.c +- bsps/arm/stm32u5/console/console-usart1.c +- bsps/arm/stm32u5/console/console-usart1-cfg.c +- bsps/arm/stm32u5/console/console-usart2.c +- bsps/arm/stm32u5/console/console-usart2-cfg.c +- bsps/arm/stm32u5/console/console-usart3.c +- bsps/arm/stm32u5/console/console-usart3-cfg.c +- bsps/arm/stm32u5/start/bspstart.c +- bsps/arm/stm32u5/start/bspstarthooks.c +- bsps/arm/stm32u5/start/getentropy-rng.c +- bsps/arm/stm32u5/start/stm32u5-hal.c +- bsps/arm/stm32u5/start/stm32u5-config-clk.c +- bsps/arm/stm32u5/start/stm32u5-config-osc.c +- bsps/arm/stm32u5/start/stm32u5-config-per.c +- bsps/arm/stm32u5/start/stm32u5-hal-uart.c +- bsps/arm/stm32u5/start/stm32u5-hal-sdmmc.c +- bsps/arm/stm32u5/start/stm32u5-init-octospi.c +- bsps/arm/stm32u5/start/stm32u5-config-rtc.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_rtc.c +- bsps/arm/stm32u5/hal/system_stm32u5xx.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_dac_ex.c +- bsps/arm/stm32u5/hal/stm32u5xx_ll_spi.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_opamp_ex.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_nand.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_lptim.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_usart_ex.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_gpio.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_uart_ex.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_rng.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_timebase_rtc_alarm.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_comp.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_sai.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_dcmi.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_wwdg.c +- bsps/arm/stm32u5/hal/stm32u5xx_ll_usart.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_tsc.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_ospi.c +- bsps/arm/stm32u5/hal/stm32u5xx_ll_crc.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_dac.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_pcd.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_xspi.c +- bsps/arm/stm32u5/hal/stm32u5xx_ll_adc.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_dma_ex.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_dma2d.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_irda.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_rcc.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_nor.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_pwr.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_adc.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_usart.c +- bsps/arm/stm32u5/hal/stm32u5xx_ll_rcc.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_otfdec.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_i2c_ex.c +- bsps/arm/stm32u5/hal/stm32u5xx_ll_lpgpio.c +- bsps/arm/stm32u5/hal/stm32u5xx_ll_crs.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_sai_ex.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_mmc.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_mmc_ex.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_sram.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_spi.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_timebase_tim.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_cordic.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_msp.c +- bsps/arm/stm32u5/hal/stm32u5xx_ll_pwr.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_dcache.c +- bsps/arm/stm32u5/hal/stm32u5xx_ll_ucpd.c +- bsps/arm/stm32u5/hal/stm32u5xx_ll_icache.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_hash_ex.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_pka.c +- bsps/arm/stm32u5/hal/stm32u5xx_ll_fmac.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_opamp.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_ltdc.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_pssi.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_jpeg.c +- bsps/arm/stm32u5/hal/stm32u5xx_ll_cordic.c +- bsps/arm/stm32u5/hal/stm32u5xx_ll_exti.c +- bsps/arm/stm32u5/hal/stm32u5xx_ll_pka.c +- bsps/arm/stm32u5/hal/stm32u5xx_ll_utils.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_cryp_ex.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_fmac.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_rcc_ex.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_icache.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_hcd.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_timebase_rtc_wakeup.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_uart.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_flash.c +- bsps/arm/stm32u5/hal/stm32u5xx_ll_gpio.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_rtc_ex.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_smbus_ex.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_smbus.c +- bsps/arm/stm32u5/hal/stm32u5xx_ll_dac.c +- bsps/arm/stm32u5/hal/stm32u5xx_ll_opamp.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_dsi.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_pwr_ex.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_gfxmmu.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_cortex.c +- bsps/arm/stm32u5/hal/stm32u5xx_ll_sdmmc.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_fdcan.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_adc_ex.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_tim.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_smartcard_ex.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_smartcard.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_gfxtim.c +- bsps/arm/stm32u5/hal/stm32u5xx_ll_lptim.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_exti.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_tim_ex.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_pcd_ex.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_sd.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_flash_ex.c +- bsps/arm/stm32u5/hal/stm32u5xx_ll_rng.c +- bsps/arm/stm32u5/hal/stm32u5xx_ll_lpuart.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_ramcfg.c +- bsps/arm/stm32u5/hal/stm32u5xx_ll_dlyb.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_sd_ex.c +- bsps/arm/stm32u5/hal/stm32u5xx_ll_fmc.c +- bsps/arm/stm32u5/hal/stm32u5xx_ll_tim.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_cryp.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_dma.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal.c +- bsps/arm/stm32u5/hal/stm32u5xx_ll_dma.c +- bsps/arm/stm32u5/hal/stm32u5xx_ll_i2c.c +- bsps/arm/stm32u5/hal/stm32u5xx_ll_rtc.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_spi_ex.c +- bsps/arm/stm32u5/hal/stm32u5xx_ll_usb.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_crc_ex.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_crc.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_i2c.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_gpu2d.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_ltdc_ex.c +- bsps/arm/stm32u5/hal/stm32u5xx_ll_comp.c +- bsps/arm/stm32u5/hal/stm32u5xx_ll_dma2d.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_iwdg.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_hash.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_mdf.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_gtzc.c +- bsps/arm/stm32u5/hal/stm32u5xx_hal_rng_ex.c +type: build diff --git a/spec/build/bsps/arm/stm32u5/optenusart1.yml b/spec/build/bsps/arm/stm32u5/optenusart1.yml new file mode 100644 index 0000000000..9a801d327e --- /dev/null +++ b/spec/build/bsps/arm/stm32u5/optenusart1.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright (C) 2024 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: false +description: | + Enable USART1 device in console driver. +enabled-by: true +format: '{}' +links: [] +name: STM32U5_CONSOLE_ENABLE_USART1 +type: build diff --git a/spec/build/bsps/arm/stm32u5/optenusart2.yml b/spec/build/bsps/arm/stm32u5/optenusart2.yml new file mode 100644 index 0000000000..b99963ae24 --- /dev/null +++ b/spec/build/bsps/arm/stm32u5/optenusart2.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright (C) 2024 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: true +description: | + Enable USART2 device in console driver. +enabled-by: true +format: '{}' +links: [] +name: STM32U5_CONSOLE_ENABLE_USART2 +type: build diff --git a/spec/build/bsps/arm/stm32u5/optenusart3.yml b/spec/build/bsps/arm/stm32u5/optenusart3.yml new file mode 100644 index 0000000000..9c7036b41e --- /dev/null +++ b/spec/build/bsps/arm/stm32u5/optenusart3.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright (C) 2024 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: false +description: | + Enable USART3 device in console driver. +enabled-by: true +format: '{}' +links: [] +name: STM32U5_CONSOLE_ENABLE_USART3 +type: build diff --git a/spec/build/bsps/arm/stm32u5/optlinkcmds.yml b/spec/build/bsps/arm/stm32u5/optlinkcmds.yml new file mode 100644 index 0000000000..6d37dad613 --- /dev/null +++ b/spec/build/bsps/arm/stm32u5/optlinkcmds.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- env-assign: null +build-type: option +copyrights: +- Copyright (C) 2024 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: linkcmds.flash +description: | + The default linker command file +enabled-by: true +format: '{}' +links: [] +name: STM32U5_DEFAULT_LINKCMDS +type: build diff --git a/spec/build/bsps/arm/stm32u5/optmemflashsz.yml b/spec/build/bsps/arm/stm32u5/optmemflashsz.yml new file mode 100644 index 0000000000..fe977ae957 --- /dev/null +++ b/spec/build/bsps/arm/stm32u5/optmemflashsz.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- env-assign: null +build-type: option +copyrights: +- Copyright (C) 2024 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: 0x00400000 +description: | + Size of the FLASH memory area in bytes. +enabled-by: true +format: '{:#010x}' +links: [] +name: STM32U5_MEMORY_FLASH_SIZE +type: build diff --git a/spec/build/bsps/arm/stm32u5/optmemintsramlpbamsz.yml b/spec/build/bsps/arm/stm32u5/optmemintsramlpbamsz.yml new file mode 100644 index 0000000000..cdca799c33 --- /dev/null +++ b/spec/build/bsps/arm/stm32u5/optmemintsramlpbamsz.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- env-assign: null +build-type: option +copyrights: +- Copyright (C) 2024 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: 0x00004000 +description: | + Size of the peripheral low-power background autonomous mode (LPBAM / SRAM 4) + memory area in bytes. +enabled-by: true +format: '{:#010x}' +links: [] +name: STM32U5_MEMORY_INT_SRAM_LPBAM_SIZE +type: build diff --git a/spec/build/bsps/arm/stm32u5/optmemintsramsz.yml b/spec/build/bsps/arm/stm32u5/optmemintsramsz.yml new file mode 100644 index 0000000000..78a2555dcb --- /dev/null +++ b/spec/build/bsps/arm/stm32u5/optmemintsramsz.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- env-assign: null +build-type: option +copyrights: +- Copyright (C) 2024 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: 0x002F0000 +description: | + Size of the Internal SRAM memory area in bytes. +enabled-by: true +format: '{:#010x}' +links: [] +name: STM32U5_MEMORY_INT_SRAM_SIZE +type: build diff --git a/spec/build/bsps/arm/stm32u5/optmemnullsz.yml b/spec/build/bsps/arm/stm32u5/optmemnullsz.yml new file mode 100644 index 0000000000..4815ca531e --- /dev/null +++ b/spec/build/bsps/arm/stm32u5/optmemnullsz.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- env-assign: null +build-type: option +copyrights: +- Copyright (C) 2024 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: 0x00000000 +description: | + Size of the NULL pointer protection area in bytes. +enabled-by: true +format: '{:#010x}' +links: [] +name: STM32U5_MEMORY_NULL_SIZE +type: build diff --git a/spec/build/bsps/arm/stm32u5/optmemoctospi1sz.yml b/spec/build/bsps/arm/stm32u5/optmemoctospi1sz.yml new file mode 100644 index 0000000000..0aeb99b636 --- /dev/null +++ b/spec/build/bsps/arm/stm32u5/optmemoctospi1sz.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- env-assign: null +build-type: option +copyrights: +- Copyright (C) 2024 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: 0x1000000 +description: | + Size of the memory connected to OCTOSPI 1 in bytes. +enabled-by: true +format: '{:#010x}' +links: [] +name: STM32U5_MEMORY_OCTOSPI_1_SIZE +type: build diff --git a/spec/build/bsps/arm/stm32u5/optmemoctospi2sz.yml b/spec/build/bsps/arm/stm32u5/optmemoctospi2sz.yml new file mode 100644 index 0000000000..79b3baf596 --- /dev/null +++ b/spec/build/bsps/arm/stm32u5/optmemoctospi2sz.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- env-assign: null +build-type: option +copyrights: +- Copyright (C) 2024 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: 0x10000000 +description: | + Size of the OCTOSPI 2 bank area in bytes. +enabled-by: true +format: '{:#010x}' +links: [] +name: STM32U5_MEMORY_OCTOSPI_2_SIZE +type: build diff --git a/spec/build/bsps/arm/stm32u5/optprintkinstance.yml b/spec/build/bsps/arm/stm32u5/optprintkinstance.yml new file mode 100644 index 0000000000..f29a93008f --- /dev/null +++ b/spec/build/bsps/arm/stm32u5/optprintkinstance.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- define-unquoted: null +build-type: option +copyrights: +- Copyright (C) 2024 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: stm32u5_usart2_instance +description: | + UART/USART instance used for printk() and getchark(). +enabled-by: true +format: '{}' +links: [] +name: STM32U5_PRINTK_INSTANCE +type: build diff --git a/spec/build/bsps/arm/stm32u5/optusart1gpiopins.yml b/spec/build/bsps/arm/stm32u5/optusart1gpiopins.yml new file mode 100644 index 0000000000..c753c71e17 --- /dev/null +++ b/spec/build/bsps/arm/stm32u5/optusart1gpiopins.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- define-unquoted: null +build-type: option +copyrights: +- Copyright (C) 2024 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: ( GPIO_PIN_9 | GPIO_PIN_10 ) +description: | + GPIO pins used for the USART1 pin configuration. +enabled-by: true +format: '{}' +links: [] +name: STM32U5_USART1_GPIO_PINS +type: build diff --git a/spec/build/bsps/arm/stm32u5/optusart2gpiopins.yml b/spec/build/bsps/arm/stm32u5/optusart2gpiopins.yml new file mode 100644 index 0000000000..1dafddf3e7 --- /dev/null +++ b/spec/build/bsps/arm/stm32u5/optusart2gpiopins.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- define-unquoted: null +build-type: option +copyrights: +- Copyright (C) 2024 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: ( GPIO_PIN_2 | GPIO_PIN_3 ) +description: | + GPIO pins used for the USART2 pin configuration. +enabled-by: true +format: '{}' +links: [] +name: STM32U5_USART2_GPIO_PINS +type: build diff --git a/spec/build/bsps/arm/stm32u5/optusart3gpiopins.yml b/spec/build/bsps/arm/stm32u5/optusart3gpiopins.yml new file mode 100644 index 0000000000..63e8d30aeb --- /dev/null +++ b/spec/build/bsps/arm/stm32u5/optusart3gpiopins.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- define-unquoted: null +build-type: option +copyrights: +- Copyright (C) 2024 embedded brains GmbH & Co. KG +default: +- enabled-by: true + value: ( GPIO_PIN_8 | GPIO_PIN_9 ) +description: | + GPIO pins used for the USART3 pin configuration. +enabled-by: true +format: '{}' +links: [] +name: STM32U5_USART3_GPIO_PINS +type: build diff --git a/spec/build/cpukit/optlibdebugger.yml b/spec/build/cpukit/optlibdebugger.yml index 19ce1a8dd4..446a6be7e3 100644 --- a/spec/build/cpukit/optlibdebugger.yml +++ b/spec/build/cpukit/optlibdebugger.yml @@ -18,6 +18,7 @@ enabled-by: - not: bsps/arm/lpc24xx - not: bsps/arm/stm32h7 - not: bsps/arm/stm32f4 + - not: bsps/arm/stm32u5 - i386 - microblaze - and: