Imagelibrary/rtems
1
0
Fork 1
mirror of https://gitlab.rtems.org/rtems/rtos/rtems.git synced 2025-12-25 22:07:15 +00:00
Code Issues Packages Projects Releases Wiki Activity

score: Add CPU_INTERRUPT_STACK_ALIGNMENT

Browse Source 
Add CPU port define for the interrupt stack alignment.  The alignment
should take the stack ABI and the cache line size into account.

Update #3459.
This commit is contained in:
Sebastian Huber
2018-06-19 14:59:51 +02:00
parent 196ce1859a
commit c8df844cf3
18 changed files with 45 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
cpukit/score/cpu/arm/include/rtems/score/cpu.h
View File

@@ -165,6 +165,8 @@
/* AAPCS, section 5.2.1.2, Stack constraints at a public interface */
#define CPU_STACK_ALIGNMENT 8
#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
/*
* Bitfield handler macros.
*

2
cpukit/score/cpu/bfin/include/rtems/score/cpu.h
View File

@@ -563,6 +563,8 @@ typedef struct {
*/
#define CPU_STACK_ALIGNMENT 8
#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
#ifndef ASM
/*

2
cpukit/score/cpu/epiphany/include/rtems/score/cpu.h
View File

@@ -465,6 +465,8 @@ typedef Context_Control CPU_Interrupt_frame;
#define CPU_STACK_ALIGNMENT 8
#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
/* ISR handler macros */
/*

2
cpukit/score/cpu/i386/include/rtems/score/cpu.h
View File

@@ -383,6 +383,8 @@ extern Context_Control_fp _CPU_Null_fp_context;
#define CPU_STACK_ALIGNMENT 16
#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
/* macros */
#ifndef ASM

2
cpukit/score/cpu/lm32/include/rtems/score/cpu.h
View File

@@ -581,6 +581,8 @@ extern Context_Control_fp _CPU_Null_fp_context;
*/
#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT
#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
/*
* ISR handler macros
*/

2
cpukit/score/cpu/m32c/include/rtems/score/cpu.h
View File

@@ -556,6 +556,8 @@ typedef struct {
*/
#define CPU_STACK_ALIGNMENT 0
#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
/*
* ISR handler macros
*/

2
cpukit/score/cpu/m68k/include/rtems/score/cpu.h
View File

@@ -354,6 +354,8 @@ extern void* _VBR;
#define CPU_STACK_ALIGNMENT 0
#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
#ifndef ASM
/* macros */

2
cpukit/score/cpu/mips/include/rtems/score/cpu.h
View File

@@ -631,6 +631,8 @@ extern Context_Control_fp _CPU_Null_fp_context;
#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT
#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
void mips_vector_exceptions( CPU_Interrupt_frame *frame );
/*

2
cpukit/score/cpu/moxie/include/rtems/score/cpu.h
View File

@@ -465,6 +465,8 @@ typedef struct {
*/
#define CPU_STACK_ALIGNMENT 0
#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
/*
* ISR handler macros
*/

2
cpukit/score/cpu/nios2/include/rtems/score/cpu.h
View File

@@ -87,6 +87,8 @@ extern "C" {
*/
#define CPU_STACK_ALIGNMENT 4
#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
/*
* A Nios II configuration with an external interrupt controller (EIC) supports
* up to 64 interrupt levels. A Nios II configuration with an internal

8
cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h
View File

@@ -695,6 +695,14 @@ extern Context_Control_fp _CPU_Null_fp_context;
*/
#define CPU_STACK_ALIGNMENT 0
/**
* The alignment of the interrupt stack in bytes.
*
* The alignment should take the stack ABI and the cache line size into
* account.
*/
#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
/*
* ISR handler macros
*/

2
cpukit/score/cpu/or1k/include/rtems/score/cpu.h
View File

@@ -462,6 +462,8 @@ typedef Context_Control CPU_Interrupt_frame;
#define CPU_STACK_ALIGNMENT 0
#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
/* ISR handler macros */
/*

2
cpukit/score/cpu/powerpc/include/rtems/score/cpu.h
View File

@@ -761,6 +761,8 @@ void ppc_set_interrupt_level( uint32_t level );
#define CPU_STACK_ALIGNMENT (PPC_STACK_ALIGNMENT)
#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
#ifndef ASM
/* The following routine swaps the endian format of an unsigned int.
* It must be static because it is referenced indirectly.

5
cpukit/score/cpu/riscv/include/rtems/score/cpu.h
View File

@@ -137,6 +137,8 @@ typedef Context_Control CPU_Interrupt_frame;
#define CPU_CONTEXT_FP_SIZE 0
Context_Control_fp _CPU_Null_fp_context;
#define CPU_CACHE_LINE_BYTES 64
#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
#if __riscv_xlen == 32
#define CPU_STACK_MINIMUM_SIZE 4096
@@ -148,6 +150,9 @@ Context_Control_fp _CPU_Null_fp_context;
#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
#define CPU_STACK_ALIGNMENT 8
#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
#define _CPU_Initialize_vectors()
/*

2
cpukit/score/cpu/sh/include/rtems/score/cpu.h
View File

@@ -438,6 +438,8 @@ void CPU_delay( uint32_t microseconds );
#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT
#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
/*
* ISR handler macros
*/

2
cpukit/score/cpu/sparc/include/rtems/score/cpu.h
View File

@@ -823,6 +823,8 @@ extern const CPU_Trap_table_entry _CPU_Trap_slot_template;
*/
#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT
#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
#ifndef ASM
/*

2
cpukit/score/cpu/sparc64/include/rtems/score/cpu.h
View File

@@ -709,6 +709,8 @@ extern const CPU_Trap_table_entry _CPU_Trap_slot_template;
#define CPU_STACK_ALIGNMENT 16
#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
#ifndef ASM
/*

2
cpukit/score/cpu/v850/include/rtems/score/cpu.h
View File

@@ -524,6 +524,8 @@ typedef struct {
*/
#define CPU_STACK_ALIGNMENT 4
#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
/*
* ISR handler macros
*/