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https://gitlab.rtems.org/rtems/rtos/rtems.git
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arm/raspberrypi: ensure that RTEMS application image can be started by U-boot.
The current versions of U-boot start kernel/RTEMS application image
with instruction and data caches enabled and it sets exception
base register to new address after its self-relocation.
ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
mcr p15, 0, r0, c12, c0, 0 /* Set VBAR */
Included changes in bsp_start_hook_0 restore default state to
allow RTEMS image to run after startup from newer U-boot version
on Raspberry Pi.
Clear interrupt enable registers in interrupt controller
to ensure that RTEMS starts from well defined state.
Updates #2783
This commit is contained in:
@@ -120,5 +120,9 @@ void bsp_interrupt_handler_default(rtems_vector_number vector)
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rtems_status_code bsp_interrupt_facility_initialize(void)
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{
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raspberrypi_set_exception_handler(ARM_EXCEPTION_IRQ, _ARMV4_Exception_interrupt);
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BCM2835_REG(BCM2835_IRQ_DISABLE1) = 0xffffffff;
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BCM2835_REG(BCM2835_IRQ_DISABLE2) = 0xffffffff;
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BCM2835_REG(BCM2835_IRQ_DISABLE_BASIC) = 0xffffffff;
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BCM2835_REG(BCM2835_IRQ_FIQ_CTRL) = 0;
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return RTEMS_SUCCESSFUL;
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}
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@@ -26,11 +26,45 @@
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#include <bsp/start.h>
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#include <bsp/raspberrypi.h>
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#include <bsp/mm.h>
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#include <libcpu/arm-cp15.h>
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void BSP_START_TEXT_SECTION bsp_start_hook_0(void)
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{
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}
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uint32_t sctlr_val;
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sctlr_val = arm_cp15_get_control();
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/*
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* Current U-boot loader seems to start kernel image
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* with I and D caches on and MMU enabled.
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* If RTEMS application image finds that cache is on
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* during startup then disable caches.
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*/
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if (sctlr_val & (ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M)) {
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if (sctlr_val & (ARM_CP15_CTRL_C | ARM_CP15_CTRL_M)) {
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/*
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* If the data cache is on then ensure that it is clean
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* before switching off to be extra carefull.
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*/
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arm_cp15_drain_write_buffer();
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arm_cp15_data_cache_clean_and_invalidate();
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}
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arm_cp15_flush_prefetch_buffer();
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sctlr_val &= ~(ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M | ARM_CP15_CTRL_A);
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arm_cp15_set_control(sctlr_val);
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arm_cp15_tlb_invalidate();
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arm_cp15_flush_prefetch_buffer();
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arm_cp15_data_cache_invalidate();
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arm_cp15_instruction_cache_invalidate();
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}
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/* Clear Translation Table Base Control Register */
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arm_cp15_set_translation_table_base_control_register(0);
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/* Clear Secure or Non-secure Vector Base Address Register */
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arm_cp15_set_vector_base_address(0);
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}
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void BSP_START_TEXT_SECTION bsp_start_hook_1(void)
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{
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