mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
synced 2025-12-05 15:15:44 +00:00
2001-03-14 Joel Sherrill <joel@OARcorp.com>
* cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h: Removed unused variable _CPU_Thread_dispatch_pointer and cleaned numerous comments.
This commit is contained in:
Joel Sherrill
@@ -1,3 +1,9 @@
|
||||
2001-03-14 Joel Sherrill <joel@OARcorp.com>
|
||||
|
||||
* cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
|
||||
Removed unused variable _CPU_Thread_dispatch_pointer
|
||||
and cleaned numerous comments.
|
||||
|
||||
2001-03-13 Joel Sherrill <joel@OARcorp.com>
|
||||
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||||
* cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
|
||||
|
||||
@@ -2,7 +2,15 @@
|
||||
* Mips CPU Dependent Source
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||||
*
|
||||
* Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
|
||||
* Joel Sherrill <joel@OARcorp.com>.
|
||||
* Joel Sherrill <joel@OARcorp.com>.
|
||||
*
|
||||
* These changes made the code conditional on standard cpp predefines,
|
||||
* merged the mips1 and mips3 code sequences as much as possible,
|
||||
* and moved some of the assembly code to C. Alan did much of the
|
||||
* initial analysis and rework. Joel took over from there and
|
||||
* wrote the JMR3904 BSP so this could be tested. Joel also
|
||||
* added the new interrupt vectoring support in libcpu and
|
||||
* tried to better support the various interrupt controllers.
|
||||
*
|
||||
* Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
|
||||
* COPYRIGHT (c) 1996 by Transition Networks Inc.
|
||||
@@ -18,9 +26,7 @@
|
||||
* Transition Networks makes no representations about the
|
||||
* suitability of this software for any purpose.
|
||||
*
|
||||
* Derived from c/src/exec/score/cpu/no_cpu/cpu.c:
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* COPYRIGHT (c) 1989-2001.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
@@ -30,13 +36,6 @@
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
/*
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||||
* Rather than deleting this, it is commented out to (hopefully) help
|
||||
* the submitter send updates.
|
||||
*
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||||
* static char _sccsid[] = "@(#)cpu.c 08/20/96 1.5\n";
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||||
*/
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||||
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#include <rtems/system.h>
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#include <rtems/score/isr.h>
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#include <rtems/score/wkspace.h>
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@@ -57,19 +56,6 @@ void _CPU_Initialize(
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void (*thread_dispatch) /* ignored on this CPU */
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)
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{
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/*
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* The thread_dispatch argument is the address of the entry point
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* for the routine called at the end of an ISR once it has been
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* decided a context switch is necessary. On some compilation
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* systems it is difficult to call a high-level language routine
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* from assembly. This allows us to trick these systems.
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*
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* If you encounter this problem save the entry point in a CPU
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* dependent variable.
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*/
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_CPU_Thread_dispatch_pointer = thread_dispatch;
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/*
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* If there is not an easy way to initialize the FP context
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* during Context_Initialize, then it is usually easier to
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@@ -80,7 +66,6 @@ void _CPU_Initialize(
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/* FP context initialization support goes here */
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_CPU_Table = *cpu_table;
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}
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/*PAGE
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@@ -129,7 +114,6 @@ void _CPU_ISR_Set_level( unsigned32 new_level )
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}
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#elif __mips == 1
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if ( (new_level & SR_IEC) == (sr & SR_IEC) )
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return;
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@@ -148,6 +132,14 @@ void _CPU_ISR_Set_level( unsigned32 new_level )
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/*PAGE
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*
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* _CPU_ISR_install_raw_handler
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*
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* Input parameters:
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* vector - interrupt vector number
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* old_handler - former ISR for this vector number
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* new_handler - replacement ISR for this vector number
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*
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* Output parameters: NONE
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*
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*/
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void _CPU_ISR_install_raw_handler(
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@@ -159,12 +151,10 @@ void _CPU_ISR_install_raw_handler(
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/*
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* This is where we install the interrupt handler into the "raw" interrupt
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* table used by the CPU to dispatch interrupt handlers.
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*
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* Because all interrupts are vectored through the same exception handler
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* this is not necessary on thi sport.
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*/
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/* Q: This will become necessary for Non IDT/Sim use...*/
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#if 0 /* not necessary */
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/* use IDT/Sim to set interrupt vector. Needed to co-exist with debugger. */
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add_ext_int_func( vector, new_handler );
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#endif
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}
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||||
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/*PAGE
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@@ -246,13 +236,3 @@ void _CPU_Thread_Idle_body( void )
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#error "IDLE: __mips not set to 1 or 3"
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#endif
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}
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extern void mips_break( int error );
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#include <stdio.h>
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void mips_fatal_error( int error )
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{
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printf("fatal error 0x%x %d\n",error,error);
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mips_break( error );
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}
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@@ -1,14 +1,22 @@
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/* cpu.h
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/*
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* Mips CPU Dependent Header File
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*
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||||
* Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
|
||||
* Joel Sherrill <joel@OARcorp.com>.
|
||||
*
|
||||
* These changes made the code conditional on standard cpp predefines,
|
||||
* merged the mips1 and mips3 code sequences as much as possible,
|
||||
* and moved some of the assembly code to C. Alan did much of the
|
||||
* initial analysis and rework. Joel took over from there and
|
||||
* wrote the JMR3904 BSP so this could be tested. Joel also
|
||||
* added the new interrupt vectoring support in libcpu and
|
||||
* tried to better support the various interrupt controllers.
|
||||
*
|
||||
* Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
|
||||
* COPYRIGHT (c) 1996 by Transition Networks Inc.
|
||||
*
|
||||
* This include file contains information pertaining to the IDT 4650
|
||||
* processor.
|
||||
*
|
||||
* Author: Craig Lebakken <craigl@transition.com>
|
||||
*
|
||||
* COPYRIGHT (c) 1996 by Transition Networks Inc.
|
||||
*
|
||||
* To anyone who acknowledges that this file is provided "AS IS"
|
||||
* without any express or implied warranty:
|
||||
* To anyone who acknowledges that this file is provided "AS IS"
|
||||
* without any express or implied warranty:
|
||||
* permission to use, copy, modify, and distribute this file
|
||||
* for any purpose is hereby granted without fee, provided that
|
||||
* the above copyright notice and this notice appears in all
|
||||
@@ -18,9 +26,7 @@
|
||||
* Transition Networks makes no representations about the suitability
|
||||
* of this software for any purpose.
|
||||
*
|
||||
* Derived from c/src/exec/score/cpu/no_cpu/cpu.h:
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* COPYRIGHT (c) 1989-2001.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
@@ -29,7 +35,6 @@
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
/* @(#)cpu.h 08/29/96 1.7 */
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||||
|
||||
#ifndef __CPU_h
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#define __CPU_h
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@@ -490,9 +495,12 @@ SCORE_EXTERN void *_CPU_Interrupt_stack_high;
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* and contains the address of the routine _Thread_Dispatch. This
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* can make it easier to invoke that routine at the end of the interrupt
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* sequence (if a dispatch is necessary).
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*/
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*
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SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)();
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*
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* NOTE: Not needed on this port.
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*/
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/*
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* Nothing prevents the porter from declaring more CPU specific variables.
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@@ -740,16 +748,15 @@ void _CPU_ISR_Set_level( unsigned32 ); /* in cpu.c */
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* halts/stops the CPU.
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*/
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void mips_fatal_error ( int error );
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#define _CPU_Fatal_halt( _error ) \
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do { \
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unsigned int _level; \
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_CPU_ISR_Disable(_level); \
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mips_fatal_error(_error); \
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loop: goto loop; \
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} while (0)
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|
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/* end of Fatal Error manager macros */
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extern void mips_break( int error );
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/* Bitfield handler macros */
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|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/* mips.h
|
||||
*
|
||||
* COPYRIGHT (c) 1989-2000.
|
||||
* COPYRIGHT (c) 1989-2001.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
|
||||
@@ -1,24 +1,9 @@
|
||||
/* mipstypes.h
|
||||
*
|
||||
* This include file contains type definitions pertaining to the IDT 4650
|
||||
* This include file contains type definitions pertaining to the MIPS
|
||||
* processor family.
|
||||
*
|
||||
* Author: Craig Lebakken <craigl@transition.com>
|
||||
*
|
||||
* COPYRIGHT (c) 1996 by Transition Networks Inc.
|
||||
*
|
||||
* To anyone who acknowledges that this file is provided "AS IS"
|
||||
* without any express or implied warranty:
|
||||
* permission to use, copy, modify, and distribute this file
|
||||
* for any purpose is hereby granted without fee, provided that
|
||||
* the above copyright notice and this notice appears in all
|
||||
* copies, and that the name of Transition Networks not be used in
|
||||
* advertising or publicity pertaining to distribution of the
|
||||
* software without specific, written prior permission.
|
||||
* Transition Networks makes no representations about the suitability
|
||||
* of this software for any purpose.
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* COPYRIGHT (c) 1989-2001.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
|
||||
@@ -1,24 +1,9 @@
|
||||
/* mipstypes.h
|
||||
*
|
||||
* This include file contains type definitions pertaining to the IDT 4650
|
||||
* This include file contains type definitions pertaining to the MIPS
|
||||
* processor family.
|
||||
*
|
||||
* Author: Craig Lebakken <craigl@transition.com>
|
||||
*
|
||||
* COPYRIGHT (c) 1996 by Transition Networks Inc.
|
||||
*
|
||||
* To anyone who acknowledges that this file is provided "AS IS"
|
||||
* without any express or implied warranty:
|
||||
* permission to use, copy, modify, and distribute this file
|
||||
* for any purpose is hereby granted without fee, provided that
|
||||
* the above copyright notice and this notice appears in all
|
||||
* copies, and that the name of Transition Networks not be used in
|
||||
* advertising or publicity pertaining to distribution of the
|
||||
* software without specific, written prior permission.
|
||||
* Transition Networks makes no representations about the suitability
|
||||
* of this software for any purpose.
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* COPYRIGHT (c) 1989-2001.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
|
||||
@@ -1,3 +1,9 @@
|
||||
2001-03-14 Joel Sherrill <joel@OARcorp.com>
|
||||
|
||||
* cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
|
||||
Removed unused variable _CPU_Thread_dispatch_pointer
|
||||
and cleaned numerous comments.
|
||||
|
||||
2001-03-13 Joel Sherrill <joel@OARcorp.com>
|
||||
|
||||
* cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
|
||||
|
||||
@@ -2,7 +2,15 @@
|
||||
* Mips CPU Dependent Source
|
||||
*
|
||||
* Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
|
||||
* Joel Sherrill <joel@OARcorp.com>.
|
||||
* Joel Sherrill <joel@OARcorp.com>.
|
||||
*
|
||||
* These changes made the code conditional on standard cpp predefines,
|
||||
* merged the mips1 and mips3 code sequences as much as possible,
|
||||
* and moved some of the assembly code to C. Alan did much of the
|
||||
* initial analysis and rework. Joel took over from there and
|
||||
* wrote the JMR3904 BSP so this could be tested. Joel also
|
||||
* added the new interrupt vectoring support in libcpu and
|
||||
* tried to better support the various interrupt controllers.
|
||||
*
|
||||
* Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
|
||||
* COPYRIGHT (c) 1996 by Transition Networks Inc.
|
||||
@@ -18,9 +26,7 @@
|
||||
* Transition Networks makes no representations about the
|
||||
* suitability of this software for any purpose.
|
||||
*
|
||||
* Derived from c/src/exec/score/cpu/no_cpu/cpu.c:
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* COPYRIGHT (c) 1989-2001.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
@@ -30,13 +36,6 @@
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
/*
|
||||
* Rather than deleting this, it is commented out to (hopefully) help
|
||||
* the submitter send updates.
|
||||
*
|
||||
* static char _sccsid[] = "@(#)cpu.c 08/20/96 1.5\n";
|
||||
*/
|
||||
|
||||
#include <rtems/system.h>
|
||||
#include <rtems/score/isr.h>
|
||||
#include <rtems/score/wkspace.h>
|
||||
@@ -57,19 +56,6 @@ void _CPU_Initialize(
|
||||
void (*thread_dispatch) /* ignored on this CPU */
|
||||
)
|
||||
{
|
||||
/*
|
||||
* The thread_dispatch argument is the address of the entry point
|
||||
* for the routine called at the end of an ISR once it has been
|
||||
* decided a context switch is necessary. On some compilation
|
||||
* systems it is difficult to call a high-level language routine
|
||||
* from assembly. This allows us to trick these systems.
|
||||
*
|
||||
* If you encounter this problem save the entry point in a CPU
|
||||
* dependent variable.
|
||||
*/
|
||||
|
||||
_CPU_Thread_dispatch_pointer = thread_dispatch;
|
||||
|
||||
/*
|
||||
* If there is not an easy way to initialize the FP context
|
||||
* during Context_Initialize, then it is usually easier to
|
||||
@@ -80,7 +66,6 @@ void _CPU_Initialize(
|
||||
/* FP context initialization support goes here */
|
||||
|
||||
_CPU_Table = *cpu_table;
|
||||
|
||||
}
|
||||
|
||||
/*PAGE
|
||||
@@ -129,7 +114,6 @@ void _CPU_ISR_Set_level( unsigned32 new_level )
|
||||
}
|
||||
|
||||
#elif __mips == 1
|
||||
|
||||
if ( (new_level & SR_IEC) == (sr & SR_IEC) )
|
||||
return;
|
||||
|
||||
@@ -148,6 +132,14 @@ void _CPU_ISR_Set_level( unsigned32 new_level )
|
||||
/*PAGE
|
||||
*
|
||||
* _CPU_ISR_install_raw_handler
|
||||
*
|
||||
* Input parameters:
|
||||
* vector - interrupt vector number
|
||||
* old_handler - former ISR for this vector number
|
||||
* new_handler - replacement ISR for this vector number
|
||||
*
|
||||
* Output parameters: NONE
|
||||
*
|
||||
*/
|
||||
|
||||
void _CPU_ISR_install_raw_handler(
|
||||
@@ -159,12 +151,10 @@ void _CPU_ISR_install_raw_handler(
|
||||
/*
|
||||
* This is where we install the interrupt handler into the "raw" interrupt
|
||||
* table used by the CPU to dispatch interrupt handlers.
|
||||
*
|
||||
* Because all interrupts are vectored through the same exception handler
|
||||
* this is not necessary on thi sport.
|
||||
*/
|
||||
/* Q: This will become necessary for Non IDT/Sim use...*/
|
||||
#if 0 /* not necessary */
|
||||
/* use IDT/Sim to set interrupt vector. Needed to co-exist with debugger. */
|
||||
add_ext_int_func( vector, new_handler );
|
||||
#endif
|
||||
}
|
||||
|
||||
/*PAGE
|
||||
@@ -246,13 +236,3 @@ void _CPU_Thread_Idle_body( void )
|
||||
#error "IDLE: __mips not set to 1 or 3"
|
||||
#endif
|
||||
}
|
||||
|
||||
extern void mips_break( int error );
|
||||
|
||||
#include <stdio.h>
|
||||
|
||||
void mips_fatal_error( int error )
|
||||
{
|
||||
printf("fatal error 0x%x %d\n",error,error);
|
||||
mips_break( error );
|
||||
}
|
||||
|
||||
@@ -1,14 +1,22 @@
|
||||
/* cpu.h
|
||||
/*
|
||||
* Mips CPU Dependent Header File
|
||||
*
|
||||
* Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
|
||||
* Joel Sherrill <joel@OARcorp.com>.
|
||||
*
|
||||
* These changes made the code conditional on standard cpp predefines,
|
||||
* merged the mips1 and mips3 code sequences as much as possible,
|
||||
* and moved some of the assembly code to C. Alan did much of the
|
||||
* initial analysis and rework. Joel took over from there and
|
||||
* wrote the JMR3904 BSP so this could be tested. Joel also
|
||||
* added the new interrupt vectoring support in libcpu and
|
||||
* tried to better support the various interrupt controllers.
|
||||
*
|
||||
* Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
|
||||
* COPYRIGHT (c) 1996 by Transition Networks Inc.
|
||||
*
|
||||
* This include file contains information pertaining to the IDT 4650
|
||||
* processor.
|
||||
*
|
||||
* Author: Craig Lebakken <craigl@transition.com>
|
||||
*
|
||||
* COPYRIGHT (c) 1996 by Transition Networks Inc.
|
||||
*
|
||||
* To anyone who acknowledges that this file is provided "AS IS"
|
||||
* without any express or implied warranty:
|
||||
* To anyone who acknowledges that this file is provided "AS IS"
|
||||
* without any express or implied warranty:
|
||||
* permission to use, copy, modify, and distribute this file
|
||||
* for any purpose is hereby granted without fee, provided that
|
||||
* the above copyright notice and this notice appears in all
|
||||
@@ -18,9 +26,7 @@
|
||||
* Transition Networks makes no representations about the suitability
|
||||
* of this software for any purpose.
|
||||
*
|
||||
* Derived from c/src/exec/score/cpu/no_cpu/cpu.h:
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* COPYRIGHT (c) 1989-2001.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
@@ -29,7 +35,6 @@
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
/* @(#)cpu.h 08/29/96 1.7 */
|
||||
|
||||
#ifndef __CPU_h
|
||||
#define __CPU_h
|
||||
@@ -490,9 +495,12 @@ SCORE_EXTERN void *_CPU_Interrupt_stack_high;
|
||||
* and contains the address of the routine _Thread_Dispatch. This
|
||||
* can make it easier to invoke that routine at the end of the interrupt
|
||||
* sequence (if a dispatch is necessary).
|
||||
*/
|
||||
*
|
||||
|
||||
SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)();
|
||||
*
|
||||
* NOTE: Not needed on this port.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Nothing prevents the porter from declaring more CPU specific variables.
|
||||
@@ -740,16 +748,15 @@ void _CPU_ISR_Set_level( unsigned32 ); /* in cpu.c */
|
||||
* halts/stops the CPU.
|
||||
*/
|
||||
|
||||
void mips_fatal_error ( int error );
|
||||
|
||||
#define _CPU_Fatal_halt( _error ) \
|
||||
do { \
|
||||
unsigned int _level; \
|
||||
_CPU_ISR_Disable(_level); \
|
||||
mips_fatal_error(_error); \
|
||||
loop: goto loop; \
|
||||
} while (0)
|
||||
|
||||
/* end of Fatal Error manager macros */
|
||||
|
||||
extern void mips_break( int error );
|
||||
|
||||
/* Bitfield handler macros */
|
||||
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/* mips.h
|
||||
*
|
||||
* COPYRIGHT (c) 1989-2000.
|
||||
* COPYRIGHT (c) 1989-2001.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
|
||||
@@ -1,24 +1,9 @@
|
||||
/* mipstypes.h
|
||||
*
|
||||
* This include file contains type definitions pertaining to the IDT 4650
|
||||
* This include file contains type definitions pertaining to the MIPS
|
||||
* processor family.
|
||||
*
|
||||
* Author: Craig Lebakken <craigl@transition.com>
|
||||
*
|
||||
* COPYRIGHT (c) 1996 by Transition Networks Inc.
|
||||
*
|
||||
* To anyone who acknowledges that this file is provided "AS IS"
|
||||
* without any express or implied warranty:
|
||||
* permission to use, copy, modify, and distribute this file
|
||||
* for any purpose is hereby granted without fee, provided that
|
||||
* the above copyright notice and this notice appears in all
|
||||
* copies, and that the name of Transition Networks not be used in
|
||||
* advertising or publicity pertaining to distribution of the
|
||||
* software without specific, written prior permission.
|
||||
* Transition Networks makes no representations about the suitability
|
||||
* of this software for any purpose.
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1999.
|
||||
* COPYRIGHT (c) 1989-2001.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
|
||||
Reference in New Issue
Block a user