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2001-02-05 Joel Sherrill <joel@OARcorp.com>

Browse Source 
* cpu_asm.S: Enhanced to save/restore more registers on
	exceptions.
	* rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
	register individually and document when it is saved.
	* idtcpu.h: Added constants for the coprocessor 1 registers
	revision and status.
This commit is contained in:
Joel Sherrill
2002-02-05 21:04:39 +00:00
parent 7d7e9fbb6a
commit a37b8f95b7
9 changed files with 457 additions and 32 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
c/src/exec/score/cpu/mips/ChangeLog
View File

@@ -1,3 +1,12 @@
2001-02-05 Joel Sherrill <joel@OARcorp.com>
* cpu_asm.S: Enhanced to save/restore more registers on
exceptions.
* rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
register individually and document when it is saved.
* idtcpu.h: Added constants for the coprocessor 1 registers
revision and status.
2001-02-05 Joel Sherrill <joel@OARcorp.com>
* rtems/Makefile.am, rtems/score/Makefile.am: Removed again.

88
c/src/exec/score/cpu/mips/cpu_asm.S
View File

@@ -30,8 +30,10 @@
* 2002: Greg Menke <gregory.menke@gsfc.nasa.gov>, overhauled cpu_asm.S,
* cpu.c and cpu.h to manage FP vs int only tasks, interrupt levels
* and deferred FP contexts.
* 2002: Joel Sherrill <joel@OARcorp.com> enhanced the exception processing
* by increasing the amount of context saved/restored.
*
* COPYRIGHT (c) 1989-2000.
* COPYRIGHT (c) 1989-2002.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
@@ -196,6 +198,8 @@ FRAME(_CPU_Context_save_fp,sp,0,ra)
ld a1,(a0)
NOP
.globl _CPU_Context_save_fp_from_exception
_CPU_Context_save_fp_from_exception:
swc1 $f0,FP0_OFFSET*F_SZ(a1)
swc1 $f1,FP1_OFFSET*F_SZ(a1)
swc1 $f2,FP2_OFFSET*F_SZ(a1)
@@ -269,6 +273,8 @@ FRAME(_CPU_Context_restore_fp,sp,0,ra)
ld a1,(a0)
NOP
.globl _CPU_Context_restore_fp_from_exception
_CPU_Context_restore_fp_from_exception:
lwc1 $f0,FP0_OFFSET*4(a1)
lwc1 $f1,FP1_OFFSET*4(a1)
lwc1 $f2,FP2_OFFSET*4(a1)
@@ -534,12 +540,84 @@ FRAME(_ISR_Handler,sp,0,ra)
_ISR_Handler_Exception:
/* if we return from the exception, it is assumed nothing */
/* bad is going on and we can continue to run normally */
/* If we return from the exception, it is assumed nothing
* bad is going on and we can continue to run normally.
* But we want to save the entire CPU context so exception
* handlers can look at it and change it.
*
* NOTE: This is the path the debugger stub will take.
*/
STREG sp,SP_OFFSET*R_SZ(sp) /* save sp */
STREG s0,S0_OFFSET*R_SZ(sp) /* save s0 - s7 */
STREG s1,S1_OFFSET*R_SZ(sp)
STREG s2,S2_OFFSET*R_SZ(sp)
STREG s3,S3_OFFSET*R_SZ(sp)
STREG s4,S4_OFFSET*R_SZ(sp)
STREG s5,S5_OFFSET*R_SZ(sp)
STREG s6,S6_OFFSET*R_SZ(sp)
STREG s7,S7_OFFSET*R_SZ(sp)
MFC0 k0,C0_CAUSE /* save cause */
NOP
STREG k0,R_CAUSE*R_SZ(sp)
/* CP0 special registers */
MFC0 t0,C0_BADVADDR
nop
STREG t0,R_BADVADDR*R_SZ(sp)
#if ( CPU_HARDWARE_FP == TRUE )
MFC0 t0,C0_SR /* FPU is enabled, save state */
srl t0,t0,16
andi t0,t0,(SR_CU1 >> 16)
beqz t0, 1f
nop
la a1,R_F0*R_SZ(sp)
jal _CPU_Context_save_fp_from_exception
nop
MFC1 t0,C1_REVISION
MFC1 t1,C1_STATUS
STREG t0,R_FEIR*R_SZ(sp)
STREG t1,R_FCSR*R_SZ(sp)
1:
#endif
move a0,sp
jal mips_vector_exceptions
nop
#if ( CPU_HARDWARE_FP == TRUE )
MFC0 t0,C0_SR /* FPU is enabled, restore state */
srl t0,t0,16
andi t0,t0,(SR_CU1 >> 16)
beqz t0, 2f
nop
la a1,R_F0*R_SZ(sp)
jal _CPU_Context_restore_fp_from_exception
nop
LDREG t0,R_FEIR*R_SZ(sp)
LDREG t1,R_FCSR*R_SZ(sp)
MTC1 t0,C1_REVISION
MTC1 t1,C1_STATUS
2:
#endif
LDREG s0,S0_OFFSET*R_SZ(sp) /* restore s0 - s7 */
LDREG s1,S1_OFFSET*R_SZ(sp)
LDREG s2,S2_OFFSET*R_SZ(sp)
LDREG s3,S3_OFFSET*R_SZ(sp)
LDREG s4,S4_OFFSET*R_SZ(sp)
LDREG s5,S5_OFFSET*R_SZ(sp)
LDREG s6,S6_OFFSET*R_SZ(sp)
LDREG s7,S7_OFFSET*R_SZ(sp)
/* do NOT restore the sp as this could mess up the world */
/* do NOT restore the cause as this could mess up the world */
j _ISR_Handler_exit
nop
@@ -746,7 +824,7 @@ ENDFRAME(_ISR_Handler)
FRAME(mips_break,sp,0,ra)
#if 1
break 0x0
break 0x0
j mips_break
#else
j ra

3
c/src/exec/score/cpu/mips/idtcpu.h
View File

@@ -427,6 +427,9 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
#define C0_ERRPC $30 /* cache error pc */
#endif
#define C1_REVISION $0
#define C1_STATUS $31
#endif XDS
#ifdef R4650

143
c/src/exec/score/cpu/mips/rtems/score/cpu.h
View File

@@ -427,25 +427,146 @@ typedef struct {
#endif
} Context_Control_fp;
/*
This struct reflects the stack frame employed in ISR_Handler. Note
that the ISR routine doesn't save all registers to this frame, so
cpu_asm.S should be consulted to see if the registers you're
interested in are actually there.
*/
* This struct reflects the stack frame employed in ISR_Handler. Note
* that the ISR routine save some of the registers to this frame for
* all interrupts and exceptions. Other registers are saved only on
* exceptions, while others are not touched at all. The untouched
* registers are not normally disturbed by high-level language
* programs so they can be accessed when required.
*
* The registers and their ordering in this struct must directly
* correspond to the layout and ordering of * shown in iregdef.h,
* as cpu_asm.S uses those definitions to fill the stack frame.
* This struct provides access to the stack frame for C code.
*
* Similarly, this structure is used by debugger stubs and exception
* processing routines so be careful when changing the format.
*
* NOTE: The comments with this structure and cpu_asm.S should be kep
* in sync. When in doubt, look in the code to see if the
* registers you're interested in are actually treated as expected.
*/
typedef struct
{
__MIPS_REGISTER_TYPE r0; /* r0 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE at; /* r1 -- saved always */
__MIPS_REGISTER_TYPE v0; /* r2 -- saved always */
__MIPS_REGISTER_TYPE v1; /* r3 -- saved always */
__MIPS_REGISTER_TYPE a0; /* r4 -- saved always */
__MIPS_REGISTER_TYPE a1; /* r5 -- saved always */
__MIPS_REGISTER_TYPE a2; /* r6 -- saved always */
__MIPS_REGISTER_TYPE a3; /* r7 -- saved always */
__MIPS_REGISTER_TYPE t0; /* r8 -- saved always */
__MIPS_REGISTER_TYPE t1; /* r9 -- saved always */
__MIPS_REGISTER_TYPE t2; /* r10 -- saved always */
__MIPS_REGISTER_TYPE t3; /* r11 -- saved always */
__MIPS_REGISTER_TYPE t4; /* r12 -- saved always */
__MIPS_REGISTER_TYPE t5; /* r13 -- saved always */
__MIPS_REGISTER_TYPE t6; /* r14 -- saved always */
__MIPS_REGISTER_TYPE t7; /* r15 -- saved always */
__MIPS_REGISTER_TYPE s0; /* r16 -- saved on exceptions */
__MIPS_REGISTER_TYPE s1; /* r17 -- saved on exceptions */
__MIPS_REGISTER_TYPE s2; /* r18 -- saved on exceptions */
__MIPS_REGISTER_TYPE s3; /* r19 -- saved on exceptions */
__MIPS_REGISTER_TYPE s4; /* r20 -- saved on exceptions */
__MIPS_REGISTER_TYPE s5; /* r21 -- saved on exceptions */
__MIPS_REGISTER_TYPE s6; /* r22 -- saved on exceptions */
__MIPS_REGISTER_TYPE s7; /* r23 -- saved on exceptions */
__MIPS_REGISTER_TYPE t8; /* r24 -- saved always */
__MIPS_REGISTER_TYPE t9; /* r25 -- saved always */
__MIPS_REGISTER_TYPE k0; /* r26 -- NOT FILLED IN, kernel tmp reg */
__MIPS_REGISTER_TYPE k1; /* r27 -- NOT FILLED IN, kernel tmp reg */
__MIPS_REGISTER_TYPE gp; /* r28 -- saved always */
__MIPS_REGISTER_TYPE sp; /* r29 -- saved on exceptions NOT RESTORED */
__MIPS_REGISTER_TYPE fp; /* r30 -- saved always */
__MIPS_REGISTER_TYPE ra; /* r31 -- saved always */
__MIPS_FPU_REGISTER_TYPE f0; /* r32 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f1; /* r33 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f2; /* r34 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f3; /* r35 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f4; /* r36 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f5; /* r37 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f6; /* r38 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f7; /* r39 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f8; /* r40 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f9; /* r41 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f10; /* r42 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f11; /* r43 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f12; /* r44 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f13; /* r45 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f14; /* r46 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f15; /* r47 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f16; /* r48 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f17; /* r49 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f18; /* r50 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f19; /* r51 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f20; /* r52 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f21; /* r53 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f22; /* r54 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f23; /* r55 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f24; /* r56 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f25; /* r57 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f26; /* r58 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f27; /* r59 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f28; /* r60 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f29; /* r61 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f30; /* r62 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f31; /* r63 -- saved if FP enabled */
__MIPS_REGISTER_TYPE epc; /* r64 -- saved always, read-only register */
/* but logically restored */
__MIPS_REGISTER_TYPE mdhi; /* r65 -- saved always */
__MIPS_REGISTER_TYPE mdlo; /* r66 -- saved always */
__MIPS_REGISTER_TYPE sr; /* r67 -- saved always, some bits are */
/* manipulated per-thread */
__MIPS_REGISTER_TYPE cause; /* r68 -- saved on exceptions NOT restored */
__MIPS_REGISTER_TYPE tlbhi; /* r69 - NOT FILLED IN, doesn't exist on */
/* all MIPS CPUs (at least MGV) */
#if __mips == 1
unsigned int regs[80];
__MIPS_REGISTER_TYPE tlblo; /* r70 - NOT FILLED IN, doesn't exist on */
/* all MIPS CPUs (at least MGV) */
#endif
#if __mips == 3
unsigned int regs[94];
__MIPS_REGISTER_TYPE tlblo0; /* r70 - NOT FILLED IN, doesn't exist on */
/* all MIPS CPUs (at least MGV) */
#endif
__MIPS_REGISTER_TYPE badvaddr; /* r71 -- saved on exceptions, read-only */
__MIPS_REGISTER_TYPE inx; /* r72 -- NOT FILLED IN, doesn't exist on */
/* all MIPS CPUs (at least MGV) */
__MIPS_REGISTER_TYPE rand; /* r73 -- NOT FILLED IN, doesn't exist on */
/* all MIPS CPUs (at least MGV) */
__MIPS_REGISTER_TYPE ctxt; /* r74 -- NOT FILLED IN, doesn't exist on */
/* all MIPS CPUs (at least MGV) */
__MIPS_REGISTER_TYPE exctype; /* r75 -- NOT FILLED IN (not enough info) */
__MIPS_REGISTER_TYPE mode; /* r76 -- NOT FILLED IN (not enough info) */
__MIPS_REGISTER_TYPE prid; /* r77 -- NOT FILLED IN (not need to do so) */
__MIPS_REGISTER_TYPE fcsr; /* r78 -- saved on exceptions */
/* (oddly not documented on MGV) */
__MIPS_REGISTER_TYPE feir; /* r79 -- saved on exceptions */
/* (oddly not documented on MGV) */
/* end of __mips == 1 so NREGS == 80 */
#if __mips == 3
__MIPS_REGISTER_TYPE tlblo1; /* r80 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE pagemask; /* r81 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE wired; /* r82 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE count; /* r83 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE compare; /* r84 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE config; /* r85 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE lladdr; /* r86 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE watchlo; /* r87 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE watchhi; /* r88 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE ecc; /* r89 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE cacheerr; /* r90 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE taglo; /* r91 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE taghi; /* r92 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE errpc; /* r93 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE xctxt; /* r94 -- NOT FILLED IN */
/* end of __mips == 3 so NREGS == 94 */
#endif
} CPU_Interrupt_frame;

9
cpukit/score/cpu/mips/ChangeLog
View File

@@ -1,3 +1,12 @@
2001-02-05 Joel Sherrill <joel@OARcorp.com>
* cpu_asm.S: Enhanced to save/restore more registers on
exceptions.
* rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
register individually and document when it is saved.
* idtcpu.h: Added constants for the coprocessor 1 registers
revision and status.
2001-02-05 Joel Sherrill <joel@OARcorp.com>
* rtems/Makefile.am, rtems/score/Makefile.am: Removed again.

88
cpukit/score/cpu/mips/cpu_asm.S
View File

@@ -30,8 +30,10 @@
* 2002: Greg Menke <gregory.menke@gsfc.nasa.gov>, overhauled cpu_asm.S,
* cpu.c and cpu.h to manage FP vs int only tasks, interrupt levels
* and deferred FP contexts.
* 2002: Joel Sherrill <joel@OARcorp.com> enhanced the exception processing
* by increasing the amount of context saved/restored.
*
* COPYRIGHT (c) 1989-2000.
* COPYRIGHT (c) 1989-2002.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
@@ -196,6 +198,8 @@ FRAME(_CPU_Context_save_fp,sp,0,ra)
ld a1,(a0)
NOP
.globl _CPU_Context_save_fp_from_exception
_CPU_Context_save_fp_from_exception:
swc1 $f0,FP0_OFFSET*F_SZ(a1)
swc1 $f1,FP1_OFFSET*F_SZ(a1)
swc1 $f2,FP2_OFFSET*F_SZ(a1)
@@ -269,6 +273,8 @@ FRAME(_CPU_Context_restore_fp,sp,0,ra)
ld a1,(a0)
NOP
.globl _CPU_Context_restore_fp_from_exception
_CPU_Context_restore_fp_from_exception:
lwc1 $f0,FP0_OFFSET*4(a1)
lwc1 $f1,FP1_OFFSET*4(a1)
lwc1 $f2,FP2_OFFSET*4(a1)
@@ -534,12 +540,84 @@ FRAME(_ISR_Handler,sp,0,ra)
_ISR_Handler_Exception:
/* if we return from the exception, it is assumed nothing */
/* bad is going on and we can continue to run normally */
/* If we return from the exception, it is assumed nothing
* bad is going on and we can continue to run normally.
* But we want to save the entire CPU context so exception
* handlers can look at it and change it.
*
* NOTE: This is the path the debugger stub will take.
*/
STREG sp,SP_OFFSET*R_SZ(sp) /* save sp */
STREG s0,S0_OFFSET*R_SZ(sp) /* save s0 - s7 */
STREG s1,S1_OFFSET*R_SZ(sp)
STREG s2,S2_OFFSET*R_SZ(sp)
STREG s3,S3_OFFSET*R_SZ(sp)
STREG s4,S4_OFFSET*R_SZ(sp)
STREG s5,S5_OFFSET*R_SZ(sp)
STREG s6,S6_OFFSET*R_SZ(sp)
STREG s7,S7_OFFSET*R_SZ(sp)
MFC0 k0,C0_CAUSE /* save cause */
NOP
STREG k0,R_CAUSE*R_SZ(sp)
/* CP0 special registers */
MFC0 t0,C0_BADVADDR
nop
STREG t0,R_BADVADDR*R_SZ(sp)
#if ( CPU_HARDWARE_FP == TRUE )
MFC0 t0,C0_SR /* FPU is enabled, save state */
srl t0,t0,16
andi t0,t0,(SR_CU1 >> 16)
beqz t0, 1f
nop
la a1,R_F0*R_SZ(sp)
jal _CPU_Context_save_fp_from_exception
nop
MFC1 t0,C1_REVISION
MFC1 t1,C1_STATUS
STREG t0,R_FEIR*R_SZ(sp)
STREG t1,R_FCSR*R_SZ(sp)
1:
#endif
move a0,sp
jal mips_vector_exceptions
nop
#if ( CPU_HARDWARE_FP == TRUE )
MFC0 t0,C0_SR /* FPU is enabled, restore state */
srl t0,t0,16
andi t0,t0,(SR_CU1 >> 16)
beqz t0, 2f
nop
la a1,R_F0*R_SZ(sp)
jal _CPU_Context_restore_fp_from_exception
nop
LDREG t0,R_FEIR*R_SZ(sp)
LDREG t1,R_FCSR*R_SZ(sp)
MTC1 t0,C1_REVISION
MTC1 t1,C1_STATUS
2:
#endif
LDREG s0,S0_OFFSET*R_SZ(sp) /* restore s0 - s7 */
LDREG s1,S1_OFFSET*R_SZ(sp)
LDREG s2,S2_OFFSET*R_SZ(sp)
LDREG s3,S3_OFFSET*R_SZ(sp)
LDREG s4,S4_OFFSET*R_SZ(sp)
LDREG s5,S5_OFFSET*R_SZ(sp)
LDREG s6,S6_OFFSET*R_SZ(sp)
LDREG s7,S7_OFFSET*R_SZ(sp)
/* do NOT restore the sp as this could mess up the world */
/* do NOT restore the cause as this could mess up the world */
j _ISR_Handler_exit
nop
@@ -746,7 +824,7 @@ ENDFRAME(_ISR_Handler)
FRAME(mips_break,sp,0,ra)
#if 1
break 0x0
break 0x0
j mips_break
#else
j ra

3
cpukit/score/cpu/mips/idtcpu.h
View File

@@ -427,6 +427,9 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
#define C0_ERRPC $30 /* cache error pc */
#endif
#define C1_REVISION $0
#define C1_STATUS $31
#endif XDS
#ifdef R4650

3
cpukit/score/cpu/mips/rtems/mips/idtcpu.h
View File

@@ -427,6 +427,9 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
#define C0_ERRPC $30 /* cache error pc */
#endif
#define C1_REVISION $0
#define C1_STATUS $31
#endif XDS
#ifdef R4650

143
cpukit/score/cpu/mips/rtems/score/cpu.h
View File

@@ -427,25 +427,146 @@ typedef struct {
#endif
} Context_Control_fp;
/*
This struct reflects the stack frame employed in ISR_Handler. Note
that the ISR routine doesn't save all registers to this frame, so
cpu_asm.S should be consulted to see if the registers you're
interested in are actually there.
*/
* This struct reflects the stack frame employed in ISR_Handler. Note
* that the ISR routine save some of the registers to this frame for
* all interrupts and exceptions. Other registers are saved only on
* exceptions, while others are not touched at all. The untouched
* registers are not normally disturbed by high-level language
* programs so they can be accessed when required.
*
* The registers and their ordering in this struct must directly
* correspond to the layout and ordering of * shown in iregdef.h,
* as cpu_asm.S uses those definitions to fill the stack frame.
* This struct provides access to the stack frame for C code.
*
* Similarly, this structure is used by debugger stubs and exception
* processing routines so be careful when changing the format.
*
* NOTE: The comments with this structure and cpu_asm.S should be kep
* in sync. When in doubt, look in the code to see if the
* registers you're interested in are actually treated as expected.
*/
typedef struct
{
__MIPS_REGISTER_TYPE r0; /* r0 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE at; /* r1 -- saved always */
__MIPS_REGISTER_TYPE v0; /* r2 -- saved always */
__MIPS_REGISTER_TYPE v1; /* r3 -- saved always */
__MIPS_REGISTER_TYPE a0; /* r4 -- saved always */
__MIPS_REGISTER_TYPE a1; /* r5 -- saved always */
__MIPS_REGISTER_TYPE a2; /* r6 -- saved always */
__MIPS_REGISTER_TYPE a3; /* r7 -- saved always */
__MIPS_REGISTER_TYPE t0; /* r8 -- saved always */
__MIPS_REGISTER_TYPE t1; /* r9 -- saved always */
__MIPS_REGISTER_TYPE t2; /* r10 -- saved always */
__MIPS_REGISTER_TYPE t3; /* r11 -- saved always */
__MIPS_REGISTER_TYPE t4; /* r12 -- saved always */
__MIPS_REGISTER_TYPE t5; /* r13 -- saved always */
__MIPS_REGISTER_TYPE t6; /* r14 -- saved always */
__MIPS_REGISTER_TYPE t7; /* r15 -- saved always */
__MIPS_REGISTER_TYPE s0; /* r16 -- saved on exceptions */
__MIPS_REGISTER_TYPE s1; /* r17 -- saved on exceptions */
__MIPS_REGISTER_TYPE s2; /* r18 -- saved on exceptions */
__MIPS_REGISTER_TYPE s3; /* r19 -- saved on exceptions */
__MIPS_REGISTER_TYPE s4; /* r20 -- saved on exceptions */
__MIPS_REGISTER_TYPE s5; /* r21 -- saved on exceptions */
__MIPS_REGISTER_TYPE s6; /* r22 -- saved on exceptions */
__MIPS_REGISTER_TYPE s7; /* r23 -- saved on exceptions */
__MIPS_REGISTER_TYPE t8; /* r24 -- saved always */
__MIPS_REGISTER_TYPE t9; /* r25 -- saved always */
__MIPS_REGISTER_TYPE k0; /* r26 -- NOT FILLED IN, kernel tmp reg */
__MIPS_REGISTER_TYPE k1; /* r27 -- NOT FILLED IN, kernel tmp reg */
__MIPS_REGISTER_TYPE gp; /* r28 -- saved always */
__MIPS_REGISTER_TYPE sp; /* r29 -- saved on exceptions NOT RESTORED */
__MIPS_REGISTER_TYPE fp; /* r30 -- saved always */
__MIPS_REGISTER_TYPE ra; /* r31 -- saved always */
__MIPS_FPU_REGISTER_TYPE f0; /* r32 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f1; /* r33 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f2; /* r34 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f3; /* r35 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f4; /* r36 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f5; /* r37 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f6; /* r38 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f7; /* r39 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f8; /* r40 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f9; /* r41 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f10; /* r42 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f11; /* r43 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f12; /* r44 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f13; /* r45 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f14; /* r46 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f15; /* r47 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f16; /* r48 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f17; /* r49 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f18; /* r50 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f19; /* r51 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f20; /* r52 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f21; /* r53 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f22; /* r54 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f23; /* r55 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f24; /* r56 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f25; /* r57 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f26; /* r58 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f27; /* r59 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f28; /* r60 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f29; /* r61 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f30; /* r62 -- saved if FP enabled */
__MIPS_FPU_REGISTER_TYPE f31; /* r63 -- saved if FP enabled */
__MIPS_REGISTER_TYPE epc; /* r64 -- saved always, read-only register */
/* but logically restored */
__MIPS_REGISTER_TYPE mdhi; /* r65 -- saved always */
__MIPS_REGISTER_TYPE mdlo; /* r66 -- saved always */
__MIPS_REGISTER_TYPE sr; /* r67 -- saved always, some bits are */
/* manipulated per-thread */
__MIPS_REGISTER_TYPE cause; /* r68 -- saved on exceptions NOT restored */
__MIPS_REGISTER_TYPE tlbhi; /* r69 - NOT FILLED IN, doesn't exist on */
/* all MIPS CPUs (at least MGV) */
#if __mips == 1
unsigned int regs[80];
__MIPS_REGISTER_TYPE tlblo; /* r70 - NOT FILLED IN, doesn't exist on */
/* all MIPS CPUs (at least MGV) */
#endif
#if __mips == 3
unsigned int regs[94];
__MIPS_REGISTER_TYPE tlblo0; /* r70 - NOT FILLED IN, doesn't exist on */
/* all MIPS CPUs (at least MGV) */
#endif
__MIPS_REGISTER_TYPE badvaddr; /* r71 -- saved on exceptions, read-only */
__MIPS_REGISTER_TYPE inx; /* r72 -- NOT FILLED IN, doesn't exist on */
/* all MIPS CPUs (at least MGV) */
__MIPS_REGISTER_TYPE rand; /* r73 -- NOT FILLED IN, doesn't exist on */
/* all MIPS CPUs (at least MGV) */
__MIPS_REGISTER_TYPE ctxt; /* r74 -- NOT FILLED IN, doesn't exist on */
/* all MIPS CPUs (at least MGV) */
__MIPS_REGISTER_TYPE exctype; /* r75 -- NOT FILLED IN (not enough info) */
__MIPS_REGISTER_TYPE mode; /* r76 -- NOT FILLED IN (not enough info) */
__MIPS_REGISTER_TYPE prid; /* r77 -- NOT FILLED IN (not need to do so) */
__MIPS_REGISTER_TYPE fcsr; /* r78 -- saved on exceptions */
/* (oddly not documented on MGV) */
__MIPS_REGISTER_TYPE feir; /* r79 -- saved on exceptions */
/* (oddly not documented on MGV) */
/* end of __mips == 1 so NREGS == 80 */
#if __mips == 3
__MIPS_REGISTER_TYPE tlblo1; /* r80 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE pagemask; /* r81 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE wired; /* r82 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE count; /* r83 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE compare; /* r84 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE config; /* r85 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE lladdr; /* r86 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE watchlo; /* r87 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE watchhi; /* r88 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE ecc; /* r89 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE cacheerr; /* r90 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE taglo; /* r91 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE taghi; /* r92 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE errpc; /* r93 -- NOT FILLED IN */
__MIPS_REGISTER_TYPE xctxt; /* r94 -- NOT FILLED IN */
/* end of __mips == 3 so NREGS == 94 */
#endif
} CPU_Interrupt_frame;