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add support for ARM11, reimplement nested interrupts
This commit is contained in:
Thomas Doerfler
@@ -1,3 +1,11 @@
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2009-12-15 Sebastian Huber <sebastian.huber@embedded-brains.de>
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* rtems/score/arm.h: Recognize ARMv5TEJ.
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* arm_exc_interrupt.S: The previous implementation was broken. In
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case of a nested interrupt the link register of the INT mode was not
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properly restored. This lead to a major rewrite. Interrupt
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processing is now done in SVC mode.
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2009-10-01 Joel Sherrill <joel.sherrill@oarcorp.com>
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* rtems/score/arm.h: Recognize ARMv7A.
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@@ -18,114 +18,98 @@
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*/
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/*
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* These two non-volatile registers contain the program status for INT and SVC
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* mode. It is important that they are directly accessible in THUMB
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* instruction mode.
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* The upper EXCHANGE_SIZE bytes of the INT stack area are used for data
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* exchange between INT and SVC mode. Below of this is the actual INT stack.
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* The exchange area is only accessed if INT is disabled.
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*/
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#define MODE_INT r4
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#define MODE_SVC r5
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/*
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* These three non-volatile registers are used to exchange information between
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* INT and SVC mode.
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*/
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#define SCRATCH_0 r6
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#define SCRATCH_1 r7
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#define SCRATCH_2 r8
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#define EXCHANGE_LR r4
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#define EXCHANGE_SPSR r5
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#define EXCHANGE_CPSR r6
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#define EXCHANGE_INT_SP r7
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/* List of scratch registers. They will be saved and restored in INT mode. */
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#define SCRATCH_LIST {SCRATCH_0, SCRATCH_1, SCRATCH_2}
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#define EXCHANGE_LIST {EXCHANGE_LR, EXCHANGE_SPSR, EXCHANGE_CPSR, EXCHANGE_INT_SP}
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#define EXCHANGE_SIZE 16
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/*
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* List of all volatile registers (r0, r1, r2, r3, r12 and lr), registers
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* containing the interrupt context (return address in SCRATCH_0 and saved
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* program status in SCRATCH_1) and non-volatile registers used for modes
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* (MODE_INT and MODE_SVC). They will be saved and restored in SVC mode.
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*/
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#define TASK_CONTEXT_LIST \
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{r0, r1, r2, r3, MODE_INT, MODE_SVC, SCRATCH_0, SCRATCH_1, r12, lr}
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#define CONTEXT_LIST {r0, r1, r2, r3, EXCHANGE_LR, EXCHANGE_SPSR, r12}
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#define CONTEXT_SIZE 28
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/*
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* List of all volatile registers (r0, r1, r2, r3, r12 and lr) and the saved
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* program status (SCRATCH_0 register). They will be saved and restored in INT
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* mode.
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*/
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#define INTERRUPT_CONTEXT_LIST \
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{r0, r1, r2, r3, SCRATCH_0, r12, lr}
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.extern _ISR_Thread_dispatch
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.extern _ISR_Nest_level
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.extern _ISR_Signals_to_thread_executing
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.extern _ISR_Thread_dispatch
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.extern _Thread_Dispatch_disable_level
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.extern bsp_interrupt_dispatch
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.macro SWITCH_FROM_THUMB_TO_ARM
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#ifdef __thumb__
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.align 2
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bx pc
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.arm
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#endif /* __thumb__ */
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.endm
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.macro SWITCH_FROM_ARM_TO_THUMB REG
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#ifdef __thumb__
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add \REG, pc, #1
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bx \REG
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.thumb
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#endif /* __thumb__ */
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.endm
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.arm
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.globl arm_exc_interrupt
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arm_exc_interrupt:
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/* Save scratch registers on INT stack */
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stmdb sp!, SCRATCH_LIST
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/* Save exchange registers to exchange area */
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stmdb sp, EXCHANGE_LIST
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/* Increment interrupt nest level */
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ldr SCRATCH_0, =_ISR_Nest_level
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ldr SCRATCH_1, [SCRATCH_0]
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add SCRATCH_2, SCRATCH_1, #1
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str SCRATCH_2, [SCRATCH_0]
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/* Branch for nested interrupts */
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cmp SCRATCH_1, #0
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bne nested_interrupt_context_save
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/* Move interrupt context and CPSR to scratch registers */
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mov SCRATCH_0, lr
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mrs SCRATCH_1, spsr
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mrs SCRATCH_2, cpsr
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/* Set exchange registers */
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mov EXCHANGE_LR, lr
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mrs EXCHANGE_SPSR, spsr
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mrs EXCHANGE_CPSR, cpsr
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sub EXCHANGE_INT_SP, sp, #EXCHANGE_SIZE
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/* Switch to SVC mode */
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orr SCRATCH_2, SCRATCH_2, #0x1
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msr cpsr_c, SCRATCH_2
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/* Save context on SVC stack */
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stmdb sp!, TASK_CONTEXT_LIST
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/* Save SVC mode program status to non-volatile register */
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mov MODE_SVC, SCRATCH_2
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/* Save INT mode program status to non-volatile register */
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bic MODE_INT, MODE_SVC, #0x1
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/* Switch to INT mode */
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msr cpsr_c, MODE_INT
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/* Restore scratch registers from INT stack */
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ldmia sp!, SCRATCH_LIST
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orr EXCHANGE_CPSR, EXCHANGE_CPSR, #0x1
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msr cpsr, EXCHANGE_CPSR
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/*
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* At this point the INT stack is in the exception entry state and
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* contains no data for us. The context is saved on the SVC stack. We
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* can easily switch modes via the registers MODE_INT and MODE_SVC
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* which are valid through subroutine calls. We can use all volatile
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* registers in both modes. Note that this comment describes the non
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* nested interrupt entry. For a nested interrupt things are
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* different, since we can save everything on the INT stack and there
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* is no need to switch modes.
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* Save context. We save the LR separately because it has to be
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* restored in SVC mode. The other registers can be restored in INT
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* mode.
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*/
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stmdb sp!, CONTEXT_LIST
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stmdb sp!, {lr}
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task_context_save_done:
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/* Remember INT stack pointer */
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mov r1, EXCHANGE_INT_SP
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/* Restore exchange registers from exchange area */
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ldmia r1, EXCHANGE_LIST
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/* Get interrupt nest level */
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ldr r0, =_ISR_Nest_level
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ldr r2, [r0]
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/* Switch stack if necessary and save original stack pointer */
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mov r3, sp
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cmp r2, #0
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moveq sp, r1
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stmdb sp!, {r3}
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/* Switch to THUMB instructions if necessary */
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#ifdef __thumb__
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add r0, pc, #1
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bx r0
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.thumb
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#endif /* __thumb__ */
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SWITCH_FROM_ARM_TO_THUMB r1
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/* Increment thread dispatch disable level */
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/* Increment interrupt nest and thread dispatch disable level */
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ldr r1, =_Thread_Dispatch_disable_level
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ldr r3, [r1]
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add r3, r3, #1
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add r2, #1
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add r3, #1
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str r2, [r0]
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str r3, [r1]
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/* Call BSP dependent interrrupt dispatcher */
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/* Call BSP dependent interrupt dispatcher */
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bl bsp_interrupt_dispatch
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/* Decrement interrupt nest and thread dispatch disable level */
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@@ -133,97 +117,80 @@ task_context_save_done:
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ldr r1, =_Thread_Dispatch_disable_level
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ldr r2, [r0]
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ldr r3, [r1]
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sub r2, r2, #1
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sub r3, r3, #1
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sub r2, #1
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sub r3, #1
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str r2, [r0]
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str r3, [r1]
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/* Switch to ARM instructions if necessary */
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#ifdef __thumb__
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.align 2
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bx pc
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.arm
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#endif /* __thumb__ */
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/* Restore stack pointer */
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SWITCH_FROM_THUMB_TO_ARM
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ldr sp, [sp]
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SWITCH_FROM_ARM_TO_THUMB r0
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/* Branch if we have a nested interrupt */
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cmp r2, #0
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bne nested_interrupt_return
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/* Branch if thread dispatching is disabled */
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/* Check thread dispatch disable level */
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cmp r3, #0
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bne thread_dispatch_done
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/*
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* Switch to SVC mode. It is important to call the thread dispatcher
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* in SVC mode since overwise the INT stack may need to store an
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* arbitrary number of contexts and it may lead to an invalid order of
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* stack operations.
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*/
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msr cpsr_c, MODE_SVC
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/* Call thread dispatcher */
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/* Check context switch necessary */
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ldr r0, =_Context_Switch_necessary
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ldrb r1, [r0]
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ldr r0, =_ISR_Signals_to_thread_executing
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cmp r1, #0
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bne do_thread_dispatch
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/* Check ISR signals to thread executing */
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ldrb r1, [r0]
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cmp r1, #0
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beq thread_dispatch_done
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/* This aligns thread_dispatch_done on a 4 byte boundary */
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#ifdef __thumb__
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ldr r0, =_ISR_Thread_dispatch
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mov lr, pc
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bx r0
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.thumb
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bx pc
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nop
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.arm
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#else
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bl _ISR_Thread_dispatch
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#endif
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#endif /* __thumb__ */
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/* Switch to INT mode */
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msr cpsr_c, MODE_INT
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do_thread_dispatch:
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/* Clear ISR signals to thread executing */
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strb r3, [r0]
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/* Thread dispatch */
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bl _Thread_Dispatch
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thread_dispatch_done:
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/* Save scratch registers on INT stack */
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stmdb sp!, SCRATCH_LIST
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/* Switch to ARM instructions if necessary */
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SWITCH_FROM_THUMB_TO_ARM
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/* Switch to SVC mode */
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msr cpsr_c, MODE_SVC
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/* Restore link register */
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ldmia sp!, {lr}
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/* Move INT mode program status to scratch register */
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mov SCRATCH_2, MODE_INT
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/*
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* XXX: Remember and restore stack pointer. The data on the stack is
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* still in use. So the stack is now in an inconsistent state. The
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* FIQ handler implementation must not use this area.
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*/
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mov r0, sp
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add sp, #CONTEXT_SIZE
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/* Restore context from SVC stack */
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ldmia sp!, TASK_CONTEXT_LIST
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/* Get INT mode program status register */
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mrs r1, cpsr
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bic r1, r1, #0x1
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/* Switch to INT mode */
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msr cpsr_c, SCRATCH_2
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msr cpsr, r1
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/* Restore interrupt context */
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mov lr, SCRATCH_0
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msr spsr, SCRATCH_1
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/* Save EXCHANGE_LR and EXCHANGE_SPSR registers to exchange area */
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stmdb sp!, {EXCHANGE_LR, EXCHANGE_SPSR}
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/* Restore scratch registers from INT stack */
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ldmia sp!, SCRATCH_LIST
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/* Return from interrupt */
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subs pc, lr, #4
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nested_interrupt_context_save:
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/* Move saved program status register to scratch register */
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mrs SCRATCH_0, spsr
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/* Save context on INT stack */
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stmdb sp!, INTERRUPT_CONTEXT_LIST
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b task_context_save_done
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nested_interrupt_return:
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/* Restore context from INT stack */
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ldmia sp!, INTERRUPT_CONTEXT_LIST
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/* Restore saved program status register */
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msr spsr, SCRATCH_0
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/* Restore scratch registers from INT stack */
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ldmia sp!, SCRATCH_LIST
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/* Restore context */
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ldmia r0, CONTEXT_LIST
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/* Set return address and program status */
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mov lr, EXCHANGE_LR
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msr spsr, EXCHANGE_SPSR
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/* Restore EXCHANGE_LR and EXCHANGE_SPSR registers from exchange area */
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ldmia sp!, {EXCHANGE_LR, EXCHANGE_SPSR}
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/* Return from interrupt */
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subs pc, lr, #4
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@@ -50,6 +50,9 @@ extern "C" {
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#elif defined(__ARM_ARCH_5TE__)
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# define CPU_MODEL_NAME "ARMv5TE"
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#elif defined(__ARM_ARCH_5TEJ__)
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# define CPU_MODEL_NAME "ARMv5TEJ"
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#elif defined(__ARM_ARCH_6J__)
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# define CPU_MODEL_NAME "ARMv6J"
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