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bsp/aarch64/zynqmp: Add support for more than 2G of DDR memory

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Add support to configure the second region of DDR memory if the
BSP configured RAM size is greater than 2G.

Add the second region's memory to the heap.
This commit is contained in:
Chris Johns
2024-08-27 15:00:09 +10:00
parent 07728e0913
commit 94443d497b
3 changed files with 100 additions and 3 deletions
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8
bsps/aarch64/xilinx-zynqmp/include/bsp.h
View File

@@ -68,6 +68,14 @@ struct rtems_termios_device_context;
* @{
*/
/*
* DDRMC mapping
*/
LINKER_SYMBOL(bsp_r0_ram_base)
LINKER_SYMBOL(bsp_r0_ram_end)
LINKER_SYMBOL(bsp_r1_ram_base)
LINKER_SYMBOL(bsp_r1_ram_end)
#define BSP_ARM_GIC_CPUIF_BASE 0xf9020000
#define BSP_ARM_GIC_DIST_BASE 0xf9010000

49
bsps/aarch64/xilinx-zynqmp/start/bspstartmmu.c
View File

@@ -39,6 +39,9 @@
#include <bsp/aarch64-mmu.h>
#include <libcpu/mmu-vmsav8-64.h>
#include <rtems/malloc.h>
#include <rtems/sysinit.h>
BSP_START_DATA_SECTION static const aarch64_mmu_config_entry
zynqmp_mmu_config_table[] = {
AARCH64_MMU_DEFAULT_SECTIONS,
@@ -55,6 +58,10 @@ zynqmp_mmu_config_table[] = {
.begin = 0xfffc0000U,
.end = 0x100000000U,
.flags = AARCH64_MMU_DATA_RW
}, { /* DDRMC_region1_mem, if not used size is 0 and ignored */
.begin = (uintptr_t) bsp_r1_ram_base,
.end = (uintptr_t) bsp_r1_ram_end,
.flags = AARCH64_MMU_DATA_RW_CACHED
}, {
.begin = 0x80000000U,
.end = 0x80100000U,
@@ -62,6 +69,25 @@ zynqmp_mmu_config_table[] = {
}
};
/*
* Create an MMU table to get the R1 base and end. This avoids
* relocation errors as the R1 addresses are in the upper A64 address
* space.
*
* The aarch64_mmu_config_table table cannot be used because the regions
* in that table have no identifiers to indicate which region is the
* the DDRMC_region1_mem region.
*/
static const struct mem_region {
uintptr_t begin;
uintptr_t end;
} bsp_r1_region[] = {
{ /* DDRMC_region1_mem, if not used size is 0 and ignored */
.begin = (uintptr_t) bsp_r1_ram_base,
.end = (uintptr_t) bsp_r1_ram_end,
}
};
/*
* Make weak and let the user override.
*/
@@ -97,3 +123,26 @@ BSP_START_TEXT_SECTION void zynqmp_setup_secondary_cpu_mmu_and_cache( void )
aarch64_mmu_enable();
}
void bsp_r1_heap_extend(void);
void bsp_r1_heap_extend(void)
{
const struct mem_region* r1 = &bsp_r1_region[0];
if (r1->begin != r1->end) {
rtems_status_code sc =
rtems_heap_extend((void*) r1->begin, r1->end - r1->begin);
if (sc != RTEMS_SUCCESSFUL) {
bsp_fatal(BSP_FATAL_HEAP_EXTEND_ERROR);
}
}
}
/*
* Initialise after the IDLE thread exists so the protected heap
* extend call has a valid context.
*/
RTEMS_SYSINIT_ITEM(
bsp_r1_heap_extend,
RTEMS_SYSINIT_IDLE_THREADS,
RTEMS_SYSINIT_ORDER_LAST
);

46
spec/build/bsps/aarch64/xilinx-zynqmp/linkcmds_lp64.yml
View File

@@ -7,6 +7,8 @@ content: |
* Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
*
* Copyright (C) 2024 Contemporary Software (Chris Johns)
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@@ -29,10 +31,42 @@ content: |
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* The RAM supports 36G of DDR4 using the DDR Memory Controller.
*
* The DDR Conroller (DDRC) supports two regions. The first covers
* the A32 address space up to the 2G mark and the second region is in
* the A64 address space at 0x000800000000 for 32G.
*/
DDRMC_REGION_0_BASE = 0x00000000000;
DDRMC_REGION_0_LENGTH = 0x00080000000;
DDRMC_REGION_1_BASE = 0x00800000000;
DDRMC_REGION_1_LENGTH = 0x00800000000;
BSP_RAM_BASE = ${BSP_XILINX_ZYNQMP_RAM_BASE};
BSP_R0_RAM_BASE = DDRMC_REGION_0_BASE;
BSP_R0_RAM_LENGTH =
${BSP_XILINX_ZYNQMP_RAM_LENGTH} >= DDRMC_REGION_0_LENGTH ?
DDRMC_REGION_0_LENGTH - BSP_RAM_BASE : ${BSP_XILINX_ZYNQMP_RAM_LENGTH};
BSP_R0_RAM_END = BSP_RAM_BASE + BSP_R0_RAM_LENGTH;
BSP_R1_RAM_BASE = DDRMC_REGION_1_BASE;
BSP_R1_RAM_LENGTH =
${BSP_XILINX_ZYNQMP_RAM_LENGTH} >= DDRMC_REGION_0_LENGTH ?
${BSP_XILINX_ZYNQMP_RAM_LENGTH} - DDRMC_REGION_0_LENGTH : 0;
AARCH64_MMU_TT_PAGES_SIZE = 0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES};
MEMORY {
RAM : ORIGIN = ${BSP_XILINX_ZYNQMP_RAM_BASE} + ${BSP_XILINX_ZYNQMP_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_ZYNQMP_RAM_LENGTH} - ${BSP_XILINX_ZYNQMP_LOAD_OFFSET} - ${BSP_XILINX_ZYNQMP_NOCACHE_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES})
NOCACHE : ORIGIN = ${BSP_XILINX_ZYNQMP_RAM_BASE} + ${BSP_XILINX_ZYNQMP_RAM_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) - ${BSP_XILINX_ZYNQMP_NOCACHE_LENGTH}, LENGTH = ${BSP_XILINX_ZYNQMP_NOCACHE_LENGTH}
RAM_MMU : ORIGIN = ${BSP_XILINX_ZYNQMP_RAM_BASE} + ${BSP_XILINX_ZYNQMP_RAM_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}), LENGTH = 0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}
RAM : ORIGIN = BSP_RAM_BASE + ${BSP_XILINX_ZYNQMP_LOAD_OFFSET},
LENGTH = BSP_R0_RAM_LENGTH - ${BSP_XILINX_ZYNQMP_LOAD_OFFSET} - ${BSP_XILINX_ZYNQMP_NOCACHE_LENGTH} - AARCH64_MMU_TT_PAGES_SIZE
RAM1 : ORIGIN = BSP_R1_RAM_BASE,
LENGTH = BSP_R1_RAM_LENGTH
NOCACHE : ORIGIN = BSP_RAM_BASE + BSP_R0_RAM_LENGTH - AARCH64_MMU_TT_PAGES_SIZE - ${BSP_XILINX_ZYNQMP_NOCACHE_LENGTH},
LENGTH = ${BSP_XILINX_ZYNQMP_NOCACHE_LENGTH}
RAM_MMU : ORIGIN = BSP_R0_RAM_END - AARCH64_MMU_TT_PAGES_SIZE,
LENGTH = AARCH64_MMU_TT_PAGES_SIZE
}
REGION_ALIAS ("REGION_START", RAM);
@@ -59,6 +93,11 @@ content: |
bsp_vector_table_in_start_section = 1;
bsp_r0_ram_base = DDRMC_REGION_0_BASE;
bsp_r0_ram_end = ORIGIN (RAM) + LENGTH (RAM);
bsp_r1_ram_base = ORIGIN (RAM1);
bsp_r1_ram_end = ORIGIN (RAM1) + LENGTH (RAM1);
bsp_translation_table_base = ORIGIN (RAM_MMU);
bsp_translation_table_end = ORIGIN (RAM_MMU) + LENGTH (RAM_MMU);
@@ -68,6 +107,7 @@ content: |
INCLUDE linkcmds.base
copyrights:
- Copyright (C) 2020 On-Line Applications Research (OAR)
- Copyright (C) 2024 Contemporary Software (Chris Johns)
enabled-by: true
install-path: ${BSP_LIBDIR}
links: []