dev/serial: Add ZYNQ_UART_[01]_BASE_ADDR

This helps to provide a shared implementation of the kernel I/O support.

bsps/aarch64/xilinx-zynqmp/console/console.c

@@ -188,11 +188,11 @@ RTEMS_SYSINIT_ITEM(
 static zynq_uart_context zynqmp_uart_instances[2] = {
   {
     .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 0" ),
-    .regs = (volatile struct zynq_uart *) 0xff000000,
+    .regs = (volatile zynq_uart *) ZYNQ_UART_0_BASE_ADDR,
     .irq = ZYNQMP_IRQ_UART_0
   }, {
     .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 1" ),
-    .regs = (volatile struct zynq_uart *) 0xff010000,
+    .regs = (volatile zynq_uart *) ZYNQ_UART_1_BASE_ADDR,
     .irq = ZYNQMP_IRQ_UART_1
   }
 };

bsps/aarch64/xilinx-zynqmp/include/bsp.h

@@ -55,6 +55,8 @@
 #include <rtems.h>
 #include <rtems/termiostypes.h>
 
+#include <dev/serial/zynq-uart-zynqmp.h>
+
 #ifdef __cplusplus
 extern "C" {
 #endif /* __cplusplus */

bsps/arm/xilinx-zynq/console/console-config.c

@@ -35,15 +35,16 @@
 
 #include <bsp/irq.h>
 #include <dev/serial/zynq-uart.h>
+#include <dev/serial/zynq-uart-regs.h>
 
 zynq_uart_context zynq_uart_instances[2] = {
   {
     .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 0" ),
-    .regs = (volatile struct zynq_uart *) 0xe0000000,
+    .regs = (volatile zynq_uart *) ZYNQ_UART_0_BASE_ADDR,
     .irq = ZYNQ_IRQ_UART_0
   }, {
     .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 1" ),
-    .regs = (volatile struct zynq_uart *) 0xe0001000,
+    .regs = (volatile zynq_uart *) ZYNQ_UART_1_BASE_ADDR,
     .irq = ZYNQ_IRQ_UART_1
   }
 };

bsps/arm/xilinx-zynq/include/bsp.h

@@ -55,6 +55,7 @@
 #include <bsp/default-initial-extension.h>
 #include <bsp/start.h>
 #include <dev/serial/zynq-uart.h>
+#include <dev/serial/zynq-uart-zynq.h>
 
 #ifdef __cplusplus
 extern "C" {

bsps/arm/xilinx-zynqmp-rpu/console/console-config.c

@@ -44,11 +44,11 @@
 static zynq_uart_context zynqmp_uart_instances[2] = {
   {
     .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 0" ),
-    .regs = (volatile struct zynq_uart *) 0xff000000,
+    .regs = (volatile zynq_uart *) ZYNQ_UART_0_BASE_ADDR,
     .irq = ZYNQMP_IRQ_UART_0
   }, {
     .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 1" ),
-    .regs = (volatile struct zynq_uart *) 0xff010000,
+    .regs = (volatile zynq_uart *) ZYNQ_UART_1_BASE_ADDR,
     .irq = ZYNQMP_IRQ_UART_1
   }
 };

bsps/arm/xilinx-zynqmp-rpu/include/bsp.h

@@ -61,6 +61,8 @@
 #include <bsp/start.h>
 #include <peripheral_maps/xilinx_zynqmp.h>
 
+#include <dev/serial/zynq-uart-zynqmp.h>
+
 #ifdef __cplusplus
 extern "C" {
 #endif /* __cplusplus */

bsps/arm/xilinx-zynqmp/console/console-config.c

@@ -44,11 +44,11 @@
 static zynq_uart_context zynqmp_uart_instances[2] = {
   {
     .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 0" ),
-    .regs = (volatile struct zynq_uart *) 0xff000000,
+    .regs = (volatile zynq_uart *) ZYNQ_UART_0_BASE_ADDR,
     .irq = ZYNQMP_IRQ_UART_0
   }, {
     .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 1" ),
-    .regs = (volatile struct zynq_uart *) 0xff010000,
+    .regs = (volatile zynq_uart *) ZYNQ_UART_1_BASE_ADDR,
     .irq = ZYNQMP_IRQ_UART_1
   }
 };

bsps/arm/xilinx-zynqmp/include/bsp.h

@@ -60,6 +60,8 @@
 #include <bsp/default-initial-extension.h>
 #include <bsp/start.h>
 
+#include <dev/serial/zynq-uart-zynqmp.h>
+
 #ifdef __cplusplus
 extern "C" {
 #endif /* __cplusplus */

bsps/include/dev/serial/zynq-uart-zynq.h

@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup zynq_uart
+ *
+ * @brief This header file provides interfaces with respect to the Zynq
+ *   platform.
+ */
+
+/*
+ * Copyright (C) 2024 embedded brains GmbH & Co. KG
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _DEV_SERIAL_ZYNQ_UART_ZYNQ_H
+#define _DEV_SERIAL_ZYNQ_UART_ZYNQ_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @addtogroup zynq_uart
+ *
+ * @{
+ */
+
+/**
+ * @brief This constant defines the Xilinx Zynq UART 0 base address.
+ */
+#define ZYNQ_UART_0_BASE_ADDR 0xe0000000
+
+/**
+ * @brief This constant defines the Xilinx Zynq UART 1 base address.
+ */
+#define ZYNQ_UART_1_BASE_ADDR 0xe0001000
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _DEV_SERIAL_ZYNQ_UART_ZYNQ_H */

bsps/include/dev/serial/zynq-uart-zynqmp.h

@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup zynq_uart
+ *
+ * @brief This header file provides interfaces with respect to the Zynq
+ *   UltraScale+ MPSoC and RFSoC platforms.
+ */
+
+/*
+ * Copyright (C) 2024 embedded brains GmbH & Co. KG
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _DEV_SERIAL_ZYNQ_UART_ZYNQMP_H
+#define _DEV_SERIAL_ZYNQ_UART_ZYNQMP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @addtogroup zynq_uart
+ *
+ * @{
+ */
+
+/**
+ * @brief This constant defines the Xilinx Zynq UART 0 base address.
+ */
+#define ZYNQ_UART_0_BASE_ADDR 0xff000000
+
+/**
+ * @brief This constant defines the Xilinx Zynq UART 1 base address.
+ */
+#define ZYNQ_UART_1_BASE_ADDR 0xff010000
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _DEV_SERIAL_ZYNQ_UART_ZYNQMP_H */

spec/build/bsps/objdevserialzynq.yml

@@ -12,6 +12,8 @@ install:
   source:
   - bsps/include/dev/serial/zynq-uart-regs.h
   - bsps/include/dev/serial/zynq-uart.h
+  - bsps/include/dev/serial/zynq-uart-zynq.h
+  - bsps/include/dev/serial/zynq-uart-zynqmp.h
 links: []
 source:
 - bsps/shared/dev/serial/zynq-uart-polled.c