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https://gitlab.rtems.org/rtems/rtos/rtems.git
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2004-07-15 Jay Monkman
* ChangeLog, Makefile.am, arm920/mmu.c, include/mmu.h: New files.
This commit is contained in:
Jay Monkman
4
c/src/lib/libcpu/arm/shared/ChangeLog
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4
c/src/lib/libcpu/arm/shared/ChangeLog
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2004-07-15 Jay Monkman
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* ChangeLog, Makefile.am, arm920/mmu.c, include/mmu.h: New files.
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54
c/src/lib/libcpu/arm/shared/Makefile.am
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54
c/src/lib/libcpu/arm/shared/Makefile.am
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##
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## $Id$
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##
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EXTRA_PROGRAMS =
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CLEANFILES =
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noinst_DATA =
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include $(top_srcdir)/../../../automake/compile.am
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# include
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if shared
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include_libcpudir = $(includedir)/libcpu
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include_libcpu_HEADERS = include/mmu.h
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## arm920
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EXTRA_PROGRAMS += arm920.rel
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CLEANFILES += arm920.rel
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arm920_rel_SOURCES = arm920/mmu.c
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arm920_rel_CPPFLAGS = $(AM_CPPFLAGS) $(CFLAGS_OPTIMIZE_V) -I$(srcdir)/src
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arm920_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
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EXTRA_PROGRAMS += arm920_g.rel
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CLEANFILES += arm920_g.rel
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arm920_g_rel_SOURCES = $(arm920_rel_SOURCES)
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arm920_g_rel_CPPFLAGS = $(AM_CPPFLAGS) $(CFLAGS_DEBUG_V) -I$(srcdir)/src
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arm920_g_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
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noinst_DATA += arm920$(LIB_VARIANT).rel
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endif
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all-local: $(PREINSTALL_FILES)
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PREINSTALL_DIRS =
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PREINSTALL_FILES =
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if shared
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$(PROJECT_INCLUDE)/libcpu/$(dirstamp):
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@$(mkdir_p) $(PROJECT_INCLUDE)/libcpu
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@: > $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
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PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
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$(PROJECT_INCLUDE)/libcpu/mmu.h: include/mmu.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
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$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/mmu.h
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PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/mmu.h
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endif
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CLEANFILES += $(PREINSTALL_FILES)
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DISTCLEANFILES = $(PREINSTALL_DIRS)
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include $(top_srcdir)/../../../automake/local.am
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242
c/src/lib/libcpu/arm/shared/arm920/mmu.c
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242
c/src/lib/libcpu/arm/shared/arm920/mmu.c
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/*
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* ARM920 MMU functions
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*
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* Copyright (c) 2004 by Cogent Computer Systems
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* Written by Jay Monkman <jtm@lopingdog.com>
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*
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* $Id$
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*/
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#include <libcpu/mmu.h>
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typedef uint32_t mmu_lvl1_t;
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extern uint32_t _ttbl_base;
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static inline uint32_t mmu_get_id(void);
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static inline uint32_t mmu_get_ctrl(void);
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static inline void mmu_set_ctrl(uint32_t val);
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static inline uint32_t mmu_get_trans_tbl(void);
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static inline void mmu_set_trans_tbl(uint32_t val);
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static inline uint32_t mmu_get_domain_ctrl(void);
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static inline void mmu_set_domain_ctrl(uint32_t val);
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static inline uint32_t mmu_get_fault_stat(void);
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static inline void mmu_set_fault_stat(uint32_t val);
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static inline uint32_t mmu_get_fault_addr(void);
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static inline void mmu_set_fault_addr(uint32_t val);
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static inline void mmu_set_cache_inval(void);
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static inline void mmu_set_tlb_inval(void);
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static inline uint32_t mmu_get_proc_id(void);
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static inline void mmu_set_proc_id(uint32_t val);
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static void mmu_set_map_inval(mmu_lvl1_t *base);
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#define MMU_CTRL_MMU_EN (1 << 0)
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#define MMU_CTRL_ALIGN_FAULT_EN (1 << 1)
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#define MMU_CTRL_D_CACHE_EN (1 << 2)
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#define MMU_CTRL_DEFAULT (0xf << 3)
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#define MMU_CTRL_LITTLE_ENDIAN (0 << 7)
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#define MMU_CTRL_BIG_ENDIAN (1 << 7)
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#define MMU_CTRL_SYS_PROT (1 << 8)
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#define MMU_CTRL_ROM_PROT (1 << 9)
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#define MMU_CTRL_I_CACHE_EN (1 << 12)
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#define MMU_CTRL_LOW_VECT (0 << 13)
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#define MMU_CTRL_HIGH_VECT (1 << 13)
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#define MMU_SET_LVL1_SECT(addr, ap, dom, ce, be) \
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(((addr) & 0xfff00000) | \
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(ap) | \
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(dom) | \
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((ce) << 3) | \
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((be) << 2) | \
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0x12)
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#define MMU_SET_LVL1_INVAL (0x0)
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#define MMU_SECT_AP_ALL (0x3 << 10)
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#define NOP ( { asm volatile ("nop\n" ); } )
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void mmu_init(mmu_sect_map_t *map)
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{
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mmu_lvl1_t *lvl1_base;
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int i;
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/* flush the cache and TLB */
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mmu_set_cache_inval();
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mmu_set_tlb_inval();
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/* set manage mode access for all domains */
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mmu_set_domain_ctrl(0xffffffff);
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lvl1_base = (mmu_lvl1_t *)&_ttbl_base;
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/* set up the trans table */
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mmu_set_map_inval(lvl1_base);
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mmu_set_trans_tbl((uint32_t) lvl1_base);
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/* create a 1:1 mapping of the entire address space */
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i = 0;
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while(map[i].size != 0) {
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int c;
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int b;
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int pbase;
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int vbase;
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int sects;
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switch (map[i].cache_flags) {
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case MMU_CACHE_NONE:
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c = 0;
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b = 0;
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break;
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case MMU_CACHE_BUFFERED:
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c = 0;
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b = 1;
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break;
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case MMU_CACHE_WTHROUGH:
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c = 1;
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b = 0;
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break;
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case MMU_CACHE_WBACK:
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c = 1;
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b = 1;
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break;
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}
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pbase = (map[i].paddr & 0xfff00000) >> 20;
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vbase = (map[i].vaddr & 0xfff00000) >> 20;
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sects = map[i].size;
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while (sects > 0) {
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lvl1_base[vbase] = MMU_SET_LVL1_SECT(pbase << 20,
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MMU_SECT_AP_ALL,
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0,
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c,
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b);
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pbase++;
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vbase++;
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sects--;
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}
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i++;
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}
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/* flush the cache and TLB */
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mmu_set_cache_inval();
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mmu_set_tlb_inval();
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NOP;
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NOP;
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/* I & D caches turned on */
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mmu_set_ctrl(MMU_CTRL_DEFAULT |
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MMU_CTRL_D_CACHE_EN |
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MMU_CTRL_I_CACHE_EN |
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MMU_CTRL_ALIGN_FAULT_EN |
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MMU_CTRL_LITTLE_ENDIAN |
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MMU_CTRL_MMU_EN);
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NOP;
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NOP;
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return;
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}
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static inline uint32_t mmu_get_id(void)
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{
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uint32_t val;
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asm volatile ("msr 15, 0, %0, cr0, cr0\n" : "=r" (val));
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return val;
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}
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static inline uint32_t mmu_get_ctrl(void)
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{
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uint32_t val;
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asm volatile ("msr 15, 0, %0, cr1, cr0\n" : "=r" (val));
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return val;
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}
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static inline void mmu_set_ctrl(uint32_t val)
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{
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asm volatile ("mcr 15, 0, %0, cr1, cr0, 0\n" : :"r" (val));
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}
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static inline uint32_t mmu_get_trans_tbl(void)
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{
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uint32_t val;
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asm volatile ("msr 15, 0, %0, cr2, cr0\n" : "=r" (val));
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return val;
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}
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static inline void mmu_set_trans_tbl(uint32_t val)
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{
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asm volatile ("mcr 15, 0, %0, cr2, cr0, 0\n" : :"r" (val));
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}
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static inline uint32_t mmu_get_domain_ctrl(void)
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{
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uint32_t val;
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asm volatile ("msr 15, 0, %0, cr3, cr0\n" : "=r" (val));
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return val;
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}
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static inline void mmu_set_domain_ctrl(uint32_t val)
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{
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asm volatile ("mcr 15, 0, %0, cr3, cr0, 0\n" : :"r" (val));
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}
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static inline uint32_t mmu_get_fault_stat(void)
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{
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uint32_t val;
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asm volatile ("msr 15, 0, %0, cr5, cr0\n" : "=r" (val));
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return val;
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}
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static inline void mmu_set_fault_stat(uint32_t val)
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{
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asm volatile ("mcr 15, 0, %0, cr5, cr0, 0\n" : :"r" (val));
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}
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static inline uint32_t mmu_get_fault_addr(void)
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{
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uint32_t val;
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asm volatile ("msr 15, 0, %0, cr6, cr0\n" : "=r" (val));
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return val;
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}
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static inline void mmu_set_fault_addr(uint32_t val)
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{
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asm volatile ("mcr 15, 0, %0, cr6, cr0, 0\n" : :"r" (val));
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}
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static inline void mmu_set_cache_inval(void)
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{
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uint32_t val = 0;
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asm volatile ("mcr 15, 0, %0, cr7, cr7, 0\n" : :"r" (val));
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}
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static inline void mmu_set_tlb_inval(void)
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{
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uint32_t val = 0;
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asm volatile ("mcr 15, 0, %0, cr8, cr7, 0\n" : :"r" (val));
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}
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static inline uint32_t mmu_get_proc_id(void)
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{
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uint32_t val;
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asm volatile ("msr 15, 0, %0, cr13, cr0\n" : "=r" (val));
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return val;
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}
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static inline void mmu_set_proc_id(uint32_t val)
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{
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asm volatile ("mcr 15, 0, %0, cr13, cr0, 0\n" : :"r" (val));
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}
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/* set all the level 1 entrys to be invalid descriptors */
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static void mmu_set_map_inval(mmu_lvl1_t *base)
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{
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int i;
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for (i = 0; i < (0x4000 / 4); i++) {
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base[i] = MMU_SET_LVL1_INVAL;
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}
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}
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30
c/src/lib/libcpu/arm/shared/include/mmu.h
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30
c/src/lib/libcpu/arm/shared/include/mmu.h
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@@ -0,0 +1,30 @@
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/*
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* ARM MMU header file
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*
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* Copyright (c) 2004 by Cogent Computer Systems
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* Written by Jay Monkman <jtm@lopingdog.com>
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*
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* $Id$
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*/
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#ifndef __MMU_H__
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#define __MMU_H__
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#include <stdint.h>
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#define MMU_SECT_SIZE 0x100000
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#define MMU_CACHE_NONE 0x0
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#define MMU_CACHE_BUFFERED 0x1
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#define MMU_CACHE_WTHROUGH 0x2
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#define MMU_CACHE_WBACK 0x3
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typedef struct {
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uint32_t paddr;
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uint32_t vaddr;
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uint32_t size; /* in MB */
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uint8_t cache_flags;
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} mmu_sect_map_t;
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void mmu_init(mmu_sect_map_t *map);
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#endif /* __MMU_H__ */
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