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arm: Fix ARMv7-M interrupt processing

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Right after a "msr basepri_max, %[basepri]" instruction an interrupt
service may still take place (observed at least on Cortex-M7).  However,
pendable service calls that are activated during this interrupt service
may be delayed until interrupts are enable again.  The
_ARMV7M_Pendable_service_call() did not check that a thread dispatch is
allowed.  Move this test from _ARMV7M_Interrupt_service_leave() to
_ARMV7M_Pendable_service_call().

Close #3060.
This commit is contained in:
Sebastian Huber
2017-07-04 14:15:03 +02:00
parent 09cbe713ff
commit 7e91901303
2 changed files with 49 additions and 31 deletions
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52
cpukit/score/cpu/arm/armv7m-isr-dispatch.c
View File

@@ -5,10 +5,10 @@
*/
/*
* Copyright (c) 2011-2014 Sebastian Huber. All rights reserved.
* Copyright (c) 2011, 2017 Sebastian Huber. All rights reserved.
*
* embedded brains GmbH
* Obere Lagerstr. 30
* Dornierstr. 4
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
@@ -48,29 +48,42 @@ static void _ARMV7M_Trigger_lazy_floating_point_context_save( void )
void _ARMV7M_Pendable_service_call( void )
{
ARMV7M_Exception_frame *ef;
_ISR_Nest_level = 1;
_ARMV7M_SCB->icsr = ARMV7M_SCB_ICSR_PENDSVCLR;
_ARMV7M_Trigger_lazy_floating_point_context_save();
ef = (ARMV7M_Exception_frame *) _ARMV7M_Get_PSP();
--ef;
_ARMV7M_Set_PSP( (uint32_t) ef );
Per_CPU_Control *cpu_self = _Per_CPU_Get();
/*
* According to "ARMv7-M Architecture Reference Manual" section B1.5.6
* "Exception entry behavior" the return address is half-word aligned.
* We must check here if a thread dispatch is allowed. Right after a
* "msr basepri_max, %[basepri]" instruction an interrupt service may still
* take place. However, pendable service calls that are activated during
* this interrupt service may be delayed until interrupts are enable again.
*/
ef->register_pc = (void *)
((uintptr_t) _ARMV7M_Thread_dispatch & ~((uintptr_t) 1));
if (
( cpu_self->isr_nest_level | cpu_self->thread_dispatch_disable_level ) == 0
) {
ARMV7M_Exception_frame *ef;
ef->register_xpsr = 0x01000000U;
cpu_self->isr_nest_level = 1;
_ARMV7M_SCB->icsr = ARMV7M_SCB_ICSR_PENDSVCLR;
_ARMV7M_Trigger_lazy_floating_point_context_save();
ef = (ARMV7M_Exception_frame *) _ARMV7M_Get_PSP();
--ef;
_ARMV7M_Set_PSP( (uint32_t) ef );
/*
* According to "ARMv7-M Architecture Reference Manual" section B1.5.6
* "Exception entry behavior" the return address is half-word aligned.
*/
ef->register_pc = (void *)
((uintptr_t) _ARMV7M_Thread_dispatch & ~((uintptr_t) 1));
ef->register_xpsr = 0x01000000U;
}
}
void _ARMV7M_Supervisor_call( void )
{
Per_CPU_Control *cpu_self = _Per_CPU_Get();
ARMV7M_Exception_frame *ef;
_ARMV7M_Trigger_lazy_floating_point_context_save();
@@ -79,10 +92,9 @@ void _ARMV7M_Supervisor_call( void )
++ef;
_ARMV7M_Set_PSP( (uint32_t) ef );
_ISR_Nest_level = 0;
RTEMS_COMPILER_MEMORY_BARRIER();
cpu_self->isr_nest_level = 0;
if ( _Thread_Dispatch_necessary ) {
if ( cpu_self->dispatch_necessary ) {
_ARMV7M_Pendable_service_call();
}
}

28
cpukit/score/cpu/arm/armv7m-isr-enter-leave.c
View File

@@ -5,10 +5,10 @@
*/
/*
* Copyright (c) 2011 Sebastian Huber. All rights reserved.
* Copyright (c) 2011, 2017 Sebastian Huber. All rights reserved.
*
* embedded brains GmbH
* Obere Lagerstr. 30
* Dornierstr. 4
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
@@ -30,19 +30,25 @@
void _ARMV7M_Interrupt_service_enter( void )
{
++_Thread_Dispatch_disable_level;
++_ISR_Nest_level;
Per_CPU_Control *cpu_self = _Per_CPU_Get();
++cpu_self->thread_dispatch_disable_level;
++cpu_self->isr_nest_level;
}
void _ARMV7M_Interrupt_service_leave( void )
{
--_ISR_Nest_level;
--_Thread_Dispatch_disable_level;
if (
_ISR_Nest_level == 0
&& _Thread_Dispatch_disable_level == 0
&& _Thread_Dispatch_necessary
) {
Per_CPU_Control *cpu_self = _Per_CPU_Get();
--cpu_self->thread_dispatch_disable_level;
--cpu_self->isr_nest_level;
/*
* Optimistically activate a pendable service call if a thread dispatch is
* necessary. The _ARMV7M_Pendable_service_call() will check that a thread
* dispatch is allowed.
*/
if ( cpu_self->dispatch_necessary ) {
_ARMV7M_SCB->icsr = ARMV7M_SCB_ICSR_PENDSVSET;
}
}