bsps/stm32h7: Add SPI support

This adds support for the 6 SPI interfaces on the STM32H7 series chips
with an initial example for the stm32h750b discovery kit development
board. Configuration is similar to existing peripherals. Chip select
lines are software-controlled since the SPI peripheral only supports a
single hardware-controlled chip select line. This implementation does
not use interrupts.

bsps/arm/stm32h7/boards/stm/stm32h750b-dk/spi2-cfg.c

@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMSTM32H7
+ *
+ * @brief This source file contains the SPI2 pin configuration.
+ */
+
+/*
+ * Copyright (C) 2024 On-Line Applications Research (OAR) Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <stm32h7/hal.h>
+
+/* Only defined if it is configured for this board */
+#ifdef SPI2
+
+const stm32h7_spi_config stm32h7_spi2_config = {
+  .cs_gpio = {
+    {
+      .regs = GPIOA,
+      .config = {
+        .Pin = GPIO_PIN_15,
+        .Mode = GPIO_MODE_OUTPUT_PP,
+        .Speed = GPIO_SPEED_FREQ_LOW,
+      }
+    },
+    {0}
+  },
+  .sck_gpio = {
+    .regs = GPIOD,
+    .config = {
+      .Pin = GPIO_PIN_3,
+      .Mode = GPIO_MODE_AF_PP,
+      .Pull = GPIO_NOPULL,
+      .Speed = GPIO_SPEED_FREQ_LOW,
+      .Alternate = GPIO_AF5_SPI2
+    }
+  },
+  .miso_gpio = {
+    .regs = GPIOI,
+    .config = {
+      .Pin = GPIO_PIN_2,
+      .Mode = GPIO_MODE_AF_PP,
+      .Pull = GPIO_NOPULL,
+      .Speed = GPIO_SPEED_FREQ_LOW,
+      .Alternate = GPIO_AF5_SPI2
+    }
+  },
+  .mosi_gpio = {
+    .regs = GPIOB,
+    .config = {
+      .Pin = GPIO_PIN_15,
+      .Mode = GPIO_MODE_AF_PP,
+      .Pull = GPIO_NOPULL,
+      .Speed = GPIO_SPEED_FREQ_LOW,
+      .Alternate = GPIO_AF5_SPI2
+    }
+  },
+  .max_speed_hz = 40000000
+};
+
+#endif /* SPI2 */

bsps/arm/stm32h7/boards/stm/stm32h750b-dk/stm32h7-config-per.c

@@ -32,9 +32,32 @@
 #include <stm32h7/hal.h>
 
 const RCC_PeriphCLKInitTypeDef stm32h7_config_peripheral_clocks = {
-  /* for stm32h750b-dk BSP we provide U(S)ART1/2/3 */
+  /* for stm32h750b-dk BSP we provide U(S)ART1/2/3 and SPI2 on STMOD+ */
   .PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2
-	  | RCC_PERIPHCLK_USART3,
+	  | RCC_PERIPHCLK_USART3
+#ifdef STM32H7_SPI2_ENABLE
+	  | RCC_PERIPHCLK_SPI2
+#endif
+	  ,
+  .PLL2.PLL2M = 3,
+  .PLL2.PLL2N = 48,
+  .PLL2.PLL2P = 5,
+  .PLL2.PLL2Q = 6,
+  .PLL2.PLL2R = 2,
+  .PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3,
+  .PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE,
+  .PLL2.PLL2FRACN = 0,
+  .PLL3.PLL3M = 25,
+  .PLL3.PLL3N = 192,
+  .PLL3.PLL3P = 2,
+  .PLL3.PLL3Q = 4,
+  .PLL3.PLL3R = 3,
+  .PLL3.PLL3RGE = RCC_PLL3VCIRANGE_0,
+  .PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE,
+  .PLL3.PLL3FRACN = 0,
   .Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2,
   .Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1,
+#ifdef STM32H7_SPI2_ENABLE
+  .Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL2,
+#endif
 };

bsps/arm/stm32h7/hal/stm32h7xx_hal_spi.c

@@ -529,6 +529,7 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
   return HAL_OK;
 }
 
+#ifndef __rtems__
 /**
   * @brief  Initialize the SPI MSP.
   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
@@ -544,6 +545,7 @@ __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
             the HAL_SPI_MspInit should be implemented in the user file
    */
 }
+#endif
 
 /**
   * @brief  De-Initialize the SPI MSP.

bsps/arm/stm32h7/include/bsp.h

@@ -65,6 +65,14 @@ void stm32h7_init_peripheral_clocks(void);
 void stm32h7_init_qspi(void);
 void SystemInit_ExtMemCtl(void);
 
+/**
+ * @brief Register SPI interfaces
+ *
+ * This initializes and registers the configured SPI devices with the RTEMS SPI
+ * framework. SPI devices are configured at BSP build time.
+ */
+void stm32h7_register_spi_devices(void);
+
 /** @} */
 
 #ifdef __cplusplus

bsps/arm/stm32h7/include/stm32h7/hal.h

@@ -31,6 +31,7 @@
 #include <stm32h7xx_hal.h>
 
 #include <rtems/termiostypes.h>
+#include <dev/spi/spi.h>
 
 #ifdef __cplusplus
 extern "C" {
@@ -69,6 +70,12 @@ typedef enum {
   STM32H7_MODULE_USB2_OTG_ULPI,
   STM32H7_MODULE_SDMMC1,
   STM32H7_MODULE_SDMMC2,
+  STM32H7_MODULE_SPI1,
+  STM32H7_MODULE_SPI2,
+  STM32H7_MODULE_SPI3,
+  STM32H7_MODULE_SPI4,
+  STM32H7_MODULE_SPI5,
+  STM32H7_MODULE_SPI6,
 } stm32h7_module_index;
 
 stm32h7_module_index stm32h7_get_module_index(const void *regs);
@@ -162,6 +169,57 @@ extern const uint32_t stm32h7_config_flash_latency;
 
 extern const RCC_PeriphCLKInitTypeDef stm32h7_config_peripheral_clocks;
 
+#define STM32H7_NUM_SOFT_CS 4
+
+typedef struct {
+  /*
+   * Some SPI peripheral configurations require multiple GPIO blocks, so
+   * configure each pin separately.
+   */
+  stm32h7_gpio_config sck_gpio;
+  stm32h7_gpio_config miso_gpio;
+  stm32h7_gpio_config mosi_gpio;
+  stm32h7_gpio_config cs_gpio[STM32H7_NUM_SOFT_CS];
+  /*
+   * This is expected to be the maximum speed of the output clock which is a
+   * factor of 2 less than the input clock.
+   */
+  uint32_t max_speed_hz;
+} stm32h7_spi_config;
+
+typedef struct {
+  spi_bus bus;
+  SPI_HandleTypeDef spi;
+  bool transmitting;
+  const stm32h7_spi_config *config;
+  rtems_vector_number irq;
+} stm32h7_spi_context;
+
+extern stm32h7_spi_context stm32h7_spi1_instance;
+
+extern const stm32h7_spi_config stm32h7_spi1_config;
+
+extern stm32h7_spi_context stm32h7_spi2_instance;
+
+extern const stm32h7_spi_config stm32h7_spi2_config;
+
+extern stm32h7_spi_context stm32h7_spi3_instance;
+
+extern const stm32h7_spi_config stm32h7_spi3_config;
+
+extern stm32h7_spi_context stm32h7_spi4_instance;
+
+extern const stm32h7_spi_config stm32h7_spi4_config;
+
+extern stm32h7_spi_context stm32h7_spi5_instance;
+
+extern const stm32h7_spi_config stm32h7_spi5_config;
+
+extern stm32h7_spi_context stm32h7_spi6_instance;
+
+extern const stm32h7_spi_config stm32h7_spi6_config;
+
+
 #ifdef __cplusplus
 }
 #endif

bsps/arm/stm32h7/spi/spi-support.c

@@ -0,0 +1,392 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMSTM32H7
+ *
+ * @brief This source file contains the shared SPI support code.
+ */
+
+/*
+ * Copyright (C) 2024 On-Line Applications Research (OAR) Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <bsp.h>
+#include <bsp/fatal.h>
+#include <inttypes.h>
+#include <rtems/bspIo.h>
+#include <rtems/sysinit.h>
+#include <stdio.h>
+
+#include <stm32h7/hal.h>
+#include <rtems/score/prioritybitmapimpl.h>
+
+/* NULLs are included for disabled devices to preserve index */
+static stm32h7_spi_context * const stm32h7_spi_instances[] = {
+#ifdef STM32H7_SPI1_ENABLE
+ #ifdef SPI1
+  &stm32h7_spi1_instance,
+ #else
+  #error SPI1 configured, but not available
+ #endif
+#else
+  NULL,
+#endif
+
+#ifdef STM32H7_SPI2_ENABLE
+ #ifdef SPI2
+  &stm32h7_spi2_instance,
+ #else
+  #error SPI2 configured, but not available
+ #endif
+#else
+  NULL,
+#endif
+
+#ifdef STM32H7_SPI3_ENABLE
+ #ifdef SPI3
+  &stm32h7_spi3_instance,
+ #else
+  #error SPI3 configured, but not available
+ #endif
+#else
+  NULL,
+#endif
+
+#ifdef STM32H7_SPI4_ENABLE
+ #ifdef SPI4
+  &stm32h7_spi4_instance,
+ #else
+  #error SPI4 configured, but not available
+ #endif
+#else
+  NULL,
+#endif
+
+#ifdef STM32H7_SPI5_ENABLE
+ #ifdef SPI5
+  &stm32h7_spi5_instance,
+ #else
+  #error SPI5 configured, but not available
+ #endif
+#else
+  NULL,
+#endif
+
+#ifdef STM32H7_SPI6_ENABLE
+ #ifdef SPI6
+  &stm32h7_spi6_instance,
+ #else
+  #error SPI6 configured, but not available
+ #endif
+#else
+  NULL,
+#endif
+
+  /* NULL is included for consistent use of commas above */
+  NULL
+};
+
+static int stm32h7_spi_set_prescaler(stm32h7_spi_context *ctx, uint32_t speed_hz)
+{
+  uint32_t prescaler_mask = SPI_BAUDRATEPRESCALER_256;
+
+  /* check speed against max divider (2 is implicit in max_speed_hz) */
+  if (speed_hz < (ctx->bus.max_speed_hz / 128)) {
+    /* clock rate request too low */
+    return 1;
+  }
+
+  if (speed_hz > ctx->bus.max_speed_hz) {
+    ctx->spi.Instance->CFG1 &= ~prescaler_mask;
+    ctx->spi.Instance->CFG1 |= SPI_BAUDRATEPRESCALER_2;
+  } else {
+    uint32_t divider = 2 * ctx->bus.max_speed_hz / speed_hz;
+    uint32_t remainder = (2 * ctx->bus.max_speed_hz) % speed_hz;
+    uint32_t prescaler_value;
+    if (divider > 256) {
+      /* not able to divide enough to accomodate clock rate request */
+      return 1;
+    }
+    /* prescaler values with scale factor N are (log2(N)-1) << 24 */
+    prescaler_value = 7 - _Bitfield_Leading_zeros[divider & 0xff];
+    if (remainder) {
+      prescaler_value++;
+    }
+    if (prescaler_value > SPI_BAUDRATEPRESCALER_256 >> 24) {
+      /* not able to divide enough to accomodate clock rate request */
+      return 1;
+    }
+    prescaler_value <<= 28;
+    ctx->spi.Instance->CFG1 &= ~prescaler_mask;
+    ctx->spi.Instance->CFG1 |= prescaler_value;
+  }
+
+  return 0;
+}
+
+static int stm32h7_spi_set_bpw(stm32h7_spi_context *ctx, uint32_t bits_per_word)
+{
+  uint32_t bits_per_word_mask = SPI_DATASIZE_32BIT;
+
+  if (bits_per_word < 4 || bits_per_word > 32) {
+    return 1;
+  }
+
+  /*
+   * bits per word starts at 4 bpw with register value 3 and counts up to 32 bpw
+   * with register value 0x1F (31)
+   */
+  ctx->spi.Instance->CFG1 &= ~bits_per_word_mask;
+  ctx->spi.Instance->CFG1 |= (bits_per_word - 1);
+
+  return 0;
+}
+
+static void stm32h7_spi_set_mode(stm32h7_spi_context *ctx, uint32_t mode)
+{
+  uint32_t mode_mask = SPI_POLARITY_HIGH | SPI_PHASE_2EDGE;
+  ctx->spi.Instance->CFG2 &= ~mode_mask;
+  if (mode & SPI_CPOL) {
+    ctx->spi.Instance->CFG2 |= SPI_POLARITY_HIGH;
+  }
+  if (mode & SPI_CPHA) {
+    ctx->spi.Instance->CFG2 |= SPI_PHASE_2EDGE;
+  }
+
+}
+
+static int stm32h7_spi_setup(spi_bus *base)
+{
+  stm32h7_spi_context *ctx = RTEMS_CONTAINER_OF(base, stm32h7_spi_context, bus);
+
+  if (stm32h7_spi_set_prescaler(ctx, ctx->bus.speed_hz)) {
+    return 1;
+  }
+
+  if (stm32h7_spi_set_bpw(ctx, ctx->bus.bits_per_word)) {
+    return 1;
+  }
+
+  stm32h7_spi_set_mode(ctx, ctx->bus.mode);
+
+  return 0;
+}
+
+static void stm32h7_spi_destroy(spi_bus *base)
+{
+  stm32h7_spi_context *ctx = RTEMS_CONTAINER_OF(base, stm32h7_spi_context, bus);
+
+  HAL_SPI_DeInit(&ctx->spi);
+
+  spi_bus_destroy(base);
+}
+
+static int stm32h7_spi_get_chip_select(
+  stm32h7_spi_context *ctx,
+  uint8_t cs,
+  GPIO_TypeDef **gpio,
+  uint16_t *pin)
+{
+  const stm32h7_gpio_config *cs_gpio;
+  if (cs >= STM32H7_NUM_SOFT_CS) {
+    return 1;
+  }
+  cs_gpio = &ctx->config->cs_gpio[cs];
+  if (cs_gpio->regs == NULL || cs_gpio->config.Pin == 0) {
+    /* The requested chip select is not configured */
+    return 1;
+  }
+  *gpio = cs_gpio->regs;
+  *pin = cs_gpio->config.Pin;
+  return 0;
+}
+
+static int stm32h7_spi_apply_premessage_settings(
+  stm32h7_spi_context *ctx,
+  const spi_ioc_transfer *msg
+)
+{
+  uint32_t mode_width = SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD;
+
+  if (msg->rx_nbits > 1 || msg->tx_nbits > 1 || (msg->mode & mode_width)) {
+    /* This device does not support dual or quad SPI */
+    return 1;
+  }
+
+  if (stm32h7_spi_set_prescaler(ctx, msg->speed_hz)) {
+    return 1;
+  }
+
+  if (stm32h7_spi_set_bpw(ctx, msg->bits_per_word)) {
+    return 1;
+  }
+
+  stm32h7_spi_set_mode(ctx, msg->mode);
+
+  GPIO_TypeDef *gpio_block = NULL;
+  uint16_t gpio_pin = 0;
+  if (stm32h7_spi_get_chip_select(ctx, msg->cs, &gpio_block, &gpio_pin)) {
+    /* Selected GPIO pin not available */
+    return 1;
+  }
+  /* pull chip select low to activate selected device */
+  HAL_GPIO_WritePin(gpio_block, gpio_pin, GPIO_PIN_RESET);
+  return 0;
+}
+
+static void stm32h7_spi_apply_postmessage_settings(
+  stm32h7_spi_context *ctx,
+  const spi_ioc_transfer *msg,
+  bool final
+)
+{
+  usleep(msg->delay_usecs);
+  if (msg->cs_change || final) {
+    GPIO_TypeDef *gpio_block = NULL;
+    uint16_t gpio_pin = 0;
+
+    /*
+     * It shouldn't be possible for this to fail since it was already checked in
+     * the premessage application
+     */
+    (void) stm32h7_spi_get_chip_select(ctx, msg->cs, &gpio_block, &gpio_pin);
+    /* bring chip select high */
+    HAL_GPIO_WritePin(gpio_block, gpio_pin, GPIO_PIN_SET);
+  }
+}
+
+static int stm32h7_spi_transfer(
+  spi_bus *base,
+  const spi_ioc_transfer *msgs,
+  uint32_t msg_count
+)
+{
+  stm32h7_spi_context *ctx = RTEMS_CONTAINER_OF(base, stm32h7_spi_context, bus);
+
+  for (int i = 0; i < msg_count; i++) {
+    const spi_ioc_transfer *msg = &msgs[i];
+    HAL_StatusTypeDef status;
+
+    if (stm32h7_spi_apply_premessage_settings(ctx, msg)) {
+      return 1;
+    }
+    /* perform transfer */
+    if (msg->tx_buf != NULL) {
+      status = HAL_SPI_Transmit(&ctx->spi, msg->tx_buf, msg->len, 100);
+      if (status != HAL_OK) {
+        return 1;
+      }
+    }
+    if (msg->rx_buf != NULL) {
+      status = HAL_SPI_Receive(&ctx->spi, msg->rx_buf, msg->len, 100);
+      if (status != HAL_OK) {
+        return 1;
+      }
+    }
+    /* set final to true on last iteration */
+    stm32h7_spi_apply_postmessage_settings(ctx, msg, i == msg_count);
+  }
+
+  return 0;
+}
+
+static int stm32h7_register_spi_device(
+  stm32h7_spi_context *ctx,
+  uint8_t device_index
+)
+{
+  char path[sizeof("/dev/spiXXX")];
+  int rv;
+  spi_bus *bus = &ctx->bus;
+
+  rv = spi_bus_init(bus);
+  if (rv) {
+    return rv;
+  }
+
+  bus->transfer = stm32h7_spi_transfer;
+  bus->destroy = stm32h7_spi_destroy;
+  bus->setup = stm32h7_spi_setup;
+  /*
+   * Max speed for these peripherals is 150MHz, but other clock limitations
+   * determined by the BSP clock configuration bring that down. The minimum
+   * required SPI internal divider is 2 which should be accounted for in the
+   * configuration's max_speed_hz parameter.
+   */
+  bus->max_speed_hz = ctx->config->max_speed_hz;
+  /*
+   * The stm32h7 SPI peripherals support a single hardware chip select which is
+   * not required to be routed to a pin by the configuration since peripheral
+   * drivers using the SPI bus will often need to use GPIO to enable
+   * peripherals. Since any hardware chip select pin can also be used as GPIO,
+   * all chip selects are used in GPIO mode.
+   */
+  bus->speed_hz = bus->max_speed_hz;
+  bus->cs_change = 0;
+  bus->cs = 0;
+  bus->bits_per_word = ctx->spi.Init.DataSize + 1;
+  bus->lsb_first = false;
+  if (ctx->spi.Init.FirstBit == SPI_FIRSTBIT_LSB) {
+    bus->lsb_first = true;
+  }
+  bus->mode = 0;
+  if (ctx->spi.Init.CLKPolarity == SPI_POLARITY_HIGH) {
+    bus->mode |= SPI_CPOL;
+  }
+  if (ctx->spi.Init.CLKPhase == SPI_PHASE_2EDGE) {
+    bus->mode |= SPI_CPHA;
+  }
+
+  if (HAL_SPI_Init(&ctx->spi)) {
+    return 1;
+  }
+
+  snprintf(path, sizeof(path), "/dev/spi%" PRIu8, device_index);
+  rv = spi_bus_register(bus, path);
+  if (rv) {
+    return rv;
+  }
+
+  return 0;
+}
+
+void stm32h7_register_spi_devices(void)
+{
+  int i;
+
+  for (i = 0; i < (RTEMS_ARRAY_SIZE(stm32h7_spi_instances)); i++) {
+    if (stm32h7_spi_instances[i] == NULL) {
+      continue;
+    }
+    if (stm32h7_register_spi_device(stm32h7_spi_instances[i], i)) {
+      bsp_fatal(STM32H7_FATAL_MMU_CANNOT_REGISTER_SPI);
+    }
+  }
+}

bsps/arm/stm32h7/spi/spi1.c

@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMSTM32H7
+ *
+ * @brief This source file contains the shared SPI1 peripheral configuration.
+ */
+
+/*
+ * Copyright (C) 2024 On-Line Applications Research (OAR) Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <stm32h7/hal.h>
+
+#ifdef SPI1
+
+/*
+ * On most stm32h7 CPUs (at least 743/747/750/753/755/757/7b3), SPI1 can occupy:
+ * AF5:
+ *   NSS A4
+ *   NSS A15
+ *   NSS G10
+ *   SCK A5
+ *   SCK B3
+ *   SCK G11
+ *   MISO A6
+ *   MISO B4
+ *   MISO G9
+ *   MOSI A7
+ *   MOSI B5
+ *   MOSI D7
+ */
+stm32h7_spi_context stm32h7_spi1_instance = {
+  .spi = {
+    .Instance = SPI1,
+    /* Configure full-duplex SPI master with 8 bit data size */
+    .Init.Mode = SPI_MODE_MASTER,
+    .Init.Direction = SPI_DIRECTION_2LINES,
+    .Init.DataSize = SPI_DATASIZE_8BIT,
+    /* Configure mode 0 */
+    .Init.CLKPolarity = SPI_POLARITY_LOW,
+    .Init.CLKPhase = SPI_PHASE_1EDGE,
+    /* Assume software-controlled-chip-select */
+    .Init.NSS = SPI_NSS_SOFT,
+    .Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2,
+    .Init.FirstBit = SPI_FIRSTBIT_MSB,
+    .Init.TIMode = SPI_TIMODE_DISABLE,
+    /* Disable CRC calculation */
+    .Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE,
+    .Init.NSSPMode = SPI_NSS_PULSE_DISABLE,
+    .Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA,
+    .Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN,
+    .Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN,
+    .Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE,
+    .Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE,
+    .Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE,
+    .Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_DISABLE,
+    .Init.IOSwap = SPI_IO_SWAP_DISABLE
+
+  },
+  .config = &stm32h7_spi1_config,
+  .irq = SPI1_IRQn
+};
+
+#endif /* SPI1 */

bsps/arm/stm32h7/spi/spi2.c

@@ -0,0 +1,99 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMSTM32H7
+ *
+ * @brief This source file contains the shared SPI2 peripheral configuration.
+ */
+
+/*
+ * Copyright (C) 2024 On-Line Applications Research (OAR) Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <stm32h7/hal.h>
+
+#ifdef SPI2
+
+/*
+ * On most stm32h7 CPUs (at least 743/747/750/753/755/757/7b3), SPI2 can occupy:
+ * AF5:
+ *   NSS A11
+ *   NSS B9
+ *   NSS B12
+ *   NSS I0
+ *   SCK A9
+ *   SCK A12
+ *   SCK B10
+ *   SCK B13
+ *   SCK D3
+ *   SCK I1
+ *   MISO B14
+ *   MISO C2
+ *   MISO I2
+ *   MOSI B15
+ *   MOSI C1
+ *   MOSI C3
+ *   MOSI I3
+ * AF7:
+ *   NSS B4
+ */
+stm32h7_spi_context stm32h7_spi2_instance = {
+  .spi = {
+    .Instance = SPI2,
+    /* Configure full-duplex SPI master with 8 bit data size */
+    .Init.Mode = SPI_MODE_MASTER,
+    .Init.Direction = SPI_DIRECTION_2LINES,
+    .Init.DataSize = SPI_DATASIZE_8BIT,
+    /* Configure mode 0 */
+    .Init.CLKPolarity = SPI_POLARITY_LOW,
+    .Init.CLKPhase = SPI_PHASE_1EDGE,
+    /* Assume software-controlled-chip-select */
+    .Init.NSS = SPI_NSS_SOFT,
+    .Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2,
+    .Init.FirstBit = SPI_FIRSTBIT_MSB,
+    .Init.TIMode = SPI_TIMODE_DISABLE,
+    /* Disable CRC calculation */
+    .Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE,
+    .Init.NSSPMode = SPI_NSS_PULSE_DISABLE,
+    .Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA,
+    .Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN,
+    .Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN,
+    .Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE,
+    .Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE,
+    .Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE,
+    .Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_DISABLE,
+    .Init.IOSwap = SPI_IO_SWAP_DISABLE
+
+  },
+  .config = &stm32h7_spi2_config,
+  .irq = SPI2_IRQn
+};
+
+#endif /* SPI2 */

bsps/arm/stm32h7/spi/spi3.c

@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMSTM32H7
+ *
+ * @brief This source file contains the shared SPI3 peripheral configuration.
+ */
+
+/*
+ * Copyright (C) 2024 On-Line Applications Research (OAR) Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <stm32h7/hal.h>
+
+#ifdef SPI3
+
+/*
+ * On most stm32h7 CPUs (at least 743/747/750/753/755/757/7b3), SPI3 can occupy:
+ * AF5:
+ *   MOSI D6
+ * AF6:
+ *   NSS A4
+ *   NSS A15
+ *   SCK B3
+ *   SCK C10
+ *   MISO B4
+ *   MISO C11
+ *   MOSI C12
+ * AF7:
+ *   MOSI B2
+ *   MOSI B5
+ */
+stm32h7_spi_context stm32h7_spi3_instance = {
+  .spi = {
+    .Instance = SPI3,
+    /* Configure full-duplex SPI master with 8 bit data size */
+    .Init.Mode = SPI_MODE_MASTER,
+    .Init.Direction = SPI_DIRECTION_2LINES,
+    .Init.DataSize = SPI_DATASIZE_8BIT,
+    /* Configure mode 0 */
+    .Init.CLKPolarity = SPI_POLARITY_LOW,
+    .Init.CLKPhase = SPI_PHASE_1EDGE,
+    /* Assume software-controlled-chip-select */
+    .Init.NSS = SPI_NSS_SOFT,
+    .Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2,
+    .Init.FirstBit = SPI_FIRSTBIT_MSB,
+    .Init.TIMode = SPI_TIMODE_DISABLE,
+    /* Disable CRC calculation */
+    .Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE,
+    .Init.NSSPMode = SPI_NSS_PULSE_DISABLE,
+    .Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA,
+    .Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN,
+    .Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN,
+    .Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE,
+    .Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE,
+    .Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE,
+    .Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_DISABLE,
+    .Init.IOSwap = SPI_IO_SWAP_DISABLE
+
+  },
+  .config = &stm32h7_spi3_config,
+  .irq = SPI3_IRQn
+};
+
+#endif /* SPI3 */

bsps/arm/stm32h7/spi/spi4.c

@@ -0,0 +1,88 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMSTM32H7
+ *
+ * @brief This source file contains the shared SPI4 peripheral configuration.
+ */
+
+/*
+ * Copyright (C) 2024 On-Line Applications Research (OAR) Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <stm32h7/hal.h>
+
+#ifdef SPI4
+
+/*
+ * On most stm32h7 CPUs (at least 743/747/750/753/755/757/7b3), SPI4 can occupy:
+ * AF5:
+ *   NSS E4
+ *   NSS E11
+ *   SCK E2
+ *   SCK E12
+ *   MISO E5
+ *   MISO E13
+ *   MOSI E6
+ *   MOSI E14
+ */
+stm32h7_spi_context stm32h7_spi4_instance = {
+  .spi = {
+    .Instance = SPI4,
+    /* Configure full-duplex SPI master with 8 bit data size */
+    .Init.Mode = SPI_MODE_MASTER,
+    .Init.Direction = SPI_DIRECTION_2LINES,
+    .Init.DataSize = SPI_DATASIZE_8BIT,
+    /* Configure mode 0 */
+    .Init.CLKPolarity = SPI_POLARITY_LOW,
+    .Init.CLKPhase = SPI_PHASE_1EDGE,
+    /* Assume software-controlled-chip-select */
+    .Init.NSS = SPI_NSS_SOFT,
+    .Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2,
+    .Init.FirstBit = SPI_FIRSTBIT_MSB,
+    .Init.TIMode = SPI_TIMODE_DISABLE,
+    /* Disable CRC calculation */
+    .Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE,
+    .Init.NSSPMode = SPI_NSS_PULSE_DISABLE,
+    .Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA,
+    .Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN,
+    .Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN,
+    .Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE,
+    .Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE,
+    .Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE,
+    .Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_DISABLE,
+    .Init.IOSwap = SPI_IO_SWAP_DISABLE
+
+  },
+  .config = &stm32h7_spi4_config,
+  .irq = SPI4_IRQn
+};
+
+#endif /* SPI4 */

bsps/arm/stm32h7/spi/spi5.c

@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMSTM32H7
+ *
+ * @brief This source file contains the shared SPI5 peripheral configuration.
+ */
+
+/*
+ * Copyright (C) 2024 On-Line Applications Research (OAR) Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <stm32h7/hal.h>
+
+#ifdef SPI5
+
+/*
+ * On most stm32h7 CPUs (at least 743/747/750/753/755/757/7b3), SPI5 can occupy:
+ * AF5:
+ *   NSS F6
+ *   NSS H5
+ *   NSS K1
+ *   SCK F7
+ *   SCK H6
+ *   SCK K0
+ *   MISO F8
+ *   MISO H7
+ *   MISO J11
+ *   MOSI F9
+ *   MOSI F11
+ *   MOSI J10
+ */
+stm32h7_spi_context stm32h7_spi5_instance = {
+  .spi = {
+    .Instance = SPI5,
+    /* Configure full-duplex SPI master with 8 bit data size */
+    .Init.Mode = SPI_MODE_MASTER,
+    .Init.Direction = SPI_DIRECTION_2LINES,
+    .Init.DataSize = SPI_DATASIZE_8BIT,
+    /* Configure mode 0 */
+    .Init.CLKPolarity = SPI_POLARITY_LOW,
+    .Init.CLKPhase = SPI_PHASE_1EDGE,
+    /* Assume software-controlled-chip-select */
+    .Init.NSS = SPI_NSS_SOFT,
+    .Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2,
+    .Init.FirstBit = SPI_FIRSTBIT_MSB,
+    .Init.TIMode = SPI_TIMODE_DISABLE,
+    /* Disable CRC calculation */
+    .Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE,
+    .Init.NSSPMode = SPI_NSS_PULSE_DISABLE,
+    .Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA,
+    .Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN,
+    .Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN,
+    .Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE,
+    .Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE,
+    .Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE,
+    .Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_DISABLE,
+    .Init.IOSwap = SPI_IO_SWAP_DISABLE
+
+  },
+  .config = &stm32h7_spi5_config,
+  .irq = SPI5_IRQn
+};
+
+#endif /* SPI5 */

bsps/arm/stm32h7/spi/spi6.c

@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMSTM32H7
+ *
+ * @brief This source file contains the shared SPI6 peripheral configuration.
+ */
+
+/*
+ * Copyright (C) 2024 On-Line Applications Research (OAR) Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <stm32h7/hal.h>
+
+#ifdef SPI6
+
+/*
+ * On most stm32h7 CPUs (at least 743/747/750/753/755/757/7b3), SPI6 can occupy:
+ * AF5:
+ *   NSS G8
+ *   SCK G13
+ *   MISO G12
+ *   MOSI G14
+ * AF7:
+ *   NSS A15
+ * AF8:
+ *   NSS A4
+ *   SCK A5
+ *   SCK B3
+ *   MISO A6
+ *   MISO B4
+ *   MOSI A7
+ *   MOSI B5
+ */
+stm32h7_spi_context stm32h7_spi6_instance = {
+  .spi = {
+    .Instance = SPI6,
+    /* Configure full-duplex SPI master with 8 bit data size */
+    .Init.Mode = SPI_MODE_MASTER,
+    .Init.Direction = SPI_DIRECTION_2LINES,
+    .Init.DataSize = SPI_DATASIZE_8BIT,
+    /* Configure mode 0 */
+    .Init.CLKPolarity = SPI_POLARITY_LOW,
+    .Init.CLKPhase = SPI_PHASE_1EDGE,
+    /* Assume software-controlled-chip-select */
+    .Init.NSS = SPI_NSS_SOFT,
+    .Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2,
+    .Init.FirstBit = SPI_FIRSTBIT_MSB,
+    .Init.TIMode = SPI_TIMODE_DISABLE,
+    /* Disable CRC calculation */
+    .Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE,
+    .Init.NSSPMode = SPI_NSS_PULSE_DISABLE,
+    .Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA,
+    .Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN,
+    .Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN,
+    .Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE,
+    .Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE,
+    .Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE,
+    .Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_DISABLE,
+    .Init.IOSwap = SPI_IO_SWAP_DISABLE
+
+  },
+  .config = &stm32h7_spi6_config,
+  .irq = SPI6_IRQn
+};
+
+#endif /* SPI6 */

bsps/arm/stm32h7/start/stm32h7-hal-spi.c

@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMSTM32H7
+ *
+ * @brief This source file contains the SPI MSP initialization implementation.
+ */
+
+/*
+ * Copyright (C) 2024 On-Line Applications Research (OAR) Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <stm32h7/hal.h>
+
+void HAL_SPI_MspInit(SPI_HandleTypeDef *spi)
+{
+  stm32h7_spi_context *ctx;
+  const stm32h7_spi_config *config;
+  stm32h7_module_index index = stm32h7_get_module_index(spi->Instance);
+
+  ctx = RTEMS_CONTAINER_OF(spi, stm32h7_spi_context, spi);
+  config = ctx->config;
+  stm32h7_clk_enable(index);
+  stm32h7_gpio_init(&config->sck_gpio);
+  stm32h7_gpio_init(&config->miso_gpio);
+  stm32h7_gpio_init(&config->mosi_gpio);
+
+  /* Configure SPI CS GPIOs */
+  for (int i = 0; i < STM32H7_NUM_SOFT_CS; i++) {
+    if (config->cs_gpio[i].regs == NULL) {
+      continue;
+    }
+    /* TODO(kmoore) handle multiple pins in a single GPIO block */
+
+    /* configure GPIO CS and set output high */
+    stm32h7_gpio_init(&config->cs_gpio[i]);
+    /* Set all GPIO CS pins high */
+    HAL_GPIO_WritePin(config->cs_gpio[i].regs, config->cs_gpio[i].config.Pin, GPIO_PIN_SET);
+  }
+}

bsps/arm/stm32h7/start/stm32h7-hal.c

@@ -90,6 +90,18 @@ stm32h7_module_index stm32h7_get_module_index(const void *regs)
     case SDMMC2_BASE:
     case DLYB_SDMMC2_BASE:
       return STM32H7_MODULE_SDMMC2;
+    case SPI1_BASE:
+      return STM32H7_MODULE_SPI1;
+    case SPI2_BASE:
+      return STM32H7_MODULE_SPI2;
+    case SPI3_BASE:
+      return STM32H7_MODULE_SPI3;
+    case SPI4_BASE:
+      return STM32H7_MODULE_SPI4;
+    case SPI5_BASE:
+      return STM32H7_MODULE_SPI5;
+    case SPI6_BASE:
+      return STM32H7_MODULE_SPI6;
   }
 
   return STM32H7_MODULE_INVALID;
@@ -151,6 +163,12 @@ static const stm32h7_clk_info stm32h7_clk[] = {
 #endif
   [STM32H7_MODULE_SDMMC1] = { &RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN },
   [STM32H7_MODULE_SDMMC2] = { &RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN },
+  [STM32H7_MODULE_SPI1] = { &RCC->APB2ENR, RCC_APB2ENR_SPI1EN },
+  [STM32H7_MODULE_SPI2] = { &RCC->APB1LENR, RCC_APB1LENR_SPI2EN },
+  [STM32H7_MODULE_SPI3] = { &RCC->APB1LENR, RCC_APB1LENR_SPI3EN },
+  [STM32H7_MODULE_SPI4] = { &RCC->APB2ENR, RCC_APB2ENR_SPI4EN },
+  [STM32H7_MODULE_SPI5] = { &RCC->APB2ENR, RCC_APB2ENR_SPI5EN },
+  [STM32H7_MODULE_SPI6] = { &RCC->APB4ENR, RCC_APB4ENR_SPI6EN },
 };
 
 void stm32h7_clk_enable(stm32h7_module_index index)
@@ -234,6 +252,12 @@ static const stm32h7_clk_info stm32h7_clk_low_power[] = {
 #endif
   [STM32H7_MODULE_SDMMC1] = { &RCC->AHB3LPENR, RCC_AHB3LPENR_SDMMC1LPEN },
   [STM32H7_MODULE_SDMMC2] = { &RCC->AHB2LPENR, RCC_AHB2LPENR_SDMMC2LPEN },
+  [STM32H7_MODULE_SPI1] = { &RCC->APB2LPENR, RCC_APB2LPENR_SPI1LPEN },
+  [STM32H7_MODULE_SPI2] = { &RCC->APB1LLPENR, RCC_APB1LLPENR_SPI2LPEN },
+  [STM32H7_MODULE_SPI3] = { &RCC->APB1LLPENR, RCC_APB1LLPENR_SPI3LPEN },
+  [STM32H7_MODULE_SPI4] = { &RCC->APB2LPENR, RCC_APB2LPENR_SPI4LPEN },
+  [STM32H7_MODULE_SPI5] = { &RCC->APB2LPENR, RCC_APB2LPENR_SPI5LPEN },
+  [STM32H7_MODULE_SPI6] = { &RCC->APB4LPENR, RCC_APB4LPENR_SPI6LPEN },
 };
 
 void stm32h7_clk_low_power_enable(stm32h7_module_index index)

bsps/include/bsp/fatal.h

@@ -224,6 +224,9 @@ typedef enum {
 
   /* AArch64 fatal codes */
   AARCH64_FATAL_MMU_CANNOT_MAP_BLOCK = BSP_FATAL_CODE_BLOCK(19),
+
+  /* STM32H7 fatal codes */
+  STM32H7_FATAL_MMU_CANNOT_REGISTER_SPI = BSP_FATAL_CODE_BLOCK(20),
 } bsp_fatal_code;
 
 RTEMS_NO_RETURN static inline void

spec/build/bsps/arm/stm32h7/bspstm32h750b-dk.yml

@@ -21,5 +21,6 @@ source:
 - bsps/arm/stm32h7/boards/stm/stm32h747i-disco/stm32h7-config-osc.c
 - bsps/arm/stm32h7/boards/stm/stm32h750b-dk/stm32h7-config-per.c
 - bsps/arm/stm32h7/boards/stm/stm32h750b-dk/system_stm32h7xx.c
+- bsps/arm/stm32h7/boards/stm/stm32h750b-dk/spi2-cfg.c
 - bsps/arm/shared/cache/cache-v7m.c
 type: build

spec/build/bsps/arm/stm32h7/grp.yml

@@ -26,6 +26,18 @@ links:
   uid: optenmpualign
 - role: build-dependency
   uid: ../optmpuctrl
+- role: build-dependency
+  uid: optenspi1
+- role: build-dependency
+  uid: optenspi2
+- role: build-dependency
+  uid: optenspi3
+- role: build-dependency
+  uid: optenspi4
+- role: build-dependency
+  uid: optenspi5
+- role: build-dependency
+  uid: optenspi6
 - role: build-dependency
   uid: optenuart4
 - role: build-dependency

spec/build/bsps/arm/stm32h7/obj.yml

@@ -333,6 +333,13 @@ source:
 - bsps/arm/stm32h7/hal/stm32h7xx_ll_usart.c
 - bsps/arm/stm32h7/hal/stm32h7xx_ll_usb.c
 - bsps/arm/stm32h7/hal/stm32h7xx_ll_utils.c
+- bsps/arm/stm32h7/spi/spi-support.c
+- bsps/arm/stm32h7/spi/spi1.c
+- bsps/arm/stm32h7/spi/spi2.c
+- bsps/arm/stm32h7/spi/spi3.c
+- bsps/arm/stm32h7/spi/spi4.c
+- bsps/arm/stm32h7/spi/spi5.c
+- bsps/arm/stm32h7/spi/spi6.c
 - bsps/arm/stm32h7/start/bspstart.c
 - bsps/arm/stm32h7/start/bspstarthooks.c
 - bsps/arm/stm32h7/start/getentropy-rng.c
@@ -341,6 +348,7 @@ source:
 - bsps/arm/stm32h7/start/stm32h7-config-pwr.c
 - bsps/arm/stm32h7/start/stm32h7-hal-eth.c
 - bsps/arm/stm32h7/start/stm32h7-hal-sdmmc.c
+- bsps/arm/stm32h7/start/stm32h7-hal-spi.c
 - bsps/arm/stm32h7/start/stm32h7-hal-uart.c
 - bsps/arm/stm32h7/start/stm32h7-hal.c
 - bsps/shared/dev/btimer/btimer-cpucounter.c

spec/build/bsps/arm/stm32h7/optenspi1.yml

@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-boolean: null
+- define-condition: null
+build-type: option
+copyrights:
+- Copyright (C) 2024 On-Line Applications Research (OAR) Corporation
+default:
+- enabled-by: true
+  value: false
+description: |
+  Enable SPI1 device for usage by the application.
+enabled-by: true
+format: '{}'
+links: []
+name: STM32H7_SPI1_ENABLE
+type: build

spec/build/bsps/arm/stm32h7/optenspi2.yml

@@ -0,0 +1,20 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-boolean: null
+- define-condition: null
+build-type: option
+copyrights:
+- Copyright (C) 2024 On-Line Applications Research (OAR) Corporation
+default:
+- enabled-by:
+  - arm/stm32h750b-dk
+  value: true
+- enabled-by: true
+  value: false
+description: |
+  Enable SPI2 device for usage by the application.
+enabled-by: true
+format: '{}'
+links: []
+name: STM32H7_SPI2_ENABLE
+type: build

spec/build/bsps/arm/stm32h7/optenspi3.yml

@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-boolean: null
+- define-condition: null
+build-type: option
+copyrights:
+- Copyright (C) 2024 On-Line Applications Research (OAR) Corporation
+default:
+- enabled-by: true
+  value: false
+description: |
+  Enable SPI3 device for usage by the application.
+enabled-by: true
+format: '{}'
+links: []
+name: STM32H7_SPI3_ENABLE
+type: build

spec/build/bsps/arm/stm32h7/optenspi4.yml

@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-boolean: null
+- define-condition: null
+build-type: option
+copyrights:
+- Copyright (C) 2024 On-Line Applications Research (OAR) Corporation
+default:
+- enabled-by: true
+  value: false
+description: |
+  Enable SPI4 device for usage by the application.
+enabled-by: true
+format: '{}'
+links: []
+name: STM32H7_SPI4_ENABLE
+type: build

spec/build/bsps/arm/stm32h7/optenspi5.yml

@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-boolean: null
+- define-condition: null
+build-type: option
+copyrights:
+- Copyright (C) 2024 On-Line Applications Research (OAR) Corporation
+default:
+- enabled-by: true
+  value: false
+description: |
+  Enable SPI5 device for usage by the application.
+enabled-by: true
+format: '{}'
+links: []
+name: STM32H7_SPI5_ENABLE
+type: build

spec/build/bsps/arm/stm32h7/optenspi6.yml

@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-boolean: null
+- define-condition: null
+build-type: option
+copyrights:
+- Copyright (C) 2024 On-Line Applications Research (OAR) Corporation
+default:
+- enabled-by: true
+  value: false
+description: |
+  Enable SPI6 device for usage by the application.
+enabled-by: true
+format: '{}'
+links: []
+name: STM32H7_SPI6_ENABLE
+type: build