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Amar Takhar
2024-07-28 16:37:58 -04:00
parent 807070a696
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47
bsps/m68k/av5282/README → bsps/m68k/av5282/README.md
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@@ -1,14 +1,15 @@
Description: Avnet MCF5282
============
Avnet MCF5282
=============
```
CPU: MCF5282, 59MHz
RAM: 16M
ROM: 8M
```
This is an evaluation board that uses the MCF5282 Coldfire CPU. It runs at about 59MHz scaled
from a 7.372MHz crystal and is integrated with the Avnet designed AvBus.
ACKNOWLEDGEMENTS:
=================
ACKNOWLEDGEMENTS
----------------
This BSP is based on the work of:
D. Peter Siddons
Brett Swimley
@@ -16,6 +17,7 @@ This BSP is based on the work of:
Eric Norum
Mike Bertosh
```
BSP NAME: av5282
BOARD: Avnet MCF5282
CPU FAMILY: ColdFire 5282
@@ -23,9 +25,12 @@ CPU: MCF5282
COPROCESSORS: N/A
DEBUG MONITOR: AVMON
```
PERIPHERALS
===========
-----------
```
TIMERS: Four PIT (RTEMS clock is PIT3), Four Timers
RESOLUTION: 10 microsecond
SERIAL PORTS: Internal UART 1, 2 and 3
@@ -34,27 +39,33 @@ DMA: none
VIDEO: none
SCSI: none
NETWORKING: Internal 10/100MHz FEC
```
DRIVER INFORMATION
==================
------------------
```
CLOCK DRIVER: PIT3
IOSUPP DRIVER: none
SHMSUPP: none
TIMER DRIVER: TIMER3
TTY DRIVER: UART1, 2 and 3
```
STDIO
=====
-----
```
PORT: UART1 Terminal
ELECTRICAL: RS-232
BAUD: 19200
BITS PER CHARACTER: 8
PARITY: None
STOP BITS: 1
```
Memory map
==========
Memory map as set up by AVMON bootstrap and BSP initialization
```
+--------------------------------------------------+
0000 0000 | 16 MByte SDRAM | 00FF FFFF
0100 0000 | --------------------------------------------- |
@@ -100,11 +111,12 @@ FF80 0000 | External 8 MByte Flash memory
. .
| | FFFF FFFF
+--------------------------------------------------+
```
============================================================================
Interrupt map
Interrupt map
=============
```
+-----+-----------------------------------------------------------------------+
| | PRIORITY |
+-----+--------+--------+--------+--------+--------+--------+--------+--------+
@@ -124,13 +136,11 @@ FF80 0000 | External 8 MByte Flash memory
+-----+--------+--------+--------+--------+--------+--------+--------+--------+
| 1 | | | | | | | | |
+-----+--------+--------+--------+--------+--------+--------+--------+--------+
============================================================================
```
TIMING TESTS
**************************
------------
```
*** TIME TEST 1 ***
rtems_semaphore_create 28
rtems_semaphore_delete 31
@@ -435,3 +445,4 @@ rtems_rate_monotonic_cancel 0
rtems_rate_monotonic_period 0
rtems_multiprocessing_announce 0
*** END OF TIME OVERHEAD ***
```

32
bsps/m68k/csb360/README → bsps/m68k/csb360/README.md
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@@ -1,9 +1,10 @@
#
# README for CSB360
#
# Copyright (C) 2004 by Cogent Computer Systems
# Author: Jay Monkman <jtm@lopingdog.com>
CSB360
======
Copyright (C) 2004 by Cogent Computer Systems
Author: Jay Monkman <jtm@lopingdog.com>
```
BSP NAME: csb360
BOARD: Cogent CSB360
BUS: none
@@ -11,9 +12,12 @@ CPU FAMILY: Motorola ColdFire MCF5272
COPROCESSORS: none
MODE: not applicable
DEBUG MONITOR: none (Hardware provides BDM)
```
PERIPHERALS
===========
-----------
```
TIMERS:
RESOLUTION:
SERIAL PORTS:
@@ -24,25 +28,27 @@ VIDEO:
SCSI:
NETWORKING:
I2C BUS:
```
DRIVER INFORMATION
==================
------------------
```
CLOCK DRIVER:
IOSUPP DRIVER:
SHMSUPP:
TIMER DRIVER:
I2C DRIVER:
```
STDIO
=====
-----
```
PORT:
ELECTRICAL:
BAUD:
BITS PER CHARACTER:
PARITY:
STOP BITS:
NOTES
=====
```

62
bsps/m68k/gen68340/README → bsps/m68k/gen68340/README.md
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@@ -1,27 +1,25 @@
#
# This package requires a version of GCC that supports the `-mcpu32' option.
#
gen68340
========
#
# Please send any comments, improvements, or bug reports to:
# Geoffroy Montel
# g_montel@yahoo.com
#
This package requires a version of GCC that supports the `-mcpu32` option.
#
# This board support package works both MC68340 and MC68349 systems.
#
# Special console features:
# - support of polled and interrupts mode (both MC68340 and MC68349)
# - support of FIFO FULL mode (only for MC68340, the MC68349 doesn't have any timer, so
# you may write your own timer driver if you have an external one)
#
# The type of the board is automatically recognised in the initialization sequence.
#
# WARNING: there's still no network driver!
# I hope it will come in the next RTEMS version!
#
Please send any comments, improvements, or bug reports to:
Geoffroy Montel
g_montel@yahoo.com
This board support package works both MC68340 and MC68349 systems.
Special console features:
- support of polled and interrupts mode (both MC68340 and MC68349)
- support of FIFO FULL mode (only for MC68340, the MC68349 doesn't have any timer, so
you may write your own timer driver if you have an external one)
The type of the board is automatically recognised in the initialization sequence.
WARNING: there's still no network driver!
I hope it will come in the next RTEMS version!
```
BSP NAME: gen68340
BOARD: Generic 68360 as described in Motorola MC68340 User's Manual
BOARD: Home made MC68340 board
@@ -34,8 +32,11 @@ MODE: not applicable
DEBUG MONITOR: none (Hardware provides BDM)
DEBUG SETUP: EST Vision Ice
```
PERIPHERALS
===========
-----------
```
TIMERS: two timers
RESOLUTION: one microsecond
SERIAL PORTS: 2 channel on the UART
@@ -44,32 +45,40 @@ DMA: yes
VIDEO: none
SCSI: none
NETWORKING: Ethernet on SCC1.
```
DRIVER INFORMATION
==================
------------------
```
CLOCK DRIVER:
IOSUPP DRIVER:
SHMSUPP: none
TIMER DRIVER: Timer 1 for timing test suites
Timer 2 for console's FIFO FULL mode
```
STDIO
=====
-----
```
PORT: 1
ELECTRICAL:
BAUD: 9600
BITS PER CHARACTER: 8
PARITY: None
STOP BITS: 1
```
NOTES
=====
Board description
-----------------
```
clock rate: 25 MHz
bus width: 16-bit PROM, 32-bit DRAM
ROM: To 1 MByte, 60 nsec (0 wait states), chip select 0
RAM: 1 to 16 MByte DRAM SIMM, 60 nsec (0 wait states), parity or nonparity
```
Host System
-----------
@@ -79,4 +88,3 @@ Verification (Standalone 68360)
-------------------------------
Single processor tests: Passed
Multi-processor tests: not applicable

64
bsps/m68k/gen68360/README → bsps/m68k/gen68360/README.md
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@@ -1,30 +1,28 @@
#
# This package requires a version of GCC that supports the `-mcpu32' option.
#
gen68360
========
#
# Copyright (c) 1996 Eric Norum <eric@norum.ca>
#
This package requires a version of GCC that supports the `-mcpu32` option.
#
# This board support package works with several different versions of
# MC68360 systems. See the conditional-compile tests in startup/init68360.c
# for examples.
#
# Decisions made at compile time include:
# - If the CPU is a member of the 68040 family, the BSP is
# compiled for a generic 68040/68360 system as described
# in Chapter 9 of the MC68360 User's Manual. This version
# can be used with the Arnewsh SBC360 card.
# - If the preprocessor symbol M68360_ATLAS_HSB is defined,
# the BSP is compiled for an Atlas HSB card.
# - If the preprocessor symbol M68360_IMD_PGH is defined,
# the BSP is compiled for an IMD PGH360 card.
# - Otherwise, the BSP is compiled for a generic 68360 system
# as described in Chapter 9 of the MC68360 User's Manual. This
# version works with the Atlas ACE360 card.
#
Copyright (c) 1996 Eric Norum <eric@norum.ca>
This board support package works with several different versions of
MC68360 systems. See the conditional-compile tests in startup/init68360.c
for examples.
Decisions made at compile time include:
- If the CPU is a member of the 68040 family, the BSP is
compiled for a generic 68040/68360 system as described
in Chapter 9 of the MC68360 User's Manual. This version
can be used with the Arnewsh SBC360 card.
- If the preprocessor symbol M68360_ATLAS_HSB is defined,
the BSP is compiled for an Atlas HSB card.
- If the preprocessor symbol M68360_IMD_PGH is defined,
the BSP is compiled for an IMD PGH360 card.
- Otherwise, the BSP is compiled for a generic 68360 system
as described in Chapter 9 of the MC68360 User's Manual. This
version works with the Atlas ACE360 card.
```
BSP NAME: gen68360 or gen68360_040
BOARD: Generic 68360 as described in Motorola MC68360 User's Manual
BOARD: Atlas Computer Equipment Inc. High Speed Bridge (HSB)
@@ -37,9 +35,11 @@ COPROCESSORS: none
MODE: not applicable
DEBUG MONITOR: none (Hardware provides BDM)
```
PERIPHERALS
===========
-----------
```
TIMERS: PIT, Watchdog, 4 general purpose, 16 RISC
RESOLUTION: one microsecond
SERIAL PORTS: 4 SCC, 2 SMC, 1 SPI
@@ -48,25 +48,27 @@ DMA: Each serial port, 2 general purpose
VIDEO: none
SCSI: none
NETWORKING: Ethernet on SCC1.
```
DRIVER INFORMATION
==================
------------------
```
CLOCK DRIVER: Programmable Interval Timer
IOSUPP DRIVER: Serial Management Controller 1
SHMSUPP: none
TIMER DRIVER: Timer 1
```
STDIO
=====
-----
```
PORT: SMC1
ELECTRICAL: EIA-232 (if board supplies level shifter)
BAUD: 9600
BITS PER CHARACTER: 8
PARITY: None
STOP BITS: 1
NOTES
=====
```
Board description
-----------------
@@ -88,6 +90,7 @@ OPENSTEP 4.2 (Intel and Motorola), Solaris 2.5, Linux 2.0.29
Verification (Standalone 68360)
-------------------------------
```
Single processor tests: Passed
Multi-processort tests: not applicable
Timing tests:
@@ -265,6 +268,7 @@ Network tests:
TCP throughput (as measured by ttcp):
Receive: 1081 kbytes/sec
Transmit: 953 kbytes/sec
```
Porting
-------

94
bsps/m68k/genmcf548x/README → bsps/m68k/genmcf548x/README.md
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@@ -1,23 +1,23 @@
# RTEMS generic mcf548x BSP
#
# Copyright (c) 2007 embedded brains GmbH & Co. KG
#
# Parts of the code has been derived from the "dBUG source code"
# package Freescale is providing for M548X EVBs. The usage of
# the modified or unmodified code and it's integration into the
# generic mcf548x BSP has been done according to the Freescale
# license terms.
#
# The Freescale license terms can be reviewed in the file
#
# LICENSE.Freescale
#
# The generic mcf548x BSP has been developed on the basic
# structures and modules of the av5282 BSP.
#
# The license and distribution terms for this file may be
# found in the file LICENSE in this distribution or at
# http://www.rtems.org/license/LICENSE.
mcf548x
=======
Copyright (c) 2007 embedded brains GmbH & Co. KG
Parts of the code has been derived from the "dBUG source code"
package Freescale is providing for M548X EVBs. The usage of
the modified or unmodified code and it's integration into the
generic mcf548x BSP has been done according to the Freescale
license terms.
The Freescale license terms can be reviewed in the file
LICENSE.Freescale
The generic mcf548x BSP has been developed on the basic
structures and modules of the av5282 BSP.
The license and distribution terms for this file may be
found in the file LICENSE in this distribution or at
http://www.rtems.org/license/LICENSE.
Description: Generic mcf548x BSP
@@ -25,8 +25,10 @@ Description: Generic mcf548x BSP
The genmcf548x supports several boards based on the Freescale MCF547x/8x
ColdFire microcontrollers
Supported Hardware: mcf5484FireEngine
=============================
-----------------------------
```
CPU: MCF548x, 200MHz
XLB: 100 MHz, which is the main clock for all onchip peripherals
RAM: 64M (m5484FireEngine)
@@ -35,9 +37,12 @@ Code-Flash: 16M (m5484FireEngine)
Core-SRAM: 8K
Core-SysRAM: 32K
Boot-Monitor:None
```
Supported Hardware: COBRA5475
=============================
-----------------------------
```
CPU: MCF5475, 266MHz
XLB: 132 MHz, which is the main clock for all onchip peripherals
RAM: 128M
@@ -45,10 +50,10 @@ Boot-Flash: 32M
Core-SRAM: 8K
Core-SysRAM: 32K
Boot-Monitor:DBug
```
ACKNOWLEDGEMENTS:
=================
-----------------
This BSP is based on the
av5282 BSP
@@ -61,30 +66,41 @@ and the work of
Eric Norum
Mike Bertosh
BSP INFO:
=========
---------
```
BSP NAME: genmcf548x
BOARD: various MCF547x/8x based boards
CPU FAMILY: ColdFire 548x
CPU: MCF5475/MCF5484
FPU: MCF548x FPU, context switch supported by RTEMS multitasking
EMAC: MCF548x EMAC context switch supported by RTEMS multitasking (handeld together with FPU context)
```
PERIPHERALS
===========
-----------
```
TIMERS: 2 slice timers, 4 general purpose timers (SLT0 is used for RTEMS clock, SLT1 is used for diagnostic pupose)
RESOLUTION: System tick 10 millieconds (via SLT0)
SERIAL PORTS: Internal PSC 0-3
NETWORKING: Internal 10/100MHz FEC on two channels
```
DRIVER INFORMATION
==================
------------------
```
CLOCK DRIVER: SLT0
TIMER DRIVER: SLT1 (diagnostics)
TTY DRIVER: PSC0-3
```
STDIO
=====
-----
```
PORT: PSC0 (UART mode) terminal
ELECTRICAL: RS-232
BAUD: 9600
@@ -92,10 +108,12 @@ BITS PER CHARACTER: 8
PARITY: None
STOP BITS: 1
MODES: Interrupt driven (polled mode alternatively)
```
----------------------------------------------------------------------
Memory map
==========
```
Memory map of m5484FireEngine as set up by BSP initialization:
+--------------------------------------------------+
@@ -137,10 +155,9 @@ FF80 0000 | External 8 MByte Flash memory | FF9F FFFF
. .
| | FFFF FFFF
+--------------------------------------------------+
```
----------------------------------------------------------------------
```
Memory map for COBRA5475 as set up by DBug:
+--------------------------------------------------+
@@ -172,11 +189,12 @@ FF00 0000 | 8K core SRAM (internal) |
. .
| | FF00 1FFF
+--------------------------------------------------+
```
============================================================================
Interrupt map
Interrupt map
=============
```
+-----+-----------------------------------------------------------------------+
| | PRIORITY |
+-----+--------+--------+--------+--------+--------+--------+--------+--------+
@@ -196,10 +214,10 @@ FF00 0000 | 8K core SRAM (internal) |
+-----+--------+--------+--------+--------+--------+--------+--------+--------+
| 1 | | | | | | | | |
+-----+--------+--------+--------+--------+--------+--------+--------+--------+
```
============================================================================
TIMING TESTS
**************************
------------
tbd.

101
bsps/m68k/mcf5206elite/README
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@@ -1,101 +0,0 @@
#
# README for MCF5206eLITE Board Support Package
#
# Copyright (C) 2000,2001 OKTET Ltd., St.-Petersburg, Russia
# Author: Victor V. Vengerov <vvv@oktet.ru>
#
# The license and distribution terms for this file may be
# found in the file LICENSE in this distribution or at
# http://www.rtems.org/license/LICENSE.
#
# This board support package works with MCF5206eLITE evaluation board with
# Motorola Coldfire MCF5206e CPU.
#
# Many thanks to Balanced Audio Technology (http://www.balanced.com),
# company which donates MCF5206eLITE evaluation board, P&E Coldfire BDM
# interface and provides support for development of this BSP and generic
# MCF5206 CPU code.
#
# Decisions made at compile time include:
#
# Decisions to be made a link-edit time are:
# - The size of memory allocator heap. By default, all available
# memory allocated for the heap. To specify amount of memory
# available for heap:
# LDFLAGS += -Wl,--defsym -Wl,HeapSize=xxx
#
# - The frequency of system clock oscillator. By default, this frequency
# is 54MHz. To select other clock frequency for your application, put
# line like this in application Makefile:
# LDFLAGS += -qclock=40000000
#
# - Select between RAM or ROM images. By default, RAM image generated
# which may be loaded starting from address 0x30000000 to the RAM.
# To prepare image intended to be stored in ROM, put the following
# line to the application Makefile:
# LDFLAGS += -qflash
#
# You may select other memory configuration providing your own
# linker script.
#
BSP NAME: mcf5206elite
BOARD: MCF5206eLITE Evaluation Board
BUS: none
CPU FAMILY: Motorola ColdFire
COPROCESSORS: none
MODE: not applicable
DEBUG MONITOR: none (Hardware provides BDM)
PERIPHERALS
===========
TIMERS: PIT, Watchdog(disabled)
RESOLUTION: one microsecond
SERIAL PORTS: 2 UART
REAL-TIME CLOCK: DS1307
NVRAM: DS1307
DMA: 2 general purpose
VIDEO: none
SCSI: none
NETWORKING: none
I2C BUS: MCF5206e MBUS module
DRIVER INFORMATION
==================
CLOCK DRIVER: Programmable Interval Timer
IOSUPP DRIVER: UART 1
SHMSUPP: none
TIMER DRIVER: yes
I2C DRIVER: yes
STDIO
=====
PORT: UART 1
ELECTRICAL: EIA-232
BAUD: 19200
BITS PER CHARACTER: 8
PARITY: None
STOP BITS: 1
NOTES
=====
Board description
-----------------
clock rate: 54 MHz default (other oscillator can be installed)
bus width: 16-bit PROM, 32-bit external SRAM
ROM: Flash memory device AM29LV800BB, 1 MByte, 3 wait states,
chip select 0
RAM: Static RAM 2xMCM69F737TQ, 1 MByte, 1 wait state, chip select 2
Host System
-----------
RedHat 6.2 (Linux 2.2.14), RedHat 7.0 (Linux 2.2.17)
Verification
------------
Single processor tests: passed
Multi-processort tests: not applicable
Timing tests: passed

107
bsps/m68k/mcf5206elite/README.md Normal file
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@@ -0,0 +1,107 @@
MCF5206eLITE
============
Copyright (C) 2000,2001 OKTET Ltd., St.-Petersburg, Russia
Author: Victor V. Vengerov <vvv@oktet.ru>
The license and distribution terms for this file may be
found in the file LICENSE in this distribution or at
http://www.rtems.org/license/LICENSE.
This board support package works with MCF5206eLITE evaluation board with
Motorola Coldfire MCF5206e CPU.
Many thanks to Balanced Audio Technology (http://www.balanced.com),
company which donates MCF5206eLITE evaluation board, P&E Coldfire BDM
interface and provides support for development of this BSP and generic
MCF5206 CPU code.
Decisions made at compile time include:
Decisions to be made a link-edit time are:
- The size of memory allocator heap. By default, all available
memory allocated for the heap. To specify amount of memory
available for heap:
LDFLAGS += -Wl,--defsym -Wl,HeapSize=xxx
- The frequency of system clock oscillator. By default, this frequency
is 54MHz. To select other clock frequency for your application, put
line like this in application Makefile:
LDFLAGS += -qclock=40000000
- Select between RAM or ROM images. By default, RAM image generated
which may be loaded starting from address 0x30000000 to the RAM.
To prepare image intended to be stored in ROM, put the following
line to the application Makefile:
LDFLAGS += -qflash
You may select other memory configuration providing your own
linker script.
```
BSP NAME: mcf5206elite
BOARD: MCF5206eLITE Evaluation Board
BUS: none
CPU FAMILY: Motorola ColdFire
COPROCESSORS: none
MODE: not applicable
DEBUG MONITOR: none (Hardware provides BDM)
```
PERIPHERALS
-----------
```
TIMERS: PIT, Watchdog(disabled)
RESOLUTION: one microsecond
SERIAL PORTS: 2 UART
REAL-TIME CLOCK: DS1307
NVRAM: DS1307
DMA: 2 general purpose
VIDEO: none
SCSI: none
NETWORKING: none
I2C BUS: MCF5206e MBUS module
```
DRIVER INFORMATION
------------------
```
CLOCK DRIVER: Programmable Interval Timer
IOSUPP DRIVER: UART 1
SHMSUPP: none
TIMER DRIVER: yes
I2C DRIVER: yes
```
STDIO
-----
```
PORT: UART 1
ELECTRICAL: EIA-232
BAUD: 19200
BITS PER CHARACTER: 8
PARITY: None
STOP BITS: 1
```
Board description
-----------------
clock rate: 54 MHz default (other oscillator can be installed)
bus width: 16-bit PROM, 32-bit external SRAM
ROM: Flash memory device AM29LV800BB, 1 MByte, 3 wait states,
chip select 0
RAM: Static RAM 2xMCM69F737TQ, 1 MByte, 1 wait state, chip select 2
Host System
-----------
RedHat 6.2 (Linux 2.2.14), RedHat 7.0 (Linux 2.2.17)
Verification
------------
Single processor tests: passed
Multi-processort tests: not applicable
Timing tests: passed

28
bsps/m68k/mcf52235/README → bsps/m68k/mcf52235/README.md
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@@ -1,5 +1,6 @@
Description: Motorola MCF52235EVB
============================================================================
Motorola MCF52235EVB
====================
CPU: MCF52235, 60MHz
SRAM: 32K
FLASH: 256K
@@ -7,14 +8,17 @@ FLASH: 256K
This is a Motorola evaluation board that uses the MCF52235 Coldfire CPU.
This board is running at 60MHz scaled from a 25MHz oscillator.
============================================================================
NOTES:
Currently this BSP must be configured with most RTEMS features turned
off as RAM usage is too high.
Configure as follows:
```shell
configure --target=m68k-rtems4.XXX --enable-rtemsbsp=mcf52235 \
```
To get the tests to compile (but not run) change the linkcmds to specify
a larger sram memory region (256K works). This of course will let you
@@ -26,24 +30,27 @@ you need for this BSP!
In you project before you include confdefs.h, define some or all of the
following:
```c
#define CONFIGURE_INIT_TASK_STACK_SIZE x
#define CONFIGURE_MINIMUM_TASK_STACK_SIZE x
#define CONFIGURE_INTERRUPT_STACK_SIZE x
```
Note that the default stack size is 1K
Note that the default number of priorities is 15
============================================================================
TODO:
*) Add drivers for I2C, ADC, FEC
*) Support for LWIP
*) Recover the 1K stack space reserved in linkcmds used for board startup.
============================================================================
Interrupt map
Interrupt map
-------------
```
+-----+-----------------------------------------------------------------------+
| | PRIORITY |
+-----+--------+--------+--------+--------+--------+--------+--------+--------+
@@ -63,9 +70,11 @@ TODO:
+-----+--------+--------+--------+--------+--------+--------+--------+--------+
| 1 | | | | | | | | |
+-----+--------+--------+--------+--------+--------+--------+--------+--------+
```
============================================================================
Timing tests
------------
```
*** TIME TEST 1 ***
rtems_semaphore_create 8
rtems_semaphore_delete 10
@@ -148,5 +157,4 @@ rtems_rate_monotonic_cancel 0
rtems_rate_monotonic_period 0
rtems_multiprocessing_announce 0
*** END OF TIME OVERHEAD ***
```

25
bsps/m68k/mcf5225x/README → bsps/m68k/mcf5225x/README.md
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@@ -1,5 +1,7 @@
mcf5225x
========
Description: embed-it dpu
============================================================================
CPU: MCF52259, ??MHz
SRAM: 64K
FLASH: 512K
@@ -10,15 +12,17 @@ This board is running at ??MHz scaled from the internal relocation 8MHz oscillat
OLD-STUFF from MCF52235 EVB ... we have to change it ...
============================================================================
NOTES:
Currently this BSP must be configured with most RTEMS features turned
off as RAM usage is too high.
Configure as follows:
configure --target=m68k-rtems4.XXX --enable-rtemsbsp=mcf52235 ...
```shell
configure --target=m68k-rtems4.XXX --enable-rtemsbsp=mcf52235 ...
```
To get the tests to compile (but not run) change the linkcmds to specify
a larger sram memory region (256K works). This of course will let you
compile all tests, but many or most of them wont run.
@@ -36,17 +40,18 @@ following:
Note that the default stack size is 1K
Note that the default number of priorities is 15
============================================================================
TODO:
*) Add drivers for I2C, ADC, FEC
*) Support for LWIP
*) Recover the 1K stack space reserved in linkcmds used for board startup.
============================================================================
Interrupt map
Interrupt map
-------------
```
+-----+-----------------------------------------------------------------------+
| | PRIORITY |
+-----+--------+--------+--------+--------+--------+--------+--------+--------+
@@ -66,9 +71,12 @@ TODO:
+-----+--------+--------+--------+--------+--------+--------+--------+--------+
| 1 | | | | | | | | |
+-----+--------+--------+--------+--------+--------+--------+--------+--------+
```
============================================================================
Timing tests
------------
```
*** TIME TEST 1 ***
rtems_semaphore_create 8
rtems_semaphore_delete 10
@@ -151,5 +159,4 @@ rtems_rate_monotonic_cancel 0
rtems_rate_monotonic_period 0
rtems_multiprocessing_announce 0
*** END OF TIME OVERHEAD ***
```

42
bsps/m68k/mcf5235/README → bsps/m68k/mcf5235/README.md
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@@ -1,5 +1,5 @@
Description: Motorola MCF5235EVB
============
Motorola MCF5235EVB
===================
CPU: MCF5235, 150MHz
RAM: 16M
ROM: 2M
@@ -15,15 +15,17 @@ LDFLAGS += -qnolinkcmds -T linkcmdsflash
Note: This BSP has also been tested with the Freescale / Axiom Manufacturing
(M5235BCC Business Card Controller) evaluation board.
ACKNOWLEDGEMENTS:
=================
-----------------
This BSP is heavily based on the work of:
D. Peter Siddons
Brett Swimley
Jay Monkman
Eric Norum
Mike Bertosh
```
BSP NAME: mcf5235
BOARD: Motorola MCF5235EVB
CPU FAMILY: ColdFire 5235
@@ -31,9 +33,11 @@ CPU: MCF5235
COPROCESSORS: N/A
DEBUG MONITOR: dBUG
```
PERIPHERALS
===========
-----------
```
TIMERS: Four PIT (RTEMS clock is PIT3), Four Timers
RESOLUTION: 10 microsecond
SERIAL PORTS: Internal UART 1, 2 and 3
@@ -42,28 +46,34 @@ DMA: none
VIDEO: none
SCSI: none
NETWORKING: Internal 10/100MHz FEC
```
DRIVER INFORMATION
==================
------------------
```
CLOCK DRIVER: PIT3
IOSUPP DRIVER: none
SHMSUPP: none
TIMER DRIVER: TIMER3
TTY DRIVER: UART1, 2 and 3
```
STDIO
=====
-----
```
PORT: UART0 Terminal
ELECTRICAL: RS-232
BAUD: 19200
BITS PER CHARACTER: 8
PARITY: None
STOP BITS: 1
```
Memory map
----------
Memory map as set up by dBUG bootstrap and BSP initialization
```
+--------------------------------------------------+
0000 0000 | 16 MByte SDRAM | 00FF FFFF
0100 0000 | --------------------------------------------- |
@@ -110,10 +120,11 @@ FFE0 0000 | External 4 MByte Flash |
. .
| | FFFF FFFF
+--------------------------------------------------+
```
============================================================================
Interrupt map
Interrupt map
-------------
```
+-----+-----------------------------------------------------------------------+
| | PRIORITY |
+-----+--------+--------+--------+--------+--------+--------+--------+--------+
@@ -133,9 +144,11 @@ FFE0 0000 | External 4 MByte Flash |
+-----+--------+--------+--------+--------+--------+--------+--------+--------+
| 1 | | | | | | | | |
+-----+--------+--------+--------+--------+--------+--------+--------+--------+
```
============================================================================
TIMING TESTS
Timing tests
------------
```
************************************
*** TIME TEST 1 ***
rtems_semaphore_create 12
@@ -441,3 +454,4 @@ rtems_rate_monotonic_cancel 0
rtems_rate_monotonic_period 0
rtems_multiprocessing_announce 0
*** END OF TIME OVERHEAD ***
```

32
bsps/m68k/mcf5329/README → bsps/m68k/mcf5329/README.md
View File

@@ -1,29 +1,33 @@
Description: Motorola MCF5329EVB Zoom + (LogicPD)
============
Motorola MCF5329EVB
===================
Zoom + (LogicPD)
```
CPU: MCF5329, 240MHz
CORESRAM: 32K
FLASH: 2M
DRAM: 32M
```
This is a Motorola Zoom evaluation board that uses the MCF5329 Coldfire CPU on
a logicPD card. This board is running at 240MHz with DRAM clocking at 80MHz.
The bsp is configured for the MT46V16M16TG-75:F DRAM.
NOTES:
======
NOTES
-----
This BSP is based heavily off the 5235 BSP.
TODO:
======
TODO
-----
Add other drivers for can, i2c, lcd (fb), qspi etc.
============================================================================
Interrupt map
Interrupt map
-------------
```
+-----+
| |
+-----+
@@ -43,8 +47,11 @@ Add other drivers for can, i2c, lcd (fb), qspi etc.
+-----+
| 1 |
+-----+
```
============================================================================
Timing tests
------------
```
Timings
*** TIME TEST 1 ***
@@ -338,5 +345,4 @@ rtems_rate_monotonic_cancel 0
rtems_rate_monotonic_period 0
rtems_multiprocessing_announce 0
*** END OF TIME OVERHEAD ***
```

13
bsps/m68k/mrm332/README → bsps/m68k/mrm332/README.md
View File

@@ -1,9 +1,10 @@
Description: mrm332
============
mrm322
======
```
CPU: MC68332 @16 or 25MHz
RAM: 32k or 512k
ROM: 512k flash
```
The Mini RoboMind is a small board based on the 68332 microcontroller
designed and build by Mark Castelluccio. For details, see:
@@ -12,9 +13,9 @@ designed and build by Mark Castelluccio. For details, see:
This BSP was ported from the efi332 BSP by Matt Cross (profesor@gweep.net),
the efi332 BSP was written by John S Gwynne.
TODO:
=====
TODO
----
- integrate the interrupt driven stdin/stdout into RTEMS to (a) reduce
the interrupt priority and (2) to prevent it from blocking.
- add a timer driver for the tmtest set.

55
bsps/m68k/uC5282/README → bsps/m68k/uC5282/README.md
View File

@@ -1,30 +1,37 @@
Description: Arcturus Networks uC DIMM ColdFire 5282
============
ColdFire 5282
=============
Arcturus Networks uC DIMM ColdFire 5282
```
CPU: MCF5282, 64MHz
RAM: 16M
SRAM: 64k (BSP places FEC buffer descriptors here)
ROM: 4M
```
This is a credit-card sized board in a DIMM format. It is part of a family
which includes Dragonball and Coldfire CPUs, with a standardized DIMM-based bus.
ACKNOWLEDGEMENTS:
=================
ACKNOWLEDGEMENTS
----------------
This BSP is based on the work of:
D. Peter Siddons
Till Straumann
Brett Swimley
Jay Monkman
TODO:
=====
TODO
----
The bsp relies on the Arcturus monitor to set up DRAM and all chip selects.
This seems OK to me, but others may find it lame.....
I/O pin restrictions make simultaneous operation of I2C, CAN and UART2
impossible. The BSP configures UART2 to use the CAN pins and leaves
the I2C pins available for use.
```
BSP NAME: uC5282
BOARD: Arcturus Netrworks uCdimm 5282
BUS: Arcturus DIMM bus, A24/D16, plus peripherals.
@@ -33,9 +40,11 @@ CPU: MCF5282
COPROCESSORS: N/A
DEBUG MONITOR: Arcturus bootloader
```
PERIPHERALS
===========
-----------
```
TIMERS: Four PIT (RTEMS clock is PIT3), Four Timers
RESOLUTION: 1 microsecond
SERIAL PORTS: Internal UART 0, 1 and 2
@@ -44,26 +53,31 @@ DMA: none
VIDEO: none
SCSI: none
NETWORKING: Internal 10/100Mbs FEC, 100 Mb/s, full/half-duplex
```
DRIVER INFORMATION
==================
------------------
```
CLOCK DRIVER: PIT3
IOSUPP DRIVER: none
SHMSUPP: none
TIMER DRIVER: TIMER3
TTY DRIVER: UART0, 1 and 2
```
STDIO
=====
-----
```
PORT: UART0 Terminal
ELECTRICAL: RS-232
BAUD: 9600
BITS PER CHARACTER: 8
PARITY: None
STOP BITS: 1
```
Downloading the image to the board.
===================================
-----------------------------------
The bootable image is generated by the make-exe target in the bsp makefile. It
generates a simple stripped binary file which is downloaded over the ethernet
port into RAM then executed or programmed into flash memory.
@@ -96,8 +110,9 @@ port into RAM then executed or programmed into flash memory.
6) Type 'goram<CR>' to start the downloaded program, or type 'program<CR>'
to burn the code onto the uCDIMM flash.
Clock Speed Determination Algorithm
===================================
-----------------------------------
Till Straumann submitted a patch to provide more dynamic clock speed
selection.
@@ -127,8 +142,9 @@ register.
We have both, 64MHz and 80MHz variants and both use a PLL reference of
8MHz so that run-time heuristics + detection 3) work fine.
EPICS Bootstrap Information
===========================
---------------------------
The EPICS startup code uses the following environment variables. If an
optional environment variable is missing the value in parentheses will be used.
All Internet addresses must be given in 'dotted-decimal' format.
@@ -152,8 +168,10 @@ NFSMOUNT - NFS information: www.xxx.yyy.zzz:/remote/path /localpath
a remote TFTP and NFS server to be handled transaparently.
============================================================================
Memory map
----------
```
Memory map as set up by dBUG bootstrap and BSP initialization
+--------------------------------------------------+
@@ -204,11 +222,13 @@ f000 0000 | 512 kByte on-chip flash (FLASHBAR) |
+--------------------------------------------------+
x - Final 16-bit location of CS2* space is reserved for FPGA interrupt status.
```
============================================================================
Interrupt map
Interrupt map
-------------
```
External interrupt lines (priority is fixed between 3 and 4):
IRQ7* - Ethernet Transceiver interrupts
IRQ1* - FPGA ('VME') interrupts.
@@ -231,6 +251,5 @@ External interrupt lines (priority is fixed between 3 and 4):
+-----+--------+--------+--------+--------+--------+--------+--------+--------+
| 1 | | | | | | | | |
+-----+--------+--------+--------+--------+--------+--------+--------+--------+
============================================================================
```

26
bsps/mips/hurricane/README → bsps/mips/hurricane/README.md
View File

@@ -1,9 +1,6 @@
#
# README,v 1.2 1998/01/16 16:56:31 joel Exp
#
# @(#)README 08/20/96 1.2
#
hurricane
=========
```
BSP NAME: hurricane
BOARD: Quick Logic Hurricane SBC with V320USC
BUS: N/A
@@ -13,9 +10,11 @@ COPROCESSORS: N/A
MODE: 32 bit mode
DEBUG MONITOR: PMON
```
PERIPHERALS
===========
-----------
```
TIMERS: V320USC internal
SERIAL PORTS: PMON controlled
REAL-TIME CLOCK: none
@@ -23,24 +22,25 @@ DMA: none
VIDEO: none
SCSI: none
NETWORKING: none
```
DRIVER INFORMATION
==================
------------------
```
CLOCK DRIVER: V320USC internal
IOSUPP DRIVER: N/A
SHMSUPP: N/A
TIMER DRIVER: V320USC internal
TTY DRIVER: uses PMON
```
STDIO
=====
-----
```
PORT: Console port 0
ELECTRICAL: RS-232
BAUD: 9600
BITS PER CHARACTER: 8
PARITY: None
STOP BITS: 1
NOTES
=====
```

8
bsps/mips/jmr3904/README → bsps/mips/jmr3904/README.md
View File

@@ -1,7 +1,9 @@
jmr3904
=======
Simple BSP for the TX3904 simulator built into gdb.
Simulator Invocation
====================
--------------------
The following is how the simulator is invoked.
target sim --board=jmr3904
@@ -11,13 +13,13 @@ the simulator will not be built for the correct instruction
and peripheral set.
Simulator Information
=====================
---------------------
The simulated system clock counts instructions. Setting the clock
source to "clock" and the divider to 1 results in the timer directly
counting the number of instructions executed.
Status
======
------
+ hello.exe locks up while running the global destructors. This almost
has to be a linkcmds issue.

25
bsps/mips/rbtx4925/README → bsps/mips/rbtx4925/README.md
View File

@@ -1,7 +1,6 @@
#
# README
#
rbtx4925
========
```
BSP NAME: rbtx4925
BOARD: Toshiba RBTX4925 SBC
BUS: N/A
@@ -12,8 +11,11 @@ MODE: 32 bit mode
DEBUG MONITOR: PMON
```
PERIPHERALS
===========
-----------
```
TIMERS: TX4925 internal
SERIAL PORTS: PMON controlled
REAL-TIME CLOCK: none
@@ -21,24 +23,25 @@ DMA: none
VIDEO: none
SCSI: none
NETWORKING: none
```
DRIVER INFORMATION
==================
------------------
```
CLOCK DRIVER: TX4925 internal
IOSUPP DRIVER: N/A
SHMSUPP: N/A
TIMER DRIVER: TX4925 internal
TTY DRIVER: uses PMON
```
STDIO
=====
-----
```
PORT: Console port 0
ELECTRICAL: RS-232
BAUD: 9600
BITS PER CHARACTER: 8
PARITY: None
STOP BITS: 1
NOTES
=====
```

24
bsps/mips/rbtx4938/README → bsps/mips/rbtx4938/README.md
View File

@@ -1,7 +1,6 @@
#
# README
#
rbtx4938
========
```
BSP NAME: rbtx4938
BOARD: Toshiba RBTX4938 SBC
BUS: N/A
@@ -11,9 +10,11 @@ COPROCESSORS: N/A
MODE: 32 bit mode
DEBUG MONITOR: PMON
```
PERIPHERALS
===========
-----------
```
TIMERS: TX4938 internal
SERIAL PORTS: PMON controlled
REAL-TIME CLOCK: none
@@ -21,24 +22,25 @@ DMA: none
VIDEO: none
SCSI: none
NETWORKING: none
```
DRIVER INFORMATION
==================
------------------
```
CLOCK DRIVER: TX4938 internal
IOSUPP DRIVER: N/A
SHMSUPP: N/A
TIMER DRIVER: TX4938 internal
TTY DRIVER: uses PMON
```
STDIO
=====
-----
```
PORT: Console port 0
ELECTRICAL: RS-232
BAUD: 9600
BITS PER CHARACTER: 8
PARITY: None
STOP BITS: 1
NOTES
=====
```

16
bsps/mips/shared/gdbstub/README → bsps/mips/shared/gdbstub/README.md
View File

@@ -1,4 +1,5 @@
/*****************************************************/
GDB stub
========
Debugged this stub against the MongooseV bsp. Relies on putting break
instructions on breakpoints and step targets- normal stuff, and does not
@@ -19,9 +20,6 @@ bugs I'm aware of.
Greg Menke
3/5/2002
/*****************************************************/
The contents of this directory are based upon the "r46kstub.tar.gz" package
released to the net by
@@ -35,14 +33,12 @@ with gdb 4.16 and an IDT R4600 Orion. The stub was modified to support
R3000 class CPUs and to work within the mips-rtems exeception processing
framework.
THe file memlimits.h could end up being target board dependent. If
The file memlimits.h could end up being target board dependent. If
this is the case, copy it to your BSP directory and modify as necessary.
--joel
8 February 2002
Original README
===============
---------------
The r46kstub directory and its compressed archive (r46kstub.tar.gz) contain
the 9/29/96 source code snapshot for a ROM-resident gdb-4.16 debug agent
@@ -56,6 +52,7 @@ of Phil Bunce's PMON program.
The distribution consists of the following files:
```
-rw-r--r-- 1 1178 Sep 29 16:34 ChangeLog
-rw-r--r-- 1 748 Jul 26 01:18 Makefile
-rw-r--r-- 1 6652 Sep 29 16:34 README
@@ -67,6 +64,7 @@ The distribution consists of the following files:
-rw-r--r-- 1 23874 Jul 21 20:31 r46kstub.c
-rw-r--r-- 1 1064 Jul 3 12:35 r46kstub.ld
-rw-r--r-- 1 13299 Sep 29 16:24 stubinit.S
```
With the exception of mips_opcode.h, which is a slightly modified version
of a header file contributed by Ralph Campbell to 4.4 BSD and is therefore
@@ -109,6 +107,7 @@ to sign-extend a pointer (the next instruction address) into a long long
code and it is doing what I had intended. But you should not see any other
warnings or errors. Here is a log of the build:
```shell
mips64orion-idt-elf-gcc -g -Wa,-ahld -Wall -membedded-data \
-O3 -c r46kstub.c >r46kstub.L
r46kstub.c: In function `doSStep':
@@ -140,6 +139,7 @@ stubinit.o
r46kstub.o
mips64orion-idt-elf-objcopy -S -R .bss -R .data -R .reginfo \
-O srec r46kstub.out r46kstub.hex
```
Limitations: stubinit.S deliberately forces the PC (which is a 64-bit
register) to contain a legitimate sign-extended 32-bit value. This was

76
bsps/nios2/README
View File

@@ -1,76 +0,0 @@
# Goal is to have BSPs build almost completely automatically from a template
# and information that comes from SOPC Builder as a .PTF file. Most of the
# code will go to a shared/ BSP directory.
#
# Ideally, updates to the PTF shouldn't cause any pain for the maintainer
# of a specific BSP (possibly with enhancements not covered by the
# automatic BSP creation).
#
# Some first steps toward utilizing SOPC Builder PTF output can be found
# in top level /tools/cpu/nios2. Also see the README there.
#
# Implemented (in shared/ subdirectory)
# Clock driver
# Timer driver
# Console via JTAG UART
#
# Todo;
# Support more peripherals. My priorities:
# - (improve) Altera Avalon JTAG UART
# - Altera Avalon UART
# - OpenCores.org I2C Master
# - Altera SPI Core / EPCS Configuration Device
# - OpenCores.org 10/100 Ethernet MAC (use existing driver)
# - (more) Altera Avalon Timer
#
# Put all drivers aside in a shared/ subdirectory.
# Update the "times" file for NIOS2 with and without icache.
#
# Missing (although it looks like it's there)
# Data cache handling (for now, don't use the "fast" NIOS2)
# SHM support (just taken over the code from no_cpu/no_bsp)
#
# Kolja Waschk, 6/2006
#
BSP NAME: nios2_eb2_1
BOARD: Altera Instruction Set Simulator Default plus second timer
BUS: Avalon
CPU FAMILY: nios2
CPU: small
COPROCESSORS: none
MODE: 32 bit mode
DEBUG MONITOR: none
PERIPHERALS
===========
TIMERS: Altera Avalon Timer
RESOLUTION: .0001 microseconds
SERIAL PORTS: Altera Avalon JTAG UART
REAL-TIME CLOCK: none
DMA: none
VIDEO: none
SCSI: none
NETWORKING: none
DRIVER INFORMATION
==================
CLOCK DRIVER: Altera Avalon Timer
IOSUPP DRIVER: none
SHMSUPP: polled
TIMER DRIVER: Altera Avalon Timer
TTY DRIVER: none
STDIO
=====
PORT: Console port 0
ELECTRICAL: JTAG
BAUD: 115200
BITS PER CHARACTER: 8
PARITY: None
STOP BITS: 1
NOTES
=====

80
bsps/nios2/README.md Normal file
View File

@@ -0,0 +1,80 @@
nios2
=====
Goal is to have BSPs build almost completely automatically from a template
and information that comes from SOPC Builder as a .PTF file. Most of the
code will go to a shared/ BSP directory.
Ideally, updates to the PTF shouldn't cause any pain for the maintainer
of a specific BSP (possibly with enhancements not covered by the
automatic BSP creation).
Some first steps toward utilizing SOPC Builder PTF output can be found
in top level /tools/cpu/nios2. Also see the README there.
Implemented (in shared/ subdirectory)
Clock driver
Timer driver
Console via JTAG UART
Todo;
Support more peripherals. My priorities:
- (improve) Altera Avalon JTAG UART
- Altera Avalon UART
- OpenCores.org I2C Master
- Altera SPI Core / EPCS Configuration Device
- OpenCores.org 10/100 Ethernet MAC (use existing driver)
- (more) Altera Avalon Timer
Put all drivers aside in a shared/ subdirectory.
Update the "times" file for NIOS2 with and without icache.
Missing (although it looks like it's there)
Data cache handling (for now, don't use the "fast" NIOS2)
SHM support (just taken over the code from no_cpu/no_bsp)
```
BSP NAME: nios2_eb2_1
BOARD: Altera Instruction Set Simulator Default plus second timer
BUS: Avalon
CPU FAMILY: nios2
CPU: small
COPROCESSORS: none
MODE: 32 bit mode
DEBUG MONITOR: none
```
PERIPHERALS
-----------
```
TIMERS: Altera Avalon Timer
RESOLUTION: .0001 microseconds
SERIAL PORTS: Altera Avalon JTAG UART
REAL-TIME CLOCK: none
DMA: none
VIDEO: none
SCSI: none
NETWORKING: none
```
DRIVER INFORMATION
------------------
```
CLOCK DRIVER: Altera Avalon Timer
IOSUPP DRIVER: none
SHMSUPP: polled
TIMER DRIVER: Altera Avalon Timer
TTY DRIVER: none
```
STDIO
-----
```
PORT: Console port 0
ELECTRICAL: JTAG
BAUD: 115200
BITS PER CHARACTER: 8
PARITY: None
STOP BITS: 1
```

66
bsps/no_cpu/no_bsp/README
View File

@@ -1,66 +0,0 @@
# This is a sample hardware description file for a BSP. This comment
# block does not have to appear in a real one. The intention of this
# file is to provide a central place to look when searching for
# information about a board when starting a new BSP. For example,
# you may want to find an existing timer driver for the chip you are
# using on your board. It is easier to grep for the chip name in
# all of the HARDWARE files than to peruse the source tree. Hopefully,
# making the HARDDWARE files accurate will also alleviate the common
# problem of not knowing anything about a board based on its BSP
# name.
#
# NOTE: If you have a class of peripheral chip on board which
# is not in this list please add it to this file so
# others will also use the same name.
#
# Timer resolution is the way it is configured in this BSP.
# On a counting timer, this is the length of time which
# corresponds to 1 count.
#
BSP NAME: fastsbc1
BOARD: Fasssst Computers, Fast SBC-1
BUS: SchoolBus
CPU FAMILY: i386
CPU: Intel Hexium
COPROCESSORS: Witch Hex87
MODE: 32 bit mode
DEBUG MONITOR: HexBug
PERIPHERALS
===========
TIMERS: Intel i8254
RESOLUTION: .0001 microseconds
SERIAL PORTS: Zilog Z8530 (with 2 ports)
REAL-TIME CLOCK: RTC-4
DMA: Intel i8259
VIDEO: none
SCSI: none
NETWORKING: none
DRIVER INFORMATION
==================
CLOCK DRIVER: RTC-4
IOSUPP DRIVER: Zilog Z8530 port A
SHMSUPP: polled and interrupts
TIMER DRIVER: Intel i8254
TTY DRIVER: stub only
STDIO
=====
PORT: Console port 0
ELECTRICAL: RS-232
BAUD: 9600
BITS PER CHARACTER: 8
PARITY: None
STOP BITS: 1
NOTES
=====
(1) 900 Mhz and 950 Mhz versions.
(2) 1 Gb or 2 Gb RAM.
(3) PC compatible if HexBug not enabled.

77
bsps/no_cpu/no_bsp/README.md Normal file
View File

@@ -0,0 +1,77 @@
no_bsp BSP Example
==================
This is a sample hardware description file for a BSP. This comment
block does not have to appear in a real one. The intention of this
file is to provide a central place to look when searching for
information about a board when starting a new BSP. For example,
you may want to find an existing timer driver for the chip you are
using on your board. It is easier to grep for the chip name in
all of the HARDWARE files than to peruse the source tree. Hopefully,
making the HARDDWARE files accurate will also alleviate the common
problem of not knowing anything about a board based on its BSP
name.
NOTE: If you have a class of peripheral chip on board which
is not in this list please add it to this file so
others will also use the same name.
Timer resolution is the way it is configured in this BSP.
On a counting timer, this is the length of time which
corresponds to 1 count.
```
BSP NAME: fastsbc1
BOARD: Fasssst Computers, Fast SBC-1
BUS: SchoolBus
CPU FAMILY: i386
CPU: Intel Hexium
COPROCESSORS: Witch Hex87
MODE: 32 bit mode
DEBUG MONITOR: HexBug
```
PERIPHERALS
-----------
```
TIMERS: Intel i8254
RESOLUTION: .0001 microseconds
SERIAL PORTS: Zilog Z8530 (with 2 ports)
REAL-TIME CLOCK: RTC-4
DMA: Intel i8259
VIDEO: none
SCSI: none
NETWORKING: none
```
DRIVER INFORMATION
------------------
```
CLOCK DRIVER: RTC-4
IOSUPP DRIVER: Zilog Z8530 port A
SHMSUPP: polled and interrupts
TIMER DRIVER: Intel i8254
TTY DRIVER: stub only
```
STDIO
-----
```
PORT: Console port 0
ELECTRICAL: RS-232
BAUD: 9600
BITS PER CHARACTER: 8
PARITY: None
STOP BITS: 1
```
NOTES
-----
(1) 900 Mhz and 950 Mhz versions.
(2) 1 Gb or 2 Gb RAM.
(3) PC compatible if HexBug not enabled.