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Add missing prototypes.

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This commit is contained in:
Ralf Corsepius
2008-08-20 03:41:07 +00:00
parent 0e4e56ba2a
commit 378bea5a7d
3 changed files with 5 additions and 5 deletions
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2
c/src/lib/libbsp/powerpc/haleakala/irq/irq.c
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@@ -66,7 +66,7 @@ static inline int IsUICIRQ(const rtems_irq_number irqLine)
); );
} }
static void WriteIState() static void WriteIState(void)
/* Write the gEnabledInts state masked by gIntInhibited to the hardware */ /* Write the gEnabledInts state masked by gIntInhibited to the hardware */
{ {
PPC_SET_DEVICE_CONTROL_REGISTER(UIC0_ER, PPC_SET_DEVICE_CONTROL_REGISTER(UIC0_ER,

4
c/src/lib/libbsp/powerpc/haleakala/irq/irq_init.c
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@@ -21,14 +21,14 @@
/* /*
* default on/off function * default on/off function
*/ */
static void nop_func() static void nop_func(void)
{ {
} }
/* /*
* default isOn function * default isOn function
*/ */
static int not_connected() static int not_connected(void)
{ {
return 0; return 0;
} }

4
c/src/lib/libbsp/powerpc/haleakala/startup/bspstart.c
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@@ -156,7 +156,7 @@ EarlyUARTInit(int baudRate)
static void static void
InitUARTClock() InitUARTClock(void)
{ {
uint32_t reg; uint32_t reg;
mfsdr(SDR0_UART0,reg); mfsdr(SDR0_UART0,reg);
@@ -184,7 +184,7 @@ void GPIO_AlternateSelect(int bitnum, int source)
} }
} }
void Init_FPGA() void Init_FPGA(void)
{ {
/* Have to write to the FPGA to enable the UART drivers */ /* Have to write to the FPGA to enable the UART drivers */
/* Have to enable CS2 as an output in GPIO to get the FPGA working */ /* Have to enable CS2 as an output in GPIO to get the FPGA working */