Imagelibrary/rtems
1
0
Fork 1
mirror of https://gitlab.rtems.org/rtems/rtos/rtems.git synced 2025-11-16 12:34:45 +00:00
Code Issues Packages Projects Releases Wiki Activity

bsps/xqspipsu: Handle SMP systems properly

Browse Source 
The NOR driver was not written with SMP systems and caching in mind.
This makes the IsBusy flag volatile for updates across cores and
introduces cache flushing and invalidation where necessary for data
manipulated by the DMA engine in the QSPI peripheral.
This commit is contained in:
Kinsey Moore
2023-06-21 10:47:33 -05:00
committed by Joel Sherrill
parent 65b0ba4d8a
commit 333fd02631
3 changed files with 29 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
bsps/include/dev/spi/xqspipsu.h
View File

@@ -259,6 +259,9 @@ typedef struct {
s32 TxBytes; /**< Number of bytes to transfer (state) */
s32 RxBytes; /**< Number of bytes left to transfer(state) */
s32 GenFifoEntries; /**< Number of Gen FIFO entries remaining */
#ifdef __rtems__
volatile
#endif
u32 IsBusy; /**< A transfer is in progress (state) */
u32 ReadMode; /**< DMA or IO mode */
u32 GenFifoCS; /**< Gen FIFO chip selection */

3
bsps/shared/dev/spi/xqspipsu-flash-helper.c
View File

@@ -314,6 +314,7 @@ static int FlashReadID(XQspiPsu *QspiPsuPtr)
}
while (TransferInProgress);
rtems_cache_invalidate_multiple_data_lines(ReadBfrPtr, 3);
/* In case of dual, read both and ensure they are same make/size */
/*
@@ -860,6 +861,7 @@ int QspiPsu_NOR_Read(
while (TransferInProgress);
}
rtems_cache_invalidate_multiple_data_lines(ReadBuffer, ByteCount);
return 0;
}
@@ -1047,6 +1049,7 @@ static int MultiDieRead(
Address += data_len;
remain_len -= data_len;
}
rtems_cache_invalidate_multiple_data_lines(ReadBfrPtr, ByteCount);
return 0;
}

23
bsps/shared/dev/spi/xqspipsu.c
View File

@@ -84,6 +84,9 @@
#include "xqspipsu.h"
#include "xqspipsu_control.h"
#include "sleep.h"
#ifdef __rtems__
#include <rtems/rtems/cache.h>
#endif
/************************** Constant Definitions *****************************/
#define MAX_DELAY_CNT 10000000U /**< Max delay count */
@@ -442,7 +445,16 @@ s32 XQspiPsu_PolledTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
for (Index = 0; Index < (s32)NumMsg; Index++) {
Xil_AssertNonvoid(Msg[Index].ByteCount > 0U);
#ifdef __rtems__
if (Msg[Index].TxBfrPtr != NULL) {
rtems_cache_flush_multiple_data_lines(Msg[Index].TxBfrPtr, Msg[Index].ByteCount);
}
#endif
}
#ifdef __rtems__
rtems_cache_flush_multiple_data_lines(Msg, NumMsg * sizeof(*Msg));
#endif
/*
* Check whether there is another transfer in progress.
* Not thread-safe
@@ -582,7 +594,18 @@ s32 XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
for (Index = 0; Index < (s32)NumMsg; Index++)
#ifdef __rtems__
{
#endif
Xil_AssertNonvoid(Msg[Index].ByteCount > 0U);
#ifdef __rtems__
if (Msg[Index].TxBfrPtr != NULL) {
rtems_cache_flush_multiple_data_lines(Msg[Index].TxBfrPtr, Msg[Index].ByteCount);
}
}
rtems_cache_flush_multiple_data_lines(Msg, NumMsg * sizeof(*Msg));
#endif
/*
* Check whether there is another transfer in progress.
* Not thread-safe