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bsps/aarch64: Set interrupt level correctly

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The existing code is functional but inccorrect and blindly modifies the
other masking bits. It is important to preserve those other bits since
they control masking of important system events.
This commit is contained in:
Kinsey Moore
2021-10-25 09:53:44 -05:00
committed by Joel Sherrill
parent 55a93ae3b4
commit 2d27725838
2 changed files with 12 additions and 6 deletions
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2
bsps/aarch64/include/dev/irq/arm-gic-arch.h
View File

@@ -49,7 +49,7 @@ extern "C" {
static inline void arm_interrupt_handler_dispatch(rtems_vector_number vector)
{
uint32_t interrupt_level = _CPU_ISR_Get_level();
AArch64_interrupt_enable(1);
_CPU_ISR_Set_level(1);
bsp_interrupt_handler_dispatch(vector);
_CPU_ISR_Set_level(interrupt_level);
}

16
cpukit/score/cpu/aarch64/cpu.c
View File

@@ -149,11 +149,17 @@ void _CPU_Context_Initialize(
void _CPU_ISR_Set_level( uint32_t level )
{
/* Set the mask bit if interrupts are disabled */
level = level ? AARCH64_PSTATE_I : 0;
__asm__ volatile (
"msr DAIF, %[level]\n"
: : [level] "r" (level)
);
if ( level ) {
__asm__ volatile (
"msr DAIFSet, #0x2\n"
: : [level] "r" (level)
);
} else {
__asm__ volatile (
"msr DAIFClr, #0x2\n"
: : [level] "r" (level)
);
}
}
uint32_t _CPU_ISR_Get_level( void )