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2004-04-22 Ralf Corsepius <ralf_corsepius@rtems.org>

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* include/bsp.h: Split out tmtest27 support.
	* include/tm27.h: New.
This commit is contained in:
Ralf Corsepius
2004-04-22 15:57:29 +00:00
parent 7f3d55573d
commit 25964be667
9 changed files with 160 additions and 96 deletions
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5
c/src/lib/libbsp/mips/genmongoosev/ChangeLog
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@@ -1,3 +1,8 @@
2004-04-22 Ralf Corsepius <ralf_corsepius@rtems.org>
* include/bsp.h: Split out tmtest27 support.
* include/tm27.h: New.
2004-04-21 Ralf Corsepius <ralf_corsepius@rtems.org>
PR 613/bsps

34
c/src/lib/libbsp/mips/genmongoosev/include/bsp.h
View File

@@ -48,42 +48,8 @@ extern "C" {
extern void assertSoftwareInterrupt(uint32_t);
/*
* Define the interrupt mechanism for Time Test 27
*
* NOTE: Following are for XXX and are board independent
*
*/
#define CLOCK_VECTOR MONGOOSEV_IRQ_TIMER1
#define MUST_WAIT_FOR_INTERRUPT 1
#if 1
#define Install_tm27_vector( handler ) \
(void) set_vector( handler, MONGOOSEV_IRQ_SOFTWARE_1, 1 );
#define Cause_tm27_intr() assertSoftwareInterrupt(0);
#define Clear_tm27_intr()
#define Lower_tm27_intr()
#else
#define Install_tm27_vector( handler ) \
(void) set_vector( handler, MONGOOSEV_IRQ_TIMER1, 1 );
#define Cause_tm27_intr() \
do { \
; \
} while(0)
#define Clear_tm27_intr()
#define Lower_tm27_intr()
#endif
/* Constants */
/* miscellaneous stuff assumed to exist */

49
c/src/lib/libbsp/mips/genmongoosev/include/tm27.h Normal file
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@@ -0,0 +1,49 @@
/*
* tm27.h
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#ifndef _TMTEST27
#error "This is an RTEMS internal file you must not include directly."
#endif
#ifndef __tm27_h
#define __tm27_h
/*
* Define the interrupt mechanism for Time Test 27
*/
#define MUST_WAIT_FOR_INTERRUPT 1
#if 1
#define Install_tm27_vector( handler ) \
(void) set_vector( handler, MONGOOSEV_IRQ_SOFTWARE_1, 1 );
#define Cause_tm27_intr() assertSoftwareInterrupt(0);
#define Clear_tm27_intr()
#define Lower_tm27_intr()
#else
#define Install_tm27_vector( handler ) \
(void) set_vector( handler, MONGOOSEV_IRQ_TIMER1, 1 );
#define Cause_tm27_intr() \
do { \
; \
} while(0)
#define Clear_tm27_intr()
#define Lower_tm27_intr()
#endif
#endif

5
c/src/lib/libbsp/mips/jmr3904/ChangeLog
View File

@@ -1,3 +1,8 @@
2004-04-22 Ralf Corsepius <ralf_corsepius@rtems.org>
* include/bsp.h: Split out tmtest27 support.
* include/tm27.h: New.
2004-04-21 Ralf Corsepius <ralf_corsepius@rtems.org>
PR 613/bsps

48
c/src/lib/libbsp/mips/jmr3904/include/bsp.h
View File

@@ -28,54 +28,6 @@ extern "C" {
#include <rtems/clockdrv.h>
#include <libcpu/tx3904.h>
/*
* Define the interrupt mechanism for Time Test 27
*
* NOTE: Following are for XXX and are board independent
*
*/
#define MUST_WAIT_FOR_INTERRUPT 1
#if 0
#define Install_tm27_vector( handler ) \
(void) set_vector( handler, TX3904_IRQ_SOFTWARE_1, 1 ); \
#define Cause_tm27_intr() \
asm volatile ( "syscall 0x01" : : );
#define CLOCK_VECTOR TX3904_IRQ_TMR0
#define Clear_tm27_intr()
#define Lower_tm27_intr()
#else
#define Install_tm27_vector( handler ) \
(void) set_vector( handler, TX3904_IRQ_TMR0, 1 ); \
#define Cause_tm27_intr() \
do { \
uint32_t _clicks = 20; \
TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CCDR, 0x3 ); \
TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CPRA, _clicks ); \
TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TISR, 0x00 ); \
TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_ITMR, 0x8001 ); \
TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TCR, 0xC0 ); \
*((volatile uint32_t*) 0xFFFFC01C) = 0x00000700; \
} while(0)
#define Clear_tm27_intr() \
do { \
TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_ITMR, 0x0001 ); \
TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CCDR, 0x3 ); \
TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TISR, 0x00 ); \
} while(0)
#define Lower_tm27_intr() \
mips_enable_in_interrupt_mask( 0xff01 );
#endif
/* Constants */
/* miscellaneous stuff assumed to exist */

63
c/src/lib/libbsp/mips/jmr3904/include/tm27.h Normal file
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@@ -0,0 +1,63 @@
/*
* tm27.h
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#ifndef _TMTEST27
#error "This is an RTEMS internal file you must not include directly."
#endif
#ifndef __tm27_h
#define __tm27_h
/*
* Define the interrupt mechanism for Time Test 27
*/
#define MUST_WAIT_FOR_INTERRUPT 1
#if 0
#define Install_tm27_vector( handler ) \
(void) set_vector( handler, TX3904_IRQ_SOFTWARE_1, 1 ); \
#define Cause_tm27_intr() \
asm volatile ( "syscall 0x01" : : );
#define CLOCK_VECTOR TX3904_IRQ_TMR0
#define Clear_tm27_intr()
#define Lower_tm27_intr()
#else
#define Install_tm27_vector( handler ) \
(void) set_vector( handler, TX3904_IRQ_TMR0, 1 ); \
#define Cause_tm27_intr() \
do { \
uint32_t _clicks = 20; \
TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CCDR, 0x3 ); \
TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CPRA, _clicks ); \
TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TISR, 0x00 ); \
TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_ITMR, 0x8001 ); \
TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TCR, 0xC0 ); \
*((volatile uint32_t*) 0xFFFFC01C) = 0x00000700; \
} while(0)
#define Clear_tm27_intr() \
do { \
TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_ITMR, 0x0001 ); \
TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CCDR, 0x3 ); \
TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TISR, 0x00 ); \
} while(0)
#define Lower_tm27_intr() \
mips_enable_in_interrupt_mask( 0xff01 );
#endif
#endif

5
c/src/lib/libbsp/mips/p4000/ChangeLog
View File

@@ -1,3 +1,8 @@
2004-04-22 Ralf Corsepius <ralf_corsepius@rtems.org>
* include/bsp.h: Split out tmtest27 support.
* include/tm27.h: New.
2004-04-21 Ralf Corsepius <ralf_corsepius@rtems.org>
PR 613/bsps

14
c/src/lib/libbsp/mips/p4000/include/bsp.h
View File

@@ -39,20 +39,6 @@ extern "C" {
extern void WriteDisplay( char * string );
/*
* Stuff for Time Test 27
*/
#define MUST_WAIT_FOR_INTERRUPT 0
#define Install_tm27_vector( handler ) set_vector( (handler), 0, 1 )
#define Cause_tm27_intr()
#define Clear_tm27_intr()
#define Lower_tm27_intr()
extern uint32_t mips_get_timer( void );
#define CPU_CLOCK_RATE_MHZ (50)

33
c/src/lib/libbsp/mips/p4000/include/tm27.h Normal file
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@@ -0,0 +1,33 @@
/*
* tm27.h
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#ifndef _TMTEST27
#error "This is an RTEMS internal file you must not include directly."
#endif
#ifndef __tm27_h
#define __tm27_h
/*
* Define the interrupt mechanism for Time Test 27
*/
#define MUST_WAIT_FOR_INTERRUPT 0
#define Install_tm27_vector( handler ) set_vector( (handler), 0, 1 )
#define Cause_tm27_intr()
#define Clear_tm27_intr()
#define Lower_tm27_intr()
#endif