mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
synced 2025-12-29 16:00:17 +00:00
Split out items shared with mvme167.
This commit is contained in:
Joel Sherrill
@@ -4,7 +4,7 @@
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AUTOMAKE_OPTIONS = foreign 1.4
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H_FILES = bsp.h coverhd.h page_table.h tod.h
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||||
H_FILES = bsp.h coverhd.h mvme16x_hw.h page_table.h tod.h
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|
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$(PROJECT_INCLUDE):
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||||
$(mkinstalldirs) $@
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||||
@@ -15,6 +15,9 @@ $(PROJECT_INCLUDE)/bsp.h: bsp.h
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$(PROJECT_INCLUDE)/coverhd.h: coverhd.h
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$(INSTALL_DATA) $< $@
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$(PROJECT_INCLUDE)/mvme16x_hw.h: mvme16x_hw.h
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$(INSTALL_DATA) $< $@
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$(PROJECT_INCLUDE)/page_table.h: page_table.h
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$(INSTALL_DATA) $< $@
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@@ -22,8 +25,8 @@ $(PROJECT_INCLUDE)/tod.h: tod.h
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$(INSTALL_DATA) $< $@
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TMPINSTALL_FILES += $(PROJECT_INCLUDE) $(PROJECT_INCLUDE)/bsp.h \
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$(PROJECT_INCLUDE)/coverhd.h $(PROJECT_INCLUDE)/page_table.h \
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$(PROJECT_INCLUDE)/tod.h
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$(PROJECT_INCLUDE)/coverhd.h $(PROJECT_INCLUDE)/mvme16x_hw.h \
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$(PROJECT_INCLUDE)/page_table.h $(PROJECT_INCLUDE)/tod.h
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all-local: $(TMPINSTALL_FILES)
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@@ -40,59 +40,10 @@ extern "C" {
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/* #define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2 */
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#define CONFIGURE_INTERRUPT_STACK_MEMORY (4 * 1024)
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||||
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||||
/*
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* Following defines must reflect the setup of the particular MVME162
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*/
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#include <mvme16x_hw.h>
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#define GROUP_BASE_ADDRESS 0x0000F200
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#define BOARD_BASE_ADDRESS 0xFFFF0000
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/* Base for local interrupters' vectors (with enable bit set) */
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#define MASK_INT 0x00800000
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#define VBR0 0x6
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#define VBR1 0x7
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/* RAM limits */
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#define RAM_START 0x00100000
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#define RAM_END 0x00200000
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/*
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* ----------------------------------
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*/
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typedef volatile struct {
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unsigned long slave_adr[2];
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unsigned long slave_trn[2];
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unsigned long slave_ctl;
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unsigned long mastr_adr[4];
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unsigned long mastr_trn;
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unsigned long mastr_att;
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unsigned long mastr_ctl;
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unsigned long dma_ctl_1;
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unsigned long dma_ctl_2;
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unsigned long dma_loc_cnt;
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unsigned long dma_vme_cnt;
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unsigned long dma_byte_cnt;
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unsigned long dma_adr_cnt;
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unsigned long dma_status;
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unsigned long to_ctl;
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unsigned long timer_cmp_1;
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unsigned long timer_cnt_1;
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unsigned long timer_cmp_2;
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unsigned long timer_cnt_2;
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unsigned long board_ctl;
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unsigned long prescaler_cnt;
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unsigned long intr_stat;
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unsigned long intr_ena;
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unsigned long intr_soft_set;
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unsigned long intr_clear;
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unsigned long intr_level[4];
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unsigned long vector_base;
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} lcsr_regs;
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#define lcsr ((lcsr_regs * const) 0xFFF40000)
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/*----------------------------------------------------------------*/
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typedef volatile struct {
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@@ -162,7 +113,7 @@ typedef volatile struct {
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unsigned long prescaler_count;
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} mcchip_regs;
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#define mcchip ((mcchip_regs * const) 0xFFF42000)
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/*----------------------------------------------------------------*/
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@@ -212,22 +163,6 @@ typedef volatile struct {
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scc[port].csr = (unsigned char)(v))
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/*----------------------------------------------------------------*/
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/*
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* The following registers are located in the VMEbus short
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* IO space and respond to address modifier codes $29 and $2D.
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* On FORCE CPU use address gcsr_vme and device /dev/vme16d32.
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*/
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typedef volatile struct {
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unsigned char chip_revision;
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unsigned char chip_id;
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unsigned char lmsig;
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unsigned char board_scr;
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unsigned short gpr[6];
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} gcsr_regs;
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#define gcsr_vme ((gcsr_regs * const) (GROUP_BASE_ADDRESS + BOARD_BASE_ADDRESS))
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#define gcsr ((gcsr_regs * const) 0xFFF40100)
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/*
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* Define the time limits for RTEMS Test Suite test durations.
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* Long test and short test duration limits are provided. These
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244
c/src/lib/libbsp/m68k/mvme162/include/mvme16x_hw.h
Normal file
244
c/src/lib/libbsp/m68k/mvme162/include/mvme16x_hw.h
Normal file
@@ -0,0 +1,244 @@
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/* mvme16x_hw.h
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*
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* This include file contains all MVME16x board IO definitions
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* and was derived by combining the common items in the
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* mvme162 and mvme167 BSPs.
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*
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* COPYRIGHT (c) 1989-2000.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.OARcorp.com/rtems/license.html.
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*
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* $Id#
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*/
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#ifndef __MVME16xHW_h
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#define __MVME16xHW_h
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#ifdef __cplusplus
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extern "C" {
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#endif
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||||
/*
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* Network driver configuration
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||||
*/
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||||
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struct rtems_bsdnet_ifconfig;
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int uti596_attach(struct rtems_bsdnet_ifconfig * pConfig, int attaching );
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#define RTEMS_BSP_NETWORK_DRIVER_NAME "uti1"
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#define RTEMS_BSP_NETWORK_DRIVER_ATTACH uti596_attach
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/*
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* This is NOT the base address of local RAM!
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* This is the base local address of the VMEbus short I/O space. A local
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* access to this space results in a A16 VMEbus I/O cycle. This base address
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||||
* is NOT configurable on the MVME167, although the types of VMEbus short I/O
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||||
* cycles generated when a cycle in the local 0xFFFF0000-0xFFFFFFFF address
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* range is generated is under control of bits 8-15 of LCSR 0xFFF4002C. The
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* GCSRs of other boards are accessible only through the VMEbus short I/O
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* space. See pages 2-45 and 2-7.
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||||
*/
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||||
#define BOARD_BASE_ADDRESS 0xFFFF0000
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||||
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||||
/*
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||||
* This address must be added to the BOARD_BASE_ADDRESS to access the GCSR of
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||||
* other MVMEs in the group, i.e. it represents the offset of the GCSRs in the
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||||
* VMEbus short I/O space. It also should represent the group address of this
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||||
* MVME167! The group address is configurable, and must match the address
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||||
* programmed into the MVME167 through the 167Bug monitor. 0xCC is the address
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* recommended by Motorola. It is arbitrary.
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||||
* See pages 2-42 and 2-97 to 2-104.
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*/
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#define GROUP_BASE_ADDRESS 0x0000CC00
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/*
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* Representation of the VMEchip2 LCSR.
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* Could be made more detailed.
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*/
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typedef volatile struct {
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unsigned long slave_adr[2];
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unsigned long slave_trn[2];
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unsigned long slave_ctl;
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unsigned long mastr_adr[4];
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unsigned long mastr_trn;
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unsigned long mastr_att;
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unsigned long mastr_ctl;
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unsigned long dma_ctl_1;
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unsigned long dma_ctl_2;
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unsigned long dma_loc_cnt;
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unsigned long dma_vme_cnt;
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unsigned long dma_byte_cnt;
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unsigned long dma_adr_cnt;
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unsigned long dma_status;
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unsigned long to_ctl;
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unsigned long timer_cmp_1;
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unsigned long timer_cnt_1;
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unsigned long timer_cmp_2;
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unsigned long timer_cnt_2;
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unsigned long board_ctl;
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unsigned long prescaler_cnt;
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unsigned long intr_stat;
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unsigned long intr_ena;
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unsigned long intr_soft_set;
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unsigned long intr_clear;
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unsigned long intr_level[4];
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unsigned long vector_base;
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} lcsr_regs;
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/*
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* Base address of VMEchip2 LCSR
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* Not configurable on the MVME167.
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* XXX what about 162?
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*/
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#define lcsr ((lcsr_regs * const) 0xFFF40000)
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/*
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* Vector numbers for the interrupts from the VMEchip2. Use the values
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* "recommended" by Motorola.
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* See pages 2-70 to 2-92, and table 2-3.
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*/
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/* MIEN (Master Interrupt Enable) bit in LCSR 0xFFF40088. */
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#define MASK_INT 0x00800000
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/* The content of VBR0 corresponds to "X" in table 2-3 */
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#define VBR0 0x6
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/* The content of VBR1 corresponds to "Y" in table 2-3 */
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#define VBR1 0x7
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/*
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* Representation of the PCCchip2
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*/
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typedef volatile struct pccchip2_regs_ {
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unsigned char chip_id; /* 0xFFF42000 */
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unsigned char chip_revision; /* 0xFFF42001 */
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unsigned char gen_control; /* 0xFFF42002 */
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unsigned char vector_base; /* 0xFFF42003 */
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unsigned long timer_cmp_1; /* 0xFFF42004 */
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unsigned long timer_cnt_1; /* 0xFFF42008 */
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unsigned long timer_cmp_2; /* 0xFFF4200C */
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unsigned long timer_cnt_2; /* 0xFFF42010 */
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unsigned char LSB_prescaler_count;/* 0xFFF42014 */
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unsigned char prescaler_clock_adjust; /* 0xFFF42015 */
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unsigned char timer_ctl_2; /* 0xFFF42016 */
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unsigned char timer_ctl_1; /* 0xFFF42017 */
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unsigned char gpi_int_ctl; /* 0xFFF42018 */
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unsigned char gpio_ctl; /* 0xFFF42019 */
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||||
unsigned char timer_int_ctl_2; /* 0xFFF4201A */
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||||
unsigned char timer_int_ctl_1; /* 0xFFF4201B */
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||||
unsigned char SCC_error; /* 0xFFF4201C */
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||||
unsigned char SCC_modem_int_ctl; /* 0xFFF4201D */
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||||
unsigned char SCC_tx_int_ctl; /* 0xFFF4201E */
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||||
unsigned char SCC_rx_int_ctl; /* 0xFFF4201F */
|
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unsigned char reserved1[3];
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||||
unsigned char modem_piack; /* 0xFFF42023 */
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unsigned char reserved2;
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||||
unsigned char tx_piack; /* 0xFFF42025 */
|
||||
unsigned char reserved3;
|
||||
unsigned char rx_piack; /* 0xFFF42027 */
|
||||
unsigned char LANC_error; /* 0xFFF42028 */
|
||||
unsigned char reserved4;
|
||||
unsigned char LANC_int_ctl; /* 0xFFF4202A */
|
||||
unsigned char LANC_berr_ctl; /* 0xFFF4202B */
|
||||
unsigned char SCSI_error; /* 0xFFF4202C */
|
||||
unsigned char reserved5[2];
|
||||
unsigned char SCSI_int_ctl; /* 0xFFF4202F */
|
||||
unsigned char print_ack_int_ctl; /* 0xFFF42030 */
|
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unsigned char print_fault_int_ctl;/* 0xFFF42031 */
|
||||
unsigned char print_sel_int_ctl; /* 0xFFF42032 */
|
||||
unsigned char print_pe_int_ctl; /* 0xFFF42033 */
|
||||
unsigned char print_busy_int_ctl; /* 0xFFF42034 */
|
||||
unsigned char reserved6;
|
||||
unsigned char print_input_status; /* 0xFFF42036 */
|
||||
unsigned char print_ctl; /* 0xFFF42037 */
|
||||
unsigned char chip_speed; /* 0xFFF42038 */
|
||||
unsigned char reserved7;
|
||||
unsigned char print_data; /* 0xFFF4203A */
|
||||
unsigned char reserved8[3];
|
||||
unsigned char int_level; /* 0xFFF4203E */
|
||||
unsigned char int_mask; /* 0xFFF4203F */
|
||||
} pccchip2_regs;
|
||||
|
||||
/*
|
||||
* Base address of the PCCchip2.
|
||||
* This is not configurable in the MVME167.
|
||||
*/
|
||||
#define pccchip2 ((pccchip2_regs * const) 0xFFF42000)
|
||||
|
||||
/*
|
||||
* On the MVME162, we have the mcchip and the pccchip2 on
|
||||
* the 167. They are similar but different enough where
|
||||
* we have to reconcile them later.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Vector numbers for the interrupts from the PCCchip2. Use the values
|
||||
* "recommended" by Motorola.
|
||||
* See page 3-15.
|
||||
*/
|
||||
#define PCCCHIP2_VBR 0x5
|
||||
|
||||
/*
|
||||
* The following registers are located in the VMEbus short
|
||||
* IO space and respond to address modifier codes $29 and $2D.
|
||||
* On FORCE CPU use address gcsr_vme and device /dev/vme16d32.
|
||||
*/
|
||||
|
||||
typedef volatile struct {
|
||||
unsigned char chip_revision;
|
||||
unsigned char chip_id;
|
||||
unsigned char lmsig;
|
||||
unsigned char board_scr;
|
||||
unsigned short gpr[6];
|
||||
} gcsr_regs;
|
||||
|
||||
#define gcsr_vme ((gcsr_regs * const) (GROUP_BASE_ADDRESS + BOARD_BASE_ADDRESS))
|
||||
#define gcsr ((gcsr_regs * const) 0xFFF40100)
|
||||
|
||||
/*
|
||||
* Representation of 82596CA LAN controller: Memory Map
|
||||
*/
|
||||
typedef volatile struct i82596_regs_ {
|
||||
unsigned short port_lower; /* 0xFFF46000 */
|
||||
unsigned short port_upper; /* 0xFFF46002 */
|
||||
unsigned long chan_attn; /* 0xFFF46004 */
|
||||
} i82596_regs;
|
||||
|
||||
/*
|
||||
* Base address of the 82596.
|
||||
*/
|
||||
#define i82596 ((i82596_regs * const) 0xFFF46000)
|
||||
|
||||
/*
|
||||
* Representation of initialization data in NVRAM
|
||||
*/
|
||||
typedef volatile struct nvram_config_ {
|
||||
unsigned char dcache_enable; /* 0xFFFC0000 */
|
||||
unsigned char icache_enable; /* 0xFFFC0001 */
|
||||
unsigned short cache_mode; /* 0xFFFC0002 */
|
||||
unsigned long ipaddr; /* 0xFFFC0004 */
|
||||
unsigned long netmask; /* 0xFFFC0008 */
|
||||
unsigned char enaddr[6]; /* 0xFFFC000C */
|
||||
unsigned short processor_id; /* 0xFFFC0012 */
|
||||
unsigned long rma_start; /* 0xFFFC0014 */
|
||||
unsigned long vma_start; /* 0xFFFC0018 */
|
||||
unsigned long ramsize; /* 0xFFFC001C */
|
||||
} nvram_config;
|
||||
|
||||
/*
|
||||
* Pointer to the base of User Area NVRAM
|
||||
*/
|
||||
#define nvram ((nvram_config * const) 0xFFFC0000)
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
/* end of include file */
|
||||
@@ -4,7 +4,8 @@
|
||||
|
||||
AUTOMAKE_OPTIONS = foreign 1.4
|
||||
|
||||
H_FILES = bsp.h coverhd.h page_table.h fatal.h
|
||||
H_FILES = bsp.h coverhd.h $(srcdir)/../../mvme162/include/mvme16x_hw.h \
|
||||
page_table.h fatal.h
|
||||
|
||||
$(PROJECT_INCLUDE):
|
||||
$(mkinstalldirs) $@
|
||||
@@ -15,6 +16,9 @@ $(PROJECT_INCLUDE)/bsp.h: bsp.h
|
||||
$(PROJECT_INCLUDE)/coverhd.h: coverhd.h
|
||||
$(INSTALL_DATA) $< $@
|
||||
|
||||
$(PROJECT_INCLUDE)/mvme16x_hw.h: $(srcdir)/../../mvme162/include/mvme16x_hw.h
|
||||
$(INSTALL_DATA) $< $@
|
||||
|
||||
$(PROJECT_INCLUDE)/page_table.h: page_table.h
|
||||
$(INSTALL_DATA) $< $@
|
||||
|
||||
@@ -22,8 +26,8 @@ $(PROJECT_INCLUDE)/fatal.h: fatal.h
|
||||
$(INSTALL_DATA) $< $@
|
||||
|
||||
TMPINSTALL_FILES += $(PROJECT_INCLUDE) $(PROJECT_INCLUDE)/bsp.h \
|
||||
$(PROJECT_INCLUDE)/coverhd.h $(PROJECT_INCLUDE)/page_table.h \
|
||||
$(PROJECT_INCLUDE)/fatal.h
|
||||
$(PROJECT_INCLUDE)/coverhd.h $(PROJECT_INCLUDE)/mvme16x_hw.h \
|
||||
$(PROJECT_INCLUDE)/page_table.h $(PROJECT_INCLUDE)/tod.h
|
||||
|
||||
all: $(TMPINSTALL_FILES)
|
||||
|
||||
|
||||
@@ -41,112 +41,12 @@ extern "C" {
|
||||
#define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 4
|
||||
#define CONFIGURE_INTERRUPT_STACK_MEMORY (4 * 1024)
|
||||
|
||||
/*
|
||||
* Network driver configuration
|
||||
*/
|
||||
|
||||
struct rtems_bsdnet_ifconfig;
|
||||
int uti596_attach(struct rtems_bsdnet_ifconfig * pConfig, int attaching );
|
||||
#define RTEMS_BSP_NETWORK_DRIVER_NAME "uti1"
|
||||
#define RTEMS_BSP_NETWORK_DRIVER_ATTACH uti596_attach
|
||||
|
||||
/*
|
||||
* This is NOT the base address of local RAM!
|
||||
* This is the base local address of the VMEbus short I/O space. A local
|
||||
* access to this space results in a A16 VMEbus I/O cycle. This base address
|
||||
* is NOT configurable on the MVME167, although the types of VMEbus short I/O
|
||||
* cycles generated when a cycle in the local 0xFFFF0000-0xFFFFFFFF address
|
||||
* range is generated is under control of bits 8-15 of LCSR 0xFFF4002C. The
|
||||
* GCSRs of other boards are accessible only through the VMEbus short I/O
|
||||
* space. See pages 2-45 and 2-7.
|
||||
*/
|
||||
#define BOARD_BASE_ADDRESS 0xFFFF0000
|
||||
|
||||
|
||||
/*
|
||||
* This address must be added to the BOARD_BASE_ADDRESS to access the GCSR of
|
||||
* other MVMEs in the group, i.e. it represents the offset of the GCSRs in the
|
||||
* VMEbus short I/O space. It also should represent the group address of this
|
||||
* MVME167! The group address is configurable, and must match the address
|
||||
* programmed into the MVME167 through the 167Bug monitor. 0xCC is the address
|
||||
* recommended by Motorola. It is arbitrary.
|
||||
* See pages 2-42 and 2-97 to 2-104.
|
||||
*/
|
||||
#define GROUP_BASE_ADDRESS 0x0000CC00
|
||||
|
||||
|
||||
/*
|
||||
* Representation of the GCSR
|
||||
*/
|
||||
typedef volatile struct gcsr_regs_ {
|
||||
unsigned char chip_revision;
|
||||
unsigned char chip_id;
|
||||
unsigned char lmsig;
|
||||
unsigned char board_scr;
|
||||
unsigned short gpr[6];
|
||||
} gcsr_regs;
|
||||
|
||||
/* Address of GCSR in VMEbus space */
|
||||
#define gcsr_vme ((gcsr_regs * const) (GROUP_BASE_ADDRESS + BOARD_BASE_ADDRESS))
|
||||
|
||||
/* Address of GCSR in local space */
|
||||
#define gcsr ((gcsr_regs * const) 0xFFF40100)
|
||||
|
||||
/*
|
||||
* Representation of the VMEchip2 LCSR.
|
||||
* Could be made more detailed.
|
||||
*/
|
||||
typedef volatile struct lcsr_regs_ {
|
||||
unsigned long slave_adr[2]; /* 0xFFF40000 */
|
||||
unsigned long slave_trn[2]; /* 0xFFF40008 */
|
||||
unsigned long slave_ctl; /* 0xFFF40010 */
|
||||
unsigned long mastr_adr[4]; /* 0xFFF40014 */
|
||||
unsigned long mastr_trn; /* 0xFFF40024 */
|
||||
unsigned long mastr_att; /* 0xFFF40028 */
|
||||
unsigned long mastr_ctl; /* 0xFFF4002C */
|
||||
unsigned long dma_ctl_1; /* 0xFFF40030 */
|
||||
unsigned long dma_ctl_2; /* 0xFFF40034 */
|
||||
unsigned long dma_loc_cnt; /* 0xFFF40038 */
|
||||
unsigned long dma_vme_cnt; /* 0xFFF4003C */
|
||||
unsigned long dma_byte_cnt; /* 0xFFF40040 */
|
||||
unsigned long dma_adr_cnt; /* 0xFFF40044 */
|
||||
unsigned long dma_status; /* 0xFFF40048 */
|
||||
unsigned long to_ctl; /* 0xFFF4004C */
|
||||
unsigned long timer_cmp_1; /* 0xFFF40050 */
|
||||
unsigned long timer_cnt_1; /* 0xFFF40054 */
|
||||
unsigned long timer_cmp_2; /* 0xFFF40058 */
|
||||
unsigned long timer_cnt_2; /* 0xFFF4005C */
|
||||
unsigned long board_ctl; /* 0xFFF40060 */
|
||||
unsigned long prescaler_cnt; /* 0xFFF40064 */
|
||||
unsigned long intr_stat; /* 0xFFF40068 */
|
||||
unsigned long intr_ena; /* 0xFFF4006C */
|
||||
unsigned long intr_soft_set; /* 0xFFF40070 */
|
||||
unsigned long intr_clear; /* 0xFFF40074 */
|
||||
unsigned long intr_level[4]; /* 0xFFF40078 */
|
||||
unsigned long vector_base; /* 0xFFF40088 */
|
||||
} lcsr_regs;
|
||||
|
||||
/*
|
||||
* Base address of VMEchip2 LCSR
|
||||
* Not configurable on the MVME167.
|
||||
*/
|
||||
#define lcsr ((lcsr_regs * const) 0xFFF40000)
|
||||
|
||||
/*
|
||||
* Vector numbers for the interrupts from the VMEchip2. Use the values
|
||||
* "recommended" by Motorola.
|
||||
* See pages 2-70 to 2-92, and table 2-3.
|
||||
*/
|
||||
|
||||
/* MIEN (Master Interrupt Enable) bit in LCSR 0xFFF40088. */
|
||||
#define MASK_INT 0x00800000
|
||||
|
||||
/* The content of VBR0 corresponds to "X" in table 2-3 */
|
||||
#define VBR0 0x6
|
||||
|
||||
/* The content of VBR1 corresponds to "Y" in table 2-3 */
|
||||
#define VBR1 0x7
|
||||
#include <mvme16x_hw.h>
|
||||
|
||||
/* GCSR is in mvme16x_hw.h */
|
||||
/* LCSR is in mvme16x_hw.h */
|
||||
/* i82596 is in mvme16x_hw.h */
|
||||
/* NVRAM is in mvme16x_hw.h */
|
||||
|
||||
/*
|
||||
* Representation of the PCCchip2
|
||||
@@ -207,14 +107,6 @@ typedef volatile struct pccchip2_regs_ {
|
||||
*/
|
||||
#define pccchip2 ((pccchip2_regs * const) 0xFFF42000)
|
||||
|
||||
/*
|
||||
* Vector numbers for the interrupts from the PCCchip2. Use the values
|
||||
* "recommended" by Motorola.
|
||||
* See page 3-15.
|
||||
*/
|
||||
#define PCCCHIP2_VBR 0x5
|
||||
|
||||
|
||||
/*
|
||||
* The MVME167 is equiped with one or two MEMC040 memory controllers at
|
||||
* 0xFFF43000 and 0xFFF43100. This port assumes that the controllers
|
||||
@@ -415,45 +307,8 @@ typedef volatile struct cd2401_regs_ {
|
||||
/*
|
||||
* Debug print functions: implemented in console.c
|
||||
*/
|
||||
void printk( char *fmt, ... );
|
||||
void BSP_output_string( char * buf );
|
||||
|
||||
/*
|
||||
* Representation of 82596CA LAN controller: Memory Map
|
||||
*/
|
||||
typedef volatile struct i82596_regs_ {
|
||||
unsigned short port_lower; /* 0xFFF46000 */
|
||||
unsigned short port_upper; /* 0xFFF46002 */
|
||||
unsigned long chan_attn; /* 0xFFF46004 */
|
||||
} i82596_regs;
|
||||
|
||||
/*
|
||||
* Base address of the 82596.
|
||||
*/
|
||||
#define i82596 ((i82596_regs * const) 0xFFF46000)
|
||||
|
||||
/*
|
||||
* Representation of initialization data in NVRAM
|
||||
*/
|
||||
typedef volatile struct nvram_config_ {
|
||||
unsigned char dcache_enable; /* 0xFFFC0000 */
|
||||
unsigned char icache_enable; /* 0xFFFC0001 */
|
||||
unsigned short cache_mode; /* 0xFFFC0002 */
|
||||
unsigned long ipaddr; /* 0xFFFC0004 */
|
||||
unsigned long netmask; /* 0xFFFC0008 */
|
||||
unsigned char enaddr[6]; /* 0xFFFC000C */
|
||||
unsigned short processor_id; /* 0xFFFC0012 */
|
||||
unsigned long rma_start; /* 0xFFFC0014 */
|
||||
unsigned long vma_start; /* 0xFFFC0018 */
|
||||
unsigned long ramsize; /* 0xFFFC001C */
|
||||
} nvram_config;
|
||||
|
||||
/*
|
||||
* Pointer to the base of User Area NVRAM
|
||||
*/
|
||||
#define nvram ((nvram_config * const) 0xFFFC0000)
|
||||
|
||||
|
||||
/* BSP-wide functions */
|
||||
|
||||
void bsp_cleanup( void );
|
||||
|
||||
244
c/src/lib/libbsp/m68k/shared/mvme/mvme16x_hw.h
Normal file
244
c/src/lib/libbsp/m68k/shared/mvme/mvme16x_hw.h
Normal file
@@ -0,0 +1,244 @@
|
||||
/* mvme16x_hw.h
|
||||
*
|
||||
* This include file contains all MVME16x board IO definitions
|
||||
* and was derived by combining the common items in the
|
||||
* mvme162 and mvme167 BSPs.
|
||||
*
|
||||
* COPYRIGHT (c) 1989-2000.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.OARcorp.com/rtems/license.html.
|
||||
*
|
||||
* $Id#
|
||||
*/
|
||||
|
||||
#ifndef __MVME16xHW_h
|
||||
#define __MVME16xHW_h
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Network driver configuration
|
||||
*/
|
||||
|
||||
struct rtems_bsdnet_ifconfig;
|
||||
int uti596_attach(struct rtems_bsdnet_ifconfig * pConfig, int attaching );
|
||||
#define RTEMS_BSP_NETWORK_DRIVER_NAME "uti1"
|
||||
#define RTEMS_BSP_NETWORK_DRIVER_ATTACH uti596_attach
|
||||
|
||||
/*
|
||||
* This is NOT the base address of local RAM!
|
||||
* This is the base local address of the VMEbus short I/O space. A local
|
||||
* access to this space results in a A16 VMEbus I/O cycle. This base address
|
||||
* is NOT configurable on the MVME167, although the types of VMEbus short I/O
|
||||
* cycles generated when a cycle in the local 0xFFFF0000-0xFFFFFFFF address
|
||||
* range is generated is under control of bits 8-15 of LCSR 0xFFF4002C. The
|
||||
* GCSRs of other boards are accessible only through the VMEbus short I/O
|
||||
* space. See pages 2-45 and 2-7.
|
||||
*/
|
||||
#define BOARD_BASE_ADDRESS 0xFFFF0000
|
||||
|
||||
/*
|
||||
* This address must be added to the BOARD_BASE_ADDRESS to access the GCSR of
|
||||
* other MVMEs in the group, i.e. it represents the offset of the GCSRs in the
|
||||
* VMEbus short I/O space. It also should represent the group address of this
|
||||
* MVME167! The group address is configurable, and must match the address
|
||||
* programmed into the MVME167 through the 167Bug monitor. 0xCC is the address
|
||||
* recommended by Motorola. It is arbitrary.
|
||||
* See pages 2-42 and 2-97 to 2-104.
|
||||
*/
|
||||
#define GROUP_BASE_ADDRESS 0x0000CC00
|
||||
|
||||
|
||||
/*
|
||||
* Representation of the VMEchip2 LCSR.
|
||||
* Could be made more detailed.
|
||||
*/
|
||||
|
||||
typedef volatile struct {
|
||||
unsigned long slave_adr[2];
|
||||
unsigned long slave_trn[2];
|
||||
unsigned long slave_ctl;
|
||||
unsigned long mastr_adr[4];
|
||||
unsigned long mastr_trn;
|
||||
unsigned long mastr_att;
|
||||
unsigned long mastr_ctl;
|
||||
unsigned long dma_ctl_1;
|
||||
unsigned long dma_ctl_2;
|
||||
unsigned long dma_loc_cnt;
|
||||
unsigned long dma_vme_cnt;
|
||||
unsigned long dma_byte_cnt;
|
||||
unsigned long dma_adr_cnt;
|
||||
unsigned long dma_status;
|
||||
unsigned long to_ctl;
|
||||
unsigned long timer_cmp_1;
|
||||
unsigned long timer_cnt_1;
|
||||
unsigned long timer_cmp_2;
|
||||
unsigned long timer_cnt_2;
|
||||
unsigned long board_ctl;
|
||||
unsigned long prescaler_cnt;
|
||||
unsigned long intr_stat;
|
||||
unsigned long intr_ena;
|
||||
unsigned long intr_soft_set;
|
||||
unsigned long intr_clear;
|
||||
unsigned long intr_level[4];
|
||||
unsigned long vector_base;
|
||||
} lcsr_regs;
|
||||
|
||||
/*
|
||||
* Base address of VMEchip2 LCSR
|
||||
* Not configurable on the MVME167.
|
||||
* XXX what about 162?
|
||||
*/
|
||||
#define lcsr ((lcsr_regs * const) 0xFFF40000)
|
||||
|
||||
/*
|
||||
* Vector numbers for the interrupts from the VMEchip2. Use the values
|
||||
* "recommended" by Motorola.
|
||||
* See pages 2-70 to 2-92, and table 2-3.
|
||||
*/
|
||||
|
||||
/* MIEN (Master Interrupt Enable) bit in LCSR 0xFFF40088. */
|
||||
#define MASK_INT 0x00800000
|
||||
|
||||
/* The content of VBR0 corresponds to "X" in table 2-3 */
|
||||
#define VBR0 0x6
|
||||
|
||||
/* The content of VBR1 corresponds to "Y" in table 2-3 */
|
||||
#define VBR1 0x7
|
||||
|
||||
/*
|
||||
* Representation of the PCCchip2
|
||||
*/
|
||||
typedef volatile struct pccchip2_regs_ {
|
||||
unsigned char chip_id; /* 0xFFF42000 */
|
||||
unsigned char chip_revision; /* 0xFFF42001 */
|
||||
unsigned char gen_control; /* 0xFFF42002 */
|
||||
unsigned char vector_base; /* 0xFFF42003 */
|
||||
unsigned long timer_cmp_1; /* 0xFFF42004 */
|
||||
unsigned long timer_cnt_1; /* 0xFFF42008 */
|
||||
unsigned long timer_cmp_2; /* 0xFFF4200C */
|
||||
unsigned long timer_cnt_2; /* 0xFFF42010 */
|
||||
unsigned char LSB_prescaler_count;/* 0xFFF42014 */
|
||||
unsigned char prescaler_clock_adjust; /* 0xFFF42015 */
|
||||
unsigned char timer_ctl_2; /* 0xFFF42016 */
|
||||
unsigned char timer_ctl_1; /* 0xFFF42017 */
|
||||
unsigned char gpi_int_ctl; /* 0xFFF42018 */
|
||||
unsigned char gpio_ctl; /* 0xFFF42019 */
|
||||
unsigned char timer_int_ctl_2; /* 0xFFF4201A */
|
||||
unsigned char timer_int_ctl_1; /* 0xFFF4201B */
|
||||
unsigned char SCC_error; /* 0xFFF4201C */
|
||||
unsigned char SCC_modem_int_ctl; /* 0xFFF4201D */
|
||||
unsigned char SCC_tx_int_ctl; /* 0xFFF4201E */
|
||||
unsigned char SCC_rx_int_ctl; /* 0xFFF4201F */
|
||||
unsigned char reserved1[3];
|
||||
unsigned char modem_piack; /* 0xFFF42023 */
|
||||
unsigned char reserved2;
|
||||
unsigned char tx_piack; /* 0xFFF42025 */
|
||||
unsigned char reserved3;
|
||||
unsigned char rx_piack; /* 0xFFF42027 */
|
||||
unsigned char LANC_error; /* 0xFFF42028 */
|
||||
unsigned char reserved4;
|
||||
unsigned char LANC_int_ctl; /* 0xFFF4202A */
|
||||
unsigned char LANC_berr_ctl; /* 0xFFF4202B */
|
||||
unsigned char SCSI_error; /* 0xFFF4202C */
|
||||
unsigned char reserved5[2];
|
||||
unsigned char SCSI_int_ctl; /* 0xFFF4202F */
|
||||
unsigned char print_ack_int_ctl; /* 0xFFF42030 */
|
||||
unsigned char print_fault_int_ctl;/* 0xFFF42031 */
|
||||
unsigned char print_sel_int_ctl; /* 0xFFF42032 */
|
||||
unsigned char print_pe_int_ctl; /* 0xFFF42033 */
|
||||
unsigned char print_busy_int_ctl; /* 0xFFF42034 */
|
||||
unsigned char reserved6;
|
||||
unsigned char print_input_status; /* 0xFFF42036 */
|
||||
unsigned char print_ctl; /* 0xFFF42037 */
|
||||
unsigned char chip_speed; /* 0xFFF42038 */
|
||||
unsigned char reserved7;
|
||||
unsigned char print_data; /* 0xFFF4203A */
|
||||
unsigned char reserved8[3];
|
||||
unsigned char int_level; /* 0xFFF4203E */
|
||||
unsigned char int_mask; /* 0xFFF4203F */
|
||||
} pccchip2_regs;
|
||||
|
||||
/*
|
||||
* Base address of the PCCchip2.
|
||||
* This is not configurable in the MVME167.
|
||||
*/
|
||||
#define pccchip2 ((pccchip2_regs * const) 0xFFF42000)
|
||||
|
||||
/*
|
||||
* On the MVME162, we have the mcchip and the pccchip2 on
|
||||
* the 167. They are similar but different enough where
|
||||
* we have to reconcile them later.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Vector numbers for the interrupts from the PCCchip2. Use the values
|
||||
* "recommended" by Motorola.
|
||||
* See page 3-15.
|
||||
*/
|
||||
#define PCCCHIP2_VBR 0x5
|
||||
|
||||
/*
|
||||
* The following registers are located in the VMEbus short
|
||||
* IO space and respond to address modifier codes $29 and $2D.
|
||||
* On FORCE CPU use address gcsr_vme and device /dev/vme16d32.
|
||||
*/
|
||||
|
||||
typedef volatile struct {
|
||||
unsigned char chip_revision;
|
||||
unsigned char chip_id;
|
||||
unsigned char lmsig;
|
||||
unsigned char board_scr;
|
||||
unsigned short gpr[6];
|
||||
} gcsr_regs;
|
||||
|
||||
#define gcsr_vme ((gcsr_regs * const) (GROUP_BASE_ADDRESS + BOARD_BASE_ADDRESS))
|
||||
#define gcsr ((gcsr_regs * const) 0xFFF40100)
|
||||
|
||||
/*
|
||||
* Representation of 82596CA LAN controller: Memory Map
|
||||
*/
|
||||
typedef volatile struct i82596_regs_ {
|
||||
unsigned short port_lower; /* 0xFFF46000 */
|
||||
unsigned short port_upper; /* 0xFFF46002 */
|
||||
unsigned long chan_attn; /* 0xFFF46004 */
|
||||
} i82596_regs;
|
||||
|
||||
/*
|
||||
* Base address of the 82596.
|
||||
*/
|
||||
#define i82596 ((i82596_regs * const) 0xFFF46000)
|
||||
|
||||
/*
|
||||
* Representation of initialization data in NVRAM
|
||||
*/
|
||||
typedef volatile struct nvram_config_ {
|
||||
unsigned char dcache_enable; /* 0xFFFC0000 */
|
||||
unsigned char icache_enable; /* 0xFFFC0001 */
|
||||
unsigned short cache_mode; /* 0xFFFC0002 */
|
||||
unsigned long ipaddr; /* 0xFFFC0004 */
|
||||
unsigned long netmask; /* 0xFFFC0008 */
|
||||
unsigned char enaddr[6]; /* 0xFFFC000C */
|
||||
unsigned short processor_id; /* 0xFFFC0012 */
|
||||
unsigned long rma_start; /* 0xFFFC0014 */
|
||||
unsigned long vma_start; /* 0xFFFC0018 */
|
||||
unsigned long ramsize; /* 0xFFFC001C */
|
||||
} nvram_config;
|
||||
|
||||
/*
|
||||
* Pointer to the base of User Area NVRAM
|
||||
*/
|
||||
#define nvram ((nvram_config * const) 0xFFFC0000)
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
/* end of include file */
|
||||
Reference in New Issue
Block a user