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2002-07-30 Joel Sherrill <joel@OARcorp.com>

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* timeMVME136.t, timedata.t: Replaced XXX's with real info.
This commit is contained in:
Joel Sherrill
2002-07-31 00:14:42 +00:00
parent 4b4d4fde1f
commit 219432f8b8
3 changed files with 20 additions and 8 deletions
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4
doc/supplements/m68k/ChangeLog
View File

@@ -1,3 +1,7 @@
2002-07-30 Joel Sherrill <joel@OARcorp.com>
* timeMVME136.t, timedata.t: Replaced XXX's with real info.
2002-07-26 Joel Sherrill <joel@OARcorp.com>
* intr_NOTIMES.t: Per PR258, changed single @ to double @ in email

12
doc/supplements/m68k/timeMVME136.t
View File

@@ -27,7 +27,8 @@ times as they pertain to the MC68020 version of RTEMS.
All times reported except for the maximum period
interrupts are disabled by RTEMS were measured using a Motorola
MVME135 CPU board. The MVME135 is a 20Mhz board with one wait
MVME135 CPU board. The MVME135 is a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
Mhz board with one wait
state dynamic memory and a MC68881 numeric coprocessor. The
Zilog 8036 countdown timer on this board was used to measure
elapsed time with a one-half microsecond resolution. All
@@ -41,7 +42,8 @@ disabled. The worst case times of the MC68020 microprocessor
were used for each instruction. Zero wait state memory was
assumed. The total CPU cycles executed with interrupts
disabled, including the instructions to disable and enable
interrupts, was divided by 20 to simulate a 20Mhz MC68020. It
interrupts, was divided by 20 to simulate a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
Mhz MC68020. It
should be noted that the worst case instruction times for the
MC68020 assume that the internal cache is disabled and that no
instructions overlap.
@@ -58,14 +60,16 @@ total of RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK
microseconds. These combine to yield a worst case
interrupt latency of less than
RTEMS_MAXIMUM_DISABLE_PERIOD + RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK
microseconds at 20Mhz. [NOTE: The maximum period with interrupts
microseconds at RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
Mhz. [NOTE: The maximum period with interrupts
disabled was last determined for Release
RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.]
It should be noted again that the maximum period with
interrupts disabled within RTEMS is hand-timed and based upon
worst case (i.e. CPU cache disabled and no instruction overlap)
times for a 20Mhz MC68020. The interrupt vector and entry
times for a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
Mhz MC68020. The interrupt vector and entry
overhead time was generated on an MVME135 benchmark platform
using the Multiprocessing Communications registers to generate
as the interrupt source.

12
doc/supplements/m68k/timedata.t
View File

@@ -58,7 +58,8 @@ times as they pertain to the MC68020 version of RTEMS.
All times reported except for the maximum period
interrupts are disabled by RTEMS were measured using a Motorola
MVME135 CPU board. The MVME135 is a 20Mhz board with one wait
MVME135 CPU board. The MVME135 is a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
Mhz board with one wait
state dynamic memory and a MC68881 numeric coprocessor. The
Zilog 8036 countdown timer on this board was used to measure
elapsed time with a one-half microsecond resolution. All
@@ -72,7 +73,8 @@ disabled. The worst case times of the MC68020 microprocessor
were used for each instruction. Zero wait state memory was
assumed. The total CPU cycles executed with interrupts
disabled, including the instructions to disable and enable
interrupts, was divided by 20 to simulate a 20Mhz MC68020. It
interrupts, was divided by 20 to simulate a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
Mhz MC68020. It
should be noted that the worst case instruction times for the
MC68020 assume that the internal cache is disabled and that no
instructions overlap.
@@ -92,14 +94,16 @@ total of RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK
microseconds. These combine to yield a worst case
interrupt latency of less than
RTEMS_MAXIMUM_DISABLE_PERIOD + RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK
microseconds at 20Mhz. [NOTE: The maximum period with interrupts
microseconds at RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
Mhz. [NOTE: The maximum period with interrupts
disabled was last determined for Release
RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.]
It should be noted again that the maximum period with
interrupts disabled within RTEMS is hand-timed and based upon
worst case (i.e. CPU cache disabled and no instruction overlap)
times for a 20Mhz MC68020. The interrupt vector and entry
times for a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
Mhz MC68020. The interrupt vector and entry
overhead time was generated on an MVME135 benchmark platform
using the Multiprocessing Communications registers to generate
as the interrupt source.