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2001-04-20 Joel Sherrill <joel@OARcorp.com>

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* cpu_asm.S: Added code to save and restore SR and EPC to
	properly support nested interrupts.  Note that the ISR
	(not RTEMS) enables interrupts allowing the nesting to occur.
This commit is contained in:
Joel Sherrill
2001-04-20 13:07:34 +00:00
parent 4ff04390ee
commit 176e1ed8aa
4 changed files with 30 additions and 0 deletions
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6
c/src/exec/score/cpu/mips/ChangeLog
View File

@@ -1,3 +1,9 @@
2001-04-20 Joel Sherrill <joel@OARcorp.com>
* cpu_asm.S: Added code to save and restore SR and EPC to
properly support nested interrupts. Note that the ISR
(not RTEMS) enables interrupts allowing the nesting to occur.
2001-03-14 Joel Sherrill <joel@OARcorp.com>
* cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:

9
c/src/exec/score/cpu/mips/cpu_asm.S
View File

@@ -426,6 +426,10 @@ FRAME(_ISR_Handler,sp,0,ra)
/* This needs to be figured out.........*/
ADDIU sp,sp,-40
STREG ra,32(sp) /* store ra on the stack */
MFC0 t0, C0_EPC /* XXX */
STREG t0,16(sp) /* XXX store EPC on the stack */
mfc0 t0,C0_SR
STREG t0,24(sp) /* XXX store SR on the stack */
/* determine if an interrupt generated this exception */
@@ -529,6 +533,10 @@ _ISR_Handler_1:
_ISR_Handler_exit:
LDREG ra,32(sp)
LDREG t0,16(sp) /* XXX restore EPC on the stack */
MTC0 t0, C0_EPC /* XXX */
LDREG t0,24(sp) /* XXX restore SR on the stack */
mtc0 t0,C0_SR
ADDIU sp,sp,40 /* Q: Again with the 40...Is this needed? */
/* restore interrupt context from stack */
@@ -563,6 +571,7 @@ _ISR_Handler_exit:
ADDIU sp,sp,EXCP_STACK_SIZE
MFC0 k0, C0_EPC
nop
rfe /* Might not need to do RFE here... */
j k0

6
cpukit/score/cpu/mips/ChangeLog
View File

@@ -1,3 +1,9 @@
2001-04-20 Joel Sherrill <joel@OARcorp.com>
* cpu_asm.S: Added code to save and restore SR and EPC to
properly support nested interrupts. Note that the ISR
(not RTEMS) enables interrupts allowing the nesting to occur.
2001-03-14 Joel Sherrill <joel@OARcorp.com>
* cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:

9
cpukit/score/cpu/mips/cpu_asm.S
View File

@@ -426,6 +426,10 @@ FRAME(_ISR_Handler,sp,0,ra)
/* This needs to be figured out.........*/
ADDIU sp,sp,-40
STREG ra,32(sp) /* store ra on the stack */
MFC0 t0, C0_EPC /* XXX */
STREG t0,16(sp) /* XXX store EPC on the stack */
mfc0 t0,C0_SR
STREG t0,24(sp) /* XXX store SR on the stack */
/* determine if an interrupt generated this exception */
@@ -529,6 +533,10 @@ _ISR_Handler_1:
_ISR_Handler_exit:
LDREG ra,32(sp)
LDREG t0,16(sp) /* XXX restore EPC on the stack */
MTC0 t0, C0_EPC /* XXX */
LDREG t0,24(sp) /* XXX restore SR on the stack */
mtc0 t0,C0_SR
ADDIU sp,sp,40 /* Q: Again with the 40...Is this needed? */
/* restore interrupt context from stack */
@@ -563,6 +571,7 @@ _ISR_Handler_exit:
ADDIU sp,sp,EXCP_STACK_SIZE
MFC0 k0, C0_EPC
nop
rfe /* Might not need to do RFE here... */
j k0