Imagelibrary/rtems
1
0
Fork 1
mirror of https://gitlab.rtems.org/rtems/rtos/rtems.git synced 2025-12-26 14:18:20 +00:00
Code Issues Packages Projects Releases Wiki Activity

serial/ns16550: Fix precision clock synthesizer

Browse Source 
The precision clock synthesizer support broke the driver on the QorIQ
P1020.  On this device the Alternate Function Register is accessed with
DLAB == 1 instead of the FIFO Control Register (FCR).  Restructure the
code to account for this.
This commit is contained in:
Sebastian Huber
2018-10-17 09:43:55 +02:00
parent d7c13c8772
commit 143c8d0d94
1 changed files with 17 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

33
bsps/shared/dev/serial/ns16550-context.c
View File

@@ -191,28 +191,22 @@ bool ns16550_probe(rtems_termios_device_context *base)
(uint8_t)(( ulBaudDivisor >> 8 ) & 0xffU )
);
/* Enable and reset transmit and receive FIFOs. TJA */
ucDataByte = SP_FIFO_ENABLE;
(*setReg)(pNS16550, NS16550_FIFO_CONTROL, ucDataByte);
ucDataByte = SP_FIFO_ENABLE | SP_FIFO_RXRST | SP_FIFO_TXRST;
if (ctx->has_precision_clock_synthesizer) {
/*
* Enable precision clock synthesizer. This must be done with DLAB == 1 in
* the line control register.
*/
ucDataByte |= 0x10;
}
(*setReg)(pNS16550, NS16550_FIFO_CONTROL, ucDataByte);
/* Clear the divisor latch and set the character size to eight bits */
/* with one stop bit and no parity checking. */
ucDataByte = EIGHT_BITS;
ctx->line_control = ucDataByte;
if (ctx->has_precision_clock_synthesizer) {
uint8_t fcr;
/*
* Enable precision clock synthesizer. This must be done with DLAB == 1 in
* the line control register.
*/
fcr = (*getReg)(pNS16550, NS16550_FIFO_CONTROL );
fcr |= 0x10;
(*setReg)(pNS16550, NS16550_FIFO_CONTROL, fcr);
(*setReg)(pNS16550, NS16550_SCRATCH_PAD, (uint8_t)(ulBaudDivisor >> 24));
(*setReg)(pNS16550, NS16550_LINE_CONTROL, ucDataByte );
(*setReg)(pNS16550, NS16550_SCRATCH_PAD, (uint8_t)(ulBaudDivisor >> 16));
@@ -220,6 +214,13 @@ bool ns16550_probe(rtems_termios_device_context *base)
(*setReg)(pNS16550, NS16550_LINE_CONTROL, ucDataByte);
}
/* Enable and reset transmit and receive FIFOs. TJA */
ucDataByte = SP_FIFO_ENABLE;
(*setReg)(pNS16550, NS16550_FIFO_CONTROL, ucDataByte);
ucDataByte = SP_FIFO_ENABLE | SP_FIFO_RXRST | SP_FIFO_TXRST;
(*setReg)(pNS16550, NS16550_FIFO_CONTROL, ucDataByte);
ns16550_enable_interrupts(ctx, NS16550_DISABLE_ALL_INTR);
/* Set data terminal ready. */